W71NW20GD3DW
Publication Release Date: September 07, 2016
- 1 - Revision 2.0
MULTI-CHIP P ACKAGE (MCP) MEMORY
1.8V 2G-BIT (16M-WORD x 8-BIT)
SLC NAND FLASH MEMORY
&
1.8V 1G-BIT (512K- WORD x 4 BANK x 32-BIT)
LOW POWER DDR (LPDDR) SDRAM
W71NW20GD3DW
Publication Release Date: September 07, 2016
- 2 - Revision 2.0
Table of Contents
1 GENER AL D E SCRIPTIO N .............................................................................................................. 3
2 FEATURES...................................................................................................................................... 3
3 BALL CONFIGURATION ................................................................................................................. 4
3.1 130-Ball Description for W29N02GZ NAND Flash Memory .................................................... 5
3.2 130-Ball Description for W94AD2KK Low Power DDR SDRAM ............................................. 5
4 Block Diagram ................................................................................................................................. 8
5 Package Specification ..................................................................................................................... 9
5.1 VFBGA130 Ball (8x9mm^2, Ball pitch:0.65mm, Ø=0.30mm) .................................................. 9
6 MCP ORDERING INFORMATION ................................................................................................ 10
7 Revision History ............................................................................................................................. 11
Table of Table
Table 3-1 W29N02GZ VFBGA-130 Ball Descript ion ............................................................................... 5
Table 3-2 W94AD2KK VFBGA-130 Ball Descr ipt ion .............................................................................. 7
Table 7-1 Revision History .................................................................................................................... 11
Table of Figure
Figure 3-1 W71NW20GD3DW, 130 Ball VFBGA Package (Top View, balls facing down) .................... 4
Figure 4-1 W71NW20GD3DW MCP Flash & LPDDR SDRAM Block Diagram ...................................... 8
Figure 5-1 130 Ball VFBGA 8x9mm Package ......................................................................................... 9
Figure 6-1 MCP Ordering Information ................................................................................................... 10
W71NW20GD3DW
Publication Release Date: September 07, 2016
- 3 - Revision 2.0
1 GENERAL DESCRIPTION
The W71NW series is a Multi-Chip Package (MCP) memory product family that consists of a 1.8V NAND
Flash Memory device and a 1.8V Low Power SDRAM device in one convenient Thin VFBGA package.
W71NW20GD3DW consists of:
• W29N02GZ - 1.8V 2G-Bit x8-BIT NAND Flash Mem ory
• W94AD2KK - 1.8V 1G-Bit x32-BIT Lo w Power DDR SDRAM
• 130 Ball VFBGA - Dimension 8x9mm, ball pitc h:0.65mm, ∅=0.30mm
2 FEATURES
W29N02GZ NAND Flash Memory W94AD2KK Low Power DDR SDRAM
• Basic Features
– Density : 2Gbit (Single chip solution)
– Vcc : 1.7V to 1.95V
– Bus width : x8
– Operating temperature
Industrial: -40°C to 85°C
• Single-Level Cell (SLC) technology.
• Organization
– Density: 2G-bit/256M-byte
– Page size
2,112 bytes (2048 + 64 bytes)
– Block size
64 pages (128K + 4K bytes)
• Highest Performance
– Read performance (Max.)
Random read: 25us
Sequential read cycle: 25ns
– Write Erase performance
Page program time: 250us(typ.)
Block erase time: 2ms(typ.)
– Endurance 100,000 Er as e/Pr o gr am
Cycles(2)
– 10-years data retention
• Command set
– Standard NAND command set
– Additional command support
Copy Back
Two-plane opera tion
– Contact Winbond for OTP feature
– Contact Winbond for block Lock feature
• Lowest power consumption
– Read: 25mA(typ.3V),T.B.D(typ.1.8V)
– Program/Erase: 10mA(typ.1.8V)
– CMOS standby: 10uA(typ.)
• VDD = 1.7~1.95V
• VDDQ = 1.7~1.95V;
• Data width: x32
• Clock rate: 200MHz (-5),166MHz (-6)
• Standard Self Refresh Mode
• Partial Arra y Self-Refresh(PASR)
• Auto Temperature Compensated Self-
Refresh(ATCSR)
• Power Down Mode
• Deep Power Down Mode (DPD Mode)
• Programmable output buffer driver
strength
• Four internal banks for concurrent
operation
• Data mask (DM) for write data
• Clock Stop capability during idle periods
• Auto Pre-charge option for each burst
access
• Double data rate for data output
• Differential clock inputs (CK and
CK
)
• Bidirectional, data strobe (DQS)
•
CAS
Latency: 2 and 3
• Burst Length: 2, 4, 8 and 16
• Burst Type: Sequential or Interleave
• 64 ms Refresh period
• Interface: LVCMOS compatible
• Support KGD(Known Good Die) form
• Operating Temperature Range
o
Industrial (-40°C ~ 85°C)
Note:
1. Endu rance speci ficati o n is based on 1bit/528 byte ECC (Error Correcting Code).
W71NW20GD3DW
Publication Release Date: September 07, 2016
- 4 - Revision 2.0
3 BALL CONFIGURATION
Figure 3-1 W71NW20GD3DW, 130 Ball VFBGA Package (Top View, balls facing down)
W71NW20GD3DW
Publication Release Date: September 07, 2016
- 5 - Revision 2.0
3.1 130-Ball Description for W29N02GZ NAND Flash Memory
Ball NO. BALL
NAME
I/O FUNCTION
B3 WP# I Write Protect
A7 WEn# I Write Enable
B4 ALE I Address Latch Enable
A4 CLE I Command Latch Enable
A6 CE# I Chip Enable
A3 RE# I Read Enab le
B6 R/B# I Ready/#Busy
M1 IO0 I/O Data Input Output 0
M2 IO1 I/O Data Input Output 1
M3 IO2 I/O Data Input Output 2
L5 IO3 I/O Data Input Output 3
N7 IO4 I/O Data Input Output 4
L6 IO5 I/O Data Input Output 5
M6 IO6 I/O Data Input Output 6
L8 IO7 I/O Data Input Output 7
A5, M5 VCCn Power Su pply NAND
A9,B1,B5,G9,H1,L2,N6,N9 VSS Ground NAND
L4 DNU1 Do Not Use
N1 DNU2 Do Not Use
Multiple NC No Connection
Table 3-1 W29N02GZ VFBGA-130 Ball Description
3.2 130-Ball Description for W94AD2KK Low Power DDR SDRAM
BALL NO. BALL
NAME I/O FUNCTION
H2 CS0 I Chip Select
D3 CKE0 I Clock Enable
F8 CLK I Clock
G8 CLK# I Clock Invert
J1 WEd# I Write Enable
G2 CAS# I Column Address Select
F2 RAS# I Row Address Select
H3 BA0 I Bank Address
J2 BA1 I Bank Address
W71NW20GD3DW
Publication Release Date: September 07, 2016
- 6 - Revision 2.0
BALL NO. BALL
NAME I/O FUNCTION
J4 A0 I Address Input Signal
K1 A1 I Address Input Signal
K2 A2 I Address Input Signal
K3 A3 I Address Input Signal
B2 A4 I Address Input Signal
C2 A5 I Address Input Signal
D1 A6 I Address Input Signal
C3 A7 I Address Input Signal
D2 A8 I Address Input Signal
C4 A9 I Address Input Signal
J3 A10 I Address Input Signal
E2 A11 I Address Input Signal
E1 A12 I Address Input Signal
L3 A13 I Address Input Signal
H8 DM0 I Input Data Mask
F6 DM1 I Input Data Mask
E8 DM2 I Input Data Mask
D7 DM3 I Input Data Mask
H7 DQS0 I/O Data Strob e
F5 DQS1 I/O Data Strobe
G7 DQS2 I/O Data Str ob e
D5 DQS3 I/O Data Strob e
K4 DQ0 I/O Data Inputs/Output
K5 DQ1 I/O Data Inputs/Output
k6 DQ2 I/O Data Inputs/Output
K7 DQ3 I/O Data Inputs/Output
J8 DQ4 I/O Data Inputs/Output
K8 DQ5 I/O Data Inputs/Output
J7 DQ6 I/O Data Inputs/Output
J5 DQ7 I/O Data Inputs/Output
J6 DQ8 I/O Data Inputs/Output
F7 DQ9 I/O Data Inputs/Output
H6 DQ10 I/O Data Inputs/Output
H5 DQ11 I/O Data Inputs/Output
G6 DQ12 I/O Data Inputs/Output
G5 DQ13 I/O Data Inputs/Output
W71NW20GD3DW
Publication Release Date: September 07, 2016
- 7 - Revision 2.0
BALL NO. BALL
NAME I/O FUNCTION
H4 DQ14 I/O Data Inputs/Output
F3 DQ15 I/O Data Inputs/Output
F4 DQ16 I/O Data Inputs/Output
E4 DQ17 I/O Data Inputs/Output
D4 DQ18 I/O Data Inputs/Output
E5 DQ19 I/O Data Inputs/Output
G3 DQ20 I/O Data Inputs/Output
G4 DQ21 I/O Data Inputs/Output
D6 DQ22 I/O Data Inputs/Output
E7 DQ23 I/O Data Inputs/Output
E6 DQ24 I/O Data Inputs/Output
C5 DQ25 I/O Data Inputs/Output
D8 DQ26 I/O Data Inputs/Output
C6 DQ27 I/O Data Inputs/Output
C8 DQ28 I/O Data Inputs/Output
C7 DQ29 I/O Data Inputs/Output
B8 DQ30 I/O Data Inputs/Output
B7 DQ31 I/O Data Inputs/Output
A8,C1,G1,G10,L1,N8 VDDd Power Supply
B9,C10,D9,E10,F9,H
10,J9,K9,L10,M9 VDDQd I/O Power Supply
A9,B1,B5,G9,H1,L2,
N6,N9 VSS Ground
B10,C9,D10,E9,F10,
H9,J10,K10,L9,M10 VSSQd I/O Ground
Table 3-2 W94AD2KK VFBGA-130 Ball Description
W71NW20GD3DW
Publication Release Date: September 07, 2016
- 8 - Revision 2.0
4 Block Diagram
Figure 4-1 W71NW20GD3DW MCP Flash & LPDDR SDRAM Bl ock Diagram
W71NW20GD3DW
Publication Release Date: September 07, 2016
- 9 - Revision 2.0
5 Package Specification
5.1 VFBGA130 Ball (8x9mm^2, Ball pitch: 0.65mm, Ø=0.30mm)
Figure 5-1 130 Ball VFBGA 8x9mm Package
W71NW20GD3DW
Publication Release Date: September 07, 2016
- 10 - Revis i on 2. 0
6 MCP ORDERING INFORMA TION
Figure 6-1 MCP Ordering Information
71 NW 2 0 G D 3 D W
Winbond Standard Product
W: Winbond
Product Family
71: MCP Product
Voltage
NW: 1.8V ONFI NAND Flash
Product Density
2: 2Gb
NAND I/O bits
0: 8 bit
Flash Generation
G= WEC 4X Technology Node
RAM Density
D= 1Gb LPDDR
RAM Option Information
3: 4X Technology *32
Package Type
D: 130 Balls VFBGA
Grade & Temperature
W: Industrial: -40°C to +85°C
W71NW20GD3DW
Publication Release Date: September 07, 2016
- 11 - Revis i on 2. 0
7 Revisi on Histor y
VERSION DATE PAGE DESCRIPTION
A 02/09/2015 New Create Preliminary
B 06/08/2015 10 Temperature Range Correction
Added Updated W29N02GW&Z Datasheet.
C 07/28/2015 9 Update POD
D 06/21/2016 4,5&7 Update package and table description
2.0 09/07/2016 NA Removed Preliminary annotation from this and the
attached documents.
Table 7-1 Revision History
Trademarks
Winbond and SpiFlash are trademarks of Winbond Electronics Corporation.
All other marks are the property of their respective owner.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in
systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, or for other applications intended to support or sustain life. Furthermore, Winbond products
are not i nte nde d f or ap pl ica t ions wher e in f ailure of Winbond pr o duc ts c ou ld r esu lt or le ad t o a s itu ati on
wherein personal injury, death or severe property or environmental damage could occur.
Winbond c ustom ers using or selling these produc ts f or use in s uch app lica tions d o so at t heir own risk
and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
W29N02GW/Z
Release Date: May 10th, 2016
1 Revision D
W29N02GW/Z
2G-BIT 1.8V
NAND FLASH MEMORY
W29N02GW/Z
Release Date: May 10th, 2016
2 Revision D
Table of Contents
1. GEN ER AL D E SCR I PTION ............................................................................................................... 7
2. FEATURES ....................................................................................................................................... 7
3. PIN DESCRITPIONS ........................................................................................................................ 8
3.1 Chip Enable (#CE) ................................................................................................................ 8
3.2 Write Enable (#WE) .............................................................................................................. 8
3.3 Read Enable (#RE) .............................................................................................................. 8
3.4 Address Latch Enable (ALE) ................................................................................................ 8
3.5 Command Latch Enable (CLE) ............................................................................................ 8
3.6 Write Protect (#WP) .............................................................................................................. 8
3.7 Ready/Busy (RY/#BY) .......................................................................................................... 8
3.8 Input and Output (I/Ox) ......................................................................................................... 8
4. BLOCK DIAGRAM ............................................................................................................................ 9
5. MEMORY ARRAY ORGANIZATION .............................................................................................. 10
5.1 Array Organization (x8) ...................................................................................................... 10
5.2 Array Organization (x16) .................................................................................................... 11
6. MODE SELECTION TABLE ........................................................................................................... 12
7. COMMAND TABLE......................................................................................................................... 13
8. DEVICE OPERATIONS .................................................................................................................. 14
8.1 READ operation .................................................................................................................. 14
8.1.1 PAGE READ (00h-30h) ........................................................................................................ 14
8.1.2 TWO PLANE READ (00h-00h-30h) ...................................................................................... 14
8.1.3 RANDOM DATA OUTPUT (05h-E0h) ................................................................................... 16
8.1.4 READ ID (90h) ...................................................................................................................... 17
8.1.5 READ PARAMETER PAGE (ECh) ....................................................................................... 18
8.1.6 READ STATUS (70h) ........................................................................................................... 20
8.1.7 READ STATUS ENHANCED (78h) ...................................................................................... 21
8.1.8 READ UNIQUE ID (EDh) ...................................................................................................... 23
8.2 PROGRAM operation ......................................................................................................... 24
8.2.1 PAGE PROGRAM (80h-10h) ................................................................................................ 24
8.2.2 SERIAL DATA INPUT (80h) ................................................................................................. 24
8.2.3 RANDOM DATA INPUT (85h) .............................................................................................. 25
8.2.4 TWO PLANE PAGE PROGRAM .......................................................................................... 25
8.3 COP Y BACK oper ati on ....................................................................................................... 27
8.3.1 READ for COPY BACK (00h-35h) ........................................................................................ 27
8.3.2 PROGRAM for COPY BACK (85 h -10h) ................................................................................ 27
8.3.3 TWO PLANE READ for COPY BACK ................................................................................... 28
8.3.4 TWO PLANE PROGRAM for COP Y BACK .......................................................................... 28
8.4 BLOCK ERASE operation .................................................................................................. 32
8.4.1 BLOCK ERASE (60h-D0h) ................................................................................................... 32
9.4.2 TWO PLANE BLOCK ERASE .................................................................................................. 33
8.5 RESET operation ................................................................................................................ 34
8.5.1 RESET (FFh) ........................................................................................................................ 34
8.6 FEATURE OPERATION..................................................................................................... 35
W29N02GW/Z
Release Date: May 10th, 2016
3 Revision D
8.6.1 GET FEATURES (EEh) ........................................................................................................ 38
8.6.2 SET FEATURES (EFh) ......................................................................................................... 39
8.7 ONE TIME PROGRAMMABLE (OTP) area ....................................................................... 40
8.8 WRITE PROTECT .............................................................................................................. 41
8.9 BLOCK LOCK ..................................................................................................................... 43
9. ELECTRICAL CHARACTERISTICS............................................................................................... 44
9.1 Absolute Maximum Ratings (1.8V) ..................................................................................... 44
9.2 Operating Ranges (1.8V) ................................................................................................... 44
9.3 Device power-up timing ...................................................................................................... 45
9.4 DC Electrical Characteristics (1.8V) ................................................................................... 46
9.5 AC Measurement Conditions (1.8V) ................................................................................... 47
9.6 AC timing characteristics for Command, Address and Data Input (1.8V) .......................... 48
9.7 AC timing characteristics for Operation (1.8V) ................................................................... 49
9.8 Program and Erase Characteristics ................................................................................... 50
10. TIMING DIAGRAMS ....................................................................................................................... 51
11. INVALID BLOCK MANAGEMENT .................................................................................................. 60
11.1 Invalid blocks ...................................................................................................................... 60
11.2 Initial invalid blocks ............................................................................................................. 60
11.3 Error in operation ................................................................................................................ 61
11.4 Addressing in program operation ....................................................................................... 62
12. REV ISI ON HI ST O RY ...................................................................................................................... 63
W29N02GW/Z
Release Date: May 10th, 2016
4 Revision D
List of Tables
Table 6-1 Addr es sing .................................................................................................................................. 10
Table 6-2 Addr es sing .................................................................................................................................. 11
Table 7-1 Mode Selection ........................................................................................................................... 12
Table 8-1 Command Table ......................................................................................................................... 13
Table 9-1 Device ID and configuration codes for Address 00h .................................................................. 17
Table 9-2 ONFI identifying codes for Address 20h ..................................................................................... 17
Table 9-3 Parameter Page Output Va lue .................................................................................................... 20
Table 9-4 Stat us Re gister Bit Def initi on ...................................................................................................... 21
Table 9-5 Features ...................................................................................................................................... 35
Table 9-6 Feature Address 80h .................................................................................................................. 36
Table 9-7 Feature Address 81h .................................................................................................................. 37
Table 10-1 Absolute Maximum Ratings ...................................................................................................... 44
Table 10-2 Operating Ranges ..................................................................................................................... 44
Table 10-3 DC Elect ric al C harac ter ist ic s .................................................................................................... 46
Table 10-4 AC Measurement Conditions .................................................................................................... 47
Table 10-5 AC timing characteristics for Command, Address and Data Input ........................................... 48
Table 10-6 AC timing characteristics for Operation .................................................................................... 49
Table 10-7 Program and Erase Characteristics .......................................................................................... 50
Table 12-1 Valid Block Number .................................................................................................................. 60
Table 12-2 Block failure .............................................................................................................................. 61
Table 16-1 History Table ............................................................................................................................. 63
W29N02GW/Z
Release Date: May 10th, 2016
5 Revision D
List of Figures
Figure 6-1 Array Organization ..................................................................................................................... 10
Figure 6-2 Array Organization ..................................................................................................................... 11
Figure 9-1 Page Read Operations .............................................................................................................. 14
Figure 9-2 Two Plane Read Page (00h-00h-30h) Operation ...................................................................... 15
Figure 9-3 Random Data Output ................................................................................................................. 16
Figure 9-4 Two Plane Random Data Read (06h-E0h) Operation ............................................................... 16
Figure 9-5 Read ID ...................................................................................................................................... 17
Figure 9-6 Read Parameter Page ............................................................................................................... 18
Figure 9-7 Read Status Operation .............................................................................................................. 20
Figure 9-8 Read Status Enhanced (78h) Operation ................................................................................... 22
Figure 9-9 Read Unique ID ......................................................................................................................... 23
Figure 9-10 Page Progr am.......................................................................................................................... 24
Figure 9-11 Random Data Input ................................................................................................................. 25
Figure 9-12 Two Plane Page Program ....................................................................................................... 26
Figure 9-13 Program for copy back Operation ............................................................................................ 29
Figure 9-14 Cop y Back Operat ion w ith Ran dom Data Input ....................................................................... 29
Figure 9-15 Two Plane Copy Back ............................................................................................................. 30
Figure 9-16 Two Plane Copy Back with Random Data Input ..................................................................... 30
Figure 9-17 Two Plane Program for copy back .......................................................................................... 31
Figure 9-18 Block Erase Operation ............................................................................................................. 32
Figure 9-19 Two Plane Block Erase Operation........................................................................................... 33
Figure 9-20 Reset Operation....................................................................................................................... 34
Figure 9-21 Get Feature Operation ............................................................................................................. 38
Figure 9-22 Set Feature Operation ............................................................................................................. 39
Figure 9-23 Erase Ena bl e ........................................................................................................................... 41
Figure 9-24 Erase Disable .......................................................................................................................... 41
Figure 9-25 Program Enable ....................................................................................................................... 41
Figure 9-26 Program Disable ...................................................................................................................... 42
Figure 9-27 Program for Copy Back Enable ............................................................................................... 42
Figure 9-28 Program for Copy Back Disable .............................................................................................. 42
Figure 10-1 Power ON/OFF sequence ....................................................................................................... 45
Figure 11-1 Command Latch Cycle ............................................................................................................ 51
Figure 11-2 Addres s Latch C ycle ................................................................................................................ 51
Figure 11-3 Data Latch Cycle ..................................................................................................................... 52
Figure 11-4 Serial Access Cycle after Read ............................................................................................... 52
Figure 11-5 Serial Access Cycle after Read (EDO) .................................................................................... 53
Figure 11-6 Read Status Operation ............................................................................................................ 53
Figure 11-7 Page Read Operation .............................................................................................................. 54
Figure 11-8 #CE Don't Care Read Operation ............................................................................................. 54
Figure 11-9 Random Data Output Operation .............................................................................................. 55
Figure 11-10 Read ID .................................................................................................................................. 56
Figure 11-11 Page Program........................................................................................................................ 56
Figure 11-12 #CE Don't Care Page Program Operation ............................................................................ 57
Figure 11-13 Page Program with Random Data Input ................................................................................ 58
W29N02GW/Z
Release Date: May 10th, 2016
6 Revision D
Figure 11-14 Copy Back ............................................................................................................................. 58
Figure 11-15 Block Erase ............................................................................................................................ 59
Figure 11-16 Reset ..................................................................................................................................... 59
Figure 12-1 Flow chart of create initial invalid block table .......................................................................... 61
Figure 12-2 Bad block Replacement ........................................................................................................... 62
W29N02GW/Z
Release Date: May 10th, 2016
7 Revision D
1. GENERAL DESCRIPTION
The W29N02GW/Z (2G-bit) NAND Flash mem or y provides a stor age soluti on for embedded s ystems with
limited spac e, pins and pow er. It is ideal for code s hadowing to RAM, solid state applications and storing
media data s uch as, voice, video, tex t and photos. T he device oper ates on a sin gle 1.7 V to 1.95V power
suppl y with active curr e nt consumption as low as 13mA at 1.8V and 10uA for CMOS standby current.
The memory array totals 276,824,064bytes, and organized into 2,048 erasable blocks of 135,168 bytes
(135,168 words ) . Each block consists of 64 programmable pages of 2,112-bytes (1056 words) e ac h. Each
page cons ists of 2,048-bytes (1024 words) for the m ain d ata stor age ar ea an d 64-bytes (32words) for the
spare data area (The spare area is typically used for error management functions).
The W29N02GW/Z supports the standard NAND flash memory interface using the multiplexed 8-bit (16-
bit) bus t o transfer data, addres ses, and c omm and instruc tions. T he five co ntrol s ignals, CLE, AL E, #CE,
#RE and #WE handle the bus interface protocol. Also, the device has two other signal pins, the #WP (Write
Protect) and the RY/#BY (Ready/Busy) for monitoring the device status.
2. FEATURES
• Basic Features
– Density : 2Gbit (Single chip solution)
– Vcc : 1.7V to 1.95V
– Bus width : x8 x16
– Operating temperature
Industrial: -40°C to 85°C
• Single-Level Cell (SLC) technology.
• Organization
– Density: 2G-bit/256M-byte
– Page size
2,112 bytes (2048 + 64 bytes)
1,056 words ( 1 024 + 32 words)
– Block size
64 pages (128K + 4K bytes)
64 pages (64K + 2K words)
• Highest Performance
– Read performance (Max.)
Random read: 25us
Sequential read cycle: 25ns
– Write Erase performance
Page program time: 250us(typ.)
Block erase time: 2ms(typ.)
– Endurance 100,000 Erase/Program
Cycles(2)
– 10-years data retention
• Command set
– Standard NAND command set
– Additional command support
Copy Back
Two-plane opera tion
– Contact Winbond for OTP feature
– Contact Winbond for block Lock feature
• Lowest power consumption
– Read: 25mA(typ.3V),T.B.D(typ.1.8V)
– Program/Erase: 10mA(typ.1.8V)
– CMOS standby: 10uA(typ.)
• Space Efficient Packaging
– 63-ball VFBGA
– Contact Winbond for stacked
packages/KGD
Note:
1. Endu rance speci ficati o n is based on 1bit/528 byte ECC (Error Correcting Code).
W29N02GW/Z
Release Date: May 10th, 2016
8 Revision D
3. PIN DESCRITPIONS
3.1 Chip Enable (#CE)
#CE pin enables and disables device operation. When #CE is high the device is disabled and the I/O
pins are set to high impeda nce and enter s into standb y mode if not bus y. When #CE is set low the
device will be enabled, power c onsum ption will i ncrease to active l evels and the device is ready for
Read and Write operations.
3.2 Wri t e E nable (#WE)
#WE pin enables the device to control write operations to input pins of the device. Such as, command
instructions, addresses and data that are latched on the rising edge of #WE.
3.3 Read Enable (#RE)
#RE p in controls seria l dat a output fr om the pre-loaded Data Register. Va lid data is present on t he
I/O bus af ter the t REA period f rom the f alling edge of #RE. Colum n addresses are incremented for
each #RE pulse.
3.4 Addres s Latch Enabl e (ALE)
ALE pin controls address input to the address register of the device. When ALE is active high,
addresses are latched via the I/O pins on the rising edge of #WE.
3.5 Comman d Latch Enable (CLE)
CLE pin controls command input to the comm and register of the device. W hen CLE is active high,
commands are latched into the command register via I/O pins on the rising edge of #WE.
3.6 Wri t e P rotect (#WP)
#WP pin can be used to prevent the inadvertent program/erase to the device. When #WP pi n is active
low, all program/erase operations are disabled.
3.7 Ready/Busy (RY/#BY)
RY/#BY pin indicates the device status. When RY/#BY output is low, it indicates that the device is
processing either a program, erase or read operations. When it returns to high, those operations have
completed. RY/#BY pin is an open drain.
3.8 Input and Output (I/Ox)
I/Ox bi-directional pins are used for the following; command, address and data operations.
W29N02GW/Z
Release Date: May 10th, 2016
9 Revision D
4. BLOCK DIAGR AM
Logic
Control
Status
Register
Command
Resister
Address
Register
High Voltage
Generator
NAND Flash
Array
Row Decoder
Column Decoder
Cache Register
Data Register
I/O
Control
#CE
ALE
CLE
#RE
#WE
#WP
I/Ox
RY/#BY
Figure 5-1 NAND Flash Memory Block Diagram
W29N02GW/Z
Release Date: May 10th, 2016
10 Revision D
5. ME M O R Y ARRAY ORGANIZATION
5.1 Array Organization (x8)
Figure 6-1 Array Organization
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1st cycle A7 A6 A5 A4 A3 A2 A1 A0
2nd cycle L L L L A11 A10 A9 A8
3rd cycle A19 A18 A17 A16 A15 A14 A13 A12
4th cycle A27 A26 A25 A24 A23 A22 A21 A20
5th cycle L L L L L L L A28
Table 6-1 Addressing
Notes:
1. “L” indicates a low condition, which must be held during the address cycle to in sure cor rect processing.
2. A0 to A11 during the 1st and 2nd cy cles are column addresses. A12 to A28 during the 3rd, 4th and 5th cycles
are row addresses.
3. A18 is plane address
4. The device ignor es an y additional address inputs that exceed the device’s requirem ent.
Plane of even
-
numbered blocks Plane of odd
-
numbered blocks
1024
blocks
Per plane
2048
blocks
Per device
Data Register
Cache Register 2048
2048
2048
2048
2112 bytes2112 bytes
64
64
64
64
1 block
1 block
1page = (2k+64bytes)
1block = (2k+64）bytes×64 pages
= (128k+4k)byte
1plane = (128k+4k)byte×1024blocks
= 1056Mb
1device = 1056M ×2planes
= 2112Mb
DQ7
DQ0
W29N02GW/Z
Release Date: May 10th, 2016
11 Revision D
5.2 Array Org anization (x16)
Figure 6-2 Array Organization
I/O[15:8] I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1st cycle L A7 A6 A5 A4 A3 A2 A1 A0
2ndcycle L L L L L L A10 A9 A8
3rd cycle L A18 A17 A16 A15 A14 A13 A12 A11
4th cycle L A26 A25 A24 A23 A22 A21 A20 A19
5th cycle L L L L L L L L A27
Table 6-2 Addressing
Notes:
1. “L” indicates a low conditio n, which mu st be held during the address cycle to insure correct processing.
2. A0 to A10 during the 1st and 2nd cy cles are column addresses. A11 to A27 during the 3rd, 4th and 5th cycles
are row addresses.
3. A17 is plane address
4. The device ignor es an y additional address inputs that exceed the device’s requirem ent.
1block = (1k+32）words×64 pages
= (64k+2k)words
1plane = (64k+2k)words×1024blocks
1device= 1056M ×2planes
= 2112Mb
Plane of even
-
numbered blocks Plane of odd
-
numbered blocks
1024
blocks
Per plane
2048
blocks
Per device
Data Register
Cache Register 1024
1024
1024
1024
1056 words 1056 words
32
32
32
32
1 block
1 block
1page = (1k+32words)
= 1056Mb
DQ15
DQ0
(0,2,4,6...,1020,1022)(1,3,5,7...,1021,1023)
W29N02GW/Z
Release Date: May 10th, 2016
12 Revision D
6. MODE SELECTION TABLE
MODE CLE ALE #CE #WE #RE #WP
Read
mode Command inpu t H L L H X
Address input L H L H X
Program
Erase
mode
Command input H L L H H
Address input L H L H H
Data input L L L H H
Sequential Read and Data output L L L H X
During read (busy) X X X X H X
During program (busy) X X X X X H
During erase (busy) X X X X X H
Write protect X X X X X L
Standby X X H X X 0V/Vcc
Table 7-1 Mode Selection
Notes:
1. “H” indicates a HIGH input level, “L” indicates a LOW input level, and “X” indicates a Don’t Care Level.
2. #WP should be biased to CMOS HIGH or LOW for standby.
W29N02GW/Z
Release Date: May 10th, 2016
13 Revision D
7. COMMAND TABLE
COMMAND 1ST
CYCLE 2ND
CYCLE 3rd
CYCLE 4th
CYCLE Acceptable
during
busy
PAGE READ 00h 30h
READ for COPY BACK 00h 35h
READ ID 90h
READ STATUS 70h Yes
RESET FFh Yes
PAGE PROGRAM 80h 10h
PROGRAM for COPY BACK 85h 10h
BLOCK ERASE 60h D0h
RANDOM DATA INPUT*1 85h
RANDOM DATA OUTPUT*1 05h E0h
READ PARAMETER PAGE ECh
READ UNIQUE ID EDh
GET FEATURES EEh
SET FEATURES EFh
READ STATUS ENHANCED 78h Yes
TWO PLANE READ PAGE 00h 00h 30h
TWO PLANE READ FOR COP Y BACK 00h 00h 35h
TWO PLANE RANDOM DATA READ 06h E0h
TWO PLANE PROGRAM(TRADITIONAL) 80h 11h 81h 10h
TWO PLANE PROGRAM(ONFI) 80h 11h 80h 10h
TWO PLANE
PROGRAM FOR COPY
BACK(TRADITIONAL) 85h 11h 81h 10h
TWO PLANE
PROGRAM FOR COPY
BACK(ONFI) 85h 11h 85h 10h
TWO PLANE BLOCK ERASE(TRADITIONAL) 60h 60h D0h
TWO PLANE BLOCK ERASE(ONFI) 60h D1h 60h D0h
Table 8-1 Command Table
Notes:
1. RANDOM DATA INPUT and RANDOM DATA OUTPUT command is only to be used within a page.
2. Any commands that are not in the above table are considered as undefined and are prohibited as inputs.
3. Do not cross plane address boundaries when using Copy Back Read and Program for copy back.
W29N02GW/Z
Release Date: May 10th, 2016
14 Revision D
8. DEVICE OPERATIONS
8.1 READ operation
8.1.1 PAGE READ (00h-30h)
When the dev ice po wers on, 00h com m and is la tched to command register . Ther ef ore, s ystem only
issues five address cycles and 30h command for initial read from the device. This operation can also
be entered by writing 00h command to the command register, and then write five address cycles,
followed by writing 30h command. After writing 30h command, the data is transferred from NAND
array to Da ta Re gist er during tR. Data trans f er pr ogr e ss c an be done by monitori ng the st at us of the
RY/#BY signal output. RY/#BY signal will be LOW during data transfer. Also, there is an alternate
method by using the READ STATUS (70h) command. If the READ STATUS command is issued
during read operation, the Read (00h) command m ust be re-issued to read out the data from Data
Register. W hen the dat a transfer is complete, RY/#BY signal goes HIG H, and th e data can be rea d
from Data Register by toggling #RE. Read is sequential from initial column address to the end of the
page. (See Figure 9-1)
Figure 9-1 Page Read Operations
8.1.2 TWO PLANE READ (00h-00h-30h)
TWO PLANE READ (00h-00h-30h) transfers two pages data from the NAND array to the data
registers. Each page address have to be indicated different plane address.
To set the TWO PLANE READ mode, write the 00h command to the command register, and then
write five address cycles for plane 0. Secondly, write the 00h command to the command register, and
five address cycles for plane 1. Finally, the 30h command is issued. The first-plane and second-plane
addresses must be identical for all of issued address except plane address.
After the 30 h com m and is written , page d ata is transf err ed from both planes to their res pectiv e data
registers in tR. RY/#BY goes LOW While these are transfered,. When the transfers are complete,
RY/#BY goes HIGH. To read out the data, at first, system writes TWO PLANE RAMDOM DATA READ
(06h-E0h) command to select a plane, next, repeatedly pulse #RE to read out the data from selected
plane. To change the plane address, issues TWO PLANE RANDOM DATA READ (06h-E0h)
Address (5cycles)30hData Output ( Serial Access )
Don’t care
l/Ox
#RE
RY/#BY
ALE
#WE
#CE
CLE
00h
tR
W29N02GW/Z
Release Date: May 10th, 2016
15 Revision D
comm and to select t he another plane addr ess, then re peatedl y pulse #RE to r ead out th e data f rom
the selected plane data register.
Alternat ively, data tra nsfer s can be monitor ed by the R EAD STAT US (70h). W hen the transf ers are
complete, status register bit 6 is set to 1. To read data from the first of the two planes even when
READ STATUS ENHANCED (78h) command is used, the system must issue the TWO PLANE
RANDOM DATA READ (06h-E0h) command at first and pulse #RE repeatedly.
Write a TWO PLANE RANDOM DATA READ (06h-E0h) command to select the other plane ,after the
data cycle is complete. pulse #RE repeatedly to output the data beginning at the specified column
address. Dur ing TW O PLANE READ o peration ,the READ STAT US ENHAN CED (78h) c omman d is
prohibited .
Figure 9-2 Two Plane Read Page (00h-00h-30h) Operation
CLE
#WE
ALE
#RE
I/O×
RY/#BY
Col
Add1
Col
Add2Row
Add1
Row
Add2
Row
Add3
30h
00h
tR
00h
Column address J Plane 1 address
Plane address M
Plane address M
Column address J Plane 0 address
1
CLE
#WE
ALE
#RE
I/O× E0h
06h D
OUT
0D
OUT
1D
OUT
n
Selected Plane data
1
RY/#BY
Plane 0 or Plane 1 address
Address (5cycles)
Col
Add1Col
Add2
Row
Add1
Row
Add2
Row
Add3
W29N02GW/Z
Release Date: May 10th, 2016
16 Revision D
8.1.3 RANDOM DA TA OUTPU T (05h-E0h)
The RANDOM DATA OUTPUT allows the selection of random column addresses to read out data
from a single or multiple of addresses. The use of the RANDOM DATA OUTPUT command is
available after the PAGE READ (00h-30h) sequence by writing the 05h command following by the
two cycle column address and then the E0h comm and. Toggling #RE will output data sequentially.
The RANDOM DATA OUTPUT command can be issued multiple times, but limited to the current
loaded page.
Figure 9-3 Random Data Output
8.1.3.1. TWO PLANE RANDOM DATA OUTPUT (06h-E0h)
TWO PLANE RANDOM DATA READ (06h-E0h) command can indicate to specified plane and
column address on data register . This command is accepted by a device when it is ready.
Issuing 06h to the command register, two column address cycles, three row address cycles, E0h are
followed, this enables data output mode on the address device’s data register at the specified column
address. After the E0h command , the host have to wait at least tWHR before requesting data output.
The selected device is in data output mode until another valid command is issued.
The TWO PLANE RANDO M D ATA READ ( 06 h-E 0h) comm and is used to s el ec t the da ta r eg ister to
be enabled for dat a out put. When the dat a output is com plete on the selected plane, the com mand
can be issued again to start data output on another plane.
If there is a n eed t o u pdat e the c ol umn address with out selecting a new data r egis t er , the R ANDOM
DATA READ (05h-E0h) command can be used instead.
Figure 9-4 Two Plane Random Data Read (06h-E0h) Operation
#RE
RY/#BY
I/Ox
05hE0h
Address(2cycles)
30h
Address(5cycles)
tR
Data out Data out
00h
CLE
ALE
#RE
I/O×
E0h
06hData Out
Data Out
#WE
#CE
Address (5cycles)
W29N02GW/Z
Release Date: May 10th, 2016
17 Revision D
8.1.4 READ ID (90h)
READ ID command is comprised of two modes determined by the input address, device (00h) or
ONFI (20h) identification information. To enter the READ ID mode, write 90h to the Command
Register followed by a 00h address c ycle, then toggle #RE for 5 single byte cycles, W29N02GW/Z.
The pre-programmed code includes the Manufacturer ID, Device ID, and Product-Specific Information
(see Table 9.1). If the READ ID command is followed by 20h address, the output code includes 4
single b yte c ycles of O NFI ident if ying inf ormat ion (See Table 9.2). The device rem ains in th e R EAD
ID Mode until the next valid command is issued.
#WE
CLE
#CE
ALE
#RE
I/Ox
90h
00h
(or 20h)
Address 1 Cycle
tAR
t RE A
tWHR
Byte0
Byte1 Byte2 Byte3 Byte4
Figure 9-5 R ead ID
# of
Byte/Cycles 1st
Byte/Cycle 2nd
Byte/Cycle 3rd
Byte/Cycle 4th
Byte/Cycle 5th
Byte/Cycle
W29N02GZ EFh AAh 90h 15h 04h
W29N02GW EFh BAh 90h 55h 04h
Description MFR ID Device ID Cache
Programming
not Supported
Page Size:2KB
Spare Area Size:64b
BLK Size w/o Spare:128KB
Organized:x8 or x16
Serial Acces s :25ns
x16 device : the ID is outputted at word units, and defined lower-byte (IO0-7). ID table shows only lower-byte ID.
Table 9-1 Device ID and configuration codes for Address 00h
# of Byte/Cycles 1st
Byte/Cycle 2nd
Byte/Cycle 3rd
Byte/Cycle 4th
Byte/Cycle
Code 4Fh 4Eh 46h 49h
Table 9-2 ONFI identifying codes for Address 20h
W29N02GW/Z
Release Date: May 10th, 2016
18 Revision D
8.1.5 READ PARAMETER PAGE (ECh)
READ PARAMETER PAGE can read out the device’s parameter data structure, such as,
manufacturer information, device organization, timing parameters, key features, and other pertinent
device par am eters. T he data s tructure is s tored wit h at least t hree copies i n the dev ice’s param eter
page. Figure 9-9 shows the READ PARAMETER PAGE timing. The RANDOM DATA OUTPUT (05h-
E0h) command is supported during data output.
I/Ox
CLE
#WE
ALE
#RE
RY/#BY
ECh P0
0
00h
tR
・・・
P1
0
P0
1
P1
1
・・・
Figure 9-6 Read Parameter Page
Byte Description Value
0-3 Parameter page sig natur e 4Fh, 4Eh, 46h, 49h
4-5 Revision number 02h, 00h
6-7 Features
supported W29N02GZ 18h,00h
W29N02GW 19h,00h
8-9 Optiona l command s supp orted 3Fh,00h
10-31 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
32-43 Device manufacturer 57h, 49h, 4Eh, 42h, 4Fh, 4Eh, 44h, 20h, 20h, 20h, 20h,
20h
44-63 Device model W29N02GZ 57h,32h,39h,4Eh,30h,32h,47h,5Ah,20h,20h,20h,20h,20
h,20h,20h,20h,20h,20h,20h,20h
W29N02GW 57h,32h,39h,4Eh,30h,32h,47h,57h,20h,20h,20h,20h,20
h,20h,20h,20h,20h,20h,20h,20h
64 Manufacturer ID EFh
65-66 Date code 00h, 00h
67-79 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h
80-83 # of data bytes per page 00h, 08h, 00h, 00h
W29N02GW/Z
Release Date: May 10th, 2016
19 Revision D
Byte Description Value
84-85 # of spare bytes per page 40h, 00h
86-89 # of data bytes per partial page 00h, 02h, 00h, 00h
90-91 # of spare bytes per parti al pa ge 10h, 00h
92-95 # of pages per block 40h, 00h, 00h, 00h
96-99 # of blocks per unit 00h, 08h, 00h, 00h
100 # of logical units 01h
101 # of address cycles 23h
102 # of bits per cell 01h
103-104 Bad blocks maximum per unit 28h, 00h
105-106 Block endurance 01h, 05h
107 Guaranteed valid blocks at beginning of
target 01h
108-109 Block endurance for guaranteed valid
blocks 00h, 00h
110 # of programs per page 04h
111 Partial programming attributes 00h
112 # of ECC bits 01h
113 # of interleaved address bits 01h
114 Interl eav ed operation attributes 0Ch
115-127 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h
128 I/O pin capaci tan ce 0Ah
129-130 Timing mode support 1Fh, 00h
131-132 Program cache timing 1Fh, 00h
133-134 Maximum page program time BCh, 02h
135-136 Maximum block erase time 10h, 27h
137-138 Maximum random read time 19h, 00h
139-140 tCCS minimum 46h, 00h
141-163 Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h
164-165 Vendor specific revision # 01h,00h
166-253 Vendor specific 00h
254-255 Integrity CRC Set at shipme nt
256-511 Value of bytes 0-255
W29N02GW/Z
Release Date: May 10th, 2016
20 Revision D
Byte Description Value
512-767 Value of bytes 0-255
>767 Additional redundant parameter pages
x16 device : the ID is outputted at word units, and defined lower-byte (IO0-7). ID table shows only lower-byte ID.
Table 9-3 Par ameter Page Output Va lue
8.1.6 READ STATUS (70h)
The W29N02GW/Z has an 8-bit Status Register which can be read during device operation. Refer to
Table 9.3 for specific Status Register definitions. After writing 70h command to the Command
Register, read cycles will only read from the Status Register. The status can be read from I/O[7:0]
outputs, as long as #CE and #RE are LOW. Note; #RE does not need to be toggled for Status Register
read. The Command Register remains in status read mode until another command is issued. To
change to normal read mode, issue the PAGE READ (00h) command. After the PAGE READ
command is issued, data output starts from the initial column address.
#CE
CLE
#WE
#RE
tCLR
I/Ox
70h Status Output
tREA
Figure 9-7 Read Status Operation
W29N02GW/Z
Release Date: May 10th, 2016
21 Revision D
SR bit Page Read Page Program Block Erase Definition
I/O 0 Not Use Pass/Fail Pass/Fail
0=Successful
Program/Erase
1=Error
in Program/Erase
I/O 2 Not Use Not Use Not Use 0
I/O 3 Not Use Not Use Not Use 0
I/O 4 Not Use Not Use Not Use 0
I/O 5 Ready/Busy Ready/Busy Ready/Busy Ready = 1
Busy = 0
I/O 6 Ready/Busy Ready/Busy Ready/Busy Ready = 1
Busy = 0
I/O 7 Write Protect Write Pr otect Write Protect Unprotected = 1
Protected = 0
Table 9-4 Status Register Bit Def ini ti on
8.1.7 READ STATUS ENHA NCED (78h)
The READ STATUS ENHANCED (78h) command returns the status of the addressed plane on a
target even when it is bus y (SR BIT 6 = 0).
Writing 78h to the command register, followed by three row address cycles containing the page, plane
and block addresses that is same as executed addresses, puts the device into read status mode. The
device stays in this mode until another valid command is issued
The device status is returned when the host requests data output. The SR BIT 6 and SR bit 5 bits of
the status register are shared for all planes on the device. The SR BIT 1 and SR BIT 0 (SR bit0) bits
are specific to the plane specified in the row address.
The READ STAT US ENHANCED (78h) command als o enab les the device for data output. T o beg in
data output following a READ operation after the device is ready (SR BIT 6 = 1), issue the READ
MODE (00h) command, then begin data output. If the host needs to change the data register that will
output data, use the TW O PLANE RANDOMDATA READ (06h-E0h) command after the device is
ready.
Use of the READ STATUS ENHANCED (78h) command is prohibited when OTP mode is enabled. It
is also prohibited following some of the other reset, identification.
W29N02GW/Z
Release Date: May 10th, 2016
22 Revision D
Figure 9-8 Read Status Enhanced (78h) Operation
CLE
ALE
#RE
I/O× Status Output
78h
#WE
#CE
Address (3cycles)
W29N02GW/Z
Release Date: May 10th, 2016
23 Revision D
8.1.8 READ UNIQUE ID (EDh)
The W29N02GW/Z NAND Flash d evice h as a m ethod to uni quel y identif y eac h NAND F lash device
by using the READ UNIQUE ID command. The format of the ID is limitless, but the ID for every NAND
Flash device manufactured, will be guaranteed to be unique.
Numerous NAND controllers typically use proprietary error correction code (ECC) schemes. In these
cases Winbond cannot protect unique ID data with factory programmed ECC. However, to ensure
data reliability, Winbond will program the NAND Flash devices with 16 bytes of unique ID code,
starting at byte 0 on the page, immediately followed by 16 bytes of the complement of that unique ID.
The combination of these two actions is then repeated 16 times. This means the final copy of the
unique ID will resides at location byte 511. At this point an XOR or exclusive operation can be
performed on the first copy of the unique ID and its complement. If the unique ID is good, the results
should yield all the bits as 1s. In the event that any of the bits are 0 after the XOR operation, the
procedure can be repeated on a subsequent copy of the unique ID data.
I/Ox
CLE
#WE
ALE
#RE
RY/#BY
EDh
Unique ID data
tR
Byte0 Byte1 Byte14 Byte15
00h
Figure 9-9 Read Unique ID
W29N02GW/Z
Release Date: May 10th, 2016
24 Revision D
8.2 PROGRAM op erat ion
8.2.1 PAGE PROGRAM (80h-10h)
The W29N02GW/Z Page Program command will program pages sequentially within a block, from the
lower order page address to higher order page address. Programming pages out of sequence is
prohibited. The W29N02GW/Z supports partial-page programming operations up to 4 times before
an erase is required if partitioning a page. Note; programming a single bit more than once without
first erasing it is not supported.
8.2.2 SERIAL DATA INPU T (80h)
Page Program operation starts with the execution of the Serial Data Input command (80h) to the
Command Register, following next by inputting five address cycles and then the data is loaded. Serial
data is lo ade d to Data Register with each #WE cycle. The Pr ogram com mand (10h) is wr itte n to the
Command Register after the serial data input is finished. At this time the internal write state controller
automatically executes the algorithms for program and verifies operations. Once the programming
starts, determining the completion of the program process can be done by monitoring the RY/#BY
output or the Status Register Bit 6, which will follow the RY/#BY signal. RY/#BY will stay LOW during
the internal array programming operation during the period of (tPROG). During page program
operation, only two commands are available, READ STATUS (70h) and RESET (FFh). When the
device status goes to the ready state, Status Register Bit 0 (I/O0) indicates whether the program
operation passed (Bit0=0) or failed (Bit0=1), (see Figure 9-13). T he Command Register remains in
read status mode until the next command is issued.
Figure 9-10 Pa ge Progr am
tPROG
Address (5cycles)
RY/#BY
I/Ox
Din80h10h70hStatus
I/O0 =0 pass
I/O0 =1 fail
W29N02GW/Z
Release Date: May 10th, 2016
25 Revision D
8.2.3 RANDO M DATA INPUT (8 5h)
After the Pag e Progr am (80h) ex ecution of the init ia l dat a has bee n loaded into the Data Regist er , if
the need for additional writing of data is required, using the RANDOM DATA INPUT (85h) command
can perform this function to a new column address prior to the Program (10h) command. The
RANDOM DATA INPUT command can be issued multiple times in the same page (See Figure 9-14).
Figure 9-11 Random Data Input
8.2.4 TWO PLANE PAGE PROGRAM
TW O PLANE P AGE PR OGR AM comm and m ake it pos sible for hos t to inp ut data t o the ad dressed
plane's data register and queue the data register to be moved to the NAND Flash array.
This c ommand c an be iss ued severa l tim es. Each tim e a new p lane addr ess is specified that pla ne
is also queu ed for data tr an sfer. To input data for the fi nal plane and to begin t he pr ogr am operation
for all previously queued planes, the PAGE PROGRAM command has to be issued. All of the queued
planes will move the data to the NAND Flash array. when it is ready (SR BIT 6 = 1),this command is
accepted.
At the block and page address is specified, input a page to the data register and queue it to be moved
to the NAND Flash array ,the 80h is issued to the command register. Unless this command has been
precede d by a TWO PLANE PAGE PROG R AM command, iss ui ng t he 80h to the command register
clears al l of the data regist ers' contents on the s elected tar get. W rite f ive address cycles conta ining
the colum n address an d row addres s; data input c ycles f ollow. Ser ial data is in put beginni ng at the
colum n addres s s pecif ied. At any time, whi le t he da ta i nput c yc le, th e RA N DO M D ATA INPUT (85h)
command can be issued. When data input is complete, write 11h to the command register. The device
will go busy (SR BIT 6 = 0, SR BIT 5 = 0) for tDBSY.
To ascertain the progress of tDBSY, the host can monitor the target's R Y/#BY signa l or, the status
operatio ns (70h, 78h) can be used a lternat ively,. W hen the device s tatus shows t hat it is read y (SR
BIT 6 = 1), additional TWO PLANE PAGE PROGRAM commands can be issued to queue additional
planes for data transfer, then, the PAGE PROGRAM commands can be issued.
When the PAGE PROGRAM command is used as the final command of a two plane program
operation, data is transferred from the data registers to the NAND Flash array for all of the addressed
RY/#BY
I/Ox
#WE
ALE
#RE
#CE
Din 70hStatus
Address (5cycles)
80h10h
Address
(2cycles)
85hDin
tPROG
Don’t care
CLE
W29N02GW/Z
Release Date: May 10th, 2016
26 Revision D
planes during tPROG. When the device is ready (SR BIT 6 = 1, SR BIT 5 = 1), the host should check
the status of the SR BIT 0 for each of the planes to verify that programming completed successfully.
When system issues TWO PLANE PAGE PROGRAM and PAGE PROGRAM commands, READ
STATUS (70h) comm and can confirm whether the operation(s) passed or failed. If the status after
READ STATUS (70h) command indicates an error (SR BIT 0 = 1 and/or SR BIT 1 = 1), READ
STATUS ENHANCED (78h) command can be determined which plane is failed.
TWO PLANE PROGRAM commands require five-cycle addresses, one address indicates the
operational plane. These addresses are subject to the following requirements:
• The column address bits must be valid address for each plane
• The plane select bit, A18, must be set to “L” for 1st address input, and set to “H” for 2nd address input.
• The page address (A17-A12) and block address (A28-A19) of first input are don’t care. It follows
secondary inputted page address and block address.
Two plane operations must be same type operation across the planes; for example, it is not possible
to perform a PROGRAM operation on one plane with an ERASE operation on another.
Figure 9-12 Two Plane Page Program
RY/#BY
Data
Input
FirstPlane
(1024 block)
Block 0
Block 2
:
Block 2044
Block 2046
Second Plane
(1024 block)
Block 1
Block 3
:
Block 2045
Block 2047
80h
Page program
Setup code
A0-A11=Valid
A12-A17=set to `Low`
A18=set to `Low`
A19-A28=set to `Low`
Confirm
Code
Multiplane Page
Program setup
code
A0-A11=Valid
A12-A17=Valid
A18=set to `High`
A19-A28=Valid
Confirm
Code
Read Status
Register
11h81h10h70hSR0
1)The same row address, except for A18, is applied to the two blocks.
2)Any command between 11h and 81h is prohibited except 70h,78h,and FFh
tDBSY tPROG
(Program busy time)
Busy Busy
Address Inputs Data Input Data Input
Address Inputs
l/Ox
80h11h
81h10h
※81h:Traditional Protocol 80h:ONFI Protocol
※
W29N02GW/Z
Release Date: May 10th, 2016
27 Revision D
8.3 COPY B ACK operation
Copy Back operations require two command sets. Issue a READ for COPY BACK (00h-35h)
command first, then the PROGRAM for COPY BACK (85h-10h) command. Copy back operations are
only supported within a same plane.
8.3.1 READ for COPY BACK (00h -35h)
The R EAD for C OPY BAC K comm and is used togeth er with the PRO GRAM for COPY BACK ( 85h-
10h) command. To start execution, READ for COPY BACK (00h) command is written to the Command
Register, followed by the five cycles of the source page address. To start the transfer of the selected
page data from the memory array to the data register, write the 35h command to the Command
Register.
After execution of the READ for COPY BACK command sequence and RY/#BY returns to HIGH
marking the completion of the operation, the transferred data from the source page into the Data
Register may be read out b y tog gling #R E. D ata is output sequent ia lly from the c olumn address that
was originally specified with the READ for COPY BACK command. RANDOM DATA OUTPUT (05h-
E0h) commands can be issued multiple times without any limitation after READ for COPY BACK
command has been executed (see Figures 9-19 and 9-20).
At this point the device is in ready state to accept the PROGRAM for COPY BACK command.
8.3.2 PROGRAM for COPY BACK (85h-10h)
After the RE AD f or CO P Y BACK c om mand operation has bee n c ompleted and R Y/# B Y goes HIG H,
the PROGRAM for COPY BACK command can be written to the Command Register. The command
results in the transf er of data to the Data R egister, then int er na l o perat ions st art p r ogr am ming of the
new destination page. The sequence would be, write 85h to the Command Register, followed by the
five cy cle destination page address to the NAND array . Next write the 10h command to the Command
Register; this will signal the internal controller to automatically start to program the data to new
destinati on page. Dur ing this pro gramm ing time, RY/# BY will LOW . The READ STATUS com mand
can be used instead of the RY/#BY signal to determine when the program is complete. When Status
Register Bit 6 (I/O6) equals to “1”, Status Register Bit 0 (I/O0) will indicate if the operation was
successful or not.
The RANDOM DATA INPU T (85h) command can be used during the PROGRAM for COPY BACK
command for modifying the original data. Once the data is copied into the Data Register using the
READ for COPY BACK (00h-35h) command, follow by writing the RANDOM DATA INPUT (85h)
comm and, along with t he address of the data to be change d. The data to be changed is placed o n
the external data pins. This operation copies the data into the Data Register. Once the 10h command
is written to the Command Register, the original data and the modified data are transferred to the
Data Register, and programming of the new page commences. The RANDOM DATA INPUT
command can be issued numerous times without limitation, as necessary before starting the
programming sequence with 10h command.
Since COPY BACK operations do not use external memory and the data of source page might include
a bit error s, a com petent ECC s cheme s hould be dev eloped to chec k the data befor e programm ing
data to a new destination page.
W29N02GW/Z
Release Date: May 10th, 2016
28 Revision D
8.3.3 TWO PLANE READ for COPY BA CK
To improve read through rate, TWO PLANE READ for COPY BACK operation is copied data
concurrently from one or two plane to the specified data registers.
TWO PLANE PROGRAM for CO P Y B AC K command can move the data in two pages from the data
registers to different pages. This operation improves system performance than PROGRAM for COPY
BACK operation.
8.3.4 TWO PLANE PRO GRAM for COPY BACK
Function of TWO PLANE PROGRAM for COPY BACK command is equal to TWO-PLANE PAGE
PROGRAM com mand, except t hat when 85h is wr itten to the comm and register , then data register
contents are not cleared. Refer to TWO-PLANE PAGE PROGRAM for more details features.
W29N02GW/Z
Release Date: May 10th, 2016
29 Revision D
Optional No limitation
RY/#BY
I/Ox
tR
CLE
#WE
ALE
#RE
#CE
00h 35h 85h 10h
tPROG
70h
Status
Output
Address(5cycles)
DataOutput Address
(2cycles)
85h
Don’t care
Address(5Cycles)
Data Input Data Input
Figure 9-13 Program for copy back Operation
Figure 9-14 Copy Back Operation with Random Data Input
Optional
Data output
No limitation
RY /#BY
I/ Ox
tR tPROG
CLE
#WE
ALE
#RE
#CE
Data Output
00hAddress (5cycles)
35h
05hAddress
(2cycles)E0h
85h
Address(5cycles)
10h70h
Status
Output
Don’t care
W29N02GW/Z
Release Date: May 10th, 2016
30 Revision D
RY/#BY
I/O× 00h Address(5cycles)
Plane 0 source
00h Address(5cycles)
Plane 1 source
35h
tR
RY/#BY
I/O×
1
85h Address(5cycles)
Plane 0 destination
11h
tDBSY
06h Address(5cycles)
Plane 0 or Plane 1 source address
E0h
#RE
Data Output 06h Address(2cycles)
Data from selected Plane Selected Plane
column address
E0h
#RE
Data Output
Data from selected plane
From new column address
85h Address(5cycles) 10h 70h Status
Plane 1 destination
2
2
RY/#BY
#RE
I/O×
Optional
tPROG
1
Figure 9-15 Two Plane Cop y Back
Figure 9-16 Two Plane Copy Back with Random Data Input
00h
I/O× Address(5cycles)
Plane 0 source
00hAddress(5cycles)
Plane 1 source
35h
tR
1
tDBSY
data
Plane 0 destination optional
Unlimited number
of repetitions
85hAddress(5cycles)10h70hStatus
Plane 1 destination
1
RY/#BY
I/O×
85hData 11h
tPROG
85h
RY/#BY
Address(5cycles)Address(2cycles)
W29N02GW/Z
Release Date: May 10th, 2016
31 Revision D
Figure 9-17 Two Plane Program for copy back
RY/#BY
tR tDBSY
Busy Busy Busy Busy
tPROG
tR
00h 35h 00h 35h 35h
Address
(5 cycles)
10h 70h SR0
Col Add.1,2
Row Add.1,2,3
Row Add1,2,3
Col Add1,2
Source address on Plane0 Source address on Plane1
Col Add1,2
Row Add.1,2,3
A0
- A11 = set to `Low’
A12-A17 = Valid
A18 = set to `High’
A19-A28 = Valid
Read
code
Read
code
Copy back
code
Copy back
code Read Status Register
85h 11h
Col Add.1,2
Source address on Plane1
Row Add1, 2,3
Destination address on Plane0
l/O
Address
(5 cycles)
Address
(5 cycles)
Address
(5 cycles)
85h
※
Spare area
SourcePage
TargetPage
Main area
First plane
SourcePage
TargetPage
Main area Spare area
Second plane
(1):Read for copy back on first plane
(2):Read for copy back on second plane
(3):Two-plane copy back program
(1) (3) (2) (3)
※85h:ONFI Protocol
81h:Traditional Protocol
A0
- A11 = don’t care
A12-A17 = don’t care
A18 = set to `Low’
A19- A28 = don’t care
Single plane copy back read can be used to two plane operation.
W29N02GW/Z
Release Date: May 10th, 2016
32 Revision D
8.4 BLOCK ERASE operation
8.4.1 BLOCK E RASE (60h-D0h)
Erase oper ations happen a t th e architectural block unit. T his W29N02GW/Z has 2048 er ase block s .
Each block is organized into 64 pages (x8:2112 bytes/page, x16:1056 words/page), 132K bytes
(x8:128K + 4K bytes, x16:64 K+ 2Kwords)/block. The BLOCK ERASE command operates on a block
by block basis.
Erase Setup command (60h) is written to the Command Register. Next, the three cycle block address
is written to the device. The page address bits are loaded during address block address c ycle, but
are ignored. The Erase Confirm command (D0h) is written to the Command Register at the rising
edge of #W E, RY/#BY goes LOW and the internal controller aut omatically handles the block erase
sequence of operation. RY/#BY goes LOW during Block Erase internal operations for a period of
tBERS,
The READ STATUS (70h) command can be used for confirm block erase status. When Status
Register Bit6 (I/O6) becomes to “1”, block erase operation is finished. Status Register Bit0 (I/O0) will
indicate a pass/fail condition (see Figure 9-24).
CLE
#WE
ALE
RY/#BY
#CE
#RE
I/Ox
t BE RS
I/ O 0 =0 pass
I/ O 0 =1 fail
Ad dr es s Input (3cycles)
60h
D0h
Status Output
70h
Don’t c a re
Figure 9-18 Block Erase Operation
W29N02GW/Z
Release Date: May 10th, 2016
33 Revision D
9.4.2 TW O PLANE BLOCK ERASE
TWO PLA NE BLOC K ERAS E (60h-D1h) command indicates two blocks in the specified plane that is
to be erased. To start ERASE operation for indicated blocks in the specified plan e, write the BLOCK
ERASE (60h-D0h) command.
To indicate a block to be erased, writing 60h to the command register, then, write three address cy cles
containing the row address, the page address is ignored. By writing D1h command to command
register, the device will go busy (SR BIT 6 = 0, SR BIT 5 = 0) for tDBSY.
To confirm bus y status duri ng tDB S Y, the hos t c an monitor R Y/#BY signal. I ns tea d, sys tem can use
READ STATUS (70h) or READ STATUS ENHANCED (78h) commands. When the status shows
ready (SR BIT 6 = 1, SR BIT 5 = 1), additional TWO PLANE BLOCK ERASE commands can be
issued for erasing two blocks in a specified plane.
When system issues TWO PLANE BLOCK ERASE (60h-D1h), and BLOCK ERASE (60h-D0h)
commands, READ ST ATU S (70 h) c omm a nd can conf irm whether the operation(s) passed or f ailed .
If the status after READ STATUS (70h) command indicates an error (SR BIT 0 = 1), READ STATUS
ENHANCED (78h) command can be determined which plane is failed.
TWO PLANE BLOCK ERASE commands require three cycles of row addresses; one address
indicates the operational plane. These addresses are subject to the following requirements:
• The plane select bit, A18, must be different for each issued address.
• Block address (A28-A19) of first input is don’t care. It follows secondary inputted block address .
Two plane operations must be same type operation across the planes; for example, it is not possible
to perform a PROGRAM operation on one plane with an ERASE operation on another.
Figure 9-19 Two Plane Block Erase Operation
RY/#BY
CLE
#WE
ALE
#RE
I/Ox
Busy
R1A R2A R3A 60hR1B R2B D0h
D1h R3B
tBERS
Busy
tDBSY
#CE
60h
Don’t care
W29N02GW/Z
Release Date: May 10th, 2016
34 Revision D
8.5 RESET operation
8.5.1 RESET (FFh)
READ, PR OGRAM, and ERASE comm ands can be a borted by the RES ET (FFh) c omm and during
the time the W29N02GW/Z is in the busy state. The Reset operation puts the device into known
status. The data that is processed in either the programming or erasing operations are no longer
valid. This means the dat a c an be part ia lly programmed or er ased and therefore data is inv alid. The
Command Register is cleared and is ready to accept next command. The Data Register contents are
marked invalid.
The Status Register indicates a value of E0h when #WP is HIGH; otherwise a value of 60h is written
when #W P is LOW. After RESET c ommand is written to the comm and register , RY/#BY goes LOW
for a period of tRST (see Figure 9-26).
CLE
#WE
RY/#BY
#CE
I/Ox
RESET
command
tRST
tWB
FFh
Figure 9-20 Reset Operation
W29N02GW/Z
Release Date: May 10th, 2016
35 Revision D
8.6 FEATURE OPERATION
The GET FEAT U RES ( EEh) an d SET FE AT URES ( EFh) c omm ands are used to change the NAND
Flash dev ice beha vior from the def ault po wer on settings. These c omm ands use a one-b yte featur e
address to determine which feature is to be read or modified. A range of 0 to 255 defines all features;
each is described in the features table (see Table 9.5 thru 9.7). The GET FEATURES (EEh) command
reads 4-Byte param eter in t he features table (See GET FEATURES function). The SET FEATURES
(EFh) command places the 4-Byte parameter in the features table (See SET FEATURES function).
W hen a featur e is set, m eaning it rem ains active by default unt il the device is powered off. T he set
feature remains the set even if a RESET (FFh) command is issued.
Feature address Description
00h N.A
02h-7Fh Reserved
80h Vendor specific par ameter : Programmable I/O drive strength
81h Vendor specific parameter : Programmable RY/#BY pull-down strength
82h-FFh Reserved
Table 9-5 Features
W29N02GW/Z
Release Date: May 10th, 2016
36 Revision D
Feature Address 80h: Programmable I/O Drive Strength
Sub feature
parameter
Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes
P1
I/O
drive strength
Full (default) Reserved (0) 0 0 00h 1
Three-quarters Reserved (0) 0 1 01h
One-half Reserved (0) 1 0 02h
One-quarter Reserved (0) 1 1 03h
P2
Reserved (0) 00h
P3
Reserved (0) 00h
P4
Reserved (0) 00h
Table 9-6 Feature Address 80h
Note:
1. The default drive strength setting is Full strength. The Programmable I/O Drive Strength mode i s used to
change from the def a ult I/O d r ive strength. Drive strength should be selected based on expected loading of
the memory bus. This table shows the four supported output drive-strength settings. The device returns to
the default drive strength mode when a power c ycl e has occurred. AC timing p arameters may need to be
relaxed if I/O drive strength is not set to ful l.
W29N02GW/Z
Release Date: May 10th, 2016
37 Revision D
Feature Address 81h: Programmable RY/#BY Pull-down Strength
Sub feature
parameter
Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Notes
P1
RY/#BY
pull-down
strength
Full (default) Reserved (0) 0 0 00h 1
Three-quarters Reserved (0) 0 1 01h
One-half Reserved (0) 1 0 02h
One-quarter Reserved (0) 1 1 03h
P2
Reserved (0) 00h
P3
Reserved (0) 00h
P4
Reserved (0) 00h
Table 9-7 Feature Address 81h
Note:
1. The default pr ogrammable RY/#BY pull-down strength is set to Full strength. T he pul l-down strength is used
to change the RY/#BY pull-down st rength. RY/#BY pull-down strength should be selected based on expected
loading of RY/#BY. The four supported pull-down strength settings are shown. The device returns to the
default pull-down strength when a power cycle has occurred.
W29N02GW/Z
Release Date: May 10th, 2016
38 Revision D
8.6.1 GET FEATURES ( EEh)
The GET FEATURES command returns the device feature settings including those previously set by
the SET FEATURES command. To use the Get Feature mode write the command (EEh) to the
Command Register followed by the single cycle byte Feature Address. RY/#BY will goes LOW for the
period of tFEAT. If Read Status (70h) command is issued for monitoring the process completion
status, Read Comm and (00h) has t o be executed t o re-establish data output m ode. Once, RY/#BY
goes HIGH, the device feature settings can be read by toggling #RE. The device remains in Feature
Mode until another valid command is issued to Command Register. See Figure 9-27.
I/Ox
CLE
#WE
ALE
#RE
RY/#BY
FA
Feature address
1 cycle
#CE
EEh
tFEAT
P1 P2 P4P3
Figure 9-21 Get Feature Operation
W29N02GW/Z
Release Date: May 10th, 2016
39 Revision D
8.6.2 SET FEATURES (EFh)
The SET FEATURES command sets the behavior parameters by selecting a specified feature
address. To change device behavioral parameters, execute Set Feature command b y writ in g EFh to
the Command Register, followed by the single cycle feature address. Each feature param eter (P1-
P4) is latch ed at the rising edge of each #WE. The RY/#BY s ign al wil l go LOW durin g th e period of
tFEAT while the four feature parameters are stored. The Read Status (70h) command can be issued
for monitoring the progress status of this operation. The parameters are stored in device until the
device goes through a power on cycle. The device remains in feature mode until another valid
command is issued to Command Register.
I/Ox
CLE
#WE
ALE
#RE
RY/#BY
FA
#CE
EFh
tFEAT
P1 P2 P4P3
tWB
tADL
Figure 9-22 Set Feature Operation
W29N02GW/Z
Release Date: May 10th, 2016
40 Revision D
8.7 ONE TIME PROGRAMMABLE (OTP) area
The device has One-Time Programmable (OTP) memory area comprised of a number of pages (2112
bytes/page) (1056words/page). T his entire r ange of pages is func tionall y guarant eed. Only the OTP
commands can acces s the OT P area. When the de vice ships f rom Winbond, the OT P area is in an
erase state (all bits equal “1”). The OTP area cannot be erased, therefore protecting the area only
prevent further programming. Contact to Winbond for using this feature.
W29N02GW/Z
Release Date: May 10th, 2016
41 Revision D
8.8 WRITE PROTECT
#WP pin can enable or disable program and erase comm ands preventing or allowing program and
erase operations. Figure 9-29 to 9-34 shows the enabling or disabling timing with #WP setup time
(tWW) that is fr om rising or falling ed ge of #W P to latch th e first commands. After first c omm and is
latched, #W P pin must not togg le until the com mand operation is complete an d the device is in the
ready state. (Status Register Bit5 (I/O5) equal 1)
I /Ox
#WE
#WP
tWW
RY/#BY
60h D0h
Figure 9-23 Erase Enable
I/Ox
#WE
#WP
tWW
RY/#BY
60hD0h
Figure 9-24 Erase Disable
I/Ox
#WE
#WP
tWW
RY/#BY
10 h
(or 15h)
80
h
Figure 9-25 Program Enable
W29N02GW/Z
Release Date: May 10th, 2016
42 Revision D
I/Ox
#WE
#WP
80 h
tWW
RY/#BY
10 h
(or 15h)
Figure 9-26 Program Disable
I
/
Ox
#WE
#WP
85h
tWW
RY/#BY
10h
Figure 9-27 Program for Copy Back Enable
I/Ox
#WE
#WP
85 h
tWW
RY/#BY
10 h
Figure 9-28 Program for Copy Back Disable
W29N02GW/Z
Release Date: May 10th, 2016
43 Revision D
8.9 BLOCK LO CK
The dev ice has block lock feature that c a n pr otec t the entire d ev ice or user can indicate a ranges of
blocks from program and erase operations. Using this feature offers increased functionality and
flexibility dat a protection to preve nt unexpect ed pro gra m and erase operations. Contact to Winbond
for using this feature.
W29N02GW/Z
Release Date: May 10th, 2016
44 Revision D
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Rat ings (1.8V)
PARAMETERS SYMBOL CONDITIONS RANGE UNIT
Supply Voltage VCC –0.6 to +2.4 V
Voltage Applied to Any Pin VIN Relative to Ground –0.6 to +2.4 V
Storage Temperature TSTG –65 to +150 °C
Short circuit output current, I/Os 5 mA
Table 10-1 Absolute Maximum Ratings
Notes:
1. Minimum DC voltage is -0.6 V on input/output pins . During transitions, this level may undershoot to -2.0V for
periods <30ns.
2. Maximum DC v oltage on input/output p ins is Vcc+0 .3V which, during transiti ons, may overshoot to Vcc+2.0V
for periods <20ns.
3. This device has been designed and tested for the speci fied operation ranges. Proper operatio n outside of
these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability.
Exposure beyond absolute maximum ratings may cause permanent damage.
9.2 Op erat ing Ranges (1.8V)
PARAMETER SYMBOL CONDITIONS SPEC UNIT
MIN MAX
Suppl y Voltage VCC 1.7 1.95 V
Ambient Temperature,
Operating TA Industrial -40 +85 °C
Table 10-2 Operating Ranges
W29N02GW/Z
Release Date: May 10th, 2016
45 Revision D
9.3 Device p ower-up timing
The device is designed to avoid unexpected program/erase operations during power transitions.
W hen the device is powere d on, an i nternal vo ltage de tector dis ables all f unctions whene ver Vcc is
below about 1.1V at 1.8V device. Write Protect (#WP) pin provides hardware protection and is
recommended to be kept at VIL during power up and power down. A recovery time of minimum 1ms
is required before internal circuit gets ready for any command sequences (See Figure 10-1).
Figure 10-1 Power ON/OFF sequence
5 ms (Max)
Vcc
RY/#BY
1ms
(Min)
Undefined
#WP
#WE
W29N02GW/Z
Release Date: May 10th, 2016
46 Revision D
9.4 DC Elect rical Characteristics (1.8V)
PARAMETER SYMBOL CONDITIONS SPEC UNIT
MIN TYP MAX
Sequential Read current Icc1
tRC= tRC MIN
#CE=VIL
IOUT=0mA - 13 20 mA
Program current Icc2 - - 10 20 mA
Erase current Icc3 - - 10 20 mA
Standby current (TTL) ISB1 #CE=VIH
#WP=0V/Vcc - - 1 mA
Standby current (CMOS) ISB2 #CE=Vcc – 0.2V
#WP=0V/Vcc - 10 50 µA
Input l eakage current ILI VIN= 0 V to Vcc - - ±10 µA
Output leakage cur rent ILO VOUT=0V to Vcc - - ±10 µA
Input hi gh voltage VIH I/O15~0, #CE,#WE,#RE,
#WP,CLE,ALE 0.8 x Vcc - Vcc + 0.3 V
Input l ow voltage VIL - -0.3 - 0.2 x Vcc V
Output high voltage(1) VOH IOH=-100µA Vcc -0.1 - - V
Output low voltag e(1) VOL IOL=+100µA - - 0.1 V
Output low curr ent IOL(RY/#BY) VOL=0.2V 3 4 mA
Table 10-3 DC Electrical C har ac teris t ics
Note:
1. VOH and VOL may need to be relaxed if I/O drive strength is not set to full.
W29N02GW/Z
Release Date: May 10th, 2016
47 Revision D
9.5 AC Measurement Con ditions (1.8V )
PARAMETER SYMBOL SPEC UNIT
MIN MAX
Input Capacitance(1), (2) CIN - 10 pF
Input/Output Capacitance(1), (2) CIO - 10 pF
Input Rise and Fall Times TR/TF - 2.5 ns
Input Pulse Voltages - 0 to VCC V
Input/Output timing Voltage - Vcc/2 V
Output load (1) CL 1TTL GATE and CL=30pF -
Table 10-4 AC Measurement Conditions
Notes:
1. Veri fi ed on device characterization , not 100% tested
2. Test conditi o ns TA=25’C, f=1M Hz, VIN=0V
W29N02GW/Z
Release Date: May 10th, 2016
48 Revision D
9.6 AC timing characteristics for Command, Address and Dat a Input (1.8V)
PARAMETER SYMBOL SPEC UNIT
MIN MAX
ALE to Data Loading Time tADL 70 - ns
ALE Hold Ti m e tALH 5 - ns
ALE setup T ime tALS 10 - ns
#CE Hold Ti m e tCH 5 - ns
CLE Hold Ti m e tCLH 5 - ns
CLE set up Time tCLS 10 - ns
#CE set up Time tCS 20 - ns
Data Hold Time tDH 5 - ns
Data setup Time tDS 10 - ns
Write Cycle Time tWC 35 - ns
#WE High Hold Time tWH 10 - ns
#WE Pulse Width tWP 12 - ns
#WP setup Time tWW 100 - ns
Table 10-5 AC timing characteristics for Command, Address and Data Input
Note:
1. tADL is the time from th e #WE rising edge of final address cycle to the #WE rising edge of first data cycle.
W29N02GW/Z
Release Date: May 10th, 2016
49 Revision D
9.7 AC timing characteristics for Op eration (1.8V)
PARAMETER SYMBOL SPEC UNIT
MIN MAX
ALE to #RE Delay tAR 10 - ns
#CE Access Time tCEA - 30 ns
#CE HIGH to Output H igh-Z(1) tCHZ - 50 ns
CLE to #RE Delay tCLR 10 - ns
#CE HIGH to Output Hold tCOH 15 - ns
Output High-Z to #RE LOW tIR 0 - ns
Data Transfer from Cell to Data Register tR - 25 µs
READ Cycle Time tRC 35 - ns
#RE Access Time tREA - 25 ns
#RE HIGH Hold Ti m e tREH 10 - ns
#RE HIGH to Output Hol d tRHOH 15 - ns
#RE HIGH to #WE LOW tRHW 100 - ns
#RE HIGH to Output Hi gh-Z(1) tRHZ - 100 ns
#RE LOW to output hold tRLOH 3 - ns
#RE Pulse Width tRP 12 - ns
Ready to #R E LOW tRR 20 - ns
Reset T ime (READ/PROGRAM/ERASE)(2) tRST - 5/10/500 µs
#WE HIGH to Busy(3) tWB - 100 ns
#WE HIGH to #RE LOW tWHR 80 - ns
Table 10-6 AC timing characteristics for Operation
Notes: AC characteristics may need to be relaxed if I/O drive strength i s not set to “full.”
1. Transition is measured ±200mV from steady-state voltage with load. This parameter is sampled and not
100 % tested
2. Do not issue new command during tWB, even if RY/#BY is ready.
W29N02GW/Z
Release Date: May 10th, 2016
50 Revision D
9.8 Program and Erase Charact eristics
PARAMETER SYMBOL SPEC UNIT
TYP MAX
Number of partial page programs NoP - 4 cycles
Page Pro gram time tPROG 250 700 µs
Busy Time for SET FEATURES /GET FEATURES tFEAT - 1 µs
Busy Tim e for progr am /erase at locked bl ock tLBSY - 3 µs
Busy Tim e for OTP program when OTP is protected tOBSY - 30 µs
Block Erase Time tBERS 2 10 ms
Last Page Program time (1) tLPROG - - -
Busy Time for Two Plane page program and Two Plane Block
Erase tDBSY 0.5 1 µs
Table 10-7 Program and Erase Characteristics
Note:
1. tLPROG = Last Page program time (tPROG) + Last -1 Page program time (tPROG) – Last page Address,
Command and Data load time.
W29N02GW/Z
Release Date: May 10th, 2016
51 Revision D
10. TIMING DIAGRAMS
Figure 11-1 Command Latch Cycle
Figure 11-2 Address Latch Cycle
tCS
Command
tWP
tCLHtCLS
tCH
tALS tALH
tDS tDH
Don’t care
CLE
#WE
ALE
I/Ox
#CE
tCS
Address
tWP
tWC
tALS tALH
tDS tDH
tCLS
tWH
Don’t care Undefined
CLE
#CE
I/Ox
#WE
ALE
W29N02GW/Z
Release Date: May 10th, 2016
52 Revision D
Figure 11-3 Data Latch Cycle
Note:
1. Din Final = 2,111(x8)
Figure 11-4 Serial Access Cycle after Read
Din 0
tWP
tCLH
tALS
tDS tDH
tWP tWP
Din 1
tDS tDH
tWH
Din Final
1
tDS tDH
tCH
tWC
Don’t care
CLE
#CE
I/Ox
#WE
ALE
tCHZ
tCEA
tRP
tRHZ
Dout Dout
tREA
tREH
tREA
Dout
tREA
tRHOH
tCOH
tRHZ
tRR tRC
Don’t care
#CE
I/Ox
#RE
RY/#BY
W29N02GW/Z
Release Date: May 10th, 2016
53 Revision D
Figure 11-5 Serial Access Cycle after Read (EDO)
Figure 11-6 Read Status Operation
tCHZ
tCEA
tRP
Dout
tREA
tREH
tREA
tCOH
tRHZ
tRR
tRC
Dout
tRHOH
tRLOH
Don’t care
I/Ox
RY/#BY
#RE
#CE
Dout
#CE
#RE
#WE
tWP tCH
tRHZ
tCHZ
CLE
I/Ox
tCOH
Status
output
tRHOH
tRP
tCEA
tCS
tCLR
tCLS tCLH
70h
tDS tDH tIR tREA
tWHR
Don’t care
W29N02GW/Z
Release Date: May 10th, 2016
54 Revision D
Busy
Dout
n+1
Dout
n
Dout
m
00h 30h
tAR
tWB
tCLR
tRC
tRR
tWC
tRP
tRHZ
tR
I/Ox
#WE
ALE
#RE
RY/#BY
CLE
#CE
Don’t care
Address(5Cycles)
Figure 11-7 Page Read Operation
CLE
#WE
ALE
RY/#BY
#CE
#RE
I/Ox
Out
tCEA
t RE A
tCOH
tCHZ
#CE
#RE
I/Ox
tR
00hAddress (4 cycles)30hData outpu t
Don’t c a re
Figure 11-8 #CE Don't Care Read Operation
W29N02GW/Z
Release Date: May 10th, 2016
55 Revision D
t RC
t RR
Colu mn address n
t RE A
Colu mn address m
t CL R
tAR
tWB
tWC
tWHR
00h30h05h E0h
Bu sy
tR
#WE
ALE
#RE
RY/#BY
CLE
#CE
I/Ox
Don’t c a re
Figure 11-9 Random Data Output Operation
W29N02GW/Z
Release Date: May 10th, 2016
56 Revision D
I/Ox
#WE
#RE
CLE
#CE
ALE
tAR
90h
(or 20h)
Address, 1 cy cle
00hByte 1
Byte 0
t RE A
Byte 2Byte 4
Byte 3
tWHR
Figure 11-10 Read ID
I/Ox
#WE
ALE
#RE
RY/#BY
CLE
#CE
80hCol
add 1Col
add 2
tWC
Ro w
add 1Ro w
add 2S ta t us
S E RIA L DATA
INPUT c omman d
70h
tPROGtWB
tADL
10h
1 up to m By t e
serial input
PRO GRAM
co mmand
READ STATUS
co mmand
x8 device:m = 2112 b y t es
tWHR
Don’t c a re
Figure 11-11 Page Pro gr a m
W29N02GW/Z
Release Date: May 10th, 2016
57 Revision D
I/Ox
CLE
#WE
ALE
#CE
80hAddress(4 cy cl es)Data input Data input 10h
#WE
#CE
tCS t CH
tWP
Don’t c a re
Figure 11-12 #CE Don't Care Page Program Operation
W29N02GW/Z
Release Date: May 10th, 2016
58 Revision D
I/Ox
CLE
#WE
ALE
#RE
#CE
80hCol
add 2
Col
add 1
ｔWC
Din
ｎ
Din
N+1
Serial Data
Inpu t Command
85hSt atu s
70h
10h
Din
N+1
Serial INPUT
Com ma nd
Program
C om ma nd
tADL
tWB
tPROG
Rand om Data Inpu t
Com ma nd
RY/#BY
Colu mn address Serial INPUT
Ro w
add2
tADL
Col
add1Col
add2Din
ｎ
Don’t c a re
Ro w
add1
Figure 11-13 Page Program with Random Data Input
Figure 11-14 Copy Back
00h
ｔWC
Serial data INPUT
Command
tADL
Program
Command
tWB
tPROG
I/Ox
CLE
#WE
ALE
#RE
#CE
RY/#BY
tWB
tR
Busy
Col
add 1 Col
add 2 Row
add1Row
add235h85hCol
add 1 Col
add 2 Row
add1Row
add2Din
1Din
n10hStatus
70h
Don’t care
W29N02GW/Z
Release Date: May 10th, 2016
59 Revision D
#RE
RY/#BY
CLE
#CE
#WE
ALE
Busy
60hD0h
tBERS
tWC
Status
70h
BLOCK ERASE SETUP
command
ERASE
command READ STATUS
command
tWB
I/Ox
Don’t care
Address(3cycles)
Figure 11-15 Block Erase
I/Ox
#WE
RY/#BY
CLE
#CE
F Fh
t RS T
RESET
co mmand
tWB
Figure 11-16 Reset
W29N02GW/Z
Release Date: May 10th, 2016
60 Revision D
11. INVALID BLOCK MANAGEMENT
11.1 Invalid blocks
The W29N02GW/Z m ay have initial invalid blocks when it ships from factory. Also, a dditional invalid
blocks may develop during the use of the device. Nvb represents the minimum number of valid blocks
in the total number of available blocks (See Table 12.1). An invalid block is defined as blocks that
contain one or more bad bits. Block 0, block address 00h is guaranteed to be a valid block at the time
of shipment.
Parameter Symbol Min Max Unit
Valid block number Nvb 2008 2048 blocks
Table 12-1 Valid Block Number
11.2 Initial invalid blocks
Initial invalid blocks are defined as blocks that contain one or more invalid bits when shipped from
factory.
Although the device contains initial in val id blocks, a valid block of the device is of the same quality
and reliability as all valid blocks in the device with reference to AC and DC specifications. The
W29N02GW/Z has internal cir cuits to iso late each b lock from other block s and therefore, the invalid
blocks will not affect the performance of the entire device.
Before the device is shipped from the factory, it will be erased and invalid blocks are marked. All initial
invalid blocks are marked with non-FFh at the first byte of spare area on the 1st or 2nd page. The initial
invalid bloc k inform ation cannot be rec overed if inadv ertentl y erase d. T herefor e, software sho uld be
created to initially check for invalid blocks by reading the marked locations before performing any
program or erase operation, and create a table of initial invalid blocks as following flow chart
W29N02GW/Z
Release Date: May 10th, 2016
61 Revision D
Figure 12-1 Flow chart of create initial invalid block table
11.3 Error in operation
Additional invalid blocks may develop in the device during its life cycle. Following the procedures
herein is required to guarantee reliable data in the de vic e.
After each program and erase operation, check the status read to determine if the operation failed. In
case of failure, a block replacement should be done with a bad-block management algorithm . The
system has to use a minimum 1-bit ECC per 528 bytes of data to ensure data recovery.
Operation Detection and recommended procedure
Erase Status read after erase Block Replacement
Program Status read after program Block Replacement
Read Ver ify ECC ECC correction
Table 12-2 Block failure
W29N02GW/Z
Release Date: May 10th, 2016
62 Revision D
Figure 12-2 Bad block Replacement
Note:
1. An error happens in the nth page of block A during program or erase operation.
2. Copy the data in block A to the same location of block B which is valid block.
3. Copy the nth page data of block A in the buffer memory to the nth page of block B
4. Creating or updating bad block table for preventing furth er program or erase to block A
.
11.4 Addressing i n pr ogr am opera t io n
The pages within the block have to be programmed sequentially from LSB (least significant bit) page
to the M SB (m ost significa nt bit) within the block. T he LSB is defined as the start page to pr ogram,
does not need to be page 0 in the block. Random page programming is prohibited.
W29N02GW/Z
Release Date: May 10th, 2016
63 Revision D
12. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
0.1 08/22/14 New Create as preliminary
0.2 10/23/14 77
79 Update POD
Correct Valid Part Numbers
0.3 05/19/15 Remove Cache operation mode
0.4 10/14/15 21 Update Read Parameter Page
A 10/15/15 Remove “Preliminary”
B 02/01/16 21, 22, 47 Update Parameter Page Output Value
Update Notes of Absolute Maximum Ratings
C 03/28/16 8, 67, 69, 70 Add TSOP-48 package
D 05/10/16 52, 53 Update AC timing characteristics
09/07/2016 Modified for MCP Combo Datasheet
Table 16-1 History Table
Trademarks
Winbond is trademark of Winbond Electronics Corporation.
All other marks are the property of their respective owner.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in
systems or equipment intended for surgical implantation, atomic energy control instruments, airplane
or spaceship instrum ents, transportation instruments, traffic signal instruments, com bustion control
instruments, or for other applications intended to support or sustain life. Furthermore, Winbond
products are not intended for applications wherein failure of Winbond products could result or lead to
a situation where in personal injury, death or severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their own
risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 1 - Revision : A01-001
1. GENERAL DESCRIPTION
W94AD6KK / W94AD2KK is a high-speed Low Power double data rate synchronous dynamic
random access memory (LPDDR SDRAM), An access to the LPDDR SDRAM is burst oriented.
Consecutive memory location in one page can be accessed at a burst length of 2, 4, 8 and 16
when a bank and row is selected by an ACTIVE command. Column addresses are automatically
generated by the LPDDR SDRAM internal counter in burst operation. Random column read is also
possible by providing its address at each clock cycle. The multiple bank nature enables
interleaving among internal banks to hide the pre-charging time. By setting programmable Mode
Registers, the system can change burst length, latency cycle, interleave or sequential burst to
maximize its performance. The device supports special low power functions such as Partial Array
Self Refresh (PASR) and Automatic Temperature Compensated Self Ref resh (ATCSR ).
2. FEATURES
• VDD = 1.7~1.95V
• VDDQ = 1.7~1.95V;
• Data width: x16 / x32
• Clock rate: 200MHz (-5),166MHz (-6)
• Standard Self Refresh Mode
• Partial Arra y Self-Refresh(PASR)
• Auto Temperature Compensated Self-Refresh(ATCSR)
• Power Down Mode
• Deep Power Down Mode (DPD Mode)
• Programmable output buffer driver strength
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• Clock Stop capability during idle periods
• Auto Pre-charge option for each burst access
• Double data rate for data output
• Differential clock inputs (CK and
CK
)
• Bidirectional, data strobe (DQS)
•
CAS
Latency: 2 and 3
• Burst Length: 2, 4, 8 and 16
• Burst Type: Sequential or Interleave
• 64 ms Refresh period
• Interface: LVCMOS compatible
• Support KGD(Known Good Die) form
• Operating Temperature Range
Mobile (-30°C ~ 85°C)
Industrial (-40°C ~ 85°C)
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 2 - Revision : A01-001
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ............................................................................................................ 1
2. FEATURES .................................................................................................................................... 1
4. PIN DESCRIPTION........................................................................................................................ 5
4.1 Signal Descriptions .............................................................................................................................. 5
4.2 Addressing Table ................................................................................................................................. 6
5. BLOCK DIAGRAM ........................................................................................................................ 7
5.1 Block Diagram ...................................................................................................................................... 7
6. FUNCTION DESCRIPTION ........................................................................................................... 9
6.1 Initialization .......................................................................................................................................... 9
6.1.1 Initialization Flow Diagram ..........................................................................................................................10
6.1.2 Initialization Waveform Sequence ...............................................................................................................11
6.2 Mode Register Set Operation ............................................................................................................. 11
6.3 Mode Register Definition .................................................................................................................... 12
6.3.1. Burst Length ...............................................................................................................................................12
6.3.2 Burst Definition ............................................................................................................................................13
6.3.3 Burst Type ...................................................................................................................................................14
6.3.4 Read Latency ..............................................................................................................................................14
6.4 Extended Mode Register Description ................................................................................................. 14
6.4.1 Extended Mode Register Definition.............................................................................................................15
6.4.2 Partial Array Self Refresh ............................................................................................................................15
6.4.3 Automatic Temperature Compensated Self Refresh ..................................................................................15
6.4.4 Output Drive Strength .................................................................................................................................15
6.5 Status Register Read ......................................................................................................................... 15
6.5.1 SRR Register Definition ..............................................................................................................................16
6.5.2 Status Register Read Timing Diagram........................................................................................................17
6.5.3 Temperature sensor output function (TQ function) and Refresh Rate ........................................................18
6.6 Commands ........................................................................................................................................ 18
6.6.1 Basic Timing Parameters for Commands ...................................................................................................18
6.6.2 Truth Table - Commands ............................................................................................................................19
6.6.3 Truth Table - DM Operations ......................................................................................................................20
6.6.4 Truth Table - CKE .......................................................................................................................................20
6.6.5 Truth Table - Current State BANKn - Command to BANKn .......................................................................21
6.6.6 Truth Table - Current State BANKn, Command to BANKm ........................................................................22
7. OPERATION ................................................................................................................................ 23
7.1. Deselect ............................................................................................................................................ 23
7.2. No Operation ..................................................................................................................................... 23
7.2.1 NOP Command ...........................................................................................................................................24
7.3 Mode Register Set ............................................................................................................................. 24
7.3.1 Mode Register Set Command .....................................................................................................................24
7.3.2 Mode Register Set Command Timing .........................................................................................................25
7.4. Active ................................................................................................................................................ 25
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 3 - Revision : A01-001
7.4.1 Active Command .........................................................................................................................................25
7.4.2 Bank Activation Command Cycle ................................................................................................................26
7.5. Read ................................................................................................................................................. 26
7.5.1 Read Command ..........................................................................................................................................26
7.5.2 Basic Read Timing Parameters ..................................................................................................................27
7.5.3 Read Burst Showing CAS Latency .............................................................................................................28
7.5.4 Read to Read ..............................................................................................................................................28
7.5.5 Consecutive Read Bursts ............................................................................................................................29
7.5.6 Non-Consecutive Read Bursts ....................................................................................................................29
7.5.7 Random Read Bursts ..................................................................................................................................30
7.5.8 Read Burst Terminate .................................................................................................................................30
7.5.9 Read to Write ..............................................................................................................................................31
7.5.10 Read to Pre-charge ...................................................................................................................................32
7.5.11 Burst Terminate of Read ...........................................................................................................................33
7.6 Write .................................................................................................................................................. 33
7.6.1 Write Command ..........................................................................................................................................33
7.6.2 Basic Write Timing Parameters ...................................................................................................................34
7.6.3 Write Burst (min. and max. tDQSS) ............................................................................................................35
7.6.4 Write to Write ...............................................................................................................................................35
7.6.5 Concatenated Write Bursts .........................................................................................................................36
7.6.6 Non-Consecutive Write Bursts ....................................................................................................................36
7.6.7 Random Write Cycles..................................................................................................................................37
7.6.8 Write to Read ..............................................................................................................................................37
7.6.9 Non-Interrupting Write to Read ...................................................................................................................37
7.6.10 Interrupting Write to Read .........................................................................................................................38
7.6.11 Write to Precharge ....................................................................................................................................38
7.6.12 Non-Interrupting Write to Precharge .........................................................................................................38
7.6.13 Interrupting Write to Precharge .................................................................................................................39
7.7 Precharge .......................................................................................................................................... 39
7.7.1 Precharge Command ..................................................................................................................................39
7.8 Auto Precharge .................................................................................................................................. 40
7.9 Refresh Requirements ....................................................................................................................... 40
7.10 Auto Refresh .................................................................................................................................... 40
7.10.1 Auto Refresh Command ............................................................................................................................40
7.11 Self Referesh ................................................................................................................................... 41
7.11.1 Self Refresh Command .............................................................................................................................41
7.11.2 Auto Refresh Cycles Back-to-Back ...........................................................................................................42
7.11.3 Self Refresh Entry and Exit .......................................................................................................................42
7.12 Power Down ..................................................................................................................................... 43
7.12.1 Power-Down Entry and Exit ......................................................................................................................43
7.13 Deep Power Down ........................................................................................................................... 44
7.13.1 Deep Power-Down Entry and Exit .............................................................................................................44
7.14 Clock Stop........................................................................................................................................ 45
7.14.1 Clock Stop Mode Entry and Exit ...............................................................................................................45
8. ELECTRICAL CHARACTERISTIC.............................................................................................. 46
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 4 - Revision : A01-001
8.1 Absolute Maximum Ratings ................................................................................................................ 46
8.2 Input/Output Capacitance................................................................................................................... 46
8.3 Electrical Characteristics and AC/DC Operating Conditions ............................................................... 47
8.3.1 Electrical Characteristics and AC/DC Operating Conditions ......................................................................47
8.4 IDD Specification Parameters and Test Conditions ............................................................................ 48
8.4.1 IDD Specification and Test Conditions (x16) ..............................................................................................48
8.4.2 IDD Specification and Test Conditions (x32) ..............................................................................................49
8.5 AC Ti mings ........................................................................................................................................ 51
8.5.1 CAS Latency Definition (With CL=3) ...........................................................................................................54
8.5.2 Output Slew Rate Characteristics ...............................................................................................................55
8.5.3 AC Overshoot/Undershoot Specification ....................................................................................................55
8.5.4 AC Overshoot and Undershoot Definition ...................................................................................................55
9. REVISION HISTORY ................................................................................................................... 56
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 5 - Revision : A01-001
4. PIN DESCRIPT ION
4.1 Signal Descriptions
SIGNAL NAME TYPE FUNCTION DESCRIPTION
A [n : 0] Input Address
Provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ/WRITE commands, to
select one location out of the memory array in the respective bank.
The address inputs also provide the opcode during a MODE
REGISTER SET command.
A10 is used for Auto Pre-charge Select.
BA0, BA1 Input Bank Select Define to which bank an ACTIVE, READ, WRITE or PRECHARGE
command is being applied.
DQ0~DQ15 (×16)
DQ0~DQ31 (×32)
I/O Data Input/ Output Data bus: Input / Output.
CS
Input Chip Select
CS
enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when
CS
is
registered HIGH.
CS
provides for external bank selection on systems
with multiple banks.
CS
is considered part of the command code.
RAS
Input Row Address
Strobe
RAS
,
CAS
and
WE
(along with
CS
) define the command being
entered.
CAS
Input Column Address
Strobe Referred to
RAS
.
WE
Input Write Enable Referred to
RAS
.
UDM / LDM(x16);
DM0 to DM3
(x32)
Input Input Mask
Input Data Mask: DM is an input m ask signal for write
data. Input data
is m asked wh en DM is sa m pled HIGH a long with t hat input da ta during
a W RITE acces s. DM is s am pled on both edges of DQS. Although DM
pins are input-only, the DM loading matches the DQ and DQS loading.
x16: LDM: DQ0 - DQ7, UDM: DQ8 – DQ15
x32: DM0: DQ0 - DQ7, DM1: DQ8 – DQ15,
DM2: DQ16 – DQ23, DM3: DQ24 – DQ31
CK /
CK
Input Clock Inputs
CK and
CK
are differential clock inputs.
All address and control input
signals are sampled on the crossing of the positive edge of CK and
negative edge of
CK
.Input and output data is referenced to the
crossing of CK and
CK
(both directions of crossing). Internal clock
signals are derived from CK/
CK
.
CKE Input Clock Enable
CKE HIGH activates, and CKE LOW deactivates internal clock signals,
and device input buffers and output drivers. Taking CKE LOW
provides PRECHARGE, POWER DOWN and SELF REFRESH
operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in
any bank). CKE is synchronous for all functions except for SELF
REFRESH EXIT, which is achieved asynchronously. Input buffers,
excluding CK,
CK
and CKE, are disabled duri ng po wer do wn and
self refresh mode which are contrived for low standby power
consumption.
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 6 - Revision : A01-001
SIGNAL NAME TYPE FUNCTION DESCRIPTION
LDQS, UDQS
(x16);
DQS0~DQS3
(x32)
I/O Data Strobe
Output with read data, input with write data. Edge-aligned with read
data, centered with write data. Used to ca ptur e wr ite da ta.
x16: LDQS: DQ0~DQ7; UDQS: DQ8~DQ15.
x32: DQS0: DQ0~DQ7; DQS1: DQ8~DQ15;
DQS2: DQ16~DQ23; DQS3: DQ24~DQ31.
VDD Supply
Power Power supply for input buffers and internal circuit.
VSS Supply
Ground Ground for input buffers and internal circuit.
VDDQ Supply
Power for I/O Buffer
Power supply separated from VDD, used for output drivers to improve
noise.
VSSQ Supply
Ground for I/O
Buffer Ground for output drivers.
TQ Output
Temperature
sensor output
Asynchro nous , LVC MOS temperature output. Output logic-HIGH state
when device temperature equals or exceeds 85°C. Output logic-LOW
state when de vice temperature is less than 85°C.
(Optional for KGD; defau lt dis ab le)
TPD Input Test Power Down
Asynchronous, LVCMOS Test Power Down for test purposes. TPD
LOW is normal operation.
Taking TPD HIGH asynchronously will place
the die in deep power down mode. The assertion of TPD HIGH must
meet all the initialization and sequencing of DPD mode.
(Optional for KGD; default disable)
NC - No Connect No internal electrical connection is present.
4.2 Addressing Table
ITEM 1Gb
Number of banks 4
Bank address pins BA0,BA1
Auto precharge pin A10/AP
X16
Row addresses A0-A13
Column addresses A0-A9
tREFI(µs) 7.8
Type Full page Reduced page
x32
Row addresses A0-A12 A0-A13
Column addresses A0-A9 A0-A8
tREFI(µs) 7.8
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 7 - Revision : A01-001
5. BLOCK DI AGRAM
5.1 Block Diagram
UDM / LDM (x16)
CK
CKE
CS
RAS
CAS
WE
A10
A0
An
BA0
BA1
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #2
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #0
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #3
DATA CONTROL
CIRCUIT
DQ
BUFFER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #1
DMn
R
O
W
D
E
C
O
R
D
E
R
R
O
W
D
E
C
O
R
D
E
R
R
O
W
D
E
C
O
R
D
E
R
R
O
W
D
E
C
O
R
D
E
R
DQ0 – DQ15 (x16)
DQ0 – DQ31 (x32)
DMn (x32)
UDQS / LDQS (x16)
DQSn (x32)
CK
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 8 - Revision : A01-001
5.2 Simplified State Diagram
ACT =Active EMRS=Ext . Mode Reg.
Set REFSX= Exit Self Refresh
BST = Burst Terminate MRS =Mode Register Set READ =Read w/o Auto Precharge
CKEL= Enter Power-Down PRE =Precharge READA =Read with Auto Precharge
CKEH=Exit Power - Down PREALL=Precharge All Bank WRITE = Write w/o Auto Precharge
DPDS= Enter Deep Power- Down REFA =Auto Refresh WRITEA =Write with Auto Precharge
DPDSX= Exit Deep Power- Down REFS = Enter Self Refresh
Note: Use caution with this diagram . It is indented to provide a floorplan of the possible state transitions and commands to control them,not
all details.In particular situations involving more than one bank are not captured in full detall.
Deep
Power
Down
DPDS
ACT
PRE PRE PRE
READA
READ A
Precharge
PREALL
WRITE A
PRE
WRITE READ
Burst
Stop
Row
Active
Active
Power
Down
Precharge
Power
Down
Auto
Refresh
Idle
All banks
precharged
MRS
EMRS
Self
Refresh
Precharge
All Bank
Power
On
Power
applied
DPDSX
MRS REFA
REFS
REFSX
CKEL
CKEH
CKEH
CKEL
WRITE
WRITEA READA
BST
READ
READA
READ
WRITE READ
WRITE
Automatic Sequence
Command Sequence
SRR
Read
Read
SRR
SRR = Status Register Read
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 9 - Revision : A01-001
6. FUNCTION DESCRIPTION
6.1 Initialization
LPDDR SDRAM must be powered up and initialized in a predefined manner. Operations procedures other than those
specified may result in undefined operation. If there is any interruption to the device power, the initialization routine
should be followed. The steps to be followed for device initialization are listed below.
The Mode Register and Extended Mode Register do not have default values. If they are not programmed during the
initialization sequence, it may lead to unspecified operation. The clock stop feature is not available until the device has
been properly initialized from Step 1 through 11.
Step 1: Provide power, the device core power (VDD) and the device I/O power (VDDQ) must be brought up
simultaneously to prevent device latch-up. Although not required, it is recommended that VDD and VDDQ
are from the same power source. Also Assert and hold Clock Enable (CKE) to a LVCMOS logic high level
Step 2: Once the system has established consistent device power and CKE is driven high, it is safe to apply stable
clock.
Step 3: There must be at least 200μs of valid clocks before any command may be given to the DRAM. Dur ing this
time NOP or DESELECT commands must be issued on the command bus.
Step 4: Issue a PRECHARGE ALL command.
Step 5: Provide NOPs or DESELECT commands for at least tRP time.
Step 6: Issue an AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time.
Issue the second AUTO REFRESH command followed by NOPs or DESELECT command for at least
tRFC time. Note as part of the initialization sequence there must be two Auto Refresh commands issued.
The typical flow is to issue them at Step 6, but they may also be issued between steps 10 and 11.
Step 7: Using the MRS command, program the base mode register. Set the desired operation modes.
Step 8: Provide NOPs or DESELECT commands for at least tMRD time.
Step 9: Us ing the MRS command, program the extended mode register for the desired operating modes. Note the
order of the base and extended mode register programmed is not important.
Step 10: Provide NOP or DESELECT commands for at least tMRD time.
Step 11: The DRAM has been properly initialized and is ready for any valid command.
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 10 - Revision : A01-001
6.1.1 Initializ ation Flow Diagram
1 VDD and VDDQ Ramp: CKE must be held high
2 Apply stable clocks
3 Wait at least 200us with NOP or DESELECT on command bus
4 PRECHARGE ALL
5Assert NOP or DESELCT for t
RP
time
6Issue two AUTO REFRESH commands each followed by
NOP or DESELECT commands for t
RFC
time
7 Configure Mode Register
8Assert NOP or DESELECT for t
MRD
time
9 Configure Extended Mode Register
10 Assert NOP or DESELECT for t
MRD
time
11 LPDDR SDRAM is ready for any valid command
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 11 - Revision : A01-001
6.1.2 Initializati on Wave form Sequence
6.2 Mode Register Set Operation
The Mode Register is used to define the specific mode of operation of the LPDDR SDRAM. This definition includes the
definition of a burst length, a burst type, a CAS latency as shown in the following figure.
The Mode Re gister is progr amm ed via the MODE RE GISTER SET comm and (with BA0=0 an d BA1=0) an d will retain
the stored information until it is reprogrammed, the device goes into Deep Power Down mode, or the device loses
power.
Mode Register bits A0-A2 specify the burst length, A3 the type of burst (sequential or interleave), A4-A6 the CAS
latency. A logic 0 should be programmed to all the undefined addresses bits to ensure future compatibility.
The Mode Re gis ter mus t be l oad ed when all ba nks are idle a nd no bur s ts are in pr ogres s , an d t he c o ntr o ller must wait
the spec ified time t MRD be for e initiatin g an y subseq uent operat ion. Violat ing e ithe r of these re quir em ents will result in
unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 12 - Revision : A01-001
6.3 Mode Register Definition
BA1 BA0 An…A7 (*1) A6 A5 A4 A3 A2 A1 A0 Address Bus
0 0 0 (*2) CAS Latency BT Burst Length Mode Reg.
A6 A5 A4 CAS Latenc y A3 Burst Type A2 A1 A0 Burst Length
0 0 0 Reserved 0 Sequential 0 0 0 Reserved
0 0 1 Reserved 1 Interleave 0 0 1 2
0 1 0 2 0 1 0 4
0 1 1 3 0 1 1 8
1 0 0 Reserved 1 0 0 16
1 0 1 Reserved 1 0 1 Reserved
1 1 0 Reserved 1 1 0 Reserved
1 1 1 Reserved 1 1 1 Reserved
Notes:
1. MSB depends on mobile DDR SDRAM density.
2. A logic 0 should be programmed to all unused / undefined bits to ensure future compatibilit y.
6.3.1. Burst Length
Read and write accesses to the LPDDR SDRAM are burst oriented, with the burst length and burst type being
programmable.
The burst length determines the maximum number of column locations that can be accessed for a given READ or
WRITE command. Burst lengths of 2, 4, or 8 locat ions are available for both the sequential and the interleaved burst
types.
When a READ or WRITE comm and is issued, a block of colum ns equal to the burst length is effectively selected. All
accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is
reached.
The block is uni quel y selec ted b y A1−An when th e bur st len gth is s et to t wo, by A2−An when th e b urst le ngth is s et to
4, by A3−An when the burst length is set to 8 (where An is the most significant column address bit for a given
configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the
block. The programmed burst length applies to both read and write bursts.
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 13 - Revision : A01-001
6.3.2 Burst Definition
BURST
LENGTH
STARTING COLUMN
ADDRESS ORDER OF ACCESSES WITHIN A BURST
(HEXADECIMAL NOTATION)
A3 A2 A1 A0 SEQUENTIAL INTERLEAVED
2 0 0 – 1 0 – 1
1 1 – 0 1 – 0
4
0 0 0 – 1 – 2 – 3 0 – 1 – 2 – 3
0 1 1 – 2 – 3 – 0 1 – 0 – 3 – 2
1 0 2 – 3 – 0 – 1 2 – 3 – 0 – 1
1 1 3 – 0 – 1 – 2 3 – 2 – 1 – 0
8
0 0 0 0 – 1 – 2 – 3 – 4 – 5 – 6 – 7 0 – 1 – 2 – 3 – 4 – 5 – 6 – 7
0 0 1 1 – 2 – 3 – 4 – 5 – 6 – 7 – 0 1 – 0 – 3 – 2 – 5 – 4 – 7 – 6
0 1 0 2 – 3 – 4 – 5 – 6 – 7 – 0 – 1 2 – 3 – 0 – 1 – 6 – 7 – 4 – 5
0 1 1 3 – 4 – 5 – 6 – 7 – 0 – 1 – 2 3 – 2 – 1 – 0 – 7 – 6 – 5 – 4
1 0 0 4 – 5 – 6 – 7 – 0 – 1 – 2 – 3 4 – 5 – 6 – 7 – 0 – 1 – 2 – 3
1 0 1 5 – 6 – 7 – 0 – 1 – 2 – 3 – 4 5 – 4 – 7 – 6 – 1 – 0 – 3 – 2
1 1 0 6 – 7 – 0 – 1 – 2 – 3 – 4 – 5 6 – 7 – 4 – 5 – 2 – 3 – 0 – 1
1 1 1 7 – 0 – 1 – 2 – 3 – 4 – 5 – 6 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0
16
0 0 0 0 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F
0 0 0 1 1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0 1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E
0 0 1 0 2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1 2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D
0 0 1 1 3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2 3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C
0 1 0 0 4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3 4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B
0 1 0 1 5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4 5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A
0 1 1 0 6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5 6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9
0 1 1 1 7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8
1 0 0 0 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7
1 0 0 1 9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6
1 0 1 0 A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5
1 0 1 1 B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A B-A-9-8-F-E-D-C-3-2-1-0-7-6-5-4
1 1 0 0 C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B C-D-E-F-8-9-A-B-4-5-6-7-0-1-2-3
1 1 0 1 D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C D-C-F-E-9-8-B-A-5-4-7-6-1-0-3-2
1 1 1 0 E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D E-F-C-D-A-B-8-9-6-7-4-5-2-3-0-1
1 1 1 1 F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E F-E-D-C-B-A-9-8-7-6-5-4-3-2-1-0
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 14 - Revision : A01-001
Notes:
1. For a burst length of two, A1-An selects the two data element block; A0 selects the first access within the block.
2. For a burst length of four, A2-An selects the four dat a ele ment blo ck; A0-A1 sel ect s the first ac ces s within the block.
3. For a burst length of eight, A3-An selects the eight data element block; A0-A2 selects the first acces s within the block .
4. For the optional burst length of sixteen, A4-An selects the sixteen data element block; A0-A3 selects the first access within the
block.
5. Whenever a boundary of the block is reached within a given sequence, the following access wraps within the block.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for
that burst take place within the block, meaning that the burst will wrap within the block if a boundary is reached.
The block is uniquely selected by A1-An when the burst length is set to two, by A2-An when the burst length is set to 4, by A3-An
when the burst length is set to 8 and A4-An when the burst length is set to 16(where An is the most significant column address
bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the
block. The programmed burst length applies to both read and write bursts.
6.3.3 Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst ty pe and the starting column address, as shown in the previous table.
6.3.4 Read Latency
The READ latency is the delay between the registration of a READ command and the availability of the fir st piece of
output data. The latency should be set to 2 or 3 clocks.
If a READ command is regi stered at a cloc k edge n an d the lat ency is 3 c loc ks , the fir st data e lem ent will be va lid at n
+ 2 tCK + t AC. If a READ command is r egist ered at a clock edge n and the latency is 2 c locks, the f irst data elem ent
will be valid at n + tCK + tAC.
6.4 Extended Mode Register Description
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional
functions include output drive strength selection and Partial Array Self Refresh (PASR). PASR is effective in Self
Refresh mode only.
The Exten ded Mod e Reg ister is progr amm ed v ia the MOD E REGISTER SET comm and (with BA1=1 and BA0=0) and
will retain the stored information until it is reprogramm ed, the device is put in Deep Power Down m ode, or the device
loses power.
The Extended Mode R eg ist er must be loaded whe n a ll banks are idl e and no bur sts are in progr ess, and the contr oller
must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements
will result in unspecified operation.
Address bits A0-A2 specify PASR, A5-A7 the Driver Strength. A logic 0 should be programmed to all the undefined
addresses bits to ensure future compatibility.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 15 - Revision : A01-001
6.4.1 Extended Mode Regi ster Definition
BA1 BA0 An…A8 (*1) A7 ~ A5 A4 A3 A2 A1 A0 Address Bus
1 0 0 (*2) DS Reserved PASR Extended Mode Reg.
A7 A6 A5 Dri ve S tr ength A2 A1 A0 PASR
0 0 0 Full Strength Driver (default) 0 0 0 All Banks
0 0 1 Half Strength Driver 0 0 1 1/2 array (BA1=0)
0 1 0 Quarter Strength Driver 0 1 0 1/4 array (BA1=BA0=0)
0 1 1 Octant Strength Driver 0 1 1 Reserved
1 0 0 Three-Quarters Strength Driver 1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
Notes:
1. MSB depends on LPDDR SDRAM density.
2. A logic 0 should be programmed to all unused / undefined bits to ensure future compatibilit y.
6.4.2 Partial Array Self Refresh
With partial array self refresh (PASR), the self refresh may be restricted to a variable portion of the total array. The
whole array (defau lt), 1/2 a rra y, or 1/4 arr a y could be select ed. Dat a outs ide th e def ined area wi ll be lost. Addres s bits
A0 to A2 are used to set PASR.
6.4.3 Automatic Temperature Compensated Self Refresh
The device has an Aut omatic T em per ature C ompensated Self Ref r es h f eatur e. It automaticall y adjus ts the refr esh r ate
based on the device temperature without any register update needed.
6.4.4 Output Drive Strength
The drive strength could be set to full, half, quarter, octant, and three-quarter strength via address bits A5, A6 and A7.
The half drive strength option is intended for lighter loads or point-to-point environments.
6.5 Status Register Read
Status Register Read (SRR) is an optional feature in JEDEC, and it is implemented in this device. With SRR, a
method is defined to read registers from the device. The encoding for an SRR comm and is the same as a MRS with
BA[1:0]=”01”. The address pins (A[n:0]) encode which register is to be read. Currently only one register is defined at
A[n:0]=0. The sequence to perform an SRR command is as follows:
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 16 - Revision : A01-001
All reads/writes must be completed
All banks must be closed
MRS with BA=01 is issue d ( SRR)
Wait tSRR
Read issued to an y bank /page
CAS latency cycles later the device returns the registers data as it would a normal read
The next command to the device can be issued tSRC after the Read command was issued.
The burst length for the SRR read is always fixed to length 2.
6.5.1 SRR Regi ster Definition
Default: (A[n:0] = 0)
x ~ DQ16 DQ15 ~ DQ13 DQ12
DQ11
DQ10 ~ DQ8 DQ7 ~ DQ4 DQ3 ~ DQ0 Rising Edge of DQ Bus
Reserved Density DT DW Refresh Rate
Revision
Identification Manufacturer
Identification SRR Register 0
DQ15
DQ14 DQ13
Density DQ3 DQ2
DQ1 DQ0 Manufacturer
0 0 0 128 1 0 0 0 Winbond
0 0 1 256
0 1 0 512
0 1 1 1024 DQ7:4 Revision ID
1 0 0 2048
(See Note1)
1 0 1 Reserved
Note1: The manufacture's revisi on number starts at
'0000' and increments by '0001' each time a change in
the manufacturer's specification(AC timi ngs, or feature
set), IBIS(pull up or pull down characterist ics), or process
occurs.
1 1 0 Reserved
1 1 1 64
DQ12 Device type
DQ10
DQ9 DQ8 Refresh Rate
0 LPDDR
0 0 0 Reserved
1 Reserved
0 0 1 Reserved
0 1 0 Reserved
0 1 1 Reserved
DQ11 Device width
1 0 0 1
0 16bit
1 0 1 0.5
1 32bit
1 1 0 0.25
1 1 1 Reserved
Notes:
2. The refresh rate multiplier is based on the memory's temperature sensor.
3. Required average periodic refresh i nterval = tREFI x multipli er
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 17 - Revision : A01-001
6.5.2 Status Regi ster Read Timing Diag ram
CMD CMD
NOP
NOP
NOPNOP
NOP MRS READ
CL=3
0
0 1
tRP tSRR tSRC
DQ:Reg out
=Don’t Care
PCHA, or PCH
CK
CK
Command
BA1,BA0
An~A0
DQS
DQ
Notes :
1.SRR can only be issued after power-up sequence is complete.
2.SRR can only be issued with all banks precharged.
3.SRR CL is unchanged from value in the mode register.
4.SRR BL is fixed at 2.
5.tSRR = 2 (min).
6.tSRC = CL + 1; (min time between read to next valid command)
7.No commands other than NOP and DES are allowed between the SRR and the READ.
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 18 - Revision : A01-001
6.5.3 Temperature sensor output function (TQ function) and Refresh Rate
The LPDDR SDRAM device is buil t w ith a temperature sensor for sensing the operating temperature inside the device.
The LPDDR SDRAM device is also built with temperature sensor output logic to drive the temperature sensor output
signal (TQ pin).
The tem perature s ensor output logic is d efault dis abled. T he temper ature sensor output log ic is able t o be enab led by
fuse at chip probing test stage only. If the tem perature sensor output logic is not enabled by fuse at chip probing test
stage, the TQ pin output will be always staying at Hi-Z status.
If the tem perature sensor o utput logic is enable d by fuse at chip probing t est stage, duri ng device initial ization the TQ
signal ou tput wi ll be inv alid unt il tT Q aft er the fir st MRS c omm and. Follo wing tT Q, the T Q signal w ill outp ut lo gic-HIGH
when the device temperature is greater than, or equal to, 85°C, and logic-LOW when the device temperature is less
than 85°C. There is no high-impedance state for this outp ut signal. The T Q output signal activates even during clock
stop, power down, and self refresh modes..
W hen TQ output is logic-HI GH, tREF wil l be shor tene d to 16m s . Additi onall y, AC par am eters s hall be d e-rated to 20%
and DC parameters shall not be guaranteed. Meanwhile, SRR[10:8] will reflect the updated status if refresh rate.
It is recommended that the customer who is interested with TQ function enabled should instruct Winbond to enable the
TQ function by fuse at chip probing test stage when doing part ordering.
6.6 Commands
All commands (address and control signals) are registered on the positive edge of clock (crossing of CK going high
and
CK
going low).
6.6.1 Basic Timing Parameters for Commands
CK
CK
Input Valid Valid Valid
t
CL
t
CH
t
CK
t
IS
t
IH
: Don't Care
NOTE: Input = A0–An, BA0, BA1, CKE, CS, RAS, CAS, WE;
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 19 - Revision : A01-001
6.6.2 Truth Table - Commands
NAME (FUNCTION)
CS
RAS
CAS
WE
BA A10/AP ADDR
NOTES
DESELECT (NOP)
H X X X X X X 2
NO OPERATION (NOP)
L H H H X X X 2
AC
TIVE (Select Bank and activate row) L L H H Valid Row Row
READ (Select
bank and column and start read burst) L H L H Valid L Col
READ with AP (Read Burst with Auto
Precharge) L H L H Valid H Col 3
WRITE (Select bank and column and start write burst)
L H L L Valid L Col
WRITE with AP (Write Burst with Auto
Precharge) L H L L Valid H Col 3
BURST TERMINATE or enter DEEP POWER DOWN
L H H L X X X 4, 5
PRECHARGE (Deactivate Row in selected bank)
L L H L Valid L X 6
PRECHAR
GE ALL (Deactivate rows in all banks) L L H L X H X 6
AUTO REFRESH or enter SELF REFRESH
L L L H X X X 7, 8, 9
MODE REGISTER SET
L L L L Valid Op-code 10
Notes:
1. All states and sequences not shown are illegal or reserved.
2. DESELECT and NOP are functionally interchangeable.
3. Auto precharge is non-persistent. A10 High enables Auto precharge, while A10 Low disables Auto precharge.
4. Burst Terminate applies to only Read bursts with Autoprecharge disabled. This command is undefined and should not be
used for Read with Auto precharge enabled, and for Wri te bursts.
5. This command is BURST TERMINATE if CKE is High and DEEP POWER DOWN entry if CKE is Low.
6. If A10 is low, bank address determines which bank is to be precharged. If A10 is high, all banks are precharged and
BA0~BA1 are don’t care.
7. This command is AUTO REFRESH if CKE is High and SELF REFRESH if CKE is low.
8. All address inputs and I/O are ‘don’t care’ except for CKE. Internal refresh counters control bank and row addressing.
9. All banks must be precharged before issuing an AUTO-REFRESH or SELF REFRESH command.
10. BA0 and BA1 value select between MRS and EMRS.
11. CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN.
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 20 - Revision : A01-001
6.6.3 Truth Table - DM Operations
FUNCTION DM DQ NOTES
Write Enable L Valid 1
Write Inhibit H X 1
Notes:Used to mask write data, provided coincident with the corresponding data.
6.6.4 Truth Table - CKE
CKEn-1 CKEn CURRENT STATE COMMANDn ACTIONn NOTES
L L Power D own X Maintain Power Down
L L Self Refresh X Maintain Self Refresh
L L Deep Power Down X Maintain Deep Power Down
L H P ower D own NOP or DESELECT Exit Power Down 5, 6, 9
L H Self Refresh NOP or DESELECT Exit Self Refresh 5, 7, 10
L H Deep Power Down NOP or DESELECT Exit Deep Power Down 5, 8
H L All Banks Idle NOP or DESELECT Precharge Power Down Entry 5
H L Bank(s) Active NOP or DESELECT Active Power Down Entry 5
H L All Banks Idle AUTO REFRESH Self Refresh Entry
H L All Banks Idle BURST TERMINATE Enter Deep Power Down
H H See the other Truth Tables
Notes:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of LPDDR immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is the result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. DESELECT and NOP are functionally interchangeable.
6. Power Down exit time (tXP) should elapse before a command other than NOP or DESELECT is issued.
7. SELF REFRESH exit time (tXSR) should elapse before a command other than NOP or DESELECT is issued.
8. The Deep Power-Down exit procedure must be followed as discussed in the Deep Power-Down section of the Functional
Description.
9. The clock mus t toggle at least once during the tXP period.
10. The clock must toggle at least once during the tXSR time.
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 21 - Revision : A01-001
6.6.5 Truth Table - Current State BANKn - Command to BANKn
CURRENT STATE
CS
RAS
CAS
WE
COMMAND ACTION NOTES
Any H X X X DESELECT NOP or Continue previous operation
L H H H No Operation NOP or Continue previous operation
Idle
L L H H ACTIVE Select and activate row
L L L H AUTO REFRESH Auto refresh 10
L L L L MRS Mode register set 10
Row Active
L H L H READ Select column & start read burst
L H L L WRITE Select column & start write burst
L L H L PRECHARGE Deactivate row in bank (or banks) 4
Read (Auto precharge
Disabled)
L H L H READ Select column & start new read burs t 5, 6
L H L L WRITE Select column & start write burst 5, 6, 13
L L H L PRECHARGE Truncate read burst, start precharge
L H H L BURST
TERMINATE Burst terminate 11
Write (Auto precharge
Disabled)
L H L H READ Select column & start read burst 5, 6, 12
L H L L WRITE Select column & start new write burst 5, 6
L L H L PRECHARGE Truncate write burst & start precharge 12
Notes:
1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self
Refresh or Power Down.
2. DESELECT and NOP are functionally interchangeable.
3. All states and sequences not shown are illegal or reserved.
4. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for
precharging.
5. A command other than NOP should not be issued to the same bank while a READ or WRITE burst with Auto Precharge is
enabled.
6. The new Read or Write command could be Auto Prechrge e nable d or Auto Pr ech arge dis abled.
7. Current State Definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register
accesses ar e in progress.
Read: A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
8. The following states must not be interrupted by a command issued to the same bank. DESEDECT or NOP commands or
allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable
commands to the other bank are determined by its current state and this table, and according to next table.
Precharging: Starts with the registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank
will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will
be in the ‘row active’ state.
Read with AP Enabled: Starts with the registration of the READ command with Auto Precharge enabled and ends when tRP
has been met. Once tRP has been met, the bank will be in the idle state.
Write with AP Enabled: Starts with registration of a W RITE command with Auto Precharge enabled and ends when tRP has
been met. Once tRP is met, the bank will be in the idle state.
9. The following states must not be interrupted by any executable command; DESEDECT or NOP commands must be applied
to each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC is met. Once tRFC is met, the
LPDDR will be in an ‘all banks idle’ state.
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 22 - Revision : A01-001
Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met.
Once tMRD is met, the LPDDR will be in an ‘all banks idle’ state.
Precharging All: Starts with the registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met,
the bank will be in the idle state.
10. Not bank-specific; requires that all banks are idle and no bursts are in progress.
11. Not bank-specific. BURST TERMINATE affects the most recent READ burst, regardless of bank.
12. Requires appropriate DM masking.
13. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURS T TE R MI N ATE mus t be used
to end the READ prior to asserting a WRITE command.
6.6.6 Truth Table - Current S tate BANKn , Command to B ANKm
CURRENT
STATE
CS
RAS
CAS
WE
COMMAND ACTION NOTES
Any H X
X
X
DESELECT NOP or Continue previous Operation
L H
H
H
NOP NOP or Continue previous Operation
Idle X X
X
X
ANY Any command allowed to bank m
Row Activating,
Active, or
Precharging
L L
H
H
ACTIVE Select and activate row
L H
L
H
READ Select column & start read burst 8
L H
L
L
WRITE Select column & start write burst 8
L L
H
L
PRECHARGE Precharge
Read with Auto
Precharge
disabled
L L
H
H
ACTIVE Select and activate row
L H
L
H
READ Select column & start new read burst 8
L H
L
L
WRITE Select column & start write burst 8,10
L L
H
L
PRECHARGE Precharge
Write with Auto
Precharge
disabled
L L
H
H
ACTIVE Select and activate row
L H
L
H
READ Select column & start read burst 8, 9
L H
L
L
WRITE Select column & start new write burst 8
L L
H
L
PRECHARGE Precharge
Read with Auto
Precharge
L L
H
H
ACTIVE Select and activate row
L H
L
H
READ Select column & start new read burst 5, 8
L H
L
L
WRITE Select column & start write burst 5, 8, 10
L L
H
L
PRECHARGE Precharge
Write with Auto
Precharge
L L
H
H
ACTIVE Select and activate row
L H
L
H
READ Select column & start read burst 5, 8
L H
L
L
WRITE Select column & start new write burst 5, 8
L L
H
L
PRECHARGE Precharge
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 23 - Revision : A01-001
Notes:
1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self
Refresh or Power Down.
2. DESELECT and NOP are functionally interchangeable.
3. All states and sequences not shown are illegal or reserved.
4. Current State Definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register
accesses ar e in progress.
Read: A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
5. Read with AP enabled and Write with AP enabled: The read with Auto Precharge enabled or Write with Auto Precharge
enabled states can be broken into two parts: the access period and the precharge period. For Read with AP, the precharge
period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible
PRECHARGE command that still accesses all the data in the burst. For Write with Auto precharge, the precharge period
begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of
the command and ends where the precharge period (or tRP) begins. During the precharge period, of the Read with Auto
Precharge enabled or Write with Auto Precharge enabled states, ACTIVE, PRECHARGE, READ, and WRITE commands to
the other bank may be applied; during the access period, only ACTIVE and PRECHARGE commands to the other banks may
be applied. In either case, all other related limitations apply (e.g. contention between READ data and WRITE data must be
avoided).
6. AUTO REFRESH, SELF REFRESH, and MODE REGISTER SET commands may only be issued when all bank are idle.
7. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
8. READs or WRITEs listed in the Command column include READs and WRITEs with Auto Precharge enabled and READs
and WRITEs with Auto Precharge disabled.
9. Requires appropriate DM masking.
10. A W RITE command may be applied after the completion of data output, otherwise a BURST TERMINATE command must be
issued to end the READ prior to asserting a WRITE command.
7. OPERATION
7.1. Deselect
The DESELECT function (
CS
= high) prevents new commands from being executed by the LPDDR SDRAM. The
LPDDR SDRAM is effectively deselected. O pera tio ns already in progress are not a ff ec ted.
7.2. No Operation
The NO OPERATION (NOP) command is used to perform a NOP to a LPDDR SDRAM that is selected (
CS
=Low).
This prevents unwanted commands from being registered during idle or wait states. Operations already in progress
are not affected.
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 24 - Revision : A01-001
7.2.1 NOP Command
= Don't Care
(High)
CK
CK
CKE
CS
RAS
CAS
WE
A0-An
BA0,BA1
7.3 Mode Register Set
The Mode Register an d the Exte nded Mode R egister are loa ded via the a ddress inp uts. The MOD E REGIST ER SET
command can only be issued when all banks are idle and no bursts are in progress, and a subsequent executable
command cannot be issued until tMRD is met.
7.3.1 Mode Register Set Command
= Don't Care
(High)
CK
CK
CKE
CS
RAS
CAS
WE
A0-An
BA0,BA1
Code
Code
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 25 - Revision : A01-001
7.3.2 Mode Regi ster Se t Comman d Timing
CK
CK
Command MRS
: Don't Care
NOTE:Code=Mode Register / Extended Mode Register selection
(BA0,BA1)and op-code (A0-An)
Code Valid
ValidNOP
tMRD
Address
7.4. Active
Before an y READ or WRITE commands can be issued to a bank in the LPDDR SDRAM, a row in that bank must be
opened. T his is accom plished b y the ACTIVE com mand: B A0 and BA1 se lect the bank , and the addr ess inpu ts select
the row to be activated. More than one bank can be active at any time.
Once a row is open, a READ or WRITE command could be issued to that row, subject to the tRCD specification.
A subs equ ent A CTIVE com mand to anot her row in t he s ame bank can only be iss ued af ter the pr e vious r o w has been
closed. The minimum time interval between two successive ACTIVE commands on the same bank is defined by tRC.
7.4.1 Active Command
= Don't Care
(High)
CK
CK
CKE
CS
RAS
CAS
WE
A0-An
BA0,BA1
RA
BA
BA=BANK Address, RA=Row
Address
A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results
in a reduction of total row-access overh ead. The minimum time interval between two successive ACT IVE commands
on different banks is defined by tRRD.
The row remains active until a PRECHARGE command (or READ or WRITE command with Auto Precharge) is issued
to the bank.
A PRECHARGE (or READ with Auto Precharge or Write with Auto Precharge) command must be issued before
opening a different row in the same bank.
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 26 - Revision : A01-001
7.4.2 Ban k Activation Co mmand Cy cle
NOPNOPNOPACT ACT NOP RD/WR
Row Row Col
BA x BA y BA y
tRCD
tRRD
= Don't Care
CK
CK
Command
A0-An
BA0,BA1
7.5. Read
The READ command is used to initiate a burst read access to an active row, with a burst length as set in the Mode
Register . BA0 and BA1 selec t the bank , and the a ddress inputs select th e starting c olumn locat ion. The value of A1 0
determines whether or not Auto Pre-charge is used. If Auto Pre-charge is selected, the row being accessed will be
pre-charged at the end of the read burst; if Auto Pre-charge is not selected, the row will remain open for subsequent
accesses.
7.5.1 Read Command
= Don't Care
(High)
CK
CK
CKE
CS
RAS
CAS
WE
A0-An CA
AP
BA=BANK Address CA=Coulmn Address AP=Auto
Precharge
BABA0,BA1
A10
Enable AP
Disable AP
The basic Read timing parameters for DQs are shown in following figure; they apply to all Read operati ons .
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 27 - Revision : A01-001
7.5.2 Basic Read Timing Parameters
CK
CK
tDQSQmax
tAC
tLZ tQH tQH
tHZ
DO n+3DO n+2DO n+1DO n
t
RPRE tRPST
tDQSCKtDQSCK
tDQSQmax
tAC
tLZ tQH tQH
tHZ
DO n+3DO n+2DO n+1DO n
t
RPRE tRPST
tDQSCK
tDQSCK
= Don,t Care
1)DO n=Data Out from column n
2)All DQ are vaild tAC after the CK edge.
All DQ are valid tDQSQ after the DQS edge, regardless of tAC
DQS
DQ
DQS
DQ
tCK
tACmax
tACmin
tCK tCH tCL
During Rea d bur s ts, D QS i s drive n by the LPDDR SD RAM a lo ng w ith t he o utpu t data. The init ia l Lo w s tate o f the DQ S
is known as the read prea mble; the Lo w state coincid ent with last data-out element is known as the r ead post-amble.
The f irst data-out elem ent is edge alig ned with the f irst rising edge of DQS and t he successive data-out ele ments are
edge aligned to successive edges of DQS. This is shown in following figure with a CAS latency of 2 and 3.
Upon completion of a read burst, assuming no other READ command has been initiated, the DQs will go to High-Z.
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 28 - Revision : A01-001
7.5.3 Read Bur st Showing CAS Latency
CL=2
DO n
DO n
= Don't Care
BA Col n
READ NOP NOP NOP NOP NOP
CK
CK
Command
Address
DQS
DQ
DQS
DQ
1)DO n=Data Out from column n
2)BA,Col n =Bank A,Column n
3)Burst Length=4;3 subsequent elements of Data Out appear inthe programmed order following DO n
4)Shown with nominal tAC, tDQSCK and tDQSQ
CL=3
7.5.4 Read to Read
Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the
new burst follows either the last element of a completed burst or the last desired element of a longer burst that is being
truncated. The new READ command should be issued X cycles after the first READ command, where X equals the
number of desired data-out element pairs (pairs are required by the 2n-prefetch architecture). This is shown in
following figure.
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 29 - Revision : A01-001
7.5.5 Consecutive Read Bursts
CL=2
DO n
DO n
= Don't Care
BA,Coln
READ NOP READ NOP NOP NOP
CK
CK
Command
Address
DQS
DQ
DQS
DQ
1) DO n (or b)=Data Out from column n (or column b)
2) Burst Length=4,8 or 16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts the first)
3) Read bursts are to an active row in the bank
4) Shown with nominal tAC, tDQSCK and tDQSQ
BA,Colb
CL=3
DO b
DO b
7.5.6 Non-Con secutiv e Read Bur sts
A READ com mand can be initia ted on any clock cycle following a pre vious READ c omm and. Non-consecut ive Reads
are shown in following figure.
CL=2
DO n
DO n
= Don't Care
BA,Col n
READ NOP NOP READ NOP NOP
CK
CK
Command
Address
DQS
DQ
DQS
DQ
1) DO n (or b) =Data Out from column n (or column b)
2) BA,Col n (b) =Bank A,Column n (b)
3) Burst Length=4; 3 subsequent elements of Data Out appear in the programmed order following DO
n (b)
4) Shown with nominal tAC, tDQSCK and tDQSQ
DO b
CL=3
BA,Col b
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 30 - Revision : A01-001
7.5.7 Random Read Bursts
Full-speed random read accesses within a page or pages can be performed as shown in following figure.
CL=2
DO n
DO n
= Don't Care
BA,Col n
READ READ NOP NOP
CK
CK
Command
Address
DQS
DQ
DQS
DQ
1) DO n ,etc. = Data Out from column n, etc.
n
I
, x
I
, etc. = Data Out elements, according to the programmed burst order
2) BA, Col n = Bank A, Column n
3) Burst Length=2,4,8 or 16 in cases shown (if burst of 4,8 or 16, the burst is interrupted)
4) Reads are to active rows in any banks
BA,Col b
CL=3
BA,Col x
READ READ
BA,Col g
DO n
I
DO x
I
DO x DO b DO gDO b
I
DO g
I
DO b
I
DO bDO x
I
DO xDO n
I
7.5.8 Read Burst Terminate
Data f rom any READ burst ma y be truncate d with a BURST TERMIN ATE command, as shown in figure. T he BURST
TERMINAT E latenc y is eq ual to the read (CAS) latency, i.e., the BURST T ERMINATE comm and should be issued X
cycles after the READ command where X equals the desired data-out element pairs.
CL=2
= Don't Care
BA,Col n
READ NOP NOP
CK
CK
Command
Address
DQS
DQ
DQS
DQ
1) DO n = Data Out from column n
2) BA,Col n = Bank A, Column n
3) Cases shown are bursts of 4,8 or 16 terminated after 2 data elements.
4) Shown with nominal tAC, tDQSCK and tDQSQ
CL=3
BST NOPNOP
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 31 - Revision : A01-001
7.5.9 Read to Write
Data from READ burst must be completed or truncated before a subsequent WRITE command can be issued. If
truncati on is nec es sary, the BUR ST TERMINATE c om mand must be used, as s h o wn in following figure f or the c as e of
nominal tDQSS
CL=2
BA,Col n
READ NOP NOP
CK
CK
Command
Address
DQS
DQ
DM
1) DO n = Data Out from column n; DI b= Data In to column b
2) Burst length = 4, 8 or 16 in the cases shown; If the burst length is 2, the BST command can be omitted
3) Shown with nominal tAC, tDQSCK and tDQSQ
BST WRITE
NOP
= Don't Care
BA,Col n
READ WRITE NOPBST NOP
NOP
BA,Col b
BA,Col b
t
DQSS
DO n
CL=3
DQS
DQ
DM
DO n
Command
Address
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 32 - Revision : A01-001
7.5.10 Read to Pre-charge
A Read burst may be followed by or truncated with a PRECHARG E command to the sam e bank (provided Auto Pre-
charge was not ac tivated). The PRECHARG E comm and should be issued X c ycles after the READ command, wh ere
X equal the number of desired data-out element pairs. This is shown in following figure. Following the PRECHARGE
comm and, a subsequ ent comm and to the sam e bank cannot b e issued unt il tRP is met. Note that part of the row pre-
charge time is hidden during the access of the last data-out elements.
In the case of a Read being executed to completion, a PRECHARGE command issued at the optimum time (as
described above) provides the same operation that would result from Read burst with Auto Pre-charge enabled. The
disadvantage of the PRECHARGE command is that it requires that the command and address buses be a vailable at
the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to
truncate burs ts .
1) DO n=Data Out from column n
2) Cases shown are either uninterrupted of 4, or interrupted bursts of 8 or 16
3) Shown with nominal tAC,tDQSCK and tDQSQ
4) Precharge may be applied at (BL/2) tCK after the READ command.
5) Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks.
6) The ACTIVE command may be applied if tRC has been met.
CL=2
DO n
DO n
= Don't Care
BA,Col n
READ NOP PRE NOP NOP ACT
CK
CK
Command
Address
DQS
DQ
DQS
DQ
CL=3
Bank
(a or all)
BA,Row
tRP
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 33 - Revision : A01-001
7.5.11 Burst Terminate of Read
The BURST TERMINATE command is used to truncate read bursts (with Auto Pre-charge disabled). The most
recently registered READ command prior to the BURST TERMINATE command will be truncated. Note that the
BURST TERMINATE command is not bank specific.
This comm and should not be used to terminate write bursts .
(High)
CK
CK
CKE
CS
RAS
CAS
WE
A0-An
BA0,BA1
= Don't Care
7.6 Write
The W RITE command is used to initiate a burst write access to an active ro w, with a burst length as set in the Mode
Register. BA0 and BA1 select the bank, and the addr ess inputs select th e starting c olumn locat ion. The v alue of A10
determines whether or not Auto Pre-charge is used. If Auto Pre-charge is selected, the row being accessed will be
pre-charged at the end of the write burst; if Auto Pre-charge is not selected, t he row will remain open for subsequent
accesses.
7.6.1 Write Command
= Don't Care
(High)
CK
CK
CKE
CS
RAS
CAS
WE
A0-An CA
AP
BA=BANK Address
CA=Coulmn Address
AP=Auto Precharge
BA
BA0,BA1
A10
Enable AP
Disable AP
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 34 - Revision : A01-001
7.6.2 Basic Write Timing Parameters
Basic Write timing parameters for DQs are shown in figure below; they apply to all Write operations.
Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing
coincident with the data. If a given DM signal is registered Low, the corresponding data will be written to the memory; if
the DM si gna l is reg is tered High, the corres po nd ing da ta i npu ts will be ignore d, an d a wr ite will n ot b e executed t o th at
byte / column location.
DI
n
DI
n
tCK tCH tCL
tDSH
tDSH
tDQSH
tDQSS
tWPRES
tWPRE
tDS
tDH tDQSL
tWPST
CK
CK
DQS
DQS
DQ, DM
Case 1:
tDQSS =
min
Case 2:
tDQSS =
max
tDH
tDS
tWPRES
tWPRE
tDQSH
tDQSS
tDSS
tDQSL
tDSS
tWPST
= Don't Care
1) DI n=Data In for column n
2) 3 subsequent elements of Data In are applied in the programmed order following DI n.
3) tDQSS: each rising edge of DQS must fall within the +/-25% window of the corresponding positive
clock edge.
DQ, DM
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 35 - Revision : A01-001
7.6.3 Write Burst (min. and max. tDQSS)
During Write bursts, the first valid data-in element will be registered on the first rising edge of DQS following the
WRITE command, and the subsequent data elements will be registered on successive edges of DQS. T he Low state
of DQS between the WRITE command and the first rising edge is called the write preamble, and the Low state on
DQS following the last data-in element is called the write post-amble.
The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a
relatively wide range - from 75% to 125% of a clock cycle. Following figure shows the two extremes of tDQSS for a
burst of 4, upon com pletion of a burst, assum ing no ot her comm ands have been initiated, the DQs will rem ain high-Z
and any additio na l input data will be ignored.
BA,Col b
WRITE NOP NOP
CK
CK
Command
Address
1) DI b = Data In to column b.
2) 3 subsequent elements of Data In are applied i nthe programmed order following DI b.
3) A non-interrupted burst of 4 is shown.
4) A10 is LOW with the WRITE command (Auto Precharge is disabled)
NOP NOPNOP
= Don't Care
DQS
DQ
DM
DQS
DQ
DM
tDQSSmin
tDQSSmax
7.6.4 Write to Write
Data for an y WRITE burs t may be c onc at ena ted with or tr uncated w ith a subs eq uent WRIT E command. In either c ase,
a continuo us flow of in put data, can b e maintained. T he new W RITE comm and can be is sued on an y pos itive edg e of
the clock following the pre vi ous W RITE com m and.
The first data-in element from the new burst is applied after either the last element of a completed burst or the last
desired data elem ent of a longer burs t whic h is being tr uncated. The ne w WRIT E command shoul d b e is s u ed X cyc les
after the first WRITE command, where X equals the number of desired data-in element pairs.
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 36 - Revision : A01-001
7.6.5 Concat enated Write Bursts
An example of concatenated write bursts is shown in figure below.
BA,Col b
WRITE NOP NOP
CK
CK
Command
Address
1) DI b (n)= Data in to column b (column n)
2)3 subsequent elements of Data In are applied in the programmed order following DI b.
3 subsequent elements of Data In are applied in the programmed order following DI n.
3) Non-interrupted bursts of 4 are shown.
4) Each WRITE command may be to any active bank
NOP NOPWRITE
= Don't Care
DQS
DQ
DM
DQS
DQ
DM
t
DQSSmin
BA,Col n
t
DQSSmax
DI b
DI b
DI n
DI n
7.6.6 Non-Consecutive Write Bursts
An example of non-consecutive write bursts is shown in figure below.
BA,Col n
BA,Col b
WRITE NOP NOP
CK
CK
Command
Address
1) Dl b (n)= Data in to column b (or column n)
2) 3 subsequent elements of Data In are applied in the programmed order following DI b.
3 subsequent elements of Data In are applied in the programmed order following DI n.
3) Non-interrupted bursts of 4 are shown.
4) Each WRITE command may be to any active bank and may be to the same or different devices.
NOP NOP WRITE
= Don't Care
DQS
DQ
DM
t
DQSSmax
BA,Col n
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 37 - Revision : A01-001
7.6.7 Random Write Cycles
Full-speed random write accesses within a page or pages can be performed as shown in figure below.
BA,Col n
BA,Col b
WRITE WRITE NOP
CK
CK
Command
Address
1) Dl b etc.= Data in to column b, etc.;
b’, etc.= the next Data In following Dl b, etc. according to the programmed burst order
2) Programmed burst length = 2, 4, 8 or 16 in cases shown. If burst of 4,8 or 16, burst would be truncated
3) Each WRITE command may be to any active bank and may be to the same or different devices.
WRITE WRITE WRITE
= Don't Care
DQS
DQ
DM
t
DQSSmax
BA,Col aBA,Col x BA,Col n BA,Col g
Di b Di b’ Di x Di x’ Di n Di n’ Di a Di a’
7.6.8 Write to Read
Data for any Write burst may be followed by a subsequent READ command.
7.6.9 Non-Inte rrupting Write to Read
To follow a Write without truncating the write burst, tWTR should be met as shown in the figure below.
BA,Col b
WRITE NOP NOP
CK
CK
Command
Address
1) Dl b = Data in to column b
3 subsequent elements of Data In are applied in the programmed order following DI b.
2) A non-interrupted burst of 4 is shown.
3) tWTR is referenced from the positive clock edge after the last Data In pair.
4) A10 is LOW with the WRITE command (Auto Precharge is disabled)
5) The READ and WRITE commands are to the same device but not necessarily to the same bank.
NOP NOP READ
= Don't Care
DQS
DQ
DM
tDQSSmax
BA,Col n
tWTR CL=3
DI b
NOP
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 38 - Revision : A01-001
7.6.10 Inter rupting Write to Read
Data for any W rite burst may be truncated b y a subsequen t READ com mand as shown in the figure below. Note that
the onl y data-in pair s that are reg istered prior to the tWTR per iod are writte n to the inter nal array, and any subsequ ent
data-in must be masked with DM.
BA,Col n
BA,Col b
WRITE NOP NOP
CK
CK
Command
Address
1) Dl b = Data in to column b. DO n=Data out from column n.
2) An interrupted burst of 4 is shown, 2 data elements are written.
3 subsequent elements of Data In are applied in the programmed order following DI b.
3) tWTR is referenced from the positive clock edge after the last Data In pair.
4)A10 is LOW with the WRITE command (Auto Precharge is disabled)
5) The READ and WRITE commands are to the same device but not necessarily to the same bank.
NOP NOP READ
= Don't Care
DQS
DQ
DM
t
DQSSmax
BA,Col n
t
WTR
CL=3
DI b DO n
NOP
7.6.11 Write to Precharge
Data for any WRITE burst may be followed by a subsequent PRECHARGE command to the same bank (provided
Auto Precharge was not activated). To follow a WRITE without truncating the WRITE burst, tWR should be met as
shown in the figure below.
7.6.12 Non-Inte rrupting Wri te to Precha rge
BA,Col nBA,Col b
WRITE NOP PRE
CK
CK
Command
Address
1) Dl b = Data in to column b
3 subsequent elements of Data In are applied in the programmed order following DI b.
2) A non-interrupted burst of 4 is shown.
3) tWR is referenced from the positive clock edge after the last Data In pair.
4) A10 is LOW with the WRITE command (Auto Precharge is disabled)
NOP NOP NOP
= Don't Care
DQS
DQ
DM
tDQSSmax
BA
a (or all)
tWR
DI b
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 39 - Revision : A01-001
7.6.13 Inter rupting Write to Pre charge
Data for any W RIT E burs t may be truncate d by a subs equen t PR ECHARGE command as s ho wn in f igure below. Note
that only data-in pairs that are registered prior to the tWR period are written to the internal array, and an y subsequent
data-in should be masked with DM, as shown in figure. Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until tRP is met.
BA,Col n BA a(or
all)
BA,Col b
WRITE PRE NOP
CK
CK
Command
Address
1) Dl b = Data in to column b.
2) An interrupted burst of 4, 8 or 16 is shown, 2 data elements are written.
3) t
WR
is referenced from the positive clock edge after the last desired Data In pair.
4) A10 is LOW with the WRITE command (Auto Precharge is disabled)
5) *1=can be Don't Care for programmed burst length of 4
6) *2=for programmed burst length of 4, DQS becomes Don't Care at this point
NOP NOP NOP
= Don't Care
DQS
DQ
DM
tDQSSmax t
WR
DI b
*1*1*1*1
*2
7.7 Precharge
The PRECH ARG E com m and is use d to deactiv ate th e open r ow in a part icular b ank or the ope n ro w in a ll ban ks . The
bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is
issued.
Input A10 determines whether one or all banks are to be precharged. In case where only one bank is to be
precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care”.
Once a ba nk has been pr e char ged, it is in the idle sta t e an d must be activ ate d pr ior to a n y RE AD or WRITE c ommand
being issued. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if the
previously open row is already in the process of precharging.
7.7.1 Precharge Command
= Don't Care
(High)
CK
CK
CKE
CS
RAS
CAS
WE
Address
BA=BANK Address
(if A10 = L,otherwise Don't Care)
BABA0,BA1
A10
All Banks
One Bank
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 40 - Revision : A01-001
7.8 Auto Precharge
Auto Precharge is a feature which performs the same individual bank precharge function as described above, but
without requiring an explicit com mand. T his is accom plished by usi ng A10 (A10 = High), to enable Auto Prec harge in
conjunct ion with a specif ic REA D or WRITE command. A precharge of t he bank / row that is ad dr ess ed with the READ
or WRITE command is automatically performed upon completion of the read or write burst. Auto Precharge is non
persistent in that it is either enabled or disabled for each individual READ or WRITE command.
Auto Prechar ge ensures that a prechar ge is init iated at the ear liest va lid stage wit hin a burst. T he user m ust not issue
another command to the same bank until the precharing time (tRP) is completed. This is determined as if an explicit
PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Operation
section of this specification.
7.9 Refresh Requirements
LPDDR SDR AM devices require a r efresh of all ro ws in any rolling 64m s interval. Eac h refresh is gener ated in one of
two ways: by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode.
Dividing the number of dev i c e rows into the rolling 6 4m s inter val def in es t he aver a ge r ef res h int er val ( t REFI), whic h is a
guideline to controllers for distributed refresh timing.
7.10 Auto Refresh
AUTO REFRESH c omm and is used duri ng norm al op eratio n of the LPDDR SDR AM. This command is non persist ent,
so it must be issued each time a refresh is required.
The refresh addres sing is g enerated by the i nter n al refresh c ontr o ller. The LPDD R SDR AM r eq uir es AUT O REFRE SH
commands at an average periodic interval of tREFI.
7.10.1 Auto Refresh Command
= Don't Care
(High)
CK
CK
CKE
CS
RAS
CAS
WE
A0-An
BA0,BA1
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 41 - Revision : A01-001
7.11 Self Referesh
The SELF REFRESH command can be used to retain data in the LPDDR SDRAM, even if the rest of the system is
powered down. When in the Self Refresh mode, the LPDDR SDRAM retains data without external clocking. The
LPDDR SDRAM device has a built-in timer to accomm odate Self Refresh operation. The SELF REFRESH comm and
is initiate d lik e an AUT O REFRESH c omm and except CKE is LOW. I nput signals except CK E are “Do n’t Ca re” during
Self Refresh. The user may halt the external clock one clock after the SELF REFRESH command is registered.
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. The clock is
internal l y dis ab led during Self R ef res h op er ati on t o s a ve power. T he minimum time that the de vic e must r emain in Self
Refresh mode is tRFC.
The proc edure f or exiti ng S elf Ref resh r equires a se quenc e of c omm ands. Fir st, the cloc k m ust be s table pr ior to CK E
going bac k High. Once Self Refres h Exit is r e gister e d, a de lay of at least tXS must be satis f ied bef ore a va li d command
can be issued to the device to allow for completion of any internal refresh in progress.
The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when
CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh an extra AUTO REFRESH command is
recommended.
In the Self Refresh mode, Partial Array Self Refresh (PASR) function is described in the Extended Mode Register
section.
7.11.1 Self Refresh Command
= Don't Care
CK
CK
CKE
CS
RAS
CAS
WE
A0-An
BA0,BA1
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 42 - Revision : A01-001
7.11.2 Auto Refresh Cycles Back-to-Back
PRE NOP ARF NOP NOP NOPARF NOP ACT
Ba,A
Row n
Row nPre All
High-z
CK
CK
Command
Address
A10 (AP)
DQ
tRP tRFC tRFC
= Don't Care
Ba A, Row n = Bank A, Row n
7.11.3 Sel f Refresh En try and Exit
PRE NOP ARF NOP ARF
NOP
Pre All
High-z
CK
CK
Command
A10 (AP)
DQ
tRP > t RFC tRFC
= Don't Care
Address
NOP
tXSR
Any Command
(Auto Refresh
Recommene
d)
Exit from
Self Refresh
Mode
Enter
Self Refresh
Mode
CKE
ACT
NOP
Ba, A
Row n
Row n
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 43 - Revision : A01-001
7.12 Power Down
Power-d own is enter ed when CK E is regis tered Lo w (no ac cess es c an be in prog ress ). If power -down occur s when all
banks are idle, this m ode is referr ed to as precharg e power-down; if power-dow n occurs when there is a row ac tive in
any bank, this mode is referred to as active power-down.
Entering power-down deactivates the input and output buffers, excluding CK,
CK
and CKE. In power-down mode,
CKE Low must be maintained, and all other input signals are “Don’t Care”. The minimum power-down duration is
specified by tCKE. However, power-down duration is limited by the refresh requirements of the device.
The power-down state is synchronously exited when CKE is registered High (along with a NOP or DESELECT
command). A valid command may be applied tXP after exit from power-down.
For Clock Stop during Power-Down mode, please refer to the Clock Stop subsection in this specification.
7.12.1 Power-Down E ntry and Exit
PRE NOP NOP NOP NOP Valid
Pre All
High-z
CK
CK
Command
A10 (AP)
DQ
tRP tCKE tXP
Address
NOP
Any CommandExit from
Power Down
Power Down
Entry
Valid
Valid
Precharge Power-Down mode shown; all banks are idle and tRP
is met when Power-down Entry command is issued = Don't Care
CKE
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 44 - Revision : A01-001
7.13 Deep Power Down
The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside the
LPDDR SDRAM are stopped and all memory data is lost in this mode. All the information in the Mode Register and the
Extended Mode Register is lost.
Deep Power-Do wn is entered usin g the BURST TERMINAT E comm and except that CKE is registered Low. Al l banks
must be in id le stat e wit h no act ivit y on th e data bus prior to ent ering t he DPD mode. W hile in th is state , C KE m ust be
held in a constant Low state.
To ex it the DPD mode, CKE is taken high after the c l o ck is st able and NOP c om mands must be m aintai ned f or at least
200μs. After 200μs a complete re-initialization is required follo wing steps 4 through 11 as def ined for the initialization
sequence.
7.13.1 Deep Pow er-Down Entry and Exit
t
RP
T=200us
Exit DPD
Mode
Enter DPD
Mode
= Don't Care
1) Clock must be stable before exiting Deep Power-Down mode. That is, the clock must be cycling
within specifications by Ta0
2) Device must be in the all banks idle state prior to entering Deep Power-Down mode
3) 200us is required before any command can be applied upon exiting Deep-Down mode
4) Upon exiting Deep Power-Down mode a PRECHARGE ALL command must be issued, followed
by two REFRESH commands and a load mode register sequence
NOP DPD NOP Valid
Valid
Ta2
Ta1
Ta0T0 T1
CK
CK
CKE
Command
Address
DQS
DQ
DM
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 45 - Revision : A01-001
7.14 Clock Stop
Stopping a clock during idle periods is an effective method of reducing power consumption.
The LPDDR SDRAM supports clock stop under the following conditions:
the last command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has
executed to completion, including any data-out during read bursts; the number of clock pulses per access
command depends on the device’s AC timing parameters and the clock frequency;
the related timing conditions (tRCD, tWR, tRP, tRFC, tMRD) has been met;
CKE is held High
W hen all conditions ha ve been met, th e d ev ice is e ith e r in “idle sta te” or “ro w act ive s tate” and cl oc k stop m ode may
be entered with CK held Low and
CK
held High.
Clock stop mode is exited by restarting the clock. At least one NOP command has to be issued before the next
access command may be applied. Additional clock pulses might be required depending on the system
characteristics.
The following Figure shows clock stop mode entry and exit.
Initially the device is in clock stop mode
The clock is restarted with the rising edge of T0 and a NOP on the command inputs
With T1 a valid access command is latched; this command is followed by NOP commands in order to allow for
clock stop as soon as this access command is completed
Tn is the last clock pulse required by the access command latched with T1
The clock can be stopped after Tn
7.14.1 Clo ck Stop Mode Ent ry and E xit
Valid
NOP CMD NOP NOP NOP
TnT2T1T0
CK
CK
CKE
Command
DQ,DQS
Timing Condition
(High-Z)
= Don't Care
Enter Clock
Stop Mode
Valid
Command
Exit Clock
Stop Mode
Clock
Stopped
Address
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 46 - Revision : A01-001
8. ELECTRICAL CHARACTERISTIC
8.1 Absolute Maximum Ratings
PARAMETER SYMBOL VALUES
UNITS
MIN MAX
Voltage on VDD relative to VSS VDD −0.5 2.3 V
Voltage on VDDQ relative to VSS VDDQ −0.5 2.3 V
Voltage on any pin relative to VSS VIN, VOUT −0.5
2.3 V
Storage Temperature TSTG −55
150 °C
Short Circuit Output Current IOUT ±50 mA
Power Dissip ati on PD 1.0 W
NOTE :
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability
8.2 Input/Output Capacitance
PARAMETER SYMBOL
MIN MAX UNITS NOTES
Input capacitance, CK,
CK
CCK 1.5 3.0 pF
Input capaci tanc e de lta, CK ,
CK
CDCK 0.25 pF
Input capacitance, all other input
-only pins CI 1.5 3.0 pF
Input capaci tanc e de lta, all other inp ut
-only pins
CDI 0.5 pF
Input/ output capacitance, DQ,DM,DQS
CIO 3.0 5.0 pF 3
Input/output capacitance delta, DQ, DM, DQS
CDIO 0.50 pF 3
Notes:
1. These values are guaranteed by design and are tested on a sample base only.
2. These capacitance values are for single monolithic devices only. Multiple die packages will have parallel capacitive loads.
3. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins.
This is required to match sign a l prop agat ion tim es of DQ, DQS and DM in the system
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 47 - Revision : A01-001
8.3 Electrical Characteristics and AC/DC Operating Conditions
All values are recommended operating conditions unless otherwise noted.
8.3.1 Electrical Characteristics an d AC/DC Operating Condition s
PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES
Suppl y Voltage VDD 1.70 1.95 V
I/O Supply Voltage VDDQ 1.70 1.95 V
ADDRESS AND COMMAND INPUTS (A0~An, BA0,BA1,CKE,
CS
,
RAS
,
CAS
,
WE
)
Input High Voltage VIH 0.8*VDDQ VDDQ + 0.3 V
Input Low Voltage VIL −0.3 0.2*VDDQ V
CLOCK INPUTS (CK,
CK
)
DC Input Voltage VIN −0.3 VDDQ + 0.3 V
DC Input Differential Voltage VID (DC) 0.4*VDDQ VDDQ + 0.6 V 2
AC Input Diff erent ial Vol tag e VID (AC) 0.6*VDDQ VDDQ + 0.6 V 2
AC Differential Crossing Voltage VIX 0.4*VDDQ 0.6*VDDQ V 3
DATA INPUTS (DQ, DM, DQS)
DC Input High Voltage VIHD (DC) 0.7*VDDQ VDDQ + 0.3 V
DC Input Low Voltage VILD (DC) −0.3 0.3*VDDQ V
AC Input High Voltag e VIHD (AC) 0.8*VDDQ VDDQ + 0.3 V
AC Input Low Volta ge VILD (AC) −0.3 0.2*VDDQ V
Control OUTPUT(TQ)
Output High Voltage (IoH=-0.1mA) VoH 0.9*VDDQ V
Output Low Volta ge (IoL=+0.1mA) VoL 0.1*VDDQ V
DATA OUTPUTS (DQ, DQS)
DC Output High Voltage (IOH=−0.1mA)
VOH 0.9*VDDQ - V
DC Output Low Voltage (IOL=0.1mA) VOL - 0.1*VDDQ V
Leakage Current
Input Leakage Current IiL -1 1 uA 4
Output Leakage Current IoL -5 5 uA 5
Notes:
1. All voltages referenced to VSS and VSSQ must be same potential.
2. VID (DC) and VID (AC) are the magnitude of the difference between the input level on CK and
CK
.
3. The value of VIX is expected to be 0.5*VDDQ and must track variations in the DC level of the same.
4. Any input 0V ≤ VIN ≤ VDD. All other pins are not tested under VIN=0V.
5. Any output 0V ≤ VOUT ≤ VDDQ. DOUT is disabled.
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 48 - Revision : A01-001
8.4 IDD Specification Parameters and Test Conditions
8.4.1 IDD Specification and Test Conditions (x16)
[Recommended Operating Conditions; Notes 1-4]
PARAMETER
SYMBOL
TEST CONDITION
- 5
- 6
UNIT
Operating one
bank active-
precharge
current
IDD0 tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH;
CS
is HIGH
between valid commands; address inputs are SWITCHING; data
bus inputs are STAB LE 70 60 mA
Precharge
power-down
standby current IDD2P all banks idle, CKE is LOW;
CS
is HIGH, tCK = tCKmin ;
address and contr ol inp uts are SWITC HIN G ; data bus input s are
STABLE
0.6 0.6 mA
Precharge
power-down
standby current
with clock stop
IDD2PS all banks idle, CKE is LOW;
CS
is HIGH, CK = LOW,
CK
=
HIGH; address and control inputs are SWITCHING; data bus
inputs are STABLE 0.6 0.6 mA
Precharge non
power-down
standby current IDD2N all banks idle, CKE is HIGH;
CS
is HIGH, tCK = tCKmin;
address and contr ol inp uts are SWITC HIN G ; data bus input s are
STABLE
15 15 mA
Precharge non
power-down
standby current
with clock stop
IDD2NS all banks idle, CKE is HIGH;
CS
is HIGH, CK = LOW,
CK
=
HIGH; address and control inputs are SWITCHING; data bus
inputs are STABLE 8 8 mA
Active power-
down standby
current IDD3P one bank active, CKE is LOW;
CS
is HIGH, tCK =
tCKmin;address and control inputs are SWITCHING; data bus
inputs are STABLE
3.6 3.6 mA
Active power-
down standby
current with
clock stop
IDD3PS one bank active, CKE is LOW;
CS
is HIGH, CK = LOW,
CK
= HIGH; address and control inputs are SWITCHING; data bus
inputs are STABLE 3.6 3.6 mA
Active non
power-down
standby current IDD3N one bank active, CKE is HIGH;
CS
is HIGH, tCK = tCKmin;
address and contr ol inp uts are SWITC HIN G ; data bus input s are
STABLE
15 15 mA
Active non
power-down
standby current
with clock stop
IDD3NS one bank active, CKE is HIGH;
CS
is HIGH, CK = LOW,
CK
= HIGH; address and control inputs are SWITCHING; data bus
inputs are STABLE 8 8 mA
Operating burst
read current IDD4R
one bank active; BL = 4; CL = 3; tCK = tCKmin ; continuous read
bursts; IOUT = 0 mA; address inputs are SWITCHING; 50% data
change each burst transfer
115 105 mA
Operating burst
write current IDD4W
one bank active; BL = 4; t CK = t CKmin ; continuous write
bursts; address inputs are SWITCHING; 50% data change
each burst transfer
115 105 mA
Auto-Refresh
Current IDD5
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is
HIGH; address and control inputs are SWITCHING; data bus
inputs are STABLE
95 95 mA
Deep Power-
Down current
IDD8(4)
Address and control inputs are STABLE; data bus inputs are
STABLE
10 10 uA
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 49 - Revision : A01-001
8.4.2 IDD Specification and Test Conditions (x32)
[Recommended Operating Conditions; Notes 1-4]
PARAMETER
SYMBOL
TEST CONDITION
- 5
- 6
UNIT
Operating one
bank active-
precharge
current
IDD0 tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH;
CS
is HIGH
between valid commands; address inputs are SWITCHING; data
bus inputs are STAB LE 70 60 mA
Precharge
power-down
standby current IDD2P all banks idle, CKE is LOW;
CS
is HIGH, tCK = tCKmin ;
address and contr ol inp uts are SWITC HI NG; data bus inputs are
STABLE
0.6 0.6 mA
Precharge
power-down
standby current
with clock stop
IDD2PS all banks idle, CKE is LOW;
CS
is HIGH, CK = LOW, =
HIGH; address and control inputs are SWITCHING; data bus
inputs are STABLE 0.6 0.6 mA
Precharge non
power-down
standby current IDD2N all banks idle, CKE is HIGH;
CS
is HIGH, tCK = tCKmin;
address and contr ol inp uts are SWITC HIN G ; data bus
inputs are STABLE
15 15 mA
Precharge non
power-down
standby current
with clock stop
IDD2NS all banks idle, CKE is HIGH;
CS
is HIGH, CK = LOW,
= HIGH; address and control inputs are SWITCHING; data
bus inputs are STAB LE
8 8 mA
Active power-
down standby
current IDD3P one bank active, CKE is LOW;
CS
is HIGH, tCK = tCKmin;
address and contr ol inp uts are SWITC HIN G ; data bus input s are
STABLE
3.6 3.6 mA
Active power-
down standby
current with
clock stop
IDD3PS one bank active, CKE is LOW;
CS
is HIGH, CK = LOW,
= HIGH; address and control inputs are SWITCHING; data bus
inputs are STABLE 3.6 3.6 mA
Active non
power-down
standby current IDD3N one bank active, CKE is HIGH;
CS
is HIGH, tCK = tCKmin;
address and contr ol inp uts are SWITC HIN G ; data bus input s are
STABLE
15 15 mA
Active non
power-down
standby current
with clock stop
IDD3NS one bank active, CKE is HIGH;
CS
is HIGH, CK = LOW,
= HIGH; address and control inputs are SWITCHING; data bus
inputs are STABLE 8 8 mA
Operating burst
read current IDD4R one bank active; BL = 4; CL = 3; tCK = tCKmin ; continuous read
bursts; IOUT = 0 mA; address inputs are SWITCHING; 50% data
change each burst transfer
115 105 mA
Operating burst
write current IDD4W
one bank active; BL = 4; t CK = t CKmin ; continuous write
bursts; address inputs are SWITCHING; 50% data change
each burst transfer
115 105 mA
Auto-Refresh
Current IDD5
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is
HIGH; address and control inputs are SWITCHING; data bus
inputs are STABLE
95 95 mA
Deep Power-
Down current
IDD8(4) Address and control inputs are STABLE; data bus inputs are
STABLE
10 10 uA
CK
CK
CK
CK
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 50 - Revision : A01-001
Notes:
1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is 1V/ns.
3. Definitions for IDD:
LOW is defined as VIN ≤ 0.1 * VDDQ;
HIGH is defined as VIN ≥ 0.9 * VDDQ;
STABLE is defined as inputs stable at a HIGH or LOW level;
SWITCHING is defined as:
- Address and command: inputs changing between HIGH and LOW once per two clock cycles;
- Data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
4. IDD8 is a typical value at 25°C.
IDD6 Con ditions :
Self Refresh
Current IDD6
CKE is LOW; CK = LOW, =
HIGH; Extended Mode Register set to
all 0’s; address and control inputs are
STABLE; data bus inputs are STABLE
PASR Range 45°C
85°C Units
Full Array 750 1300 uA
1/2 Array 600 1050
1/4 Array 500 900
.
CK
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 51 - Revision : A01-001
8.5 AC Timings
[Recommended Operating Conditions: Notes 1-9]
PARAMETER SYMBOL - 5 - 6 UNIT NOTES
MIN MAX MIN MAX
DQ output access time
from CK/
CK
CL=3 tAC 2.0 5.0 2.0 5.0 ns
CL=2 2.0 6.5 2.0 6.5
DQS
output access time from
CK
CL=3 tDQSCK 2.0 5.0 2.0 5.0 ns
CL=2 2.0 6.5 2.0 6.5
Clock high-level width tCH 0.45 0.55 0.45 0.55 tCK
Clock low-level width tCL 0.45 0.55 0.45 0.55 tCK
Clock half period tHP Min
(tCL, tCH)
Min
(tCL, tCH)
ns 10,11
Clo ck cycle time CL=3 tCK 5 6 ns 12
CL=2 12 12 ns 12
DQ and DM input setup
time
fast tDS 0.48 0.6 ns 13,14,15
slow 0.58 0.7 ns 13,14,16
DQ and DM input hold time fast tDH 0.48 0.6 ns 13,14,15
slow 0.58 0.7 ns 13,14,16
DQ and DM input pulse width tDIPW 1.4 1.6 ns 17
Address and control input
setup time
fast tIS 0.9 1.1 ns 15,18
slow 1.1 1.3 ns 16,18
Address and control input
hold time
fast tIH 0.9 1.1 ns 15,18
slow 1.1 1.3 ns 16,18
Address and control input pulse width tIPW 2.3 2.6 ns 17
DQ & DQS low-impedance time from
CK/
CK
tLZ 1.0 1.0 ns 19
DQ & DQS high-impedance
time from CK/
CK
CL=3 tHZ 5.0 5.0 ns 19
CL=2 6.5 6.5
DQS-DQ skew tDQSQ 0.4 0.5 ns 20
DQ/DQS output hold time from DQS tQH tHP-
tQHS tHP-
tQHS ns 11
Data hold skew factor tQHS 0.5 065 ns 11
Write command to 1st DQS latching
transition tDQSS 0.75 1.25 0.75 1.25 tCK
DQS input high-level width tDQSH 0.4 0.6 0.4 0.6 tCK
DQS input low-level width tDQSL 0.4 0.6 0.4 0.6 tCK
DQS falling edge to CK setup time tDSS 0.2 0.2 tCK
DQS falling edge hold time from CK tDSH 0.2 0.2 tCK
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 52 - Revision : A01-001
PARAMETER SYMBOL - 5 - 6 UNIT NOTES
MIN MAX MIN MAX
MOD E REGISTER SET com mand
period tMRD 2 2 tCK
Write preamble setup time tWPRES 0 0 ns 21
Write postambl e tWPST 0.4 0.6 0.4 0.6 tCK 22
Write preamble tWPRE 0.25 0.25 tCK
Read preamble CL = 3 tRPRE 0.9 1.1 0.9 1.1 tCK 23
CL = 2 0.5 1.1 0.5 1.1 tCK 23
Read postamble tRPST 0.4 0.6 0.4 0.6 tCK
ACTIVE to PRECHARGE command
period tRAS 40 70,000 42 70,000 ns
ACTIVE to ACTIVE command period tRC tRAS+
tRP tRAS+
tRP ns
AUTO R EFR ESH to AC TIVE/AUTO
REFRESH command period tRFC 72 72 ns
ACTIVE to READ or WRITE delay tRCD 15 18 ns
PRECHARGE command period tRP 3 3 tCK
ACTIVE bank A to ACTIVE bank B
delay tRRD 10 12 ns
WRITE recovery time tWR 15 15 ns 24
Auto precharge write recovery +
precharge tim e tDAL - - tCK 25
Internal write t o Read command delay tWTR 1 1 tCK
Self Refresh exit to next valid command
delay tXSR 120 120 ns 26
Exit power down to next valid command
delay tXP 2 1 tCK 27
CKE min. pulse width (high and low
pulse width) tCKE 1 1 tCK
Refresh Period tREF 64 64 ms
Average periodic ref resh i nterval tREFI 7.8 7.8 μs 28,29
MRS for SRR to REA D tSRR 2 2 tCK
READ of SRR to next valid command tSRC CL+1 CL+1 tCK
Internal temperature sensor to
valid temperature output enable
tTQ 2 2 ms
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 53 - Revision : A01-001
Notes:
1. All voltages referenced to VSS.
2. All parameters assume proper device initialization.
3. Tests for AC timing may be conducted at nominal supply voltage levels, but the related specifications and
device operation are guaranteed for the full voltage and temperature range specified.
4. The c ircuit sh own belo w repr esents t he tim ing ref eren ce load use d in defin ing t he re levant tim ing p aram eters of
the part. It is not intended to be either a precise representation of the typical system environment nor a depiction
of the actual load presented by a production tester. System designers will use IBIS or other simulation too ls to
correlate the timing reference load to system environment. Manufacturers will correlate to their production test
conditio ns ( ge ner a ll y a c o a x ial tr ans mission lin e t er minated at t he tes ter el ec tr on i cs ) . For the h alf s trength dr iver
with a nominal 10pF load parameters tAC and tQH are expected to be in the same range. However, these
parameters are not subject to production test but are estimated by design / characterization. Use of IBIS or
other simulation tools for system design validation is suggested.
Time Reference Load
I/O
Z
0
= 50 Ohms 20pF
5. The CK/
CK
input reference voltage level (for timing referenced to CK/
CK
) is the po int at which CK and
CK
cross; the input reference voltage level for signals other than CK/
CK
is VDDQ/2.
6. The timing reference voltage level is VDDQ/2.
7. AC and DC input and output voltage levels are defined in the section for Electrical Characteristics and AC/DC
operating conditions.
8. A CK/
CK
differential slew rate of 2.0 V/ns is assumed for all parameters.
9.
CAS
latenc y definition: with C L = 3 th e firs t data elem ent is val id at (2 * tC K + tAC) aft er the cloc k at which th e
READ command was registered ; with CL = 2 the first data element is valid at (tCK + tAC) after the clock at
which the READ command was registered
10. Min (tC L, tC H) ref er s to the smaller of the actual clock lo w time and the act ual c lo ck high time as prov ide d to the
device (i.e. this value can be greater than the minimum specification limits of tCL and tCH)
11. tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or
clock low (tCL, tCH). tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the
worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition,
both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel
variation of the output drivers.
12. The only time that the clock frequency is allowed to change is during clock stop, power-down or self-refresh
modes.
13. The transition time for DQ, DM and DQS inputs is measured between VIL(DC) to VIH(AC) for rising input
signals, and VIH(DC) to VIL(AC) for falling input signals.
14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold
times. Signal transitions through the DC region must be monotonic.
15. Input slew rate ≥ 1.0 V/ns.
16. Input slew rate ≥ 0.5 V/ns and < 1.0 V/ns.
17. These parameters guarantee device timing but they are not necessarily tested on each device.
18. The transition time for address and command inputs is measured between VIH and VIL.
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 54 - Revision : A01-001
19. tHZ and tLZ transiti ons occur in the s ame ac cess tim e wind ows as valid dat a trans itions. T hese param eters are
not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving
(LZ).
20. tDQSQ consists of dat a pin skew a nd output pattern effects , and p-channel to n-channel variation of the output
drivers for any given cycle.
21. T he specif ic requir em ent is that DQS be val id (HIGH , LOW , or som e point on a vali d transi tion) on or bef ore the
corresponding CK edge. A valid transition is defined as monotonic and meeting the input slew rate
specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning
from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS.
22. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
23. A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-
down element in the system. It is recommended to turn off the weak pull-down element during read and write
bursts (DQS drivers enabled).
24. At least one clock cycle is required during tWR time when in auto precharge mode.
25. tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms, if not already an integer, round to the next higher integer.
26. There must be at least two clock pulses during the tXSR period.
27. There must be at least one clock pulse during the tXP period.
28. tREFI va lues ar e dependent on dens i t y and bus width.
29. A m aximum of 8 Refresh com mands can be posted to an y given LPDD R, meanin g that the m aximum absolute
interval between any Refresh command and the next Refresh command is 8*tREFI.
8.5.1 CAS La tency De finition ( Wi th CL=3 )
CL=3
tLZmin
tRPRE
tDQSCKmin tDQSCKmin
tRPST
T5nT5T4nT3nT2n T4T3T2
READ NOP NOP NOP NOP NOPNOPCommand
CK
CK
DQS
All DQ,
collectively
1)DQ transitioning after DQS transition define tDQSQ window.
2)ALL DQ must transition by tDQSQ after DQS transitions, regardless of tAC
3)tAC is the DQ output window relative to CK,and is the long term component of DQ skew.
T0 T1 T2 T2n T3 T3n T4 T4n T5 T5n T6
tLZmin
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 55 - Revision : A01-001
8.5.2 Output Slew Rate Characteristics
PARAMETER MIN MAX UNIT NOTES
Pull-up and Pull-Down Slew Rate for Full Strength Driver 0.7 2.5 V/ns 1,2
Pull-up and Pull-Down Slew Rate for Three-Quarter Strength Driver 0.5 1.75 V/ns 1,2
Pull-up and Pull-Down Slew Rate for Half Strength Driver 0.3 1.0 V/ns 1,2
Output Slew rate Matching ratio (Pull-up to Pull-down) 0.7 1.4 - 3
Notes:
1. Measured with a test load of 20 pF connected to VSSQ.
2. Output slew rate for rising edge is measured bet ween VI LD(DC) to VIHD(AC) and for falling edge bet ween VIHD(DC) t o VILD(AC).
3. The ratio of pull -up slew rate to pull-down slew rate is specifi ed for the sam e temperature and volt age, over the entire temperature and
voltage range. For a given output, it represents the maxim um difference bet ween pull-up and pull -down drivers due to process variation.
8.5.3 AC Overshoot/ Undershoot Specifica tion
PARAMETER SPECIFICATION
Maximum peak amplitude allowed for overshoot
0.5 V
Maximum peak amplitude allowed for undershoot
0.5 V
The area between overshoot signal and VDD must be less than or equal to
3 V-ns
The area between undershoot signal and GND must be less than or equal to
3 V-ns
8.5.4 AC Overshoot and Unde rshoot Definition
VDD
VSS
2.5
2.0
1.5
1.0
0.5
0
-0.5
Overshoot Area
Undershoot Area
Max Amplitude = 0.5V Max Area = 3V-ns
Voltage (V)
Time
(ns)
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 56 - Revision : A01-001
9. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
P01-001 11/19/2012 All First preliminary release.
P01-002 03/25/2013 49,50 Update IDD3P & IDD3PS value.
A01-001 07/01/2013 All
51 Remove text "Preliminary" & release to active version.
Add PASR value.
09/07/2016 Modified for MCP Combo Datasheet
W94AD6KK / W94AD2KK
1Gb Mobile LPDDR
Publication Release Date : Jul y 01, 2013
- 57 - Revision : A01-001
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or
equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for
other applications intended to support or sustain life. Further more, Winbond products are not intended for
applications wherein failure of Winbond products could result or lead to a situation wherein personal injury,
death or severe property or environm ental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Winbond for any damages resulting fr o m such improper use or sales.
-------------------------------------------------------------------------------------------------------------------------------------------------
Please note that all data and specifications are subj ect to change without n otic e.
All the trademarks of products and companies mentioned in the datasheet belong to their respective owners.