STD10N60DM2 N-channel 600 V, 0.440 typ., 8 A MDmeshTM DM2 Power MOSFET in a DPAK package Datasheet - production data Features Order code VDS @ TJmax. RDS(on) max. ID PTOT STD10N60DM2 650 V 0.530 8A 109 W Figure 1: Internal schematic diagram Fast-recovery body diode Extremely low gate charge and input capacitance Low on-resistance 100% avalanche tested Extremely high dv/dt ruggedness Zener-protected Applications Switching applications Description This high voltage N-channel Power MOSFET is part of the MDmeshTM DM2 fast recovery diode series. It offers very low recovery charge (Qrr) and time (trr) combined with low RDS(on), rendering it suitable for the most demanding high efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. Table 1: Device summary Order code Marking Package Packing STD10N60DM2 10N60DM2 DPAK Tape and reel June 2016 DocID029382 Rev 1 This is information on a product in full production. 1/14 www.st.com Contents STD10N60DM2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/14 4.1 DPAK (TO-252) type A package information..................................... 9 4.2 DPAK (TO-252) packing information ............................................... 11 Revision history ............................................................................ 13 DocID029382 Rev 1 STD10N60DM2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit 25 V Drain current (continuous) at Tcase = 25 C 8 Drain current (continuous) at Tcase = 100 C 5 IDM(1) Drain current (pulsed) 32 A PTOT W ID Total dissipation at Tcase = 25 C 109 dv/dt(2) Peak diode recovery voltage slope 40 dv/dt(3) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range Tj Operating junction temperature range A V/ns -55 to 150 C Value Unit Notes: (1) Pulse width is limited by safe operating area. (2) ISD 8 A, di/dt=900 A/s; VDS peak < V(BR)DSS,VDD = 400 V (3) VDS 480 V. Table 3: Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Thermal resistance junction-case Thermal resistance junction-ambient 1.14 50 C/W Notes: (1)When mounted on 1 inch FR-4 board, 2oz Cu. Table 4: Avalanche characteristics Symbol Parameter IAR(1) Avalanche current, repetitive or not repetitive EAS(2) Single pulse avalanche energy Value Unit 2 A 300 mJ Notes: (1) pulse width limited by Tjmax (2) starting Tj = 25 C, ID = IAR, VDD = 50 V. DocID029382 Rev 1 3/14 Electrical characteristics 2 STD10N60DM2 Electrical characteristics (Tcase = 25 C unless otherwise specified) Table 5: Static Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1.5 VGS = 0 V, VDS = 600 V, Tcase = 125 C(1) 100 Gate-body leakage current VDS = 0 V, VGS = 25 V 10 A VGS(th) Gate threshold voltage VDS = VGS, ID = 250 A 4 5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 4 A 0.440 0.530 Min. Typ. Max. Unit - 529 - - 28 - - 0.72 - IDSS Zero gate voltage drain current IGSS 3 A Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 47 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 6.5 - Qg Total gate charge - 15 - Qgs Gate-source charge - 3.7 - Qgd Gate-drain charge VDD = 480 V, ID = 8 A, VGS = 10 V (see Figure 15: "Test circuit for gate charge behavior") - 8 - VDS = 100 V, f = 1 MHz, VGS = 0 V pF nC Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 7: Switching times Symbol td(on) tr td(off) tf 4/14 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. VDD = 300 V, ID = 4 A RG = 4.7 , VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") - 11 - - 5 - - 28 - - 11.5 - DocID029382 Rev 1 Unit ns STD10N60DM2 Electrical characteristics Table 8: Source-drain diode Symbol Parameter Test conditions ISD(1) Source-drain current ISDM(2) Source-drain current (pulsed) VSD(3) Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Min. Typ. Max. Unit - 8 A - 32 A VGS = 0 V, ISD = 8 A - 1.6 V ISD = 8 A, di/dt = 100 A/s, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 90 ns - 225 C - 5 A ISD = 8 A, di/dt = 100 A/s, VDD = 60 V, Tj = 150 C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 190 ns - 684 nC - 7.2 A Notes: (1) Limited by maximum junction temperature. (2) Pulse width is limited by safe operating area. (3) Pulse test: pulse duration = 300 s, duty cycle 1.5%. Table 9: Gate-source Zener diode Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)GSO Gate-source breakdown voltage IGS = 250 A, ID = 0 A 30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DocID029382 Rev 1 5/14 Electrical characteristics 2.1 6/14 STD10N60DM2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID029382 Rev 1 STD10N60DM2 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Output capacitance stored energy Figure 13: Source-drain diode forward characteristics DocID029382 Rev 1 7/14 Test circuits 3 8/14 STD10N60DM2 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform DocID029382 Rev 1 STD10N60DM2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK (R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 4.1 DPAK (TO-252) type A package information Figure 20: DPAK (TO-252) type A package outline 0068772_A_21 DocID029382 Rev 1 9/14 Package information STD10N60DM2 Table 10: DPAK (TO-252) type A mechanical data mm Dim. Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 4.60 4.70 4.80 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 (L1) 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 5.10 5.25 6.60 1.00 0.20 0 8 Figure 21: DPAK (TO-252) recommended footprint (dimensions are in mm) 10/14 DocID029382 Rev 1 STD10N60DM2 4.2 Package information DPAK (TO-252) packing information Figure 22: DPAK (TO-252) tape outline Figure 23: DPAK (TO-252) reel outline DocID029382 Rev 1 11/14 Package information STD10N60DM2 Table 11: DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Min. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 12/14 Max. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID029382 Rev 1 18.4 22.4 STD10N60DM2 5 Revision history Revision history Table 12: Document revision history Date Revision 17-Jun-2016 1 DocID029382 Rev 1 Changes First release. 13/14 STD10N60DM2 IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2016 STMicroelectronics - All rights reserved 14/14 DocID029382 Rev 1