PIC24FJ128GA008-I/PT - Microchip Technology, Inc.

 2005-2012 Microchip Technology Inc. DS39747F-page 1

PIC24FJ128GA010 FAMILY

High-Performance CPU:

• Modified Harvard Architecture

• Up to 16 MIPS Operation @ 32 MHz

• 8 MHz Internal Oscillator with 4x PLL Option and

Multiple Divide Options

• 17-Bit x 17-Bit Single-Cycle Hardware

Multiplier

• 32-Bit by 16-Bit Hardware Divider

• 16 x 16-Bit Working Register Array

• C Compiler Optimized Instruction Set Architecture:

- 76 base instructions

- Flexible addressing modes

• Two Address Generation Units for Separate Read

and Write Addressing of Data Memory

S pecial Microcontroller Features:

• Operating Voltage Range of 2.0V to 3.6V

• Flash Program Memory:

- 1000 erase/write cycles

- 20-year data retention minimum

• Self-Reprogrammable under Software Control

• Selectable Power Management modes:

- Sleep, Idle and Alternate Clock modes

• Fail-Safe Clock Monitor Operation:

- Detects clock failure and switches to on-chip,

low-power RC oscillator

• On-Chip 2.5V Regulator

• JTAG Boundary Scan and Programming Support

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT) with On-Chip,

Low-Power RC Oscillator for Reliable Operation

• In-Circuit Serial Programming™ (ICSP™) and

In-Circuit Emulation (ICE) via 2 Pins

Analog Features:

• 10-Bit, Up to 16-Channel Analog-to-Digital Converter

- 500 ksps conversion rate

- Conversion available during Sleep and Idle

• Dual Analog Comparators with Programmable

Input/Output Configuration

Peripheral Feat ures:

• Two 3-Wire/4-Wire SPI modules, Supporting

4 Frame modes with 8-Level FIFO Buffer

•Two I

2C™ modules Support Multi-Master/Slave

mode and 7-Bit/10-Bit Addressing

• Two UART modules:

- Supports RS-232, RS-485 and LIN/J2602

- On-chip hardware encoder/decoder for IrDA®

- Auto-wake-up on Start bit

- Auto-Baud Detect

- 4-level FIFO buffer

• Parallel Master Slave Port (PMP/PSP):

- Supports 8-bit or 16-bit data

- Supports 16 address lines

• Hardware Real-Time Clock/Calendar (RTCC):

- Provides clock, calendar and alarm functions

• Programmable Cyclic Redundancy Check (CRC)

- User-programmable polynomial

- 8/16-level FIFO buffer

• Five 16-Bit Timers/Counters with Programmable

Prescaler

• Five 16-Bit Capture Inputs

• Five 16-Bit Compare/PWM Outputs

• High-Current Sink/Source (18 mA/18 mA) on All

I/O Pins

• Configurable, Open-Drain Output on Digital I/O Pins

• Up to 5 External Interrupt Sources

• 5.5V Tolerant Input (digital pins only)

Device Pins Program

Memory

(Bytes)

SRAM

(Bytes) Timers

16-Bit

Capture

Input

Compare/

PWM Outp ut

UART

SPI I2C™ 10-Bit

A/D (ch)

Comparators

PMP/PSP

JTAG

PIC24FJ64GA006 64 64K 8K 5 5 5 2 2 2 16 2 Y Y

PIC24FJ96GA006 64 96K 8K 5 5 5 2 2 2 16 2 Y Y

PIC24FJ128GA006 64 128K 8K 5 5 5 2 2 2 16 2 Y Y

PIC24FJ64GA008 80 64K 8K 5 5 5 2 2 2 16 2 Y Y

PIC24FJ96GA008 80 96K 8K 5 5 5 2 2 2 16 2 Y Y

PIC24FJ128GA008 80 128K 8K 5 5 5 2 2 2 16 2 Y Y

PIC24FJ64GA010 100 64K 8K 5 5 5 2 2 2 16 2 Y Y

PIC24FJ96GA010 100 96K 8K 5 5 5 2 2 2 16 2 Y Y

PIC24FJ128GA010 100 128K 8K 5 5 5 2 2 2 16 2 Y Y

64/80/100-Pin, General Purpose, 16-Bit Flash Microcontr ollers

PIC24FJ128GA010 FAMILY

DS39747F-page 2  2005-2012 Microchip Technology Inc.

Pin Diagrams

PIC24FJXXGA006

CN15/RD6

PMRD/CN14/RD5

PMWR/OC5/IC5/CN13/RD4

PMBE/OC4/RD3

OC3/RD2

OC2/RD1

PMD4/RE4

PMD3/RE3

PMD2/RE2

PMD1/RE1

RF0

VCAP/VDDCORE

SOSCI/CN1/RC13

OC1/RD0

IC3/PMCS2/INT3/RD10

IC2/U1CTS/INT2/RD9

IC1/RTCC/INT1/RD8

IC4/PMCS1/INT4/RD11

OSC2/CLKO/RC15

OSC1/CLKI/RC12

VDD

SCL1/RG2

U1RTS/BCLK1/SCK1/INT0/RF6

U1RX/SDI1/RF2

U1TX/SDO1/RF3

SDA1/RG3

SOSCO/T1CK/CN0/RC14

AVDD

U2CTS/C1OUT/AN8/RB8

PMA7/C2OUT/AN9/RB9

TMS/PMA13/CVREF/AN10/RB10

TDO/PMA12/AN11/RB11

VDD

PGC2/EMUC2/AN6/OCFA/RB6

PGD2/EMUD2/AN7/RB7

PMA8/U2TX/SCL2/CN18/RF5

PMA9/U2RX/SDA2/CN17/RF4

PMD5/RE5

PMD6/RE6

PMD7/RE7

PMA5/SCK2/CN8/RG6

VDD

C1IN+/AN5/CN7/RB5

C1IN-/AN4/CN6/RB4

C2IN+/AN3/CN5/RB3

C2IN-/AN2/SS1/CN4/RB2

PMA4/SDI2/CN9/RG7

PMA3/SDO2/CN10/RG8

PGC1/EMUC1/VREF-/AN1/CN3/RB1

PGD1/EMUD1/PMA6/VREF+/AN0/CN2/RB0

PMA2/SS2/CN11/RG9

MCLR

TCK/PMA11/AN12/RB12

TDI/PMA10/AN13/RB13

PMA1/U2RTS/BCLK2/AN14/RB14

PMA0/AN15/OCFB/CN12/RB15

PMD0/RE0

RF1

CN16/RD7

VSS

Vss

ENVREG

AVSS

64-Pin TQFP/QFN(1)

PIC24FJXXXGA006

Legend: Shaded pins indicate pins that are tolerant to up to +5.5 VDC.

Note 1: Bottom pad of QFN package must be connected to VSS.

 2005-2012 Microchip Technology Inc. DS39747F-page 3

PIC24FJ128GA010 FAMILY

Pin Diagrams (Continued)

PIC24FJXXGA008

PMRD/CN14/RD5

PMWR/OC5/CN13/RD4

CN19/RD13

IC5/RD12

PMBE/OC4/RD3

OC3/RD2

OC2/RD1

PMD2/RE2

PMD1/RE1

PMD0/RE0

RG0

PMD4/RE4

PMD3/RE3

RF0

VCAP/VDDCORE

SOSCI/CN1/RC13

OC1/RD0

IC3/PMCS2/RD10

IC2/RD9

IC1/RTCC/RD8

IC4/PMCS1/RD11

SDA2/INT4/RA15

SCL2/INT3/RA14

OSC2/CLKO/RC15

OSC1/CLKI/RC12

VDD

SCL1/RG2

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

SDA1/RG3

U1RX/RF2

U1TX/RF3

SOSCO/T1CK/CN0/RC14

PMA6/VREF+/RA10

PMA7/VREF-/RA9

AVDD

U2CTS/C1OUT/AN8/RB8

C2OUT/AN9/RB9

PMA13/CVREF/AN10/RB10

PMA12/AN11/RB11

VDD

U1CTS/CN20/RD14

U1RTS/BCLK1/CN21/RD15

PGC2/EMUC2/AN6/OCFA/RB6

PGD2/EMUD2/AN7/RB7

PMA8/U2TX/CN18/RF5

PMA9/U2RX/CN17/RF4

PMD5/RE5

PMD6/RE6

PMD7/RE7

T2CK/RC1

T4CK/RC3

PMA5/SCK2/CN8/RG6

VDD

TMS/INT1/RE8

TDO/INT2/RE9

C1IN+/AN5/CN7/RB5

C1IN-/AN4/CN6/RB4

C2IN+/AN3/CN5/RB3

C2IN-/AN2/SS1/CN4/RB2

PMA4/SDI2/CN9/RG7

PMA3/SDO2/CN10/RG8

PGC1/EMUC1/AN1/CN3/RB1

PGD1/EMUD1/AN0/CN2/RB0

PMA2/SS2/CN11/RG9

MCLR

TCK/PMA11/AN12/RB12

TDI/PMA10/AN13/RB13

PMA1/U2RTS/BCLK2/AN14/RB14

PMA0/AN15/OCFB/CN12/RB15

RG1

RF1

CN16/RD7

CN15/RD6

VSS

ENVREG

AVSS

80-Pin TQFP

PIC24FJXXXGA008

Legend: Shaded pins indicate pins that are tolerant to up to +5.5 VDC.

PIC24FJ128GA010 FAMILY

DS39747F-page 4  2005-2012 Microchip Technology Inc.

Pin Diagrams (Continued))

100

PMRD/CN14/RD5

PMWR/OC5/CN13/RD4

CN19/RD13

IC5/RD12

PMBE/OC4/RD3

OC3/RD2

OC2/RD1

RA7

RA6

PMD2/RE2

RG13

RG12

RG14

PMD1/RE1

PMD0/RE0

RG0

PMD4/RE4

PMD3/RE3

RF0

SOSCI/CN1/RC13

OC1/RD0

IC3/PMCS2/RD10

IC2/RD9

IC1/RTCC/RD8

IC4/PMCS1/RD11

INT4/RA15

INT3/RA14

OSC2/CLKO/RC15

OSC1/CLKI/RC12

VDD

SCL1/RG2

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

SDA1/RG3

U1RX/RF2

U1TX/RF3

VSS

SOSCO/T1CK/CN0/RC14

PMA6/VREF+/RA10

PMA7/VREF-/RA9

AVDD

AVSS

C1OUT/AN8/RB8

C2OUT/AN9/RB9

PMA13/CVREF/AN10/RB10

PMA12/AN11/RB11

VDD

U2CTS/RF12

U2RTS/BCLK2/RF13

U1CTS/CN20/RD14

U1RTS/BCLK1/CN21/RD15

VDD

VSS

PGC2/EMUC2/AN6/OCFA/RB6

PGD2/EMUD2/AN7/RB7

PMA8/U2TX/CN18/RF5

PMA9/U2RX/CN17/RF4

PMD5/RE5

PMD6/RE6

PMD7/RE7

T2CK/RC1

T3CK/RC2

T4CK/RC3

T5CK/RC4

PMA5/SCK2/CN8/RG6

VDD

TMS/RA0

INT1/RE8

INT2/RE9

C1IN+/AN5/CN7/RB5

C1IN-/AN4/CN6/RB4

C2IN+/AN3/CN5/RB3

C2IN-/AN2/SS1/CN4/RB2

PMA4/SDI2/CN9/RG7

PMA3/SDO2/CN10/RG8

PGC1/EMUC1/AN1/CN3/RB1

PGD1/EMUD1/AN0/CN2/RB0

VDD

RG15

PMA2/SS2/CN11/RG9

MCLR

PMA11/AN12/RB12

PMA10/AN13/RB13

PMA1/AN14/RB14

PMA0/AN15/OCFB/CN12/RB15

RG1

RF1

ENVREG

CN15/RD6

TDO/RA5

SDA2/RA3

SCL2/RA2

VSS

VCAP/VDDCORE

TDI/RA4

TCK/RA1

100-Pin TQFP

CN16/RD7

PIC24FJXXGA010

PIC24FJXXXGA010

Legend: Shaded pins indicate pins that are tolerant to up to +5.5 VDC.

 2005-2012 Microchip Technology Inc. DS39747F-page 5

PIC24FJ128GA010 FAMILY

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 19

3.0 CPU............................................................................................................................................................................................ 25

4.0 Memory Organization ................................................................................................................................................................. 31

5.0 Flash Program Memory.............................................................................................................................................................. 51

6.0 Resets ........................................................................................................................................................................................ 57

7.0 Interrupt Controller ..................................................................................................................................................................... 63

8.0 Oscillator Configuration .............................................................................................................................................................. 97

9.0 Power-Saving Features............................................................................................................................................................ 105

10.0 I/O Ports ................................................................................................................................................................................... 107

11.0 Timer1 ...................................................................................................................................................................................... 111

12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 113

13.0 Input Capture............................................................................................................................................................................ 119

14.0 Output Compare....................................................................................................................................................................... 121

15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 127

16.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 137

17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 145

18.0 Parallel Master Port (PMP)....................................................................................................................................................... 153

19.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 163

20.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 175

21.0 10-bit High-Speed A/D Converter............................................................................................................................................. 179

22.0 Comparator Module.................................................................................................................................................................. 189

23.0 Comparator Voltage Reference................................................................................................................................................ 193

24.0 Special Features ...................................................................................................................................................................... 195

25.0 Instruction Set Summary.......................................................................................................................................................... 205

26.0 Development Support............................................................................................................................................................... 213

27.0 Electrical Characteristics.......................................................................................................................................................... 217

28.0 Packaging Information.............................................................................................................................................................. 231

Appendix A: Revision History............................................................................................................................................................. 245

Index ................................................................................................................................................................................................. 247

The Microchip Web Site ..................................................................................................................................................................... 251

Customer Change Notification Service .............................................................................................................................................. 251

Customer Support .............................................................................................................................................................................. 251

Reader Response .............................................................................................................................................................................. 252

Product Identification System ............................................................................................................................................................ 253

PIC24FJ128GA010 FAMILY

DS39747F-page 6  2005-2012 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We

welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer No tific atio n Syst em

 2005-2012 Microchip Technology Inc. DS39747F-page 7

PIC24FJ128GA010 FAMILY

1.0 DEVICE OVERVIEW

This document contains device-specific information for

the following devices:

• PIC24FJ64GA006

• PIC24FJ64GA008

• PIC24FJ64GA010

• PIC24FJ96GA006

• PIC24FJ96GA008

• PIC24FJ96GA010

• PIC24FJ128GA006

• PIC24FJ128GA008

• PIC24FJ128GA010

This family introduces a new line of Microchip devices:

a 16-bit microcontroller family with a broad peripheral

feature set and enhanced computational performance.

The PIC24FJ128GA010 family offers a new migration

option for those high-performance applications which

may be outgrowing their 8-bit platforms, but don’t

require the numerical processing power of a digital

signal processor.

1.1 Core Features

1.1.1 16-BIT ARCHITECTURE

Central to all PIC24F devices is the 16-bit modified

Harvard architecture, first introduced with Microchip’s

dsPIC® digital signal controllers. The PIC24F CPU core

offers a wide range of enhancements, such as:

• 16-bit data and 24-bit address paths, with the

ability to move information between data and

memory spaces

• Linear addressing of up to 8 Mbytes (program

space) and 64 Kbytes (data)

• A 16-element working register array with built-in

software stack support

• A 17 x 17 hardware multiplier with support for

integer math

• Hardware support for 32 by 16-bit division

• An instruction set that supports multiple

addressing modes and is optimized for high-level

languages such as ‘C’

• Operational performance up to 16 MIPS

1.1.2 POWER-SAVING TECHNOLOGY

All of the devices in the PIC24FJ128GA010 family

incorporate a range of features that can significantly

reduce power consumption during operation. Key

items include:

•On-the-Fly Clock Switching: The device clock

can be changed under software control to the

Timer1 source or the internal low-power RC

oscillator during operation, allowing the user to

incorporate power-saving ideas into their software

designs.

•Doze Mode Operation: When timing-sensitive

applications, such as serial communications,

require the uninterrupted operation of peripherals,

the CPU clock speed can be selectively reduced,

allowing incremental power savings without

missing a beat.

•Instruction-Bas ed Pow er-Saving Mod es: The

microcontroller can suspend all operations, or

selectively shut down its core while leaving its

peripherals active, with a single instruction in

software.

1.1.3 OSCILLATOR OPTIONS AND

FEATURES

All of the devices in the PIC24FJ128GA010 family offer

five different oscillator options, allowing users a range

of choices in developing application hardware. These

include:

• Two Crystal modes using crystals or ceramic

resonators.

• Two External Clock modes offering the option of a

divide-by-2 clock output.

• A Fast Internal Oscillator (FRC) with a nominal

8 MHz output, which can also be divided under

software control to provide clock speeds as low as

31 kHz.

• A Phase Lock Loop (PLL) frequency multiplier,

available to the external oscillator modes and the

FRC oscillator, which allows clock speeds of up to

32 MHz.

• A separate internal RC oscillator (LPRC) with a

fixed, 31 kHz output, which provides a low-power

option for timing-insensitive applications.

The internal oscillator block also provides a stable ref-

erence source for the Fail-Safe Clock Monitor. This

option constantly monitors the main clock source

against a reference signal provided by the internal

oscillator and enables the controller to switch to the

internal oscillator, allowing for continued low-speed

operation or a safe application shutdown.

PIC24FJ128GA010 FAMILY

DS39747F-page 8  2005-2012 Microchip Technology Inc.

1.1.4 EASY MIGRATION

Regardless of the memory size, all devices share the

same rich set of peripherals, allowing for a smooth

migration path as applications grow and evolve.

The consistent pinout scheme used throughout the

entire family also aids in migrating to the next larger

device. This is true when moving between devices with

the same pin count, or even jumping from 64-pin to

80-pin to 100-pin devices.

The PIC24F family is pin-compatible with devices in the

dsPIC33 family, and shares some compatibility with the

pinout schema for PIC18 and dsPIC30. This extends

the ability of applications to grow from the relatively

simple, to the powerful and complex, yet still selecting

a Microchip device.

1.2 O ther Special Features

•Communications: The PIC24FJ128GA010

family incorporates a range of serial communica-

tion peripherals to handle a range of application

requirements. All devices are equipped with two

independent UARTs with built-in IrDA

encoder/decoders. There are also two indepen-

dent SPI modules, and two independent I2C

modules that support both Master and Slave

modes of operation.

•Parallel Master/Enhanced Parallel Slave Port:

One of the general purpose I/O ports can be

reconfigured for enhanced parallel data communi-

cations. In this mode, the port can be configured

for both master and slave operations, and

supports 8-bit and 16-bit data transfers with up to

16 external address lines in Master modes.

•Real-Time Clock/Calendar: This module

implements a full-featured clock and calendar with

alarm functions in hardware, freeing up timer

resources and program memory space for use of

the core application.

•10-Bit A/D Converter: This module incorporates

programmable acquisition time, allowing for a

channel to be selected and a conversion to be

initiated without waiting for a sampling period, as

well as faster sampling speeds.

1.3 D etails on Individual Family

Members

Devices in the PIC24FJ128GA010 family are available

in 64-pin, 80-pin and 100-pin packages. The general

block diagram for all devices is shown in Figure 1-1.

The devices are differentiated from each other in two

ways:

1. Flash program memory (64 Kbytes for

PIC24FJ64GA devices, 96 Kbytes for

PIC24FJ96GA devices and 128 Kbytes for

PIC24FJ128GA devices).

2. Available I/O pins and ports (53 pins on 6 ports for

64-pin devices, 69 pins on 7 ports for 80-pin

devices and 84 pins on 7 ports for 100-pin

devices). Note also that, since interrupt-on-change

inputs are available on every I/O pin for this family

of devices, the number of CN inputs also differs

between package sizes.

All other features for devices in this family are identical.

These are summarized in Ta b l e 1 - 1 .

A list of the pin features available on the

PIC24FJ128GA010 family devices, sorted by function,

is shown in Ta b l e 1 -2. Note that this table shows the pin

location of individual peripheral features and not how

they are multiplexed on the same pin. This information

is provided in the pinout diagrams in the beginning of

the data sheet. Multiplexed features are sorted by the

priority given to a feature, with the highest priority

peripheral being listed first.

 2005-2012 Microchip Technology Inc. DS39747F-page 9

PIC24FJ128GA010 FAMILY

TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ128GA010 FAMILY

Features

PIC24FJ64GA006

PIC24FJ96GA006

PIC24FJ128GA006

PIC24FJ64GA008

PIC24FJ96GA008

PIC24FJ128GA008

PIC24FJ64GA010

PIC24FJ96GA010

PIC24FJ128GA010

Operating Frequency DC – 32 MHz

Program Memory (Bytes) 64K 96K 128K 64K 96K 128K 64K 96K 128K

Program Memory (Instructions) 22,016 32,768 44,032 22,016 32,768 44,032 22,016 32,768 44,032

Data Memory (Bytes) 8192

Interrupt Sources

(Soft Vectors/NMI Traps)

(39/4)

I/O Ports Ports B, C, D, E, F, G Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G

Total I/O Pins 53 69 84

Timers:

Total Number (16-bit) 5

32-Bit (from paired 16-bit timers) 2

Input Capture Channels 5

Output Compare/PWM

Channels

Input Change Notification

Interrupt

19 22

Serial Communications:

UART 2

SPI (3-wire/4-wire) 2

I2C™ 2

Parallel Communications

(PMP/PSP)

Yes

JTAG Boundary Scan Yes

10-Bit Analog-to-Digital Module

(input channels)

Analog Comparators 2

Resets (and Delays) POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, Configuration Word

Mismatch, REPEAT Instruction, Hardware Traps (PWRT, OST, PLL Lock)

Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations

Packages 64-Pin TQFP/QFN 80-Pin TQFP 100-Pin TQFP

PIC24FJ128GA010 FAMILY

DS39747F-page 10  2005-2012 Microchip Technology Inc.

FIGURE 1-1: PIC24FJ128G A0 10 FAMILY GENERAL BLOCK DIAGRAM

Instruction

Decode &

Control

PCL

Program Counter

16-Bit ALU

Data Bus

Inst Register

PCH

Divide

Support

Inst Latch

EA MUX

Read AGU

Write AGU

Interrupt

Controller

PSV & Table

Data Access

Control Block

Stack

Control

Logic

Repeat

Control

Logic

Data Latch

Data RAM

Address

Latch

Address Latch

Program Memory

Data Latch

Address Bus

Literal Data

Control Signals

16 x 16

W Reg Array

Multiplier

17x17

OSC1/CLKI

OSC2/CLKO

VDD,

Timing

Generation

VSS MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset(2)

Precision

Reference

Band Gap

FRC/LPRC

Oscillators

Regulator

Voltage

VDDCORE/VCAP

ENVREG

UART1/2

Comparators

Timer2/3Timer1 RTCC

IC1-5

A/D

10-Bit

PWM/ SPI1/2 I2C1/2

Timer4/5

PORTA(1)

PORTC

PORTD(1)

PORTE(1)

PORTF(1)

PORTG(1)

RA0:RA7,

RC1:RC4,

RD0:RD15

RE0:RE9

RF0:RF8,

RG0:RG9,

PORTB(1)

RB0:RB15

RA9:RA10,

RA14:15

RC12:RC15

RF12:RF13

RG12:RG15

Note 1: Not all pins or features are implemented on all device pinout configurations. See Ta b l e 1- 2 for I/O port pin descriptions.

2: BOR functionality is provided when the on-board voltage regulator is enabled.

PMP/PSP

OC1-5 CN1-22(1)

 2005-2012 Microchip Technology Inc. DS39747F-page 11

PIC24FJ128GA010 FAMILY

TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIP TION S

Function Pin Number I/O Input

Buffer Description

64-Pin 80-Pin 100-Pin

AN0 16 20 25 I ANA A/D Analog Inputs.

AN1151924IANA

AN2141823IANA

AN3131722IANA

AN4121621IANA

AN5 11 15 20 I ANA

AN6172126IANA

AN7182227IANA

AN8212732IANA

AN9222833IANA

AN10 23 29 34 I ANA

AN11 24 30 35 I ANA

AN12 27 33 41 I ANA

AN13 28 34 42 I ANA

AN14 29 35 43 I ANA

AN15 30 36 44 I ANA

AVDD 19 25 30 P — Positive Supply for Analog Modules.

AVSS 20 26 31 P — Ground Reference for Analog Modules.

BCLK1353848O—UART1 IrDA

® Baud Clock.

BCLK2293539O—UART2 IrDA

® Baud Clock.

C1IN- 12 16 21 I ANA Comparator 1 Negative Input.

C1IN+ 11 15 20 I ANA Comparator 1 Positive Input.

C1OUT 21 27 32 O — Comparator 1 Output.

C2IN- 14 18 23 I ANA Comparator 2 Negative Input.

C2IN+ 13 17 22 I ANA Comparator 2 Positive Input.

C2OUT 22 28 33 O — Comparator 2 Output.

CLKI 39 49 63 I ANA Main Clock Input Connection.

CLKO 40 50 64 O — System Clock Output.

CN0 48 60 74 I ST Interrupt-on-Change Inputs.

CN1475973IST

CN2162025IST

CN3151924IST

CN4141823IST

CN5131722IST

CN6121621IST

CN7 11 15 20 I ST

CN8 4 6 10 I ST

CN9 5 7 11 I ST

CN10 6 8 12 I ST

CN11 8 10 14 I ST

CN12303644IST

CN13526681IST

CN14536782IST

CN15546883IST

CN16556984IST

CN17313949IST

Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer

PIC24FJ128GA010 FAMILY

DS39747F-page 12  2005-2012 Microchip Technology Inc.

CN18 32 40 50 I ST Interrupt-on-Change Inputs.

CN19 — 65 80 I ST

CN20 — 37 47 I ST

CN21 — 38 48 I ST

CVREF 23 29 34 O ANA Comparator Voltage Reference Output.

EMUC1 15 19 24 I/O ST In-Circuit Emulator Clock Input/Output.

EMUD1 16 20 25 I/O ST In-Circuit Emulator Data Input/Output.

EMUC2 17 21 26 I/O ST In-Circuit Emulator Clock Input/Output.

EMUD2 18 22 27 I/O ST In-Circuit Emulator Data Input/Output.

ENVREG 57 71 86 I ST Enable for On-Chip Voltage Regulator.

IC1 42 54 68 I ST Input Capture Inputs.

IC2435569IST

IC3445670IST

IC4455771IST

IC5526479IST

INT0 35 45 55 I ST External Interrupt Inputs.

INT1 42 13 18 I ST

INT2 43 14 19 I ST

INT3 44 52 66 I ST

INT4 45 53 67 I ST

MCLR 7 9 13 I ST Master Clear (Device Reset) Input. This line is brought

low to cause a Reset.

OC1 46 58 72 O — Output Compare/PWM Outputs.

OC2496176O—

OC3506277O—

OC4516378O—

OC5526681O—

OCFA 17 21 26 I ST Output Compare Fault A Input.

OCFB 30 36 44 I ST Output Compare Fault B Input.

OSC1 39 49 63 I ANA Main Oscillator Input Connection.

OSC2 40 50 64 O ANA Main Oscillator Output Connection.

PGC1 15 19 24 I/O ST In-Circuit Debugger and ICSP™ Programming Clock.

PGD1 16 20 25 I/O ST In-Circuit Debugger and ICSP Programming Data.

PGC2 17 21 26 I/O ST In-Circuit Debugger and ICSP™ Programming Clock.

PGD2 18 22 27 I/O ST In-Circuit Debugger and ICSP Programming Data.

TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Function Pin Number I/O Input

Buffer Description

64-Pin 80-Pin 100-Pin

Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer

 2005-2012 Microchip Technology Inc. DS39747F-page 13

PIC24FJ128GA010 FAMILY

PMA0 30 36 44 I/O ST/TTL Parallel Master Port Address Bit 0 Input (Buffered Slave

modes) and Output (Master modes).

PMA1 29 35 43 I/O ST/TTL Parallel Master Port Address Bit 1 Input (Buffered Slave

modes) and Output (Master modes).

PMA2 8 10 14 O — Parallel Master Port Address (Demultiplexed Master

modes).

PMA3 6 8 12 O —

PMA4 5 7 11 O —

PMA5 4 6 10 O —

PMA6 16 24 29 O —

PMA7 22 23 28 O —

PMA8 32 40 50 O —

PMA9 31 39 49 O —

PMA10 28 34 42 O —

PMA11 27 33 41 O —

PMA12 24 30 35 O —

PMA13 23 29 34 O —

PMBE 51 63 78 O — Parallel Master Port Byte Enable Strobe.

PMCS1 45 57 71 I/O ST/TTL Parallel Master Port Chip Select 1 Strobe/Address bit 14.

PMCS2 44 56 70 O — Parallel Master Port Chip Select 2 Strobe/Address bit 15.

PMD0 60 76 93 I/O ST/TTL Parallel Master Port Data (Demultiplexed Master mode)

or Address/Data (Multiplexed Master modes).

PMD1 61 77 94 I/O ST/TTL

PMD2 62 78 98 I/O ST/TTL

PMD3 63 79 99 I/O ST/TTL

PMD4 64 80 100 I/O ST/TTL

PMD5 1 1 3 I/O ST/TTL

PMD6 2 2 4 I/O ST/TTL

PMD7 3 3 5 I/O ST/TTL

PMRD 53 67 82 I/O ST/TTL Parallel Master Port Read Strobe.

PMWR 52 66 81 I/O ST/TTL Parallel Master Port Write Strobe.

TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Function Pin Number I/O Input

Buffer Description

64-Pin 80-Pin 100-Pin

Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer

PIC24FJ128GA010 FAMILY

DS39747F-page 14  2005-2012 Microchip Technology Inc.

RA0 — — 17 I/O ST PORTA Digital I/O.

RA1 — — 38 I/O ST

RA2 — — 58 I/O ST

RA3 — — 59 I/O ST

RA4 — — 60 I/O ST

RA5 — — 61 I/O ST

RA6 — — 91 I/O ST

RA7 — — 92 I/O ST

RA9 — 23 28 I/O ST

RA10 — 24 29 I/O ST

RA14 — 52 66 I/O ST

RA15 — 53 67 I/O ST

RB0 16 20 25 I/O ST PORTB Digital I/O.

RB1151924I/OST

RB2141823I/OST

RB3131722I/OST

RB4121621I/OST

RB5 11 15 20 I/O ST

RB6172126I/OST

RB7182227I/OST

RB8212732I/OST

RB9222833I/OST

RB10 23 29 34 I/O ST

RB11 24 30 35 I/O ST

RB12 27 33 41 I/O ST

RB13 28 34 42 I/O ST

RB14 29 35 43 I/O ST

RB15 30 36 44 I/O ST

RC1 — 4 6 I/O ST PORTC Digital I/O.

RC2 — — 7 I/O ST

RC3 — 5 8 I/O ST

RC4 — — 9 I/O ST

RC12394963I/OST

RC13475973I/OST

RC14486074I/OST

RC15405064I/OST

TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Function Pin Number I/O Input

Buffer Description

64-Pin 80-Pin 100-Pin

Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer

 2005-2012 Microchip Technology Inc. DS39747F-page 15

PIC24FJ128GA010 FAMILY

RD0 46 58 72 I/O ST PORTD Digital I/O.

RD1496176I/OST

RD2506277I/OST

RD3516378I/OST

RD4526681I/OST

RD5536782I/OST

RD6546883I/OST

RD7556984I/OST

RD8425468I/OST

RD9435569I/OST

RD10445670I/OST

RD11 45 57 71 I/O ST

RD12 — 64 79 I/O ST

RD13 — 65 80 I/O ST

RD14 — 37 47 I/O ST

RD15 — 38 48 I/O ST

RE0 60 76 93 I/O ST PORTE Digital I/O.

RE1617794I/OST

RE2627898I/OST

RE3637999I/OST

RE4 64 80 100 I/O ST

RE5 1 1 3 I/O ST

RE6 2 2 4 I/O ST

RE7 3 3 5 I/O ST

RE8 — 13 18 I/O ST

RE9 — 14 19 I/O ST

RF0 58 72 87 I/O ST PORTF Digital I/O.

RF1597388I/OST

RF2344252I/OST

RF3334151I/OST

RF4313949I/OST

RF5324050I/OST

RF6354555I/OST

RF7 — 44 54 I/O ST

RF8 — 43 53 I/O ST

RF12 — — 40 I/O ST

RF13 — — 39 I/O ST

TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Function Pin Number I/O Input

Buffer Description

64-Pin 80-Pin 100-Pin

Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer

PIC24FJ128GA010 FAMILY

DS39747F-page 16  2005-2012 Microchip Technology Inc.

RG0 — 75 90 I/O ST PORTG Digital I/O.

RG1 — 74 89 I/O ST

RG2374757I/OST

RG3364656I/OST

RG6 4 6 10 I/O ST

RG7 5 7 11 I/O ST

RG8 6 8 12 I/O ST

RG9 8 10 14 I/O ST

RG12 — — 96 I/O ST

RG13 — — 97 I/O ST

RG14 — — 95 I/O ST

RG15 — — 1 I/O ST

RTCC 42 54 68 O — Real-Time Clock Alarm Output.

SCK1 35 45 55 O — SPI1 Serial Clock Output.

SCK2 4 6 10 I/O ST SPI2 Serial Clock Output.

SCL1 37 47 57 I/O I2C I2C1 Synchronous Serial Clock Input/Output.

SCL2 32 52 58 I/O I2C I2C2 Synchronous Serial Clock Input/Output.

SDA1 36 46 56 I/O I2C I2C1 Data Input/Output.

SDA2 31 53 59 I/O I2C I2C2 Data Input/Output.

SDI1 34 44 54 I ST SPI1 Serial Data Input.

SDI2 5 7 11 I ST SPI2 Serial Data Input.

SDO1 33 43 53 O — SPI1 Serial Data Output.

SDO2 6 8 12 O — SPI2 Serial Data Output.

SOSCI 47 59 73 I ANA Secondary Oscillator/Timer1 Clock Input.

SOSCO 48 60 74 O ANA Secondary Oscillator/Timer1 Clock Output.

SS1 14 18 23 I/O ST Slave Select Input/Frame Select Output (SPI1).

SS2 8 10 14 I/O ST Slave Select Input/Frame Select Output (SPI2).

T1CK 48 60 74 I ST Timer1 Clock.

T2CK — 4 6 I ST Timer2 External Clock Input.

T3CK — — 7 I ST Timer3 External Clock Input.

T4CK — 5 8 I ST Timer4 External Clock Input.

T5CK — — 9 I ST Timer5 External Clock Input.

TCK 27 33 38 I ST JTAG Test Clock/Programming Clock Input.

TDI 28 34 60 I ST JTAG Test Data/Programming Data Input.

TDO 24 14 61 O — JTAG Test Data Output.

TMS 23 13 17 I ST JTAG Test Mode Select Input.

TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Function Pin Number I/O Input

Buffer Description

64-Pin 80-Pin 100-Pin

Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer

 2005-2012 Microchip Technology Inc. DS39747F-page 17

PIC24FJ128GA010 FAMILY

U1CTS 43 37 47 I ST UART1 Clear-to-Send Input.

U1RTS 35 38 48 O — UART1 Request-to-Send Output.

U1RX 34 42 52 I ST UART1 Receive.

U1TX 33 41 51 O DIG UART1 Transmit Output.

U2CTS 21 27 40 I ST UART2 Clear-to-Send Input.

U2RTS 29 35 39 O — UART2 Request-to-Send Output.

U2RX 31 39 49 I ST UART 2 Receive Input.

U2TX 32 40 50 O — UART2 Transmit Output.

VDD 10, 26, 38 12, 32, 48 2, 16, 37,

46, 62

P — Positive Supply for Peripheral Digital Logic and I/O Pins.

VDDCAP 56 70 85 P — External Filter Capacitor Connection (regulator is

enabled).

VDDCORE 56 70 85 P — Positive Supply for Microcontroller Core Logic (regulator

is disabled).

VREF- 15 23 28 I ANA A/D and Comparator Reference Voltage (Low) Input.

VREF+ 16 24 29 I ANA A/D and Comparator Reference Voltage (High) Input.

VSS 9, 25, 41 11, 31, 51 15, 36, 45,

65, 75

P — Ground Reference for Logic and I/O Pins.

TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Function Pin Number I/O Input

Buffer Description

64-Pin 80-Pin 100-Pin

Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer

PIC24FJ128GA010 FAMILY

DS39747F-page 18  2005-2012 Microchip Technology Inc.

NOTES:

 2005-2012 Microchip Technology Inc. DS39747F-page 19

PIC24FJ128GA010 FAMILY

2.0 GUIDELINES FOR GETTING

STARTED WITH 16-BIT

MICROCONTROLLERS

2.1 Basic Connection Requirements

Getting started with the PIC24FJ128GA010 family

family of 16-bit microcontrollers requires attention to a

minimal set of device pin connections before

proceeding with development.

The following pins must always be connected:

•All V

DD and VSS pins

(see Section 2.2 “Power Supply Pins”)

•All AV

DD and AVSS pins, regardless of whether or

not the analog device features are used

(see Section 2.2 “Power Supply Pins”)

•MCLR

(see Section 2.3 “Master Clear (MCLR) Pin” )

• ENVREG/DISVREG and VCAP/VDDCORE pins

(PIC24F J devices only)

(see Section 2.4 “Voltage Regulator Pins

(ENVREG/DISVREG and VCAP/VDDCORE)”)

These pins must also be connected if they are being

used in the end application:

• PGECx/PGEDx pins used for In-Circuit Serial

Programming™ (ICSP™) and debugging purposes

(see Section 2.5 “ICSP Pins”)

• OSCI and OSCO pins when an external oscillator

source is used

(see Section 2.6 “External Oscillator Pins”)

Additionally, the following pins may be required:

•V

REF+/VREF- pins used when external voltage

reference for analog modules is implemented

The minimum mandatory connections are shown in

Figure 2-1.

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECTIONS

Note: The AVDD and AVSS pins must always be

connected, regardless of whether any of

the analog modules are being used.

PIC24FJXXXX

VDD

VSS

VDD

VSS

VDD

AVDD

AVSS

VDD

VSS

VDD

MCLR

VCAP/VDDCORE

R2 (EN/DIS)VREG

(1)

C2(2)

C3(2)

C4(2)

C5(2)

C6(2)

Key (all values are recommendations):

C1 through C6: 0.1 F, 20V ceramic

C7: 10 F, 6.3V or greater, tantalum or ceramic

R1: 10 kΩ

R2: 100Ω to 470Ω

Note 1: See Secti on 2.4 “Voltage Regulat or Pins

(ENVREG/DISVREG and VCAP/VDDCORE)”

for explanation of ENVREG/DISVREG pin

connections.

2: The example shown is for a PIC24F device

with five VDD/VSS and AVDD/AVSS pairs.

Other devices may have more or less pairs;

adjust the number of decoupling capacitors

appropriately.

(1)

PIC24FJ128GA010 FAMILY

DS39747F-page 20  2005-2012 Microchip Technology Inc.

2.2 Power Supply Pins

2.2.1 DECOUPLING CAPACITORS

The use of decoupling capacitors on every pair of

power supply pins, such as VDD, VSS, AVDD and

AVSS is required.

Consider the following criteria when using decoupling

capacitors:

•Value and type of capacitor: A 0.1 F (100 nF),

10-20V capacitor is recommended. The capacitor

should be a low-ESR device with a resonance

frequency in the range of 200 MHz and higher.

Ceramic capacitors are recommended.

•Placement on the printed circuit board: The

decoupling capacitors should be placed as close

to the pins as possible. It is recommended to

place the capacitors on the same side of the

board as the device. If space is constricted, the

capacitor can be placed on another layer on the

PCB using a via; however, ensure that the trace

length from the pin to the capacitor is no greater

than 0.25 inch (6 mm).

•Handling high-frequency noise: If the board is

experiencing high-frequency noise (upward of

tens of MHz), add a second ceramic type capaci-

tor in parallel to the above described decoupling

capacitor. The value of the second capacitor can

be in the range of 0.01 F to 0.001 F. Place this

second capacitor next to each primary decoupling

capacitor. In high-speed circuit designs, consider

implementing a decade pair of capacitances as

close to the power and ground pins as possible

(e.g., 0.1 F in parallel with 0.001 F).

•Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first,

and then to the device pins. This ensures that the

decoupling capacitors are first in the power chain.

Equally important is to keep the trace length

between the capacitor and the power pins to a

minimum, thereby reducing PCB trace

inductance.

2.2.2 TANK CAPACITORS

On boards with power traces running longer than six

inches in length, it is suggested to use a tank capacitor

for integrated circuits including microcontrollers to

supply a local power source. The value of the tank

capacitor should be determined based on the trace

resistance that connects the power supply source to

the device, and the maximum current drawn by the

device in the application. In other words, select the tank

capacitor so that it meets the acceptable voltage sag at

the device. Typical values range from 4.7 F to 47 F.

2.3 M aster Clear (MCLR) Pin

The MCLR pin provides two specific device

functions: device Reset, and device programming

and debugging. If programming and debugging are

not required in the end application, a direct

connection to VDD may be all that is required. The

addition of other components, to help increase the

application’s resistance to spurious Resets from

voltage sags, may be beneficial. A typical

configuration is shown in Figure 2-1. Other circuit

designs may be implemented, depending on the

application’s requirements.

During programming and debugging, the resistance

and capacitance that can be added to the pin must

be considered. Device programmers and debuggers

drive the MCLR pin. Consequently, specific voltage

levels (VIH and VIL) and fast signal transitions must

not be adversely affected. Therefore, specific values

of R1 and C1 will need to be adjusted based on the

application and PCB requirements. For example, it is

recommended that the capacitor, C1, be isolated

from the MCLR pin during programming and

debugging operations by using a jumper (Figure 2-2).

The jumper is replaced for normal run-time

operations.

Any components associated with the MCLR pin

should be placed within 0.25 inch (6 mm) of the pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN

CONNECTIONS

Note 1: R1  10 k is recommended. A suggested

starting value is 10 k. Ensure that the

MCLR pin VIH and VIL specifications are met.

2: R2  470 will limit any current flowing into

MCLR from the external capacitor, C, in the

event of MCLR pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS). Ensure that the MCLR pin

VIH and VIL specifications are met.

VDD

MCLR

PIC24FXXXX

 2005-2012 Microchip Technology Inc. DS39747F-page 21

PIC24FJ128GA010 FAMILY

2.4 Voltage Regulator Pins

(ENVREG/DISVREG and

VCAP/VDDCORE)

The on-chip voltage regulator enable/disable pin

(ENVREG or DISVREG, depending on the device

family) must always be connected directly to either a

supply voltage or to ground. The particular connection

is determined by whether or not the regulator is to be

used:

• For ENVREG, tie to VDD to enable the regulator,

or to ground to disable the regulator

• For DISVREG, tie to ground to enable the

regulator or to VDD to disable the regulator

Refer to Section 24.2 “On-Chip Voltage Regulator”

for details on connecting and using the on-chip

regulator.

When the regulator is enabled, a low-ESR (< 5Ω)

capacitor is required on the VCAP/VDDCORE pin to

stabilize the voltage regulator output voltage. The

VCAP/VDDCORE pin must not be connected to VDD and

must use a capacitor of 10 µF connected to ground. The

type can be ceramic or tantalum. Suitable examples of

capacitors are shown in Ta ble 2-1. Capacitors with

equivalent specification can be used.

Designers may use Figure 2-3 to evaluate ESR

equivalence of candidate devices.

The placement of this capacitor should be close to

VCAP/VDDCORE. It is recommended that the trace

length not exceed 0.25 inch (6 mm). Refer to

Section 27.0 “Electrical Characteristics” for

additional information.

When the regulator is disabled, the VCAP/VDDCORE pin

must be tied to a voltage supply at the VDDCORE level.

Refer to Section 27.0 “Electrical Characte ristics” for

information on VDD and VDDCORE.

FIGURE 2-3: FREQUENCY vs. ESR

PERFORMANCE FOR

SUGGESTED VCAP

Note: This section applies only to PIC24F J

devices with an on-chip voltage regulator.

0.1

0.01

0.001 0.01 0.1 1 10 100 1000 10,000

Frequ en cy (MH z)

ESR ()

Note: Typical data measurement at 25°C, 0V DC bias.

TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS

Make Part # Nominal

Capacitance Base Tolerance Rated Voltage Temp. Range

TDK C3216X7R1C106K 10 µF ±10% 16V -55 to 125ºC

TDK C3216X5R1C106K 10 µF ±10% 16V -55 to 85ºC

Panasonic ECJ-3YX1C106K 10 µF ±10% 16V -55 to 125ºC

Panasonic ECJ-4YB1C106K 10 µF ±10% 16V -55 to 85ºC

Murata GRM32DR71C106KA01L 10 µF ±10% 16V -55 to 125ºC

Murata GRM31CR61C106KC31L 10 µF ±10% 16V -55 to 85ºC

PIC24FJ128GA010 FAMILY

DS39747F-page 22  2005-2012 Microchip Technology Inc.

2.4.1 CONSIDERATIONS FOR CERAMIC

CAPACITORS

In recent years, large value, low-voltage, surface-mount

ceramic capacitors have become very cost effective in

sizes up to a few tens of microfarad. The low-ESR, small

physical size and other properties make ceramic

capacitors very attractive in many types of applications.

Ceramic capacitors are suitable for use with the inter-

nal voltage regulator of this microcontroller. However,

some care is needed in selecting the capacitor to

ensure that it maintains sufficient capacitance over the

intended operating range of the application.

Typical low-cost, 10 F ceramic capacitors are available

in X5R, X7R and Y5V dielectric ratings (other types are

also available, but are less common). The initial toler-

ance specifications for these types of capacitors are

often specified as ±10% to ±20% (X5R and X7R), or

-20%/+80% (Y5V). However, the effective capacitance

that these capacitors provide in an application circuit will

also vary based on additional factors, such as the

applied DC bias voltage and the temperature. The total

in-circuit tolerance is, therefore, much wider than the

initial tolerance specification.

The X5R and X7R capacitors typically exhibit satisfac-

tory temperature stability (ex: ±15% over a wide

temperature range, but consult the manufacturer's data

sheets for exact specifications). However, Y5V capaci-

tors typically have extreme temperature tolerance

specifications of +22%/-82%. Due to the extreme tem-

perature tolerance, a 10 F nominal rated Y5V type

capacitor may not deliver enough total capacitance to

meet minimum internal voltage regulator stability and

transient response requirements. Therefore, Y5V

capacitors are not recommended for use with the

internal regulator if the application must operate over a

wide temperature range.

In addition to temperature tolerance, the effective

capacitance of large value ceramic capacitors can vary

substantially, based on the amount of DC voltage

applied to the capacitor. This effect can be very signifi-

cant, but is often overlooked or is not always

documented.

Typical DC bias voltage vs. capacitance graph for X7R

type capacitors is shown in Figure 2-4.

FIGURE 2-4: DC BIAS VOLTAGE vs.

CAPACITANCE

CHARACTERISTICS

When selecting a ceramic capacitor to be used with the

internal voltage regulator, it is suggested to select a

high-voltage rating, so that the operating voltage is a

small percentage of the maximum rated capacitor volt-

age. For example, choose a ceramic capacitor rated at

16V for the 2.5V or 1.8V core voltage. Suggested

capacitors are shown in Table 2-1.

2.5 ICSP Pins

The PGECx and PGEDx pins are used for In-Circuit

Serial Programming (ICSP) and debugging purposes.

It is recommended to keep the trace length between

the ICSP connector and the ICSP pins on the device as

short as possible. If the ICSP connector is expected to

experience an ESD event, a series resistor is recom-

mended, with the value in the range of a few tens of

ohms, not to exceed 100Ω.

Pull-up resistors, series diodes and capacitors on the

PGECx and PGEDx pins are not recommended as they

will interfere with the programmer/debugger communi-

cations to the device. If such discrete components are

an application requirement, they should be removed

from the circuit during programming and debugging.

Alternatively, refer to the AC/DC characteristics and

timing requirements information in the respective

device Flash programming specification for information

on capacitive loading limits and pin input voltage high

(VIH) and input low (VIL) requirements.

For device emulation, ensure that the “Communication

Channel Select” (i.e., PGECx/PGEDx pins),

programmed into the device, matches the physical

connections for the ICSP to the Microchip

debugger/emulator tool.

For more information on available Microchip

development tools connection requirements, refer to

Section 26.0 “Development Support”.

-80

-70

-60

-50

-40

-30

-20

-10

5 1011121314151617

DC Bias Voltage (VDC)

Capacitance Change (%)

01234 6789

16V Capacitor

10V Capacitor

6.3V Capacitor

 2005-2012 Microchip Technology Inc. DS39747F-page 23

PIC24FJ128GA010 FAMILY

2.6 External Oscillator Pins

Many microcontrollers have options for at least two

oscillators: a high-frequency primary oscillator and a

low-frequency secondary oscillator (refer to

Section 8.0 “Oscillator Configuration” for details).

The oscillator circuit should be placed on the same

side of the board as the device. Place the oscillator

circuit close to the respective oscillator pins with no

more than 0.5 inch (12 mm) between the circuit

components and the pins. The load capacitors should

be placed next to the oscillator itself, on the same side

of the board.

Use a grounded copper pour around the oscillator cir-

cuit to isolate it from surrounding circuits. The

grounded copper pour should be routed directly to the

MCU ground. Do not run any signal traces or power

traces inside the ground pour. Also, if using a two-sided

board, avoid any traces on the other side of the board

where the crystal is placed.

Layout suggestions are shown in Figure 2-5. In-line

packages may be handled with a single-sided layout

that completely encompasses the oscillator pins. With

fine-pitch packages, it is not always possible to com-

pletely surround the pins and components. A suitable

solution is to tie the broken guard sections to a mirrored

ground layer. In all cases, the guard trace(s) must be

returned to ground.

In planning the application’s routing and I/O assign-

ments, ensure that adjacent port pins, and other

signals in close proximity to the oscillator, are benign

(i.e., free of high frequencies, short rise and fall times

and other similar noise).

For additional information and design guidance on

oscillator circuits, please refer to these Microchip

Application Notes, available at the corporate web site

(www.microchip.com):

• AN826, “Crystal Oscillator Basics and Crystal

Selection for rfPIC™ and PICmicro® Device s”

• AN849, “Basic PICmicro® Oscillator Design”

• AN943, “Practical PICmicro® Oscillator Analysis

and Design”

•AN949, “Ma king Your Oscillator Work”

FIGURE 2-5: SUGGESTED

PLACEMENT OF THE

OSCILLATOR CIRCUIT

GND

OSCI

OSCO

SOSCO

SOSC I

Copper Pour Primary Oscillator

Crystal

Secondary

Crystal

DEVICE PINS

Primary

Oscillator

Sec Oscillator: C1 Sec Oscillator: C2

(tied to ground)

GND

OSCO

OSCI

Bottom Layer

Copper Pour

Oscillator

Crystal

Top Layer Copper Pour

DEVICE PINS

(tied to ground)

Single-Sided and In-line Layou ts:

Fine-Pitch (Dual-Sided) Layouts:

Oscillator

PIC24FJ128GA010 FAMILY

DS39747F-page 24  2005-2012 Microchip Technology Inc.

2.7 C onfigurati on of Analog and

Digital Pins During ICSP

Operations

If an ICSP compliant emulator is selected as a debug-

ger, it automatically initializes all of the A/D input pins

(ANx) as “digital” pins. Depending on the particular

device, this is done by setting all bits in the ADnPCFG

All PIC24F devices will have either one or more

ADnPCFG registers or several ANSx registers (one for

each port); no device will have both. Refer to

Section 2 1.0 “10-bit High-Speed A/D Converter” for

more specific information.

The bits in these registers that correspond to the A/D

pins that initialized the emulator must not be changed

by the user application firmware; otherwise,

communication errors will result between the debugger

and the device.

If your application needs to use certain A/D pins as

analog input pins during the debug session, the user

application must modify the appropriate bits during

initialization of the A/D module, as follows:

• For devices with an ADnPCFG register, clear the

bits corresponding to the pin(s) to be configured

as analog. Do not change any other bits, particu-

larly those corresponding to the PGECx/PGEDx

pair, at any time.

• For devices with ANSx registers, set the bits

corresponding to the pin(s) to be configured as

analog. Do not change any other bits, particularly

those corresponding to the PGECx/PGEDx pair,

at any time.

When a Microchip debugger/emulator is used as a

programmer, the user application firmware must

correctly configure the ADnPCFG or ANSx registers.

Automatic initialization of this register is only done

during debugger operation. Failure to correctly

configure the register(s) will result in all A/D pins being

recognized as analog input pins, resulting in the port

value being read as a logic '0', which may affect user

application functionality.

2.8 U nused I/Os

Unused I/O pins should be configured as outputs and

driven to a logic low state. Alternatively, connect a 1 kΩ

to 10 kΩ resistor to VSS on unused pins and drive the

output to logic low.

 2005-2012 Microchip Technology Inc. DS39747F-page 25

PIC24FJ128GA010 FAMILY

3.0 CPU

The PIC24F CPU has a 16-bit (data) modified Harvard

architecture with an enhanced instruction set, and a

24-bit instruction word with a variable length opcode

field. The Program Counter (PC) is 23 bits wide and

addresses up to 4M instructions of user program

memory space. A single-cycle instruction prefetch

mechanism is used to help maintain throughput and

provides predictable execution. All instructions execute

in a single cycle, with the exception of instructions that

change the program flow, the double-word move

(MOV.D) instruction and the table instructions.

Overhead-free program loop constructs are supported

using the REPEAT instructions, which are interruptible

at any point.

PIC24F devices have sixteen 16-bit working registers

in the programmer’s model. Each of the working

registers can act as a data, address or address offset

a Software Stack Pointer for interrupts and calls.

The upper 32 Kbytes of the data space memory map

can optionally be mapped into program space at any

16K word boundary defined by the 8-bit Program

Space Visibility Page (PSVPAG) register. The program

to data space mapping feature lets any instruction

access program space as if it were data space.

The Instruction Set Architecture (ISA) has been signifi-

cantly enhanced beyond that of the PIC18, but

maintains an acceptable level of backward compatibility.

All PIC18 instructions and addressing modes are

supported either directly or through simple macros.

Many of the ISA enhancements have been driven by

compiler efficiency needs.

The core supports Inherent (no operand), Relative,

Literal, Memory Direct and three groups of addressing

modes. All modes support Register Direct and various

7 addressing modes. Instructions are associated with

predefined addressing modes depending upon their

functional requirements.

For most instructions, the core is capable of executing

a data (or program data) memory read, a working reg-

ister (data) read, a data memory write and a program

(instruction) memory read per instruction cycle. As a

result, three parameter instructions can be supported,

allowing trinary operations (that is, A + B = C) to be

executed in a single cycle.

A high-speed, 17-bit by 17-bit multiplier has been

included to significantly enhance the core arithmetic

capability and throughput. The multiplier supports

signed, unsigned and Mixed mode 16-bit by 16-bit or

8-bit by 8-bit integer multiplication. All multiply

instructions execute in a single cycle.

The 16-bit ALU has been enhanced with integer divide

assist hardware that supports an iterative, non-restoring

divide algorithm. It operates in conjunction with the

REPEAT instruction looping mechanism, and a selection

of iterative divide instructions, to support 32-bit (or

16-bit) divided by 16-bit integer signed and unsigned

division. All divide operations require 19 cycles to

complete but are interruptible at any cycle boundary.

The PIC24F has a vectored exception scheme with up

to 8 sources of non-maskable traps and up to

118 interrupt sources. Each interrupt source can be

assigned to one of seven priority levels.

A block diagram of the CPU is shown in Figure 3-1.

3.1 Programmer’s Model

The programmer’s model for the PIC24F is shown in

Figure 3-2. All registers in the programmer’s model are

memory mapped and can be manipulated directly by

instructions. A description of each register is provided

in Ta b l e 3 - 1 . All registers associated with the

programmer’s model are memory mapped.

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 2. “CPU”

(DS39703) in the “PIC24F Family Reference

Manual” for more information.

PIC24FJ128GA010 FAMILY

DS39747F-page 26  2005-2012 Microchip Technology Inc.

FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM

Instruction

Decode &

Control

PCL

Program Counter

16-Bit ALU

Data Bus

Instruction Reg

PCH

16 x 16

W Register Array

Divide

Support

ROM Latch

EA MUX

RAGU

WAGU

Interrupt

Controller

Stack

Control

Logic

Loop

Control

Logic

Data Latch

Data RAM

Address

Latch

Control Signals

to Various Blocks

Program Memory

Data Latch

Address Bus

Literal Data

16 16

Hardware

Multiplier

To Peripheral Modules

Address Latch

PSV & Table

Data Access

Control Block

 2005-2012 Microchip Technology Inc. DS39747F-page 27

PIC24FJ128GA010 FAMILY

TABLE 3-1: CPU CORE REGISTERS

FIGURE 3-2: PROGRAMME R’S MODEL

W0 through W15 Working Register Array

PC 23-Bit Program Counter

SR ALU STATUS Register

SPLIM Stack Pointer Limit Value Register

TBLPAG Table Memory Page Address Register

PSVPAG Program Space Visibility Page Address Register

RCOUNT Repeat Loop Counter Register

CORCON CPU Control Register

NOVZ C

TBLPAG

22 0

7 0

015

Program Counter

Data Table Page Address

STATUS Register (SR)

Working/Address

Registers

W0 (WREG)

W10

W11

W12

W13

Frame Pointer

Stack Pointer

PSVPAG

7 0 Program Space Visibility

RCOUNT

15 0

Repeat Loop Counter

SPLIM Stack Pointer Limit

SRL

Registers or bits are shadowed for PUSH.S and POP.S instructions.

Page Address

15 0

Core Control Register (CORCON)

SRH

W14

W15

DC IPL

210

———————

IPL3 PSV

————————————

——

Divider Working Registers

Multiplier Registers

15 0

PIC24FJ128GA010 FAMILY

DS39747F-page 28  2005-2012 Microchip Technology Inc.

3.2 CPU Control Registers

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —DC

bit 15 bit 8

R/W-0(1)R/W-0(1)R/W-0(1)R-0 R/W-0 R/W-0 R/W-0 R/W-0

IPL2(2)IPL1(2)IPL0(2)RA N OV Z C

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-9 Unimplemented: Read as ‘0’

bit 8 DC: ALU Half Carry/Borrow bit

1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)

of the result occurred

0 = No carry-out from the 4th or 8th low-order bit of the result has occurred

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2)

111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled

110 = CPU Interrupt Priority Level is 6 (14)

101 = CPU Interrupt Priority Level is 5 (13)

100 = CPU Interrupt Priority Level is 4 (12)

011 = CPU Interrupt Priority Level is 3 (11)

010 = CPU Interrupt Priority Level is 2 (10)

001 = CPU Interrupt Priority Level is 1 (9)

000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit

1 = REPEAT loop in progress

0 = REPEAT loop not in progress

bit 3 N: ALU Negative bit

1 = Result was negative

0 = Result was non-negative (zero or positive)

bit 2 OV: ALU Overflow bit

1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation

0 = No overflow has occurred

bit 1 Z: ALU Zero bit

1 = An operation, which effects the Z bit, has set it at some time in the past

0 = The most recent operation, which effects the Z bit, has cleared it (i.e., a non-zero result)

bit 0 C: ALU Carry/Borrow bit

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

2: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority Level.

The value in parentheses indicates the IPL when IPL3 = 1.

 2005-2012 Microchip Technology Inc. DS39747F-page 29

PIC24FJ128GA010 FAMILY

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0

— — — —IPL3

(1)PSV — —

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-4 Unimplemented: Read as ‘0’

bit 3 IPL3: CPU Interrupt Priority Level Status bit(1)

1 = CPU Interrupt Priority Level is greater than 7

0 = CPU Interrupt Priority Level is 7 or less

bit 2 PSV: Program Space Visibility in Data Space Enable bit

1 = Program space is visible in data space

0 = Program space is not visible in data space

bit 1-0 Unimplemented: Read as ‘0’

Note 1: User interrupts are disabled when IPL3 = 1.

PIC24FJ128GA010 FAMILY

DS39747F-page 30  2005-2012 Microchip Technology Inc.

3.3 A rithmetic Logic Unit (ALU)

The PIC24F ALU is 16 bits wide and is capable of addi-

tion, subtraction, bit shifts and logic operations. Unless

otherwise mentioned, arithmetic operations are 2’s

complement in nature. Depending on the operation, the

ALU may affect the values of the Carry (C), Zero (Z),

Negative (N), Overflow (OV) and Digit Carry (DC)

Status bits in the SR register. The C and DC Status bits

operate as Borrow and Digit Borrow bits, respectively,

for subtraction operations.

The ALU can perform 8-bit or 16-bit operations,

depending on the mode of the instruction that is used.

Data for the ALU operation can come from the W

addressing mode of the instruction. Likewise, output

data from the ALU can be written to the W register array

or a data memory location.

The PIC24F CPU incorporates hardware support for

both multiplication and division. This includes a dedi-

cated hardware multiplier and support hardware for

16-bit divisor division.

3.3.1 MULTIPLIER

The ALU contains a high-speed, 17-bit x 17-bit

multiplier. It supports unsigned, signed or mixed sign

operation in several multiplication modes:

1. 16-bit x 16-bit signed

2. 16-bit x 16-bit unsigned

3. 16-bit signed x 5-bit (literal) unsigned

4. 16-bit unsigned x 16-bit unsigned

5. 16-bit unsigned x 5-bit (literal) unsigned

6. 16-bit unsigned x 16-bit signed

7. 8-bit unsigned x 8-bit unsigned

3.3.2 DIVIDER

The divide block supports 32-bit/16-bit and 16-bit/16-bit

signed and unsigned integer divide operation with the

following data sizes:

1. 32-bit signed/16-bit signed divide

2. 32-bit unsigned/16-bit unsigned divide

3. 16-bit signed/16-bit signed divide

4. 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0

and the remainder in W1. 16-bit signed and unsigned

DIV instructions can specify any W register for both the

16-bit divisor (Wn) and any W register (aligned) pair

(W(m+1):Wm) for the 32-bit dividend. The divide algo-

rithm takes one cycle per bit of divisor, so both

32-bit/16-bit and 16-bit/16-bit instructions take the

same number of cycles to execute.

3.3.3 MULTI-BIT SHIFT SUPPORT

The PIC24F ALU supports both single bit and

single-cycle, multi-bit arithmetic and logic shifts.

Multi-bit shifts are implemented using a shifter block,

capable of performing up to a 15-bit arithmetic right

shift, or up to a 15-bit left shift, in a single cycle. All

multi-bit shift instructions only support Register Direct

Addressing for both the operand source and result

destination.

A full summary of instructions that use the shift

operation is provided below in Tabl e 3 - 2.

TABLE 3-2: INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION

Instruction Description

ASR Arithmetic shift right source register by one or more bits.

SL Shift left source register by one or more bits.

LSR Logical shift right source register by one or more bits.

 2005-2012 Microchip Technology Inc. DS39747F-page 31

PIC24FJ128GA010 FAMILY

4.0 MEMORY ORGANIZATION

As Harvard architecture devices, PIC24F micro-

controllers feature separate program and data memory

spaces and busses. This architecture also allows the

direct access of program memory from the data space

during code execution.

4.1 Program Address Space

The program address memory space of

PIC24FJ128GA010 family devices is 4M instructions.

The space is addressable by a 24-bit value derived from

either the 23-bit Program Counter (PC) during program

execution, or from table operation or data space

remapping, as described in Section 4.3 “Interfacing

Program and Dat a Me mory S paces”.

User access to the program memory space is restricted

to the lower half of the address range (000000h to

7FFFFFh). The exception is the use of TBLRD/TBLWT

operations, which use TBLPAG<7> to permit access to

the Configuration bits and Device ID sections of the

configuration memory space.

Memory maps for the PIC24FJ128GA010 family of

devices are shown in Figure 4-1.

FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GA010 FAMILY DEVICES

Reset Address

000000h

0000FEh

000002h

000100h

Device Configuration

User Flash

Program Memory

00AC00h

00ABFEh

(22K instructions)

800000h

F80000h

Registers F8000Eh

F80010h

DEVID (2)

FEFFFEh

FF0000h

FFFFFEh

F7FFFEh

Unimplemented

(Read ‘0’s)

GOTO Instruction

000004h

Reserved

7FFFFEh

Reserved

000200h

0001FEh

000104h

Alternate Vector Table

Reserved

Interrupt Vector Table

Reset Address

Device Configuration

User Flash

Program Memory

(32K instructions)

Registers

DEVID (2)

Unimplemented

(Read ‘0’s)

GOTO

Instruction

Reserved

Alternate Vector Table

Reserved

Interrupt Vector Table

Reset Address

Device Configuration

User Flash

Program Memory

(44K instructions)

Registers

DEVID (2)

Unimplemented

(Read ‘0’s)

GOTO Instruction

Reserved

Alternate Vector Table

Reserved

Interrupt Vector Table

PIC24FJ64GA PIC24FJ96GA PIC24FJ128GA

Configuration Memory Space User Memory Space

Flash Config Words

010000h

00FFFEh

015800h

0157FEh

Note: Memory areas are not shown to scale.

PIC24FJ128GA010 FAMILY

DS39747F-page 32  2005-2012 Microchip Technology Inc.

4.1.1 PROGRAM MEMORY

ORGANIZATION

The program memory space is organized in

word-addressable blocks. Although it is treated as

24 bits wide, it is more appropriate to think of each

address of the program memory as a lower and upper

word, with the upper byte of the upper word being

unimplemented. The lower word always has an even

address, while the upper word has an odd address

(Figure 4-2).

Program memory addresses are always word-aligned

on the lower word, and addresses are incremented or

decremented by two during code execution. This

arrangement also provides compatibility with data

memory space addressing and makes it possible to

access data in the program memory space.

4.1.2 HARD MEMORY VECTORS

All PIC24F devices reserve the addresses between

00000h and 000200h for hard coded program execu-

tion vectors. A hardware Reset vector is provided to

redirect code execution from the default value of the

PC on device Reset to the actual start of code. A GOTO

instruction is programmed by the user at 000000h, with

the actual address for the start of code at 000002h.

PIC24F devices also have two Interrupt Vector Tables

(IVT), located from 000004h to 0000FFh, and 000100h

to 0001FFh. These vector tables allow each of the

many device interrupt sources to be handled by sepa-

rate ISRs. A more detailed discussion of the Interrupt

Vector Tables is provided in Section 7.1 “Interrupt

Vector Table”.

4.1.3 FLASH CONFIGURATION WORDS

In PIC24FJ128GA010 family devices, the top two words

of on-chip program memory are reserved for configura-

tion information. On device Reset, the configuration

information is copied into the appropriate Configuration

registers. The addresses of the Flash Configuration

Word for devices in the PIC24FJ128GA010 family are

shown in Table 4-1. Their location in the memory map is

shown with the other memory vectors in Figure 4-1.

The Configuration Words in program memory are a

compact format. The actual Configuration bits are

mapped in several different registers in the configuration

memory space. Their order in the Flash Configuration

Words do not reflect a corresponding arrangement in the

configuration space. Additional details on the device

Configuration Words are provided in Section 24.1

“Configuration Bits”.

TABLE 4-1: FLASH CONFIGURATION

WORDS FOR

PIC24FJ128GA010 FAMILY

DEVICES

FIGURE 4-2: PROGRAM MEMORY ORGANIZATION

Device Program

Memory

(Words)

Configuration

Word

Addresses

PIC24FJ64GA 22,016 00ABFCh:

00ABFEh

PIC24FJ96GA 32,768 00FFFCh:

00FFFEh

PIC24FJ128GA 44,032 0157FCh:

0157FEh

0816

PC Address

000000h

000002h

000004h

000006h

00000000

Program Memory

‘Phantom’ Byte’

(read as ‘0’)

least significant word

most significant word

Instruction Width

000001h

000003h

000005h

000007h

msw

Address (lsw Address)

 2005-2012 Microchip Technology Inc. DS39747F-page 33

PIC24FJ128GA010 FAMILY

4.2 Data Address Space

The PIC24F core has a separate, 16-bit wide data mem-

ory space, addressable as a single linear range. The

data space is accessed using two Address Generation

Units (AGUs), one each for read and write operations.

The data space memory map is shown in Figure 4-3.

All Effective Addresses (EAs) in the data memory

space are 16 bits wide and point to bytes within the

data space. This gives a data space address range of

64 Kbytes or 32K words. The lower half of the data

memory space (that is, when EA<15> = 0) is used for

implemented memory addresses, while the upper half

(EA<15> = 1) is reserved for the Program Space Visi-

bility area (see Section 4.3.3 “Reading Data from

Program Memory Using Program Spa ce Visibility”).

PIC24FJ128GA010 family devices implement a total of

8 Kbytes of data memory. Should an EA point to a

location outside of this area, an all zero word or byte will

be returned.

4.2.1 DATA SPACE WIDTH

The data memory space is organized in

byte-addressable, 16-bit wide blocks. Data is aligned in

data memory and registers as 16-bit words, but all data

space EAs resolve to bytes. The Least Significant Bytes

(LSBs) of each word have even addresses, while the

Most Significant Bytes (MSBs) have odd addresses.

FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24FJ128GA010 FAMILY DEVICES

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 3. “Data Mem-

ory” (DS39717) in the “PIC24F Family

Reference Manual” for more information.

0000h

07FEh

FFFEh

LSB

Address

LSBMSB

MSB

Address

0001h

07FFh

1FFFh

FFFFh

8001h 8000h

7FFFh

0801h 0800h

2001h

Near

1FFEh

SFR

SFR Space

Data RAM

2000h

7FFFh

Program Space

Visibility Area

Note: Data memory areas are not shown to scale.

27FEh

2800h

27FFh

2801h

Space

Data Space

Implemented

Data RAM

Unimplemented

Read as ‘0’

PIC24FJ128GA010 FAMILY

DS39747F-page 34  2005-2012 Microchip Technology Inc.

4.2.2 DATA MEMORY ORGANIZATION

AND ALIGNMENT

To maintain backward compatibility with PIC® devices

and improve data space memory usage efficiency, the

PIC24F instruction set supports both word and byte

operations. As a consequence of byte accessibility, all

Effective Address calculations are internally scaled to

step through word-aligned memory. For example, the

core recognizes that Post-Modified Register Indirect

Addressing mode [Ws++] will result in a value of

Ws + 1 for byte operations and Ws + 2 for word

operations.

Data byte reads will read the complete word which con-

tains the byte, using the LSb of any EA to determine

which byte to select. The selected byte is placed onto

the LSB of the data path. That is, data memory and reg-

isters are organized as two parallel, byte-wide entities

with shared (word) address decode, but separate write

lines. Data byte writes only write to the corresponding

side of the array or register which matches the byte

address.

All word accesses must be aligned to an even address.

Misaligned word data fetches are not supported, so

care must be taken when mixing byte and word opera-

tions, or translating from 8-bit MCU code. If a

misaligned read or write is attempted, an address error

trap will be generated. If the error occurred on a read,

the instruction underway is completed; if it occurred on

a write, the instruction will be executed but the write will

not occur. In either case, a trap is then executed, allow-

ing the system and/or user to examine the machine

state prior to execution of the address Fault.

All byte loads into any W register are loaded into the

Least Significant Byte. The Most Significant Byte is not

modified.

A Sign-Extend (SE) instruction is provided to allow

users to translate 8-bit signed data to 16-bit signed

values. Alternatively, for 16-bit unsigned data, users

can clear the MSB of any W register by executing a

Zero-Extend (ZE) instruction on the appropriate

address.

Although most instructions are capable of operating on

word or byte data sizes, it should be noted that some

instructions operate only on words.

4.2.3 NEAR DATA SPACE

The 8-Kbyte area, between 0000h and 1FFFh, is

referred to as the Near Data Space (NDS). Locations in

this space are directly addressable via a 13-bit abso-

lute address field within all memory direct instructions.

The remainder of the data space is indirectly address-

able. Additionally, the whole data space is addressable

using MOV instructions, which support Memory Direct

Addressing with a 16-bit address field.

4.2.4 SFR SPACE

The first 2 Kbytes of the Near Data Space, from 0000h

to 07FFh, are primarily occupied with Special Function

Registers (SFRs). These are used by the PIC24F core

and peripheral modules for controlling the operation of

the device.

SFRs are distributed among the modules that they con-

trol, and are generally grouped together by module.

Much of the SFR space contains unused addresses;

these are read as ‘0’. A diagram of the SFR space,

showing where SFRs are actually implemented, is

shown in Table 4-2 . Each implemented area indicates

a 32-byte region where at least one address is imple-

mented as an SFR. A complete listing of implemented

SFRs, including their addresses, is shown in Tables 4-3

through 4-30.

TABLE 4-2: IMPLEMENTED REGIONS OF SFR DATA SPACE

SFR Space Address

xx00 xx20 xx40 xx60 xx80 xxA0 xxC0 xxE0

000h Core ICN Interrupts —

100h Timers Capture — Compare — — —

200h I2C™ UART SPI —— I/O

300h A/D ——————

400h ————————

500h ————————

600h PMP RTC/Comp CRC ——— I/O

700h —— System NVM/PMD — — — —

Legend: — = No implemented SFRs in this block

 2005-2012 Microchip Technology Inc. DS39747F-page 35

PIC24FJ128GA010 FAMILY

TABLE 4-3: CPU CORE REGISTERS MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

WREG0 0000 Working Register 0 0000

WREG1 0002 Working Register 1 0000

WREG2 0004 Working Register 2 0000

WREG3 0006 Working Register 3 0000

WREG4 0008 Working Register 4 0000

WREG5 000A Working Register 5 0000

WREG6 000C Working Register 6 0000

WREG7 000E Working Register 7 0000

WREG8 0010 Working Register 8 0000

WREG9 0012 Working Register 9 0000

WREG10 0014 Working Register 10 0000

WREG11 0016 Working Register 11 0000

WREG12 0018 Working Register 12 0000

WREG13 001A Working Register 13 0000

WREG14 001C Working Register 14 0000

WREG15 001E Working Register 15 0800

SPLIM 0020 Stack Pointer Limit xxxx

PCL 002E Program Counter Low Word 0000

PCH 0030 — — — — — — — — Program Counter High Byte 0000

TBLPAG 0032 — — — — — — — — Table Page Address Pointer 0000

PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer 0000

RCOUNT 0036 Repeat Loop Counter xxxx

SR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C 0000

CORCON 0044 — — — — — — — — — — — —IPL3PSV— — 0000

DISICNT 0052 —— Disable Interrupts Counter xxxx

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ128GA010 FAMILY

DS39747F-page 36  2005-2012 Microchip Technology Inc.

TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP

File

Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

INTCON1 0080 NSTDIS — — — — — — — — — — MATHERR ADDRERR STKERR OSCFAIL —0000

INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000

IFS0 0084 —— AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000

IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF — — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000

IFS2 0088 ——PMPIF— — —OC5IF— IC5IF IC4IF IC3IF — — — SPI2IF SPF2IF 0000

IFS3 008A —RTCIF— — — — — — — INT4IF INT3IF —— MI2C2IF SI2C2IF —0000

IFS4 008C — — — — — — — — — — — — CRCIF U2ERIF U1ERIF —0000

IEC0 0094 —— AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000

IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE — — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000

IEC2 0098 ——PMPIE— — —OC5IE— IC5IE IC4IE IC3IE — — — SPI2IE SPF2IE 0000

IEC3 009A —RTCIE — — — — — — — INT4IE INT3IE —— MI2C2IE SI2C2IE —0000

IEC4 009C — — — — — — — — — — — — CRCIE U2ERIE U1ERIE —0000

IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444

IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — — 4440

IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 4444

IPC3 00AA — — — — — — — — — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 0044

IPC4 00AC — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444

IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004

IPC6 00B0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — — — — 4440

IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4444

IPC8 00B4 — — — — — — — — — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 0044

IPC9 00B6 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — — — — 4440

IPC10 00B8 — — — — — — — — — OC5IP2 OC5IP1 OC5IP0 — — — — 0040

IPC11 00BA — — — — — — — — — PMPIP2 PMPIP1 PMPIP0 — — — — 0040

IPC12 00BC — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — 0440

IPC13 00BE — — — — — INT4IP2 INT4IP1 INT4IP0 — INT3IP2 INT3IP1 INT3IP0 — — — — 0440

IPC15 00C2 — — — — — RTCIP2 RTCIP1 RTCIP0 — — — — — — — — 0400

IPC16 00C4 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — 4440

INTTREG 00E0 CPUIRQ —VHOLD— ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

 2005-2012 Microchip Technology Inc. DS39747F-page 37

PIC24FJ128GA010 FAMILY

TABLE 4-5: ICN REGISTER MAP

File

Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000

CNEN2 0062 — — — — — — — — — —CN21IE

(1)CN20IE(1)CN19IE(1)CN18IE CN17IE CN16IE 0000

CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000

CNPU2 006A — — — — — — — — — — CN21PUE(1)CN20PUE(1)CN19PUE(1)CN18PUE CN17PUE CN16PUE 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal

Note 1: Implemented in 80-pin and 100-pin devices only.

TABLE 4-6: TIMER REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

TMR1 0100 Timer1 Register xxxx

PR1 0102 Period Register 1 FFFF

T1CON 0104 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 —TSYNCTCS —0000

TMR2 0106 Timer2 Register xxxx

TMR3HLD 0108 Timer3 Holding Register (For 32-bit timer operations only) xxxx

TMR3 010A Timer3 Register xxxx

PR2 010C Period Register 2 FFFF

PR3 010E Period Register 3 FFFF

T2CON 0110 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 T32 —TCS—0000

T3CON 0112 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 ——TCS—0000

TMR4 0114 Timer4 Register xxxx

TMR5HLD 0116 Timer5 Holding Register (For 32-bit operations only) xxxx

TMR5 0118 Timer5 Register xxxx

PR4 011A Period Register 4 FFFF

PR5 011C Period Register 5 FFFF

T4CON 011E TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 T32 —TCS—0000

T5CON 0120 TON —TSIDL— — — — — — TGATE TCKPS1 TCKPS0 ——TCS—0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ128GA010 FAMILY

DS39747F-page 38  2005-2012 Microchip Technology Inc.

TABLE 4-7: INPUT CAPTURE REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

IC1BUF 0140 Input 1 Capture Register xxxx

IC1CON 0142 ——ICSIDL— — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000

IC2BUF 0144 Input 2 Capture Register xxxx

IC2CON 0146 ——ICSIDL— — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000

IC3BUF 0148 Input 3 Capture Register xxxx

IC3CON 014A ——ICSIDL— — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000

IC4BUF 014C Input 4 Capture Register xxxx

IC4CON 014E ——ICSIDL— — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000

IC5BUF 0150 Input 5 Capture Register xxxx

IC5CON 0152 ——ICSIDL— — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-8: OUTPUT COMPARE REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

OC1RS 0180 Output Compare 1 Secondary Register xxxx

OC1R 0182 Output Compare 1 Register xxxx

OC1CON 0184 ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000

OC2RS 0186 Output Compare 2 Secondary Register xxxx

OC2R 0188 Output Compare 2 Register xxxx

OC2CON 018A ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000

OC3RS 018C Output Compare 3 Secondary Register xxxx

OC3R 018E Output Compare 3 Register xxxx

OC3CON 0190 ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000

OC4RS 0192 Output Compare 4 Secondary Register xxxx

OC4R 0194 Output Compare 4 Register xxxx

OC4CON 0196 ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000

OC5RS 0198 Output Compare 5 Secondary Register xxxx

OC5R 019A Output Compare 5 Register xxxx

OC5CON 019C ——OCSIDL— — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

 2005-2012 Microchip Technology Inc. DS39747F-page 39

PIC24FJ128GA010 FAMILY

TABLE 4-9: I2C1 REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

I2C1RCV 0200 — ——————— Receive Register 0000

I2C1TRN 0202 — ——————— Transmit Register 00FF

I2C1BRG 0204 — — — — — — — Baud Rate Generator 0000

I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000

I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A PSR/WRBF TBF 0000

I2C1ADD 020A — ————— Address Register 0000

I2C1MSK 020C — ————— Address Mask 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-10: I2C2 REGISTER MA P

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

I2C2RCV 0210 — ——————— Receive Register 0000

I2C2TRN 0212 — ——————— Transmit Register 00FF

I2C2BRG 0214 — — — — — — — Baud Rate Generator 0000

I2C2CON 0216 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000

I2C2STAT 0218 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2CPOV D/A PSR/WRBF TBF 0000

I2C2ADD 021A — — — — — — Address Register 0000

I2C2MSK 021C — — — — — — Address Mask 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ128GA010 FAMILY

DS39747F-page 40  2005-2012 Microchip Technology Inc.

TABLE 4-11: UART1 REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000

U1STA 0222 UTXISEL1 TXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110

U1TXREG 0224 — — — — — — — Transmit Register xxxx

U1RXREG 0226 — — — — — — — Receive Register 0000

U1BRG 0228 Baud Rate Generator Prescaler 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-12: UART2 REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000

U2STA 0232 UTXISEL1 TXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110

U2TXREG 0234 — — — — — — — Transmit Register xxxx

U2RXREG 0236 — — — — — — — Receive Register 0000

U2BRG 0238 Baud Rate Generator Prescaler 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-13: SPI1 REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

SPI1STAT 0240 SPIEN —SPISIDL—— SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000

SPI1CON1 0242 ——— DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000

SPI1CON2 0244 FRMEN SPIFSD SPIFPOL ——————————— SPIFE SPIBEN 0000

SPI1BUF 0248 SPI1 Transmit and Receive Buffer 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-14: SPI2 REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

SPI2STAT 0260 SPIEN — SPISIDL —— SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000

SPI2CON1 0262 ——— DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000

SPI2CON2 0264 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000

SPI2BUF 0268 SPI2 Transmit and Receive Buffer 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

 2005-2012 Microchip Technology Inc. DS39747F-page 41

PIC24FJ128GA010 FAMILY

TABLE 4-15: A/D REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

ADC1BUF0 0300 A/D Data Buffer 0 xxxx

ADC1BUF1 0302 A/D Data Buffer 1 xxxx

ADC1BUF2 0304 A/D Data Buffer 2 xxxx

ADC1BUF3 0306 A/D Data Buffer 3 xxxx

ADC1BUF4 0308 A/D Data Buffer 4 xxxx

ADC1BUF5 030A A/D Data Buffer 5 xxxx

ADC1BUF6 030C A/D Data Buffer 6 xxxx

ADC1BUF7 030E A/D Data Buffer 7 xxxx

ADC1BUF8 0310 A/D Data Buffer 8 xxxx

ADC1BUF9 0312 A/D Data Buffer 9 xxxx

ADC1BUFA 0314 A/D Data Buffer 10 xxxx

ADC1BUFB 0316 A/D Data Buffer 11 xxxx

ADC1BUFC 0318 A/D Data Buffer 12 xxxx

ADC1BUFD 031A A/D Data Buffer 13 xxxx

ADC1BUFE 031C A/D Data Buffer 14 xxxx

ADC1BUFF 031E A/D Data Buffer 15 xxxx

AD1CON1 0320 ADON —ADSIDL— — — FORM1 FORM0 SSRC2 SSRC1 SSRC0 —— ASAM SAMP DONE 0000

AD1CON2 0322 VCFG2 VCFG1 VCFG0 r — CSCNA ——BUFS— SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS 0000

AD1CON3 0324 ADRC —— SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000

AD1CHS 0328 CH0NB — — — CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA — — — CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000

AD1PCFG 032C PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000

AD1CSSL 0330 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’; r = reserved, maintain as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-16: PORTA REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

TRISA 02C0 TRISA15(1)TRISA14(1)— — —TRISA10

(1)TRISA9(1)—TRISA7

(2)TRISA6(2)TRISA5(2)TRISA4(2)TRISA3(2)TRISA2(2)TRISA1(2)TRISA0(2)C6FF

PORTA 02C2 RA15(1)RA14(1)— — —RA10

(1)RA9(1)—RA7RA6RA5

(2)RA4(2)RA3(2)RA2(2)RA1(2)RA0(2)xxxx

LATA 02C4 LATA15(1)LATA14(1)— — —LATA10

(1)LATA9(1)—LATA7LATA6LATA5

(2)LATA4(2)LATA3(2)LATA2(2)LATA1(2)LATA0(2)xxxx

ODCA 06C0 ODA15(1)ODA14(1)— — —ODA10

(1)ODA9(1)— ODA7 ODA6 ODA5(2)ODA4(2)ODA3(2)ODA2(2)ODA1(2)ODA0(2)0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

Note 1: Implemented in 80-pin and 100-pin devices only.

2: Implemented in 100-pin devices only.

PIC24FJ128GA010 FAMILY

DS39747F-page 42  2005-2012 Microchip Technology Inc.

TABLE 4-17: PORTB REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

TRISB 02C6 TRISB15 TRISB14 TRISB13(1)TRISB12(1)TRISB11(1)TRISB10(1)TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF

PORTB 02C8 RB15 RB14 RB13(1)RB12(1)RB11(1)RB10(1)RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx

LATB 02CA LATB15 LATB14 LATB13(1)LATB12(1)LATB11(1)LATB10(1)LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx

ODCB 06C6 ODB15 ODB14 ODB13(1)ODB12(1)ODB11(1)ODB10(1)ODB9 ODB8 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices

Note 1: Unimplemented when JTAG is enabled.

TABLE 4-18: PORTC REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

TRISC 02CC TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — —TRISC4

(2)TRISC3(1)TRISC2(2)TRISC1(1)—F01E

PORTC 02CE RC15 RC14 RC13 RC12 — — — — — — — RC4(2)RC3(1)RC2(2)RC1(1)—xxxx

LATC 02D0 LATC15 LATC14 LATC13 LATC12 — — — — — — —LATC4

(2)LATC3(1)LATC2(2)LATC1(1)—xxxx

ODCC 06CC ODC15 ODC14 ODC13 ODC12 — — — — — — — ODC4(2)ODC3(1)ODC2(2)ODC1(1)—0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

Note 1: Implemented in 80-pin and 100-pin devices only.

2: Implemented in 100-pin devices only

TABLE 4-19: PORTD REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

TRISD 02D2 TRISD15(1)TRISD14(1)TRISD13(1)TRISD12(1)TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FFFF

PORTD 02D4 RD15(1)RD14(1)RD13(1)RD12(1)RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx

LATD 02D6 LATD15(1)LATD14(1)LATD13(1)LATD12(1)LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx

ODCD 06D2 ODD15(1)ODD14(1)ODD13(1)ODD12(1)ODD11 ODD10 ODD9 ODD8 ODD7 ODD6 ODD5 ODD4 ODD3 ODD2 ODD1 ODD0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

Note 1: Implemented in 80-pin and 100-pin devices only.

 2005-2012 Microchip Technology Inc. DS39747F-page 43

PIC24FJ128GA010 FAMILY

TABLE 4-20: PORTE REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

TRISE 02D8 —————— TRISE9(1)TRISE8(1)TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 03FF

PORTE 02DA ——————RE9

(1)RE8(1)RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx

LATE 02DC ——————LATE9

(1)LATE8(1)LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx

ODCE 06D8 ——————ODE9

(1)ODE8(1)ODE7 ODE6 ODE5 ODE4 ODE3 ODE2 ODE1 ODE0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

Note 1: Implemented in 80-pin and 100-pin devices only.

TABLE 4-21: PORTF REGIS TER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

TRISF 02DE ——TRISF13

(1)TRISF12(1)— — —TRISF8

(2)TRISF7(2)TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 31FF

PORTF 02E0 ——RF13

(1)RF12(1)— — —RF8

(2)RF7(2)RF6RF5RF4RF3RF2RF1RF0xxxx

LATF 02E2 ——LATF13

(1)LATF12(1)— — —LATF8

(2)LATF7(2)LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx

ODCF 06DE ——ODF13

(1)ODF12(1)— — —ODF8

(2)ODF7(2)ODF6 ODF5 ODF4 ODF3 ODF2 ODF1 ODF0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

Note 1: Implemented in 100-pin devices only.

2: Implemented in 80-pin and 100-pin devices only.

TABLE 4-22: PORTG REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

TRISG 02E4 TRISG15 TRISG14(1)TRISG13(1)TRISG12(1)—— TRISG9 TRISG8 TRISG7 TRISG6 —— TRISG3 TRISG2 TRISG1(2)TRISG0(2)F3CF

PORTG 02E6 RG15 RG14(1)RG13(1)RG12(1)—— RG9 RG8 RG7 RG6 —— RG3 RG2 RG1(2)RG0(2)xxxx

LATG 02E8 LATG15 LATG14(1)LATG13(1)LATG12(1)——LATG9LATG8LATG7LATG6—— LATG3 LATG2 LATG1(2)LATG0(2)xxxx

ODCG 06E4 ODG15 ODG14(1)ODG13(1)ODG12(1)—— ODG9 ODG8 ODG7 ODG6 —— ODG3 ODG2 ODG1(2)ODG0(2)0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

Note 1: Implemented in 100-pin devices only.

2: Implemented in 80-pin and 100-pin devices only.

TABLE 4-23: PAD CONFIGURATION MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

PADCFG1 02FC — — — — — — — — — — — — — — RTSECSEL PMPTTL 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

PIC24FJ128GA010 FAMILY

DS39747F-page 44  2005-2012 Microchip Technology Inc.

TABLE 4-24: PARALLEL MASTER/SLAVE PORT REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

PMCON 0600 PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSP 0000

PMMODE 0602 BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 0000

PMADDR(1)

0604 CS2 CS1 Parallel Port Destination Address<13:0> (Master modes) 0000

PMDOUT1(1)Parallel Port Data Out Register 1 (Buffers 0 and 1) 0000

PMDOUT2 0606 Parallel Port Data Out Register 2 (Buffers 2 and 3) 0000

PMDIN1 0608 Parallel Port Data In Register 1 (Buffers 0 and 1) 0000

PMDIN2 060A Parallel Port Data In Register 2 (Buffers 2 and 3) 0000

PMAEN 060C PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 0000

PMSTAT 060E IBF IBOV —— IB3F IB2F IB1F IB0F OBE OBUF —— OB3E OB2E OB1E OB0E 008F

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: PMADDR and PMDOUT1 share the same physical register. The register functions as PMDOUT1 only in Slave modes and as PMADDR only in Master modes.

TABLE 4-25: REAL-TIME CLOCK AND CALENDAR REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

ALRMVAL 0620 Alarm Value Register Window Based on ALRMPTR<1:0> xxxx

ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000

RTCVAL 0624 RTCC Value Register Window Based on RTCPTR<1:0> xxxx

RCFGCAL(1)0626 RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: RCFGCAL register Reset value is dependent on the type of Reset.

TABLE 4-26: DUAL COMPARATOR REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

CMCON 0630 CMIDL — C2EVT C1EVT C2EN C1EN C2OUTEN C1OUTEN C2OUT C1OUT C2INV C1INV C2NEG C2POS C1NEG C1POS 0000

CVRCON 0632 — — — — — — — — CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

 2005-2012 Microchip Technology Inc. DS39747F-page 45

PIC24FJ128GA010 FAMILY

TABLE 4-27: CRC REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

CRCCON 0640 —— CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT — CRCGO PLEN3 PLEN2 PLEN1 PLEN0 0000

CRCXOR 0642 CRC XOR Polynomial Register 0000

CRCDAT 0644 CRC Data Input Register 0000

CRCWDAT 0646 CRC Result Register 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-28: SYSTEM REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

RCON 0740 TRAPR IOPUWR ———— CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx(1)

OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK —LOCK—CF— SOSCEN OSWEN xxxx(2)

CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 — — — — — — — — 0100

OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: RCON register Reset values are dependent on the type of Reset.

2: OSCCON register Reset values are dependent on the FOSC Configuration bits and by type of Reset.

TABLE 4-29: NVM REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

NVMCON 0760 WR WREN WRERR — — — — — —ERASE—— NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1)

NVMKEY 0766 ———————— NVMKEY<7:0> 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.

TABLE 4-30: PMD REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

PMD1 0770 T5MD T4MD T3MD T2MD T1MD — — — I2C1MD U2MD U1MD SPI2MD SPI1MD —— ADC1MD 0000

PMD2 0772 — — — IC5MD IC4MD IC3MD IC2MD IC1MD — — — OC5MD OC4MD OC3MD OC2MD OC1MD 0000

PMD3 0774 — — — — — CMPMD RTCCMD PMPMD CRCPMD — — — — —I2C2MD—0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24FJ128GA010 FAMILY

DS39747F-page 46  2005-2012 Microchip Technology Inc.

4.2.5 SOFTWARE STACK

In addition to its use as a working register, the W15 reg-

ister in PIC24F devices is also used as a Software

Stack Pointer. The pointer always points to the first

available free word and grows from lower to higher

addresses. It predecrements for stack pops and post-

increments for stack pushes, as shown in Figure 4-4.

Note that for a PC push during any CALL instruction,

the MSB of the PC is zero-extended before the push,

ensuring that the MSB is always clear.

The Stack Pointer Limit register (SPLIM) associated

with the Stack Pointer sets an upper address boundary

for the stack. SPLIM is uninitialized at Reset. As is the

case for the Stack Pointer, SPLIM<0> is forced to ‘0’

because all stack operations must be word-aligned.

Whenever an EA is generated using W15 as a source

or destination pointer, the resulting address is com-

pared with the value in SPLIM. If the contents of the

Stack Pointer (W15) and the SPLIM register are equal

and a push operation is performed, a stack error trap

will not occur. The stack error trap will occur on a

subsequent push operation. Thus, for example, if it is

desirable to cause a stack error trap when the stack

grows beyond address, 2000h, in RAM, initialize the

SPLIM with the value, 1FFEh.

Similarly, a Stack Pointer underflow (stack error) trap is

generated when the Stack Pointer address is found to

be less than 0800h. This prevents the stack from

interfering with the Special Function Register (SFR)

space.

A write to the SPLIM register should not be immediately

followed by an indirect read operation using W15.

FIGURE 4-4: CALL STACK FRAME

4.3 Interfacing Program and Data

Memory Spaces

The PIC24F architecture uses a 24-bit wide program

space and 16-bit wide data space. The architecture is

also a modified Harvard scheme, meaning that data

can also be present in the program space. To use this

data successfully, it must be accessed in a way that

preserves the alignment of information in both spaces.

Aside from normal execution, the PIC24F architecture

provides two methods by which program space can be

accessed during operation:

• Using table instructions to access individual bytes

or words anywhere in the program space

• Remapping a portion of the program space into

the data space (Program Space Visibility)

Table instructions allow an application to read or write

to small areas of the program memory. This makes the

method ideal for accessing data tables that need to be

updated from time to time. It also allows access to all

bytes of the program word. The remapping method

allows an application to access a large block of data on

a read-only basis, which is ideal for look ups from a

large table of static data. It can only access the least

significant word of the program word.

4.3.1 ADDRESSING PROGRAM SPACE

Since the address ranges for the data and program

spaces are 16 and 24 bits, respectively, a method is

needed to create a 23-bit or 24-bit program address

from 16-bit data registers. The solution depends on the

interface method to be used.

For table operations, the 8-bit Table Page register

(TBLPAG) is used to define a 32K word region within

the program space. This is concatenated with a 16-bit

EA to arrive at a full 24-bit program space address. In

this format, the Most Significant bit of TBLPAG is used

to determine if the operation occurs in the user memory

(TBLPAG<7> = 0) or the configuration memory

(TBLPAG<7> = 1).

For remapping operations, the 8-bit Program Space

Visibility register (PSVPAG) is used to define a

16K word page in the program space. When the Most

Significant bit of the EA is ‘1’, PSVPAG is concatenated

with the lower 15 bits of the EA to form a 23-bit program

space address. Unlike table operations, this limits

remapping operations strictly to the user memory area.

Table 4-31 and Figure 4-5 show how the program EA is

created for table operations and remapping accesses

from the data EA. Here, P<23:0> refers to a program

space word, whereas D<15:0> refers to a data space

word.

Note: A PC push during exception processing

will concatenate the SRL register to the

MSB of the PC prior to the push.

PC<15:0>

000000000

015

W15 (before CALL)

W15 (after CALL)

Stack Grows Towards

Higher Address

0000h

PC<22:16>

POP : [--W15]

PUSH : [W15++]

 2005-2012 Microchip Technology Inc. DS39747F-page 47

PIC24FJ128GA010 FAMILY

TABLE 4-31: PROGRAM SPACE ADDRESS CONSTRUCTION

FIGURE 4-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

Access Type Access

Space Program S pace Address

<23> <22:16> <15> <14:1> <0>

Instruction Access

(Code Execution)

User 0PC<22:1> 0

0xx xxxx xxxx xxxx xxxx xxx0

TBLRD/TBLWT

(Byte/Word Read/Write)

User TBLPAG<7:0> Data EA<15:0>

0xxx xxxx xxxx xxxx xxxx xxxx

Configuration TBLPAG<7:0> Data EA<15:0>

1xxx xxxx xxxx xxxx xxxx xxxx

Program Space Visibility

(Block Remap/Read)

User 0PSVPAG<7:0> Data EA<14:0>(1)

0 xxxx xxxx xxx xxxx xxxx xxxx

Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of

the address is PSVPAG<0>.

0Program Counter

23 Bits

PSVPAG

8 Bits

15 Bits

Program Counter(1)

Select

TBLPAG

8 Bits

16 Bits

Byte Select

1/0

User/Configuration

Table Operations(2)

Program Space Visibility(1)

Space Select

24 Bits

23 Bits

(Remapping)

1/0

Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of

data in the program and data spaces.

2: Table operations are not required to be word-aligned. Table read operations are permitted in the

configuration memory space.

PIC24FJ128GA010 FAMILY

DS39747F-page 48  2005-2012 Microchip Technology Inc.

4.3.2 DATA ACCESS FROM PROGRAM

MEMORY USING TABLE

INSTRUCTIONS

The TBLRDL and TBLWTL instructions offer a direct

method of reading or writing the lower word of any

address within the program space, without going

through data space. The TBLRDH and TBLWTH instruc-

tions are the only method to read or write the upper 8 bits

of a program space word as data.

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to data space addresses.

Program memory can thus be regarded as two 16-bit,

word-wide address spaces, residing side by side, each

with the same address range. TBLRDL and TBLWTL

access the space which contains the least significant

data word, and TBLRDH and TBLWTH access the space

which contains the upper data byte.

Two table instructions are provided to move byte or

word-sized (16-bit) data to and from program space.

Both function as either byte or word operations.

1. TBLRDL (Table Read Low): In Word mode, it

maps the lower word of the program space

location (P<15:0>) to a data address (D<15:0>).

In Byte mode, either the upper or lower byte of

the lower program word is mapped to the lower

byte of a data address. The upper byte is

selected when byte select is ‘1’; the lower byte

is selected when it is ‘0’.

2. TBLRDH (Table Read High): In Word mode, it

maps the entire upper word of a program address

(P<23:16>) to a data address. Note that

D<15:8>, the “phantom byte”, will always be ‘0’.

In Byte mode, it maps the upper or lower byte of

the program word to D<7:0> of the data

address, as above. Note that the data will

always be ‘0’ when the upper “phantom” byte is

selected (byte select = 1).

In a similar fashion, two table instructions, TBLWTH

and TBLWTL, are used to write individual bytes or

words to a program space address. The details of

their operation are explained in Section 5.0 “Flash

Program Memory”.

For all table operations, the area of program memory

space to be accessed is determined by the Table Page

memory space of the device, including user and config-

uration spaces. When TBLPAG<7> = 0, the Table Page

is located in the user memory space. When

TBLPAG<7> = 1, the page is located in configuration

space.

FIGURE 4-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

Note: Only table read operations will execute in

the configuration memory space, and only

then, in implemented areas such as the

Device ID. Table write operations are not

allowed.

081623

00000000

‘Phantom’ Byte

TBLRDH.B (Wn<0> = 0)

TBLRDL.W

TBLRDL.B (Wn<0> = 1)

TBLRDL.B (Wn<0> = 0)

23 15 0

TBLPAG

000000h

800000h

020000h

030000h

Program Space

Data EA<15:0>

The address for the table operation is determined by the data EA

within the page defined by the TBLPAG register.

Only read operations are shown; write operations are also valid in

the user memory area.

 2005-2012 Microchip Technology Inc. DS39747F-page 49

PIC24FJ128GA010 FAMILY

4.3.3 READING DATA FROM PROGRAM

MEMORY USING PROGRAM SPACE

VISIBILITY

The upper 32 Kbytes of data space may optionally be

mapped into any 16K word page of the program space.

This provides transparent access of stored constant

data from the data space without the need to use

special instructions (i.e., TBLRDL/H).

Program space access through the data space occurs

if the Most Significant bit of the data space EA is ‘1’ and

Program Space Visibility is enabled by setting the PSV

bit in the Core Control register (CORCON<2>). The

location of the program memory space to be mapped

into the data space is determined by the Program

Space Visibility Page register (PSVPAG). This 8-bit

16K words in program space. In effect, PSVPAG func-

tions as the upper 8 bits of the program memory

address, with the 15 bits of the EA functioning as the

lower bits. Note that by incrementing the PC by 2 for

each program memory word, the lower 15 bits of data

space addresses directly map to the lower 15 bits in the

corresponding program space addresses.

Data reads to this area add an additional cycle to the

instruction being executed, since two program memory

fetches are required.

Although each data space address, 8000h and higher,

maps directly into a corresponding program memory

address (see Figure 4-7), only the lower 16 bits of the

24-bit program word are used to contain the data. The

upper 8 bits of any program space locations used as

data should be programmed with ‘1111 1111’ or

‘0000 0000’ to force a NOP. This prevents possible

issues should the area of code ever be accidentally

executed.

For operations that use PSV and are executed outside

a REPEAT loop, the MOV and MOV.D instructions will

require one instruction cycle in addition to the specified

execution time. All other instructions will require two

instruction cycles in addition to the specified execution

time.

For operations that use PSV which are executed inside

a REPEAT loop, there will be some instances that

require two instruction cycles in addition to the

specified execution time of the instruction:

• Execution in the first iteration

• Execution in the last iteration

• Execution prior to exiting the loop due to an

interrupt

• Execution upon re-entering the loop after an

interrupt is serviced

Any other iteration of the REPEAT loop will allow the

instruction accessing data, using PSV, to execute in a

single cycle.

FIGURE 4-7: PROGRAM SPACE VISIBILITY OPERATION

Note: PSV access is temporarily disabled during

table reads/writes.

23 15 0

PSVPAG

Data SpaceProgram Space

0000h

8000h

FFFFh

02 000000h

800000h

010000h

018000h

When CORCON<2> = 1 and EA<15> = 1:

PSV Area

The data in the page

designated by PSV-

PAG is mapped into

the upper half of the

data memory

space....

Data EA<14:0>

...while the lower 15

bits of the EA specify

an exact address

within the PSV area.

This corresponds

exactly to the same

lower 15 bits of the

actual program space

address.

PIC24FJ128GA010 FAMILY

DS39747F-page 50  2005-2012 Microchip Technology Inc.

NOTES:

 2005-2012 Microchip Technology Inc. DS39747F-page 51

PIC24FJ128GA010 FAMILY

5.0 FLASH PROGRAM MEMORY

The PIC24FJ128GA010 family of devices contains

internal Flash program memory for storing and execut-

ing application code. The memory is readable, writable

and erasable during normal operation over the

specified VDD range.

Flash memory can be programmed in four ways:

1. In-Circuit Serial Programming™ (ICSP™)

2. Run-Time Self-Programming (RTSP)

3. JTAG

4. Enhanced In-Circuit Serial Programming

(Enhanced ICSP)

ICSP allows a PIC24FJ128GA010 family device to be

serially programmed while in the end application circuit.

This is simply done with two lines for Programming

Clock and Programming Data (which are named PGCx

and PGDx, respectively), and three other lines for

power (VDD), ground (VSS) and Master Clear (MCLR).

This allows customers to manufacture boards with

unprogrammed devices and then program the micro-

controller just before shipping the product. This also

allows the most recent firmware or a custom firmware

to be programmed.

RTSP is accomplished using TBLRD (table read) and

TBLWT (table write) instructions. With RTSP, the user

may write program memory data in blocks of 64 instruc-

tions (192 bytes) at a time, and erase program memory

in blocks of 512 instructions (1536 bytes) at a time.

5.1 Table Instructions and Flash

Programming

Regardless of the method used, all programming of

Flash memory is done with the table read and table

write instructions. These allow direct read and write

access to the program memory space from the data

memory while the device is in normal operating mode.

The 24-bit target address in the program memory is

formed using the TBLPAG<7:0> bits and the Effective

Address (EA) from a W register specified in the table

instruction, as shown in Figure 5-1.

The TBLRDL and the TBLWTL instructions are used to

read or write to bits<15:0> of program memory.

TBLRDL and TBLWTL can access program memory in

both Word and Byte modes.

The TBLRDH and TBLWTH instructions are used to read

or write to bits<23:16> of program memory. TBLRDH

and TBLWTH can also access program memory in Word

or Byte mode.

FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 4. “Program

Memory” (DS39715) in the “PIC24F

Family Reference Manual” for more

information.

0Program Counter

24 Bits

Program

TBLPAG Reg

8 Bits

Working Reg EA

16 Bits

Using

Byte

24-Bit EA

1/0

Select

Table

Instruction

Counter

Using

User/Configuration

Space Select

PIC24FJ128GA010 FAMILY

DS39747F-page 52  2005-2012 Microchip Technology Inc.

5.2 RTSP Operation

The PIC24F Flash program memory array is organized

into rows of 64 instructions or 192 bytes. RTSP allows

the user to erase blocks of eight rows (512 instructions)

at a time and to program one row at a time. It is also

possible to program single words.

The 8-row erase blocks and single row write blocks are

edge-aligned, from the beginning of program memory,

on boundaries of 1536 bytes and 192 bytes,

respectively.

When data is written to program memory using TBLWT

instructions, the data is not written directly to memory.

Instead, data written using table writes is stored in

holding latches until the programming sequence is

executed.

Any number of TBLWT instructions can be executed

and a write will be successfully performed. However,

64 TBLWT instructions are required to write the full row

of memory.

To ensure that no data is corrupted during a write, any

unused addresses should be programmed with

FFFFFFh. This is because the holding latches reset to

an unknown state, so if the addresses are left in the

Reset state, they may overwrite the locations on rows

which were not rewritten.

The basic sequence for RTSP programming is to set up

a Table Pointer, then do a series of TBLWT instructions

to load the buffers. Programming is performed by

setting the control bits in the NVMCON register.

Data can be loaded in any order and the holding regis-

ters can be written to multiple times before performing

a write operation. Subsequent writes, however, will

wipe out any previous writes.

All of the table write operations are single-word writes

(2 instruction cycles), because only the buffers are

written. A programming cycle is required for

programming each row.

5.3 JTAG Operation

The PIC24F family supports JTAG programming and

boundary scan. Boundary scan can improve the manu-

facturing process by verifying pin to PCB connectivity.

Programming can be performed with industry standard

JTAG programmers supporting Serial Vector Format

(SVF).

5.4 Enh a n c ed In -Cir c u it Se r ia l

Programming

Enhanced In-Circuit Serial Programming uses an on-

board bootloader, known as the program executive, to

manage the programming process. Using an SPI data

frame format, the program executive can erase,

program and verify program memory. See the device

programming specification for more information on

Enhanced ICSP

5.5 Control Registers

There are two SFRs used to read and write the

program Flash memory: NVMCON and NVMKEY.

The NVMCON register (Register 5-1) controls which

blocks are to be erased, which memory type is to be

programmed and the start of the programming cycle.

NVMKEY is a write-only register that is used for write

protection. To start a programming or erase sequence,

the user must consecutively write 55h and AAh to the

NVMKEY register. Refer to Section 5.6 “Programming

Operations” for further details.

5.6 Programming Operations

A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP

mode. During a programming or an erase operation,

the processor stalls (Waits) until the operation is

finished. Setting the WR bit (NVMCON<15>) starts the

operation and the WR bit is automatically cleared when

the operation is finished.

Configuration Word values are stored in the last two

locations of program memory. Performing a page erase

operation on the last page of program memory clears

these values and enables code protection. As a result,

avoid performing page erase operations on the last

page of program memory.

Note: Writing to a location multiple times without

erasing is not recommended.

 2005-2012 Microchip Technology Inc. DS39747F-page 53

PIC24FJ128GA010 FAMILY

R/SO-0(1)R/W-0(1)R/W-0(1)U-0 U-0 U-0 U-0 U-0

WR WREN WRERR — — — — —

bit 15 bit 8

U-0 R/W-0(1)U-0 U-0 R/W-0(1)R/W-0(1)R/W-0(1)R/W-0(1)

— ERASE ——NVMOP3

(2)NVMOP2(2)NVMOP1(2)NVMOP0(2)

bit 7 bit 0

Legend: SO = Settable Only bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 WR: Write Control bit

1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is

cleared by hardware once operation is complete.

0 = Program or erase operation is complete and inactive

bit 14 WREN: Write Enable bit

1 = Enables Flash program/erase operations

0 = Inhibits Flash program/erase operations

bit 13 WRERR: Write Sequence Error Flag bit

1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically

on any set attempt of the WR bit)

0 = The program or erase operation completed normally

bit 12-7 Unimplemented: Read as ‘0’

bit 6 ERASE: Erase/Program Enable bit

1 = Performs the erase operation specified by NVMOP<3:0> on the next WR command

0 = Performs the program operation specified by NVMOP<3:0> on the next WR command

bit 5-4 Unimplemented: Read as ‘0’

bit 3-0 NVMOP<3:0>: NVM Operation Select bits(2)

1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(3)

0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1)

0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)

0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1)

Note 1: These bits can only be reset on a POR.

2: All other combinations of NVMOP<3:0> are unimplemented.

3: Available in ICSP™ mode only. Refer to the device programming specifications.

PIC24FJ128GA010 FAMILY

DS39747F-page 54  2005-2012 Microchip Technology Inc.

5.6.1 PROGRAMMING ALGORITHM FOR

FLASH PROGRAM MEMORY

The user can program one row of program Flash memory

at a time. To do this, it is necessary to erase the 8-row

erase block containing the desired row. The general

process is:

1. Read eight rows of program memory

(512 instructions) and store in data RAM.

2. Update the program data in RAM with the

desired new data.

3. Erase the block (see Example 5-1):

a) Set the NVMOP bits (NVMCON<3:0>) to

‘0010’ to configure for block erase. Set the

ERASE (NVMCON<6>) and WREN

(NVMCON<14>) bits.

b) Write the starting address of the block to be

erased into the TBLPAG and W registers.

c) Write 55h to NVMKEY.

d) Write AAh to NVMKEY.

e) Set the WR bit (NVMCON<15>). The erase

cycle begins and the CPU stalls for the dura-

tion of the erase cycle. When the erase is

done, the WR bit is cleared automatically.

4. Write the first 64 instructions from data RAM into

the program memory buffers (see Example 5-2).

5. Write the program block to Flash memory:

a) Set the NVMOP bits to ‘0001’ to configure

for row programming. Clear the ERASE bit

and set the WREN bit.

b) Write 55h to NVMKEY.

c) Write AAh to NVMKEY.

d) Set the WR bit. The programming cycle

begins and the CPU stalls for the duration of

the write cycle. When the write to Flash

memory is done, the WR bit is cleared

automatically.

6. Repeat Steps 4 and 5, using the next available

64 instructions from the block in data RAM by

incrementing the value in TBLPAG, until all

512 instructions are written back to Flash

memory.

For protection against accidental operations, the write

initiate sequence for NVMKEY must be used to allow

any erase or program operation to proceed. After the

programming command has been executed, the user

must wait for the programming time until programming

is complete. The two instructions following the start of

the programming sequence should be NOPs, as shown

in Example 5-3.

EXAMPL E 5-1: E RASING A PROGRAM MEMORY BLOCK

; Set up NVMCON for block erase operation

MOV #0x4042, W0 ;

MOV W0, NVMCON ; Initialize NVMCON

; Init pointer to row to be ERASED

MOV #tblpage(PROG_ADDR), W0 ;

MOV W0, TBLPAG ; Initialize PM Page Boundary SFR

MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointer

TBLWTL W0, [W0] ; Set base address of erase block

DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions

MOV #0x55, W0

MOV W0, NVMKEY ; Write the 55 key

MOV #0xAA, W1 ;

MOV W1, NVMKEY ; Write the AA key

BSET NVMCON, #WR ; Start the erase sequence

NOP ; Insert two NOPs after the erase

NOP ; command is asserted

 2005-2012 Microchip Technology Inc. DS39747F-page 55

PIC24FJ128GA010 FAMILY

EXAMPLE 5-2: LOADING THE WRITE BUFFERS

EXAMPLE 5-3: INITIATIN G A PROGRAMMING SE QUENCE

; Set up NVMCON for row programming operations

MOV #0x4001, W0 ;

MOV W0, NVMCON ; Initialize NVMCON

; Set up a pointer to the first program memory location to be written

; program memory selected, and writes enabled

MOV #0x0000, W0 ;

MOV W0, TBLPAG ; Initialize PM Page Boundary SFR

MOV #0x6000, W0 ; An example program memory address

; Perform the TBLWT instructions to write the latches

; 0th_program_word

MOV #LOW_WORD_0, W2 ;

MOV #HIGH_BYTE_0, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

; 1st_program_word

MOV #LOW_WORD_1, W2 ;

MOV #HIGH_BYTE_1, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

; 2nd_program_word

MOV #LOW_WORD_2, W2 ;

MOV #HIGH_BYTE_2, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

•

; 63rd_program_word

MOV #LOW_WORD_31, W2 ;

MOV #HIGH_BYTE_31, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0] ; Write PM high byte into program latch

DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions

MOV #0x55, W0

MOV W0, NVMKEY ; Write the 55 key

MOV #0xAA, W1 ;

MOV W1, NVMKEY ; Write the AA key

BSET NVMCON, #WR ; Start the program/erase sequence

BTSC NVMCON, #15 ; and wait for it to be

BRA $-2 ; completed

PIC24FJ128GA010 FAMILY

DS39747F-page 56  2005-2012 Microchip Technology Inc.

5.6.2 PROGRAMMING A SINGLE WORD

OF FLASH PROGRAM MEMORY

If a Flash location has been erased, it can be pro-

grammed using table write instructions to write an

instruction word (24-bit) into the write latch. The

TBLPAG register is loaded with the 8 Most Significant

Bytes of the Flash address. The TBLWTL and TBLWTH

instructions write the desired data into the write latches

and specify the lower 16 bits of the program memory

address to write to. To configure the NVMCON register

for a word write, set the NVMOP bits (NVMCON<3:0>)

to ‘0011’. The write is performed by executing the

unlock sequence and setting the WR bit.

EXAMPLE 5-4: PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY

; Setup a pointer to data Program Memory

MOV #tblpage(PROG_ADDR), W0 ;

MOV W0, TBLPAG ;Initialize PM Page Boundary SFR

MOV #tbloffset(PROG_ADDR), W0 ;Initialize a register with program memory address

MOV #LOW_WORD_N, W2 ;

MOV #HIGH_BYTE_N, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

; Setup NVMCON for programming one word to data Program Memory

MOV #0x4003, W0 ;

MOV W0, NVMCON ; Set NVMOP bits to 0011

DISI #5 ; Disable interrupts while the KEY sequence is

written

MOV #0x55, W0 ; Write the key sequence

MOV W0, NVMKEY

MOV #0xAA, W0

MOV W0, NVMKEY

BSET NVMCON, #WR ; Start the write cycle

 2005-2012 Microchip Technology Inc. DS39747F-page 57

PIC24FJ128GA010 FAMILY

6.0 RESETS

The Reset module combines all Reset sources and

controls the device Master Reset Signal, SYSRST. The

following is a list of device Reset sources:

• POR: Power-on Reset

•MCLR

: Pin Reset

•SWR: RESET Instruction

• WDT: Watchdog Timer Reset

• BOR: Brown-out Reset

• CM: Configuration Word Mismatch Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Opcode Reset

• UWR: Uninitialized W Register Reset

A simplified block diagram of the Reset module is

shown in Figure 6-1.

Any active source of Reset will make the SYSRST sig-

nal active. Many registers associated with the CPU and

peripherals are forced to a known Reset state. Most

registers are unaffected by a Reset; their status is

unknown on POR and unchanged by all other Resets.

All types of device Reset will set a corresponding status

bit in the RCON register to indicate the type of Reset

(see Register 6-1). A POR will clear all bits except for

the BOR and POR bits (RCON<1:0>), which are set.

The user may set or clear any bit at any time during

code execution. The RCON bits only serve as status

bits. Setting a particular Reset status bit in software will

not cause a device Reset to occur.

The RCON register also has other bits associated with

the Watchdog Timer and device power-saving states.

The function of these bits is discussed in other sections

of this manual.

FIGURE 6-1: RESE T SYSTEM BLOCK DIAGRAM

Note: This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive refer-

ence source. Refer to Section 7 . “Res et”

(DS39712) in the “PIC24F Family

Reference Ma nual” for more information.

Note: Refer to the specific peripheral or CPU

section of this manual for register Reset

states.

Note: The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset will be meaningful.

MCLR

VDD

VDD Rise

Detect

POR

Sleep or Idle

Brown-out

Reset

Enable Voltage Regulator

RESET

Instruction

WDT

Module

Glitch Filter

BOR

Trap Conflict

Illegal Opcode

Uninitialized W Register

SYSRST

Configuration Word Mismatch Reset

PIC24FJ128GA010 FAMILY

DS39747F-page 58  2005-2012 Microchip Technology Inc.

R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

TRAPR IOPUWR — — — —CMVREGS

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1

EXTR SWR SWDTEN(2)WDTO SLEEP IDLE BOR POR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 TRAPR: Trap Reset Flag bit

1 = A Trap Conflict Reset has occurred

0 = A Trap Conflict Reset has not occurred

bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit

1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an

Address Pointer caused a Reset

0 = An illegal opcode or uninitialized W Reset has not occurred

bit 13-10 Unimplemented: Read as ‘0’

bit 9 CM: Configuration Word Mismatch Reset Flag bit

1 = A Configuration Word Mismatch Reset has occurred

0 = A Configuration Word Mismatch Reset has not occurred

bit 8 VREGS: Voltage Regulator Standby Enable bit

1 = Regulator remains active during Sleep

0 = Regulator goes to standby during Sleep

bit 7 EXTR: External Reset (MCLR) Pin bit

1 = A Master Clear (pin) Reset has occurred

0 = A Master Clear (pin) Reset has not occurred

bit 6 SWR: Software Reset (Instruction) Flag bit

1 = A RESET instruction has been executed

0 = A RESET instruction has not been executed

bit 5 SWDTEN: Software Enable/Disable of WDT bit(2)

1 = WDT is enabled

0 = WDT is disabled

bit 4 WDTO: Watchdog Timer Time-out Flag bit

1 = WDT time-out has occurred

0 = WDT time-out has not occurred

bit 3 SLEEP: Wake From Sleep Flag bit

1 = Device has been in Sleep mode

0 = Device has not been in Sleep mode

bit 2 IDLE: Wake-up From Idle Flag bit

1 = Device was in Idle mode

0 = Device was not in Idle mode

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

 2005-2012 Microchip Technology Inc. DS39747F-page 59

PIC24FJ128GA010 FAMILY

TABLE 6-1: RESET FLAG BIT OPERATION

6.1 Clock Source Selection at Reset

If clock switching is enabled, the system clock source at

device Reset is chosen as shown in Table 6-2. If clock

switching is disabled, the system clock source is always

selected according to the oscillator Configuration bits.

Refer to Section 8.0 “Oscillator Configuration” for

further details.

TABLE 6-2: OSCILLATOR SELECTION vs.

TYPE OF RESET (CLOCK

SWITCHING ENAB LED)

6.2 Device Reset Times

The Reset times for various types of device Reset are

summarized in Table 6-3. Note that the system Reset

signal, SYSRST

, is released after the POR and PWRT

delay times expire.

The time that the device actually begins to execute

code will also depend on the system oscillator delays,

which include the Oscillator Start-up Timer (OST) and

the PLL lock time. The OST and PLL lock times occur

in parallel with the applicable SYSRST delay times.

The FSCM delay determines the time at which the

FSCM begins to monitor the system clock source after

the SYSRST signal is released.

bit 1 BOR: Brown-out Reset Flag bit

1 = A Brown-out Reset has occurred (note that BOR is also set after a Power-on Reset)

0 = A Brown-out Reset has not occurred

bit 0 POR: Power-on Reset Flag bit

1 = A Power-on Reset has occurred

0 = A Power-on Reset has not occurred

Flag Bit Setting Even t Clear ing Even t

TRAPR (RCON<15>) Trap conflict event POR

IOPUWR (RCON<14>) Illegal opcode or uninitialized W register access POR

EXTR (RCON<7>) MCLR Reset POR

SWR (RCON<6>) RESET instruction POR

WDTO (RCON<4>) WDT time-out PWRSAV instruction, POR

SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR

IDLE (RCON<2>) PWRSAV #IDLE instruction POR

BOR (RCON<1>) POR, BOR —

POR (RCON<0>) POR —

Note: All Reset flag bits may be set or cleared by the user software.

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

Reset Type Clock Source Determinant

POR Oscillator Configuration bits

(FNOSC<2:0>)

BOR

MCLR COSC Control bits

(OSCCON<14:12>)

WDTR

SWR

PIC24FJ128GA010 FAMILY

DS39747F-page 60  2005-2012 Microchip Technology Inc.

TABLE 6-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS

Reset Type Clock Source SYSRST Delay System Clock

Delay FSCM

Delay Notes

POR EC, FRC, FRCDIV, LPRC TPOR + TSTARTUP + TRST ——1, 2, 3

ECPLL, FRCPLL TPOR + TSTARTUP + TRST TLOCK TFSCM 1, 2, 3, 5, 6

XT, HS, SOSC TPOR + TSTARTUP + TRST TOST TFSCM 1, 2, 3, 4, 6

XTPLL, HSPLL TPOR + TSTARTUP + TRST TOST + TLOCK TFSCM 1, 2, 3, 4, 5, 6

BOR EC, FRC, FRCDIV, LPRC TSTARTUP + TRST ——2, 3

ECPLL, FRCPLL TSTARTUP + TRST TLOCK TFSCM 2, 3, 5, 6

XT, HS, SOSC TSTARTUP + TRST TOST TFSCM 2, 3, 4, 6

XTPLL, HSPLL TSTARTUP + TRST TOST + TLOCK TFSCM 2, 3, 4, 5, 6

MCLR Any Clock TRST ——3

WDT Any Clock TRST ——

Software Any Clock TRST ——

Illegal Opcode Any Clock TRST ——

Uninitialized W Any Clock TRST ——

Trap Conflict Any Clock TRST ——

Note 1: TPOR = Power-on Reset delay (10 s nominal).

2: T

STARTUP = TVREG (10 s nominal) if the on-chip regulator is enabled or TPWRT (64 ms nominal) if an

on-chip regulator is disabled.

3: TRST = Internal state Reset time (20 s nominal).

4: T

OST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the

oscillator clock to the system.

5: TLOCK = PLL lock time.

6: TFSCM = Fail-Safe Clock Monitor delay (100 s nominal).

 2005-2012 Microchip Technology Inc. DS39747F-page 61

PIC24FJ128GA010 FAMILY

6.2.1 POR AND LONG OSCILLATOR

START-UP TIMES

The oscillator start-up circuitry and its associated delay

timers are not linked to the device Reset delays that

occur at power-up. Some crystal circuits (especially

low-frequency crystals) will have a relatively long

start-up time. Therefore, one or more of the following

conditions is possible after SYSRST is released:

• The oscillator circuit has not begun to oscillate.

• The Oscillator Start-up Timer has NOT expired (if

a crystal oscillator is used).

• The PLL has not achieved a lock (if PLL is used).

The device will not begin to execute code until a valid

clock source has been released to the system. There-

fore, the oscillator and PLL start-up delays must be

considered when the Reset delay time must be known.

6.2.2 FAIL-SAFE CLOCK MONITOR

(FSCM) AND DEVICE RESETS

If the FSCM is enabled, it will begin to monitor the sys-

tem clock source when SYSRST is released. If a valid

clock source is not available at this time, the device will

automatically switch to the FRC oscillator and the user

can switch to the desired crystal oscillator in the Trap

Service Routine.

6.2.2.1 FSCM Delay for Crystal and PLL

Clock Sources

When the system clock source is provided by a crystal

oscillator and/or the PLL, a small delay, TFSCM, will

automatically be inserted after the POR and PWRT

delay times. The FSCM will not begin to monitor the

system clock source until this delay expires. The FSCM

delay time is nominally 100 s and provides additional

time for the oscillator and/or PLL to stabilize. In most

cases, the FSCM delay will prevent an oscillator failure

trap at a device Reset when the PWRT is disabled.

6.3 Special Functi on Re gister Reset

States

Most of the Special Function Registers (SFRs) associ-

ated with the PIC24F CPU and peripherals are reset to a

particular value at a device Reset. The SFRs are

grouped by their peripheral or CPU function and their

Reset values are specified in each section of this manual.

The Reset value for each SFR does not depend on the

type of Reset, with the exception of four registers. The

Reset value for the Reset Control register, RCON, will

depend on the type of device Reset. The Reset value for

the Oscillator Control register, OSCCON, will depend on

the type of Reset and the programmed values of the

oscillator Configuration bits in the FOSC Device Config-

uration register (see Table 6-2). The RCFGCAL and

NVMCON registers are only affected by a POR.

PIC24FJ128GA010 FAMILY

DS39747F-page 62  2005-2012 Microchip Technology Inc.

NOTES:

 2005-2012 Microchip Technology Inc. DS39747F-page 63

PIC24FJ128GA010 FAMILY

7.0 INTERRUPT CONTROLLER

The PIC24F interrupt controller reduces the numerous

peripheral interrupt request signals to a single interrupt

request signal to the PIC24F CPU. It has the following

features:

• Up to 8 processor exceptions and software traps

• 7 user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

• A unique vector for each interrupt or exception

source

• Fixed priority within a specified user priority level

• Alternate Interrupt Vector Table (AIVT) for debug

support

• Fixed interrupt entry and return latencies

7.1 Interrupt Vector Table

The Interrupt Vector Table (IVT) is shown in Figure 7-1.

The IVT resides in program memory, starting at location,

000004h. The IVT contains 126 vectors, consisting of

8 non-maskable trap vectors, plus up to 118 sources of

interrupt. In general, each interrupt source has its own

vector. Each interrupt vector contains a 24-bit wide

address. The value programmed into each interrupt vec-

tor location is the starting address of the associated

Interrupt Service Routine (ISR).

Interrupt vectors are prioritized in terms of their natural

priority; this is linked to their position in the vector table.

All other things being equal, lower addresses have a

higher natural priority. For example, the interrupt asso-

ciated with Vector 0 will take priority over interrupts at

any other vector address.

PIC24FJ128GA010 family devices implement non-

maskable traps and unique interrupts. These are

summarized in Ta b l e 7 - 1 and Tab l e 7 - 2.

7.1.1 ALTERNATE INTERRUPT VECTOR

TABL E

The Alternate Interrupt Vector Table (AIVT) is located

after the IVT, as shown in Figure 7-1. Access to the

AIVT is provided by the ALTIVT control bit

(INTCON2<15>). If the ALTIVT bit is set, all interrupt

and exception processes will use the alternate vectors

instead of the default vectors. The alternate vectors are

organized in the same manner as the default vectors.

The AIVT supports emulation and debugging efforts by

providing a means to switch between an application

and a support environment without requiring the inter-

rupt vectors to be reprogrammed. This feature also

enables switching between applications for evaluation

of different software algorithms at run time. If the AIVT

is not needed, the AIVT should be programmed with

the same addresses used in the IVT.

7.2 Reset Sequence

A device Reset is not a true exception because the

interrupt controller is not involved in the Reset process.

The PIC24F device clears its registers in response to a

Reset which forces the PC to zero. The microcontroller

then begins program execution at location, 000000h.

The user programs a GOTO instruction at the Reset

address, which redirects program execution to the

appropriate start-up routine.

Note: This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 8. “Interrupts”

(DS39707) in the “PIC24F Family

Reference Ma nual” for more information.

Note: Any unimplemented or unused vector

locations in the IVT and AIVT should be

programmed with the address of a default

interrupt handler routine that contains a

RESET instruction.

PIC24FJ128GA010 FAMILY

DS39747F-page 64  2005-2012 Microchip Technology Inc.

FIGURE 7-1: PIC24F INTERRUPT VECTOR TABLE

TABLE 7-1: TRAP VECTOR DETAILS

Vector Number IVT Address AIVT Address Trap Source

0 000004h 000104h Reserved

1 000006h 000106h Oscillator Failure

2 000008h 000108h Address Error

3 00000Ah 00010Ah Stack Error

4 00000Ch 00010Ch Math Error

5 00000Eh 00010Eh Reserved

6 000010h 000110h Reserved

7 000012h 000112h Reserved

Reset – GOTO Instruction 000000h

Reset – GOTO Address 000002h

Reserved 000004h

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

Interrupt Vector 0 000014h

Interrupt Vector 1

—

Interrupt Vector 52 00007Ch

Interrupt Vector 53 00007Eh

Interrupt Vector 54 000080h

—

Interrupt Vector 116 0000FCh

Interrupt Vector 117 0000FEh

Reserved 000100h

Reserved 000102h

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

Interrupt Vector 0 000114h

Interrupt Vector 1

—

Interrupt Vector 52 00017Ch

Interrupt Vector 53 00017Eh

Interrupt Vector 54 000180h

—

Interrupt Vector 116

Interrupt Vector 117 0001FEh

Start of Code 000200h

Decreasing Natural Order Priority

Interrupt Vector Table (IVT)(1)

Alternate Interrupt Vector Table (AIVT)(1)

Note 1: See Table 7-2 for the interrupt vector list.

 2005-2012 Microchip Technology Inc. DS39747F-page 65

PIC24FJ128GA010 FAMILY

TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS

Interrupt Source Vector

Number IVT Address AIVT

Address

Interrupt Bit Locations

Flag Enable Priority

ADC1 Conversion Done 13 00002Eh 00012Eh IFS0<13> IEC0<13> IPC3<6:4>

Comparator Event 18 000038h 000138h IFS1<2> IEC1<2> IPC4<10:8>

CRC Generator 67 00009Ah 00019Ah IFS4<3> IEC4<3> IPC16<14:12>

External Interrupt 0 0 000014h 000114h IFS0<0> IEC0<0> IPC0<2:0>

External Interrupt 1 20 00003Ch 00013Ch IFS1<4> IEC1<4> IPC5<2:0>

External Interrupt 2 29 00004Eh 00014Eh IFS1<13> IEC1<13> IPC7<6:4>

External Interrupt 3 53 00007Eh 00017Eh IFS3<5> IEC3<5> IPC13<6:4>

External Interrupt 4 54 000080h 000180h IFS3<6> IEC3<6> IPC13<10:8>

I2C1 Master Event 17 000036h 000136h IFS1<1> IEC1<1> IPC4<6:4>

I2C1 Slave Event 16 000034h 000134h IFS1<0> IEC1<0> IPC4<2:0>

I2C2 Master Event 50 000078h 000178h IFS3<2> IEC3<2> IPC12<10:8>

I2C2 Slave Event 49 000076h 000176h IFS3<1> IEC3<1> IPC12<6:4>

Input Capture 1 1 000016h 000116h IFS0<1> IEC0<1> IPC0<6:4>

Input Capture 2 5 00001Eh 00011Eh IFS0<5> IEC0<5> IPC1<6:4>

Input Capture 3 37 00005Eh 00015Eh IFS2<5> IEC2<5> IPC9<6:4>

Input Capture 4 38 000060h 000160h IFS2<6> IEC2<6> IPC9<10:8>

Input Capture 5 39 000062h 000162h IFS2<7> IEC2<7> IPC9<14:12>

Input Change Notification 19 00003Ah 00013Ah IFS1<3> IEC1<3> IPC4<14:12>

Output Compare 1 2 000018h 000118h IFS0<2> IEC0<2> IPC0<10:8>

Output Compare 2 6 000020h 000120h IFS0<6> IEC0<6> IPC1<10:8>

Output Compare 3 25 000046h 000146h IFS1<9> IEC1<9> IPC6<6:4>

Output Compare 4 26 000048h 000148h IFS1<10> IEC1<10> IPC6<10:8>

Output Compare 5 41 000066h 000166h IFS2<9> IEC2<9> IPC10<6:4>

Parallel Master Port 45 00006Eh 00016Eh IFS2<13> IEC2<13> IPC11<6:4>

Real-Time Clock/Calendar 62 000090h 000190h IFS3<14> IEC3<14> IPC15<10:8>

SPI1 Error 9 000026h 000126h IFS0<9> IEC0<9> IPC2<6:4>

SPI1 Event 10 000028h 000128h IFS0<10> IEC0<10> IPC2<10:8>

SPI2 Error 32 000054h 000154h IFS2<0> IEC0<0> IPC8<2:0>

SPI2 Event 33 000056h 000156h IFS2<1> IEC2<1> IPC8<6:4>

Timer1 3 00001Ah 00011Ah IFS0<3> IEC0<3> IPC0<14:12>

Timer2 7 000022h 000122h IFS0<7> IEC0<7> IPC1<14:12>

Timer3 8 000024h 000124h IFS0<8> IEC0<8> IPC2<2:0>

Timer4 27 00004Ah 00014Ah IFS1<11> IEC1<11> IPC6<14:12>

Timer5 28 00004Ch 00014Ch IFS1<12> IEC1<12> IPC7<2:0>

UART1 Error 65 000096h 000196h IFS4<1> IEC4<1> IPC16<6:4>

UART1 Receiver 11 00002Ah 00012Ah IFS0<11> IEC0<11> IPC2<14:12>

UART1 Transmitter 12 00002Ch 00012Ch IFS0<12> IEC0<12> IPC3<2:0>

UART2 Error 66 000098h 000198h IFS4<2> IEC4<2> IPC16<10:8>

UART2 Receiver 30 000050h 000150h IFS1<14> IEC1<14> IPC7<10:8>

UART2 Transmitter 31 000052h 000152h IFS1<15> IEC1<15> IPC7<14:12>

PIC24FJ128GA010 FAMILY

DS39747F-page 66  2005-2012 Microchip Technology Inc.

7.3 Interrupt Control and Status

Registers

The PIC24FJ128GA010 family devices implement a

total of 29 registers for the interrupt controller:

• INTCON1

• INTCON2

• IFS0 through IFS4

• IEC0 through IEC4

• IPC0 through IPC14, and IPC16

•INTTREG

Global interrupt control functions are controlled from

INTCON1 and INTCON2. INTCON1 contains the Inter-

rupt Nesting Disable (NSTDIS) bit, as well as the

control and status flags for the processor trap sources.

The INTCON2 register controls the external interrupt

request signal behavior and the use of the Alternate

Interrupt Vector Table.

The IFS registers maintain all of the interrupt request

flags. Each source of interrupt has a status bit which is

set by the respective peripherals, or external signal,

and is cleared via software.

The IEC registers maintain all of the interrupt enable

bits. These control bits are used to individually enable

interrupts from the peripherals or external signals.

The IPC registers are used to set the Interrupt Priority

Level for each source of interrupt. Each user interrupt

source can be assigned to one of eight priority levels.

The interrupt sources are assigned to the IFSx, IECx

and IPCx registers in the same sequence that they are

listed in Table 7-2. For example, the INT0 (External

Interrupt 0) is shown as having a vector number and a

natural order priority of 0. Thus, the INT0IF status bit is

found in IFS0<0>, the enable bit in IEC0<0> and the

priority bits in the first position of IPC0 (IPC0<2:0>).

Although they are not specifically part of the interrupt

control hardware, two of the CPU control registers con-

tain bits that control interrupt functionality. The CPU

STATUS register (SR) contains the IPL<2:0> bits

(SR<7:5>). These indicate the current CPU Interrupt

Priority Level. The user may change the current CPU

priority level by writing to the IPL bits.

The CORCON register contains the IPL3 bit, which

together with IPL<2:0>, also indicates the current CPU

priority level. IPL3 is a read-only bit so that trap events

cannot be masked by the user software.

The interrupt controller has the Interrupt Controller Test

interrupt controller. When an interrupt request occurs,

its associated vector number and the new interrupt pri-

ority level are latched into INTTREG. This information

can be used to determine a specific interrupt source if

a generic ISR is used for multiple vectors, such as

when ISR remapping is used in bootloader applica-

tions. It also could be used to check if another interrupt

is pending while in an ISR.

All Interrupt registers are described in Register 7-1

through Register 7-30, in the following pages.

 2005-2012 Microchip Technology Inc. DS39747F-page 67

PIC24FJ128GA010 FAMILY

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —DC

(1)

bit 15 bit 8

R/W-0(1)R/W-0(1)R/W-0(1)R-0 R/W-0 R/W-0 R/W-0 R/W-0

IPL2(2,3)IPL1(2,3)IPL0(2,3)RA(1)N(1)OV(1)Z(1)C(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)

111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled

110 = CPU Interrupt Priority Level is 6 (14)

101 = CPU Interrupt Priority Level is 5 (13)

100 = CPU Interrupt Priority Level is 4 (12)

011 = CPU Interrupt Priority Level is 3 (11)

010 = CPU Interrupt Priority Level is 2 (10)

001 = CPU Interrupt Priority Level is 1 (9)

000 = CPU Interrupt Priority Level is 0 (8)

Note 1: See Register 3-1 for the description of the remaining bit(s) that are not dedicated to interrupt control functions.

2: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority Level. The

value in parentheses indicates the Interrupt Priority Level if IPL3 = 1.

3: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0

— — — —IPL3

(2)PSV(1)— —

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 3 IPL3: CPU Interrupt Priority Level Status bit(2)

1 = CPU Interrupt Priority Level is greater than 7

0 = CPU Interrupt Priority Level is 7 or less

Note 1: See Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control functions.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

PIC24FJ128GA010 FAMILY

DS39747F-page 68  2005-2012 Microchip Technology Inc.

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

NSTDIS — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

— — — MATHERR ADDRERR STKERR OSCFAIL —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 NSTDIS: Interrupt Nesting Disable bit

1 = Interrupt nesting is disabled

0 = Interrupt nesting is enabled

bit 14-5 Unimplemented: Read as ‘0’

bit 4 MATHERR: Arithmetic Error Trap Status bit

1 = Overflow trap has occurred

0 = Overflow trap has not occurred

bit 3 ADDRERR: Address Error Trap Status bit

1 = Address error trap has occurred

0 = Address error trap has not occurred

bit 2 STKERR: Stack Error Trap Status bit

1 = Stack error trap has occurred

0 = Stack error trap has not occurred

bit 1 OSCFAIL: Oscillator Failure Trap Status bit

1 = Oscillator failure trap has occurred

0 = Oscillator failure trap has not occurred

bit 0 Unimplemented: Read as ‘0’

 2005-2012 Microchip Technology Inc. DS39747F-page 69

PIC24FJ128GA010 FAMILY

R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

ALTIVT DISI — — — — — —

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — INT4EP INT3EP INT2EP INT1EP INT0EP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit

1 = Use alternate vector table

0 = Use standard (default) vector table

bit 14 DISI: DISI Instruction Status bit

1 = DISI instruction is active

0 = DISI is not active

bit 13-5 Unimplemented: Read as ‘0’

bit 4 INT4EP: External Interrupt 4 Edge Detect Polarity Select bit

1 = Interrupt on negative edge

0 = Interrupt on positive edge

bit 3 INT3EP: External Interrupt 3 Edge Detect Polarity Select bit

1 = Interrupt on negative edge

0 = Interrupt on positive edge

bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1 = Interrupt on negative edge

0 = Interrupt on positive edge

bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit

1 = Interrupt on negative edge

0 = Interrupt on positive edge

bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit

1 = Interrupt on negative edge

0 = Interrupt on positive edge

PIC24FJ128GA010 FAMILY

DS39747F-page 70  2005-2012 Microchip Technology Inc.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 AD1IF: A/D Conversion Complete Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 9 SPF1IF: SPI1 Fault Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 8 T3IF: Timer3 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 7 T2IF: Timer2 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 4 Unimplemented: Read as ‘0’

bit 3 T1IF: Timer1 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 0 INT0IF: External Interrupt 0 Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

 2005-2012 Microchip Technology Inc. DS39747F-page 71

PIC24FJ128GA010 FAMILY

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF —

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — INT1IF CNIF CMIF MI2C1IF SI2C1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 14 U2RXIF: UART2 Receiver Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 13 INT2IF: External Interrupt 2 Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 12 T5IF: Timer5 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 11 T4IF: Timer4 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 10 OC4IF: Output Compare Channel 4 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 9 OC3IF: Output Compare Channel 3 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 8-5 Unimplemented: Read as ‘0’

bit 4 INT1IF: External Interrupt 1 Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 3 CNIF: Input Change Notification Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 2 CMIF: Comparator Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 1 MI2C1IF: Master I2C1 Event Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

PIC24FJ128GA010 FAMILY

DS39747F-page 72  2005-2012 Microchip Technology Inc.

U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0

——PMPIF— — —OC5IF—

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

IC5IF IC4IF IC3IF — — — SPI2IF SPF2IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 PMPIF: Parallel Master Port Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 12-10 Unimplemented: Read as ‘0’

bit 9 OC5IF: Output Compare Channel 5 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 8 Unimplemented: Read as ‘0’

bit 7 IC5IF: Input Capture Channel 5 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 6 IC4IF: Input Capture Channel 4 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 4-2 Unimplemented: Read as ‘0’

bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 0 SPF2IF: SPI2 Fault Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

 2005-2012 Microchip Technology Inc. DS39747F-page 73

PIC24FJ128GA010 FAMILY

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

—PMPIF— — — — — —

bit 15 bit 8

U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0

— INT4IF INT3IF —— MI2C2IF SI2C2IF —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14 RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 13-7 Unimplemented: Read as ‘0’

bit 6 INT4IF: External Interrupt 4 Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 5 INT3IF: External Interrupt 3 Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 4-3 Unimplemented: Read as ‘0’

bit 2 MI2C2IF: Master I2C2 Event Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 0 Unimplemented: Read as ‘0’

PIC24FJ128GA010 FAMILY

DS39747F-page 74  2005-2012 Microchip Technology Inc.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0

— — — — CRCIF U2ERIF U1ERIF —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-4 Unimplemented: Read as ‘0’

bit 3 CRCIF: CRC Generator Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 2 U2ERIF: UART2 Error Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 1 U1ERIF: UART1 Error Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 0 Unimplemented: Read as ‘0’

 2005-2012 Microchip Technology Inc. DS39747F-page 75

PIC24FJ128GA010 FAMILY

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 AD1IE: A/D Conversion Complete Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 10 SPI1IE: SPI1 Transfer Complete Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 9 SPF1IE: SPI1 Fault Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 8 T3IE: Timer3 Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 7 T2IE: Timer2 Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 4 Unimplemented: Read as ‘0’

bit 3 T1IE: Timer1 Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 0 INT0IE: External Interrupt 0 Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

PIC24FJ128GA010 FAMILY

DS39747F-page 76  2005-2012 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE —

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — INT1IE CNIE CMIE MI2C1IE SI2C1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 14 U2RXIE: UART2 Receiver Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 13 INT2IE: External Interrupt 2 Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 12 T5IE: Timer5 Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 11 T4IE: Timer4 Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 10 OC4IE: Output Compare Channel 4 Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 9 OC3IE: Output Compare Channel 3 Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 8-5 Unimplemented: Read as ‘0’

bit 4 INT1IE: External Interrupt 1 Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 3 CNIE: Input Change Notification Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 2 CMIE: Comparator Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 1 MI2C1IE: Master I2C1 Event Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 0 SI2C1IE: Slave I2C1 Event Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

 2005-2012 Microchip Technology Inc. DS39747F-page 77

PIC24FJ128GA010 FAMILY

U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0

——PMPIE— — —OC5IE—

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

IC5IE IC4IE IC3IE — — — SPI2IE SPF2IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 PMPIE: Parallel Master Port Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 12-10 Unimplemented: Read as ‘0’

bit 9 OC5IE: Output Compare Channel 5 Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 8 Unimplemented: Read as ‘0’

bit 7 IC5IE: Input Capture Channel 5 Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 6 IC4IE: Input Capture Channel 4 Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 4-2 Unimplemented: Read as ‘0’

bit 1 SPI2IE: SPI2 Event Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

PIC24FJ128GA010 FAMILY

DS39747F-page 78  2005-2012 Microchip Technology Inc.

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

—RTCIE— — — — — —

bit 15 bit 8

U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0

— INT4IE INT3IE —— MI2C2IE SI2C2IE —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 13-7 Unimplemented: Read as ‘0’

bit 6 INT4IE: External Interrupt 4 Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 5 INT3IE: External Interrupt 3 Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 4-3 Unimplemented: Read as ‘0’

bit 2 MI2C2IE: Master I2C2 Event Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 1 SI2C2IE: Slave I2C2 Event Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 0 Unimplemented: Read as ‘0’

 2005-2012 Microchip Technology Inc. DS39747F-page 79

PIC24FJ128GA010 FAMILY

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0

— — — — CRCIE U2ERIE U1ERIE —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-4 Unimplemented: Read as ‘0’

bit 3 CRCIE: CRC Generator Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 2 U2ERIE: UART2 Error Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 1 U1ERIE: UART1 Error Interrupt Enable bit

1 = Interrupt request is enabled

0 = Interrupt request is not enabled

bit 0 Unimplemented: Read as ‘0’

PIC24FJ128GA010 FAMILY

DS39747F-page 80  2005-2012 Microchip Technology Inc.

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 INT0IP<2:0:> External Interrupt 0 Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

 2005-2012 Microchip Technology Inc. DS39747F-page 81

PIC24FJ128GA010 FAMILY

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— IC2IP2 IC2IP1 IC2IP0 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

PIC24FJ128GA010 FAMILY

DS39747F-page 82  2005-2012 Microchip Technology Inc.

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SPF1IP<2:0>: SPI1 Fault Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

 2005-2012 Microchip Technology Inc. DS39747F-page 83

PIC24FJ128GA010 FAMILY

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 AD1IP<2:0>: A/D Conversion Complete Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

PIC24FJ128GA010 FAMILY

DS39747F-page 84  2005-2012 Microchip Technology Inc.

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 CNIP<2:0>: Input Change Notification Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 CMIP<2:0>: Comparator Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 MI2C1IP<2:0>: Master I2C1 Event Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 SI2C1IP<2:0>: Slave I2C1 Event Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

 2005-2012 Microchip Technology Inc. DS39747F-page 85

PIC24FJ128GA010 FAMILY

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — INT1IP2 INT1IP1 INT1IP0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 Unimplemented: Read as ‘0’

bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

PIC24FJ128GA010 FAMILY

DS39747F-page 86  2005-2012 Microchip Technology Inc.

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— OC3IP2 OC3IP1 OC3IP0 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T4IP<2:0>: Timer4 Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

 2005-2012 Microchip Technology Inc. DS39747F-page 87

PIC24FJ128GA010 FAMILY

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

PIC24FJ128GA010 FAMILY

DS39747F-page 88  2005-2012 Microchip Technology Inc.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 SPF2IP<2:0>: SPI2 Fault Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

 2005-2012 Microchip Technology Inc. DS39747F-page 89

PIC24FJ128GA010 FAMILY

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— IC3IP2 IC3IP1 IC3IP0 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 IC5IP<2:0>: Input Capture Channel 5 Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 IC4IP<2:0>: Input Capture Channel 4 Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

PIC24FJ128GA010 FAMILY

DS39747F-page 90  2005-2012 Microchip Technology Inc.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— OC5IP2 OC5IP1 OC5IP0 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 OC5IP<2:0>: Output Compare Channel 5 Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— PMPIP2 PMPIP1 PMPIP0 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 PMPIP<2:0>: Parallel Master Port Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

 2005-2012 Microchip Technology Inc. DS39747F-page 91

PIC24FJ128GA010 FAMILY

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 MI2C2IP<2:0>: Master I2C2 Event Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SI2C2IP<2:0>: Slave I2C2 Event Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

PIC24FJ128GA010 FAMILY

DS39747F-page 92  2005-2012 Microchip Technology Inc.

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — INT4IP2 IN4IP1 INT4IP0

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— INT3IP2 INT3IP1 INT3IP0 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 INT4IP<2:0>: External Interrupt 4 Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 INT3IP<2:0>: External Interrupt 3 Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

 2005-2012 Microchip Technology Inc. DS39747F-page 93

PIC24FJ128GA010 FAMILY

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — RTCIP2 RTCIP1 RTCIP0

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 RTCIP<2:0>: Real-Time Clock/Calendar Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 7-0 Unimplemented: Read as ‘0’

PIC24FJ128GA010 FAMILY

DS39747F-page 94  2005-2012 Microchip Technology Inc.

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— U1ERIP2 U1ERIP1 U1ERIP0 — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 CRCIP2:0>: CRC Generator Error Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 U2ERIP<2:0>: UART2 Error Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 U1ERIP<2:0>: UART1 Error Interrupt Priority bits

111 = Interrupt is Priority 7 (highest priority interrupt)

•

001 = Interrupt is Priority 1

000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

 2005-2012 Microchip Technology Inc. DS39747F-page 95

PIC24FJ128GA010 FAMILY

R-0 U-0 R/W-0 U-0 R-0 R-0 R-0 R-0

CPUIRQ —VHOLD— ILR3ILR2ILR1ILR0

bit 15 bit 8

U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

— VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CPUIRQ: Interrupt Request from Interrupt Controller CPU bit

1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens

when the CPU priority is higher than the interrupt priority

0 = No interrupt request is unacknowledged

bit 14 Unimplemented: Read as ‘0’

bit 13 VHOLD: Vector Number Capture Configuration bit

1 = The VECNUM bits contain the value of the highest priority pending interrupt

0 = The VECNUM bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt that

has occurred with higher priority than the CPU, even if other interrupts are pending)

bit 12 Unimplemented: Read as ‘0’

bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits

1111 = CPU Interrupt Priority Level is 15

•

0001 = CPU Interrupt Priority Level is 1

0000 = CPU Interrupt Priority Level is 0

bit 7 Unimplemented: Read as ‘0’

bit 6-0 VECNUM<6:0>: Pending Interrupt Vector ID bits (pending vector number is VECNUM + 8)

0111111 = Interrupt Vector pending is number 135

•

0000001 = Interrupt Vector pending is number 9

0000000 = Interrupt Vector pending is number 8

PIC24FJ128GA010 FAMILY

DS39747F-page 96  2005-2012 Microchip Technology Inc.

7.4 Interrupt Setup Procedures

7.4.1 INITIALIZATION

To configure an interrupt source:

1. Set the NSTDIS Control bit (INTCON1<15>) if

nested interrupts are not desired.

2. Select the user-assigned priority level for the

interrupt source by writing the control bits in the

appropriate IPCx Control register. The priority

level will depend on the specific application and

type of interrupt source. If multiple priority levels

are not desired, the IPCx register control bits for

all enabled interrupt sources may be

programmed to the same non-zero value.

3. Clear the interrupt flag status bit associated with

the peripheral in the associated IFSx Status

4. Enable the interrupt source by setting the inter-

rupt enable control bit associated with the

source in the appropriate IECx Control register.

7.4.2 INTERRUPT SERVICE ROUTINE

The method that is used to declare an ISR and initialize

the IVT with the correct vector address will depend on

the programming language (i.e., ‘C’ or assembler) and

the language development toolsuite that is used to

develop the application. In general, the user must clear

the interrupt flag in the appropriate IFSx register for the

source of interrupt that the ISR handles. Otherwise, the

ISR will be re-entered immediately after exiting the

routine. If the ISR is coded in assembly language, it

must be terminated using a RETFIE instruction to

unstack the saved PC value, SRL value and old CPU

priority level.

7.4.3 TRAP SERVICE ROUTINE

A Trap Service Routine (TSR) is coded like an ISR,

except that the appropriate trap status flag in the

INTCON1 register must be cleared to avoid re-entry

into the TSR.

7.4.4 INTERRUPT DISABLE

All user interrupts can be disabled using the following

procedure:

1. Push the current SR value onto the software

stack using the PUSH instruction.

2. Force the CPU to Priority Level 7 by inclusive

ORing the value OEh with SRL.

To enable user interrupts, the POP instruction may be

used to restore the previous SR value.

Note that only user interrupts with a priority level of 7 or

less can be disabled. Trap sources (Level 8-15) cannot

be disabled.

The DISI instruction provides a convenient way to dis-

able interrupts of Priority Levels 1-6 for a fixed period of

time. Level 7 interrupt sources are not disabled by the

DISI instruction.

Note: At a device Reset, the IPC registers are

initialized, such that all user interrupt

sources are assigned to Priority Level 4.

 2005-2012 Microchip Technology Inc. DS39747F-page 97

PIC24FJ128GA010 FAMILY

8.0 OSCILLATOR

CONFIGURATION

The oscillator system for PIC24FJ128GA010 family

devices has the following features:

• A total of four external and internal oscillator options

as clock sources, providing 11 different clock modes

• On-chip 4x PLL to boost internal operating frequency

on select internal and external oscillator sources

• Software-controllable switching between various

clock sources

• Software-controllable postscaler for selective

clocking of CPU for system power savings

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and permits safe application recovery

or shutdown

A simplified diagram of the oscillator system is shown

in Figure 8-1.

FIGURE 8-1: PIC24FJ128G A0 10 FAMILY CLOCK DIAGRAM

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 6. “Oscillator”

(DS39700) in the “PIC24F Family

Reference Manual” for more information.

PIC24FJ128GA010 Family

Secondar y Osc illa to r

SOSCEN

Enable

Oscillator

SOSCO

SOSCI

Clock Source Option

for Other Modules

OSC2

OSC1

Primary Oscillator

XTPLL, HSPLL,

XT, HS, EC

CPU

Peripherals

Postscaler

CLKDIV<10:8>

WDT, PWRT

8 MHz

FRCDIV

31 kHz (Nominal)

FRC

Oscillator

LPRC

Oscillator

SOSC

LPRC

Postscaler

Clock Control Logic

Fail-Safe

Clock

Monitor

CLKDIV<14:12>

FRC

ECPLL, FRCPLL

CLKO

(Nominal)

4 x PLL

8 MHz/

4 MHz

PIC24FJ128GA010 FAMILY

DS39747F-page 98  2005-2012 Microchip Technology Inc.

8.1 CPU Clocking Scheme

The system clock source can be provided by one of

four sources:

• Primary Oscillator (POSC) on the OSC1 and

OSC2 pins

• Secondary Oscillator (SOSC) on the SOSCI and

SOSCO pins

• Fast Internal RC (FRC) Oscillator

• Low-Power Internal RC (LPRC) Oscillator

The primary oscillator and FRC sources have the

option of using the internal 4x PLL. The frequency of

the FRC clock source can optionally be reduced by the

programmable clock divider. The selected clock source

generates the processor and peripheral clock sources.

The processor clock source is divided by two to pro-

duce the internal instruction cycle clock, FCY. In this

document, the instruction cycle clock is also denoted

by FOSC/2. The internal instruction cycle clock, FOSC/2,

can be provided on the OSC2 I/O pin for some

operating modes of the primary oscillator.

8.2 Oscillator Configuration

The oscillator source (and operating mode) that is

used at a device Power-on Reset event is selected

using Configuration bit settings. The oscillator Config-

uration bit settings are located in the Configuration

registers in the program memory (refer to

Section 24.1 “Configuration Bits” for further

details). The Primary Oscillator Configuration bits,

POSCMD<1:0> (Configuration Word 2<1:0>), and

the Initial Oscillator Select Configuration bits,

FNOSC<2:0> (Configuration Word 2<10:8>), select

the oscillator source that is used at a Power-on Reset.

The FRC primary oscillator with postscaler (FRCDIV)

is the default (unprogrammed) selection. The second-

ary oscillator, or one of the internal oscillators, may be

chosen by programming these bit locations.

The Configuration bits allow users to choose between

the various clock modes, shown in Tabl e 8 - 1 .

8.2.1 CLOCK SWITCHING MODE

CONFIGURATION BITS

The FCKSM Configuration bits (Configuration Word 2<7:6>)

are used to jointly configure device clock switching and

the Fail-Safe Clock Monitor (FSCM). Clock switching is

enabled only when FCKSM1 is programmed (‘0’). The

FSCM is enabled only when FCKSM<1:0> are both

programmed (‘00’).

TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Oscillator Mode Oscillator Source POSCMD<1:0> F NOSC<2:0> Note

Fast RC Oscillator with Postscaler

(FRCDIV)

Internal 11 111 1, 2

(Reserved) Internal xx 110 1

Low-Power RC Oscillator (LPRC) Internal 11 101 1

Secondary (Timer1) Oscillator

(SOSC)

Secondary 11 100 1

Primary Oscillator (HS) with PLL

Module (HSPLL)

Primary 10 011

Primary Oscillator (XT) with PLL

Module (XTPLL)

Primary 01 011

Primary Oscillator (EC) with PLL

Module (ECPLL)

Primary 00 011

Primary Oscillator (HS) Primary 10 010

Primary Oscillator (XT) Primary 01 010

Primary Oscillator (EC) Primary 00 010

Fast RC Oscillator with PLL Module

(FRCPLL)

Internal 11 001 1

Fast RC Oscillator (FRC) Internal 11 000 1

Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.

2: This is the default oscillator mode for an unprogrammed (erased) device.

 2005-2012 Microchip Technology Inc. DS39747F-page 99

PIC24FJ128GA010 FAMILY

8.3 Control Registers

The operation of the oscillator is controlled by three

Special Function Registers:

• OSCCON

•CLKDIV

•OSCTUN

The OSCCON register (Register 8-1) is the main con-

trol register for the oscillator. It controls clock source

switching, and allows the monitoring of clock sources.

The Clock Divider register (Register 8-2) controls the

features associated with Doze mode, as well as the

postscaler for the FRC oscillator.

The FRC Oscillator Tune register (Register 8-3) allows

the user to fine-tune the FRC oscillator over a range of

approximately ±12%. Each increment may adjust the

FRC frequency by varying amounts and may not be

monotonic. The next closest frequency may be multiple

steps apart.

U-0 R-0 R-0 R-0 U-0 R/W-x(1)R/W-x(1)R/W-x(1)

— COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0

bit 15 bit 8

R/SO-0 U-0 R-0(2)U-0 R/CO-0 U-0 R/W-0 R/W-0

CLKLOCK —LOCK—CF — SOSCEN OSWEN

bit 7 bit 0

Legend: CO = Clearable Only bit SO = Settable Only bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 COSC<2:0>: Current Oscillator Selection bits

111 = Fast RC Oscillator with Postscaler (FRCDIV)

110 = Reserved

101 = Low-Power RC Oscillator (LPRC)

100 = Secondary Oscillator (SOSC)

011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)

010 = Primary Oscillator (XT, HS, EC)

001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL)

000 = Fast RC Oscillator (FRC)

bit 11 Unimplemented: Read as ‘0’

bit 10-8 NOSC<2:0>: New Oscillator Selection bits(1)

111 = Fast RC Oscillator with Postscaler (FRCDIV)

110 = Reserved

101 = Low-Power RC Oscillator (LPRC)

100 = Secondary Oscillator (SOSC)

011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)

010 = Primary Oscillator (XT, HS, EC)

001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL)

000 = Fast RC Oscillator (FRC)

bit 7 CLKLOCK: Clock Selection Lock Enable bit

If FSCM is enabled (FCKSM1 = 1):

1 = Clock and PLL selections are locked

0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit

If FSCM is disabled (FCKSM1 = 0):

Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.

bit 6 Unimplemented: Read as ‘0’

Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.

2: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.

PIC24FJ128GA010 FAMILY

DS39747F-page 100  2005-2012 Microchip Technology Inc.

bit 5 LOCK: PLL Lock Status bit(2)

1 = PLL module is in lock or PLL module start-up timer is satisfied

0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled

bit 4 Unimplemented: Read as ‘0’

bit 3 CF: Clock Fail Detect bit

1 = FSCM has detected a clock failure

0 = No clock failure has been detected

bit 2 Unimplemented: Read as ‘0’

bit 1 SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit

1 = Enable secondary oscillator

0 = Disable secondary oscillator

bit 0 OSWEN: Oscillator Switch Enable bit

1 = Initiate an oscillator switch to clock source specified by NOSC<2:0> bits

0 = Oscillator switch is complete

Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.

2: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.

 2005-2012 Microchip Technology Inc. DS39747F-page 101

PIC24FJ128GA010 FAMILY

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1

ROI DOZE2 DOZE1 DOZE0 DOZEN(1)RCDIV2 RCDIV1 RCDIV0

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ROI: Recover on Interrupt bit

1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1

0 = Interrupts have no effect on the DOZEN bit

bit 14-12 DOZE<2:0>: CPU Peripheral Clock Ratio Select bits

111 = 1:128

110 = 1:64

101 = 1:32

100 = 1:16

011 = 1:8

010 = 1:4

001 = 1:2

000 = 1:1

bit 11 DOZEN: DOZE Enable bit(1)

1 = DOZE<2:0> bits specify the CPU peripheral clock ratio

0 = CPU peripheral clock ratio set to 1:1

bit 10-8 RCDIV<2:0>: FRC Postscaler Select bits

111 = 31.25 kHz (divide-by-256)

110 = 125 kHz (divide-by-64)

101 = 250 kHz (divide-by-32)

100 = 500 kHz (divide-by-16)

011 = 1 MHz (divide-by-8)

010 = 2 MHz (divide-by-4)

001 = 4 MHz (divide-by-2)

000 = 8 MHz (divide-by-1)

bit 7-0 Unimplemented: Read as ‘0’

Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.

PIC24FJ128GA010 FAMILY

DS39747F-page 102  2005-2012 Microchip Technology Inc.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— TUN5 TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-6 Unimplemented: Read as ‘0’

bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits

011111 = Maximum frequency deviation

011110 =



000001 =

000000 = Center frequency, oscillator is running at factory calibrated frequency

111111 =



100001 =

100000 = Minimum frequency deviation

 2005-2012 Microchip Technology Inc. DS39747F-page 103

PIC24FJ128GA010 FAMILY

8.4 Clock Switching Operation

With few limitations, applications are free to switch

between any of the four clock sources (POSC, SOSC,

FRC and LPRC) under software control and at any

time. To limit the possible side effects that could result

from this flexibility, PIC24F devices have a safeguard

lock built into the switching process.

8.4.1 ENABLING CLOCK SWITCHING

To enable clock switching, the FCKSM1 Configuration bit

in the Flash Configuration Word 2 register must be pro-

grammed to ‘0’. (Refer to Section 24.1 “Configuration

Bits” for further details.) If the FCKSM1 Configuration bit

is unprogrammed (‘1’), the clock switching function and

Fail-Safe Clock Monitor function are disabled. This is the

default setting.

The NOSC control bits (OSCCON<10:8>) do not

control the clock selection when clock switching is dis-

abled. However, the COSC bits (OSCCON<14:12>)

will reflect the clock source selected by the FNOSC

Configuration bits.

The OSWEN control bit (OSCCON<0>) has no effect

when clock switching is disabled; it is held at ‘0’ at all

times.

8.4.2 OSCILLATOR SWITCHING

SEQUENCE

At a minimum, performing a clock switch requires this

basic sequence:

1. If desired, read the COSC bits

(OSCCON<14:12>) to determine the current

oscillator source.

2. Perform the unlock sequence to allow a write to

the OSCCON register high byte.

3. Write the appropriate value to the NOSC control

bits (OSCCON<10:8>) for the new oscillator

source.

4. Perform the unlock sequence to allow a write to

the OSCCON register low byte.

5. Set the OSWEN bit to initiate the oscillator

switch.

Once the basic sequence is completed, the system

clock hardware responds automatically as follows:

1. The clock switching hardware compares the

COSC status bits with the new value of the

NOSC control bits. If they are the same, then the

clock switch is a redundant operation. In this

case, the OSWEN bit is cleared automatically

and the clock switch is aborted.

2. If a valid clock switch has been initiated, the

LOCK (OSCCON<5>) and CF (OSCCON<3>)

status bits are cleared.

3. The new oscillator is turned on by the hardware

if it is not currently running. If a crystal oscillator

must be turned on, the hardware will wait until

the OST expires. If the new source is using the

PLL, then the hardware waits until a PLL lock is

detected (LOCK = 1).

4. The hardware waits for ten clock cycles from the

new clock source and then performs the clock

switch.

5. The hardware clears the OSWEN bit to indicate a

successful clock transition. In addition, the NOSC

bit values are transferred to the COSC status bits.

6. The old clock source is turned off at this time

with the exception of LPRC (if WDT or FSCM is

enabled) or SOSC (if SOSCEN remains set).

Note: Primary oscillator mode has three

different submodes (XT, HS and EC)

which are determined by the POSCMD

Configuration bits. While an application

can switch to and from primary oscillator

mode in software, it cannot switch

between the different primary submodes

without reprogramming the device.

Note 1: The processor will continue to execute

code throughout the clock switching

sequence. Timing-sensitive code should

not be executed during this time.

2: Direct clock switches between any

primary oscillator mode with PLL and

FRCPLL mode are not permitted. This

applies to clock switches in either direc-

tion. In these instances, the application

must switch to FRC mode as a transition

clock source between the two PLL

modes.

PIC24FJ128GA010 FAMILY

DS39747F-page 104  2005-2012 Microchip Technology Inc.

A recommended code sequence for a clock switch

includes the following:

1. Disable interrupts during the OSCCON register

unlock and write sequence.

2. Execute the unlock sequence for the OSCCON

high byte by writing 78h and 9Ah to

OSCCON<15:8> in two back-to-back

instructions.

3. Write new oscillator source to the NOSC control

bits in the instruction immediately following the

unlock sequence.

4. Execute the unlock sequence for the OSCCON

low byte by writing 46h and 57h to

OSCCON<7:0> in two back-to-back instructions.

5. Set the OSWEN bit in the instruction immediately

following the unlock sequence.

6. Continue to execute code that is not

clock-sensitive (optional).

7. Invoke an appropriate amount of software delay

(cycle counting) to allow the selected oscillator

and/or PLL to start and stabilize.

8. Check to see if OSWEN is ‘0’. If it is, the switch

was successful. If OSWEN is still set, then

check the LOCK bit to determine the cause of

the failure.

The core sequence for unlocking the OSCCON register

and initiating a clock switch is shown in Example 8-1.

EXAMPLE 8-1: BASIC CODE SEQUENCE

FOR CLOCK SWITCHING

.global __reset

.include "p24fxxxx.inc"

.text

__reset:

;Place the new oscillator selection in W0

;OSCCONH (high byte) Unlock Sequence

DISI #18

PUSH w1

PUSH w2

PUSH w3

MOV #OSCCONH, w1

MOV #0x78, w2

MOV #0x9A, w3

MOV.b w2, [w1]

MOV.b w3, [w1]

;Set new oscillator selection

MOV.b WREG, OSCCONH

;OSCCONL (low byte) unlock sequence

MOV #OSCCONL, w1

MOV #0x46, w2

MOV #0x57, w3

MOV.b w2, [w1]

MOV.b w3, [w1]

;Start oscillator switch operation

BSET OSCCON, #0

POP w3

POP w2

POP w1

.end

 2005-2012 Microchip Technology Inc. DS39747F-page 105

PIC24FJ128GA010 FAMILY

9.0 POWER-SAVING FEATURES

The PIC24FJ128GA010 family of devices provides the

ability to manage power consumption by selectively

managing clocking to the CPU and the peripherals. In

general, a lower clock frequency and a reduction in the

number of circuits being clocked constitutes lower

consumed power. All PIC24F devices manage power

consumption in four different ways:

• Clock Frequency

• Instruction-Based Sleep and Idle modes

• Software-Controlled Doze mode

• Selective Peripheral Control in Software

Combinations of these methods can be used to selec-

tively tailor an application’s power consumption, while

still maintaining critical application features, such as

timing-sensitive communications.

9.1 Clock Frequency and Clock

Switching

PIC24F devices allow for a wide range of clock

frequencies to be selected under application control. If

the system clock configuration is not locked, users can

choose low-power or high-precision oscillators by simply

changing the NOSC bits. The process of changing a sys-

tem clock during operation, as well as limitations to the

process, are discussed in more detail in Section 8.0

“Oscillator Configuration”.

9.2 Instruction-Based Power-Saving

Modes

PIC24F devices have two special power-saving modes

that are entered through the execution of a special

PWRSAV instruction. Sleep mode stops clock operation

and halts all code execution; Idle mode halts the CPU

and code execution, but allows peripheral modules to

continue operation. The assembly syntax of the

PWRSAV instruction is shown in Example 9-1.

Sleep and Idle modes can be exited as a result of an

enabled interrupt, WDT time-out or a device Reset.

When the device exits these modes, it is said to

“wake-up”.

9.2.1 SLEEP MODE

Sleep mode has these features:

• The system clock source is shut down. If an

on-chip oscillator is used, it is turned off.

• The device current consumption will be reduced

to a minimum provided that no I/O pin is sourcing

current.

• The Fail-Safe Clock Monitor does not operate

during Sleep mode since the system clock source

is disabled.

• The LPRC clock will continue to run in Sleep

mode if the WDT is enabled.

• The WDT, if enabled, is automatically cleared

prior to entering Sleep mode.

• Some device features or peripherals may

continue to operate in Sleep mode. This includes

items, such as the input change notification on the

I/O ports, or peripherals that use an external clock

input. Any peripheral that requires the system

clock source for its operation will be disabled in

Sleep mode.

The device will wake-up from Sleep mode on any of

these events:

• On any interrupt source that is individually

enabled

• On any form of device Reset

• On a WDT time-out

On wake-up from Sleep, the processor will restart with

the same clock source that was active when Sleep

mode was entered.

EXAMPL E 9-1: PWRSAV INSTRUCTION SYNTAX

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 10. Power-

Saving Features” (DS39698) in the

“PIC24F Family Reference Manual” for

more information. Note: SLEEP_MODE and IDLE_MODE are con-

stants defined in the assembler include

file for the selected device.

PWRSAV#SLEEP_MODE ; Put the device into SLEEP mode

PWRSAV#IDLE_MODE ; Put the device into IDLE mode

PIC24FJ128GA010 FAMILY

DS39747F-page 106  2005-2012 Microchip Technology Inc.

9.2.2 IDLE MODE

Idle mode has these features:

• The CPU will stop executing instructions.

• The WDT is automatically cleared.

• The system clock source remains active. By

default, all peripheral modules continue to operate

normally from the system clock source, but can

also be selectively disabled (see Section 9 .4

“Selective Peripheral Module Control”).

• If the WDT or FSCM is enabled, the LPRC will

also remain active.

The device will wake from Idle mode on any of these

events:

• Any interrupt that is individually enabled.

• Any device Reset.

• A WDT time-out.

On wake-up from Idle, the clock is re-applied to the

CPU and instruction execution begins immediately,

starting with the instruction following the PWRSAV

instruction or the first instruction in the ISR.

9.2.3 INTERRUPTS COINCIDENT WITH

POWER SAVE INSTRUCTIONS

Any interrupt that coincides with the execution of a

PWRSAV instruction will be held off until entry into Sleep

or Idle mode has completed. The device will then

wake-up from Sleep or Idle mode.

9.3 Doze Mode

Generally, changing clock speed and invoking one of

the power-saving modes are the preferred strategies

for reducing power consumption. There may be cir-

cumstances, however, where this is not practical. For

example, it may be necessary for an application to

maintain uninterrupted synchronous communication,

even while it is doing nothing else. Reducing system

clock speed may introduce communication errors,

while using a power-saving mode may stop

communications completely.

Doze mode is a simple and effective alternative method

to reduce power consumption while the device is still

executing code. In this mode, the system clock contin-

ues to operate from the same source and at the same

speed. Peripheral modules continue to be clocked at the

same speed, while the CPU clock speed is reduced.

Synchronization between the two clock domains is

maintained, allowing the peripherals to access the SFRs

while the CPU executes code at a slower rate.

Doze mode is enabled by setting the DOZEN bit

(CLKDIV<11>). The ratio between peripheral and core

clock speed is determined by the DOZE<2:0> bits

(CLKDIV<14:12>). There are eight possible

configurations, from 1:1 to 1:128, with 1:1 being the

default.

It is also possible to use Doze mode to selectively

reduce power consumption in event driven applica-

tions. This allows clock-sensitive functions, such as

synchronous communications, to continue without

interruption while the CPU idles, waiting for something

to invoke an interrupt routine. Enabling the automatic

return to full-speed CPU operation on interrupts is

enabled by setting the ROI bit (CLKDIV<15>). By

default, interrupt events have no effect on Doze mode

operation.

9.4 Selective Peripheral Module

Control

Idle and Doze modes allow users to substantially

reduce power consumption by slowing or stopping the

CPU clock. Even so, peripheral modules still remain

clocked, and thus, consume power. There may be

cases where the application needs what these modes

do not provide: the allocation of power resources to

CPU processing with minimal power consumption from

the peripherals.

PIC24F devices address this requirement by allowing

peripheral modules to be selectively disabled, reducing

or eliminating their power consumption. This can be

done with two control bits:

• The Peripheral Enable bit, generically named

“XXXEN”, located in the module’s main control

SFR.

• The Peripheral Module Disable (PMD) bit, generi-

cally named “XXXMD”, located in one of the PMD

Control registers.

Both bits have similar functions in enabling or disabling its

associated module. Setting the PMD bit for a module dis-

ables all clock sources to that module, reducing its power

consumption to an absolute minimum. In this state, the

control and status registers associated with the periph-

eral will also be disabled, so writes to those registers will

have no effect and read values will be invalid. Many

peripheral modules have a corresponding PMD bit.

In contrast, disabling a module by clearing its XXXEN

bit disables its functionality, but leaves its registers

available to be read and written to. Power consumption

is reduced, but not by as much as the PMD bit does.

Most peripheral modules have an enable bit;

exceptions include Capture, Compare and RTCC.

To achieve more selective power savings, peripheral

modules can also be selectively disabled when the

device enters Idle mode. This is done through the

control bit of the generic name format, “XXXIDL”. By

default, all modules that can operate during Idle mode

will do so. Using the disable on Idle feature allows

further reduction of power consumption during Idle

mode, enhancing power savings for extremely critical

power applications.

 2005-2012 Microchip Technology Inc. DS39747F-page 107

PIC24FJ128GA010 FAMILY

10.0 I/O PORTS

All of the device pins (except VDD, VSS, MCLR and

OSC1/CLKI) are shared between the peripherals and

the parallel I/O ports. All I/O input ports feature Schmitt

Trigger inputs for improved noise immunity.

10.1 Parallel I/O (PIO) Ports

A parallel I/O port that shares a pin with a peripheral is,

in general, subservient to the peripheral. The periph-

eral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ownership of the output data and control signals of

the I/O pin. The logic also prevents “loop through”, in

which a port’s digital output can drive the input of a

peripheral that shares the same pin. Figure 10-1 shows

how ports are shared with other peripherals and the

associated I/O pin to which they are connected.

When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as

a general purpose output pin is disabled. The I/O pin

may be read, but the output driver for the parallel port

bit will be disabled. If a peripheral is enabled, but the

peripheral is not actively driving a pin, that pin may be

driven by a port.

All port pins have three registers directly associated

with their operation as digital I/O. The Data Direction

or an output. If the data direction bit is a ‘1’, then the pin

is an input. All port pins are defined as inputs after a

Reset. Reads from the latch (LATx), read the latch.

Writes to the latch, write the latch. Reads from the port

(PORTx), read the port pins, while writes to the port

pins, write the latch.

Any bit and its associated data and control registers

that are not valid for a particular device will be

disabled. That means the corresponding LATx and

TRISx registers, and the port pin will read as zeros.

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is nevertheless,

regarded as a dedicated port because there is no

other competing source of outputs. An example is the

INT4 pin.

FIGURE 10-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Note: This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive refer-

ence source. Refer to Section 12. “I/O

Port s with Peripheral Pin Sele ct (PPS)”

(DS39711) in the “PIC24F Family

Reference Ma nual” for more information.

WR LAT +

TRIS Latch

I/O Pin

WR PORT

Data Bus

Data Latch

Read PORT

Read TRIS

WR TRIS

Peripheral Output Data

Output Enable

Peripheral Input Data

I/O

Peripheral Module

Peripheral Output Enable

PIO Modul e

Out put Multiple x ers

Output Data

Input Data

Peripheral Module Enable

Read LAT

PIC24FJ128GA010 FAMILY

DS39747F-page 108  2005-2012 Microchip Technology Inc.

10.1.1 OPEN-DRAIN CONFIGURATION

In addition to the PORT, LAT and TRIS registers for

data control, each port pin can also be individually con-

figured for either digital or open-drain output. This is

controlled by the Open-Drain Control register, ODCx,

associated with each port. Setting any of the bits con-

figures the corresponding pin to act as an open-drain

output.

The open-drain feature allows the generation of

outputs higher than VDD (e.g., 5V) on any desired

digital only pins by using external pull-up resistors. The

maximum open-drain voltage allowed is the same as

the maximum VIH specification.

10.2 Configur ing Analog Port Pins

The use of the AD1PCFG and TRIS registers control

the operation of the A/D port pins. The port pins that are

desired as analog inputs must have their correspond-

ing TRIS bit set (input). If the TRIS bit is cleared

(output), the digital output level (VOH or VOL) will be

converted.

When reading the PORT register, all pins configured as

analog input channels will read as cleared (a low level).

Pins configured as digital inputs will not convert an

analog input. Analog levels on any pin that is defined as

a digital input (including the ANx pins) may cause the

input buffer to consume current that exceeds the

device specifications.

10.2.1 I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically this instruction

would be a NOP.

10.2.2 ANALOG INPUT PINS AND

VOLTAGE CONSIDERATIONS

The voltage tolerance of pins used as device inputs is

dependent on the pin’s input function. Pins that are

used as digital only inputs are able to handle DC volt-

ages up to 5.5V, a level typical for digital logic circuits.

In contrast, pins that also have analog input functions

of any kind can only tolerate voltages up to VDD. On

these pins, voltage excursions beyond VDD are always

to be avoided. Table 10-1 summarizes the input capa-

bilities. Refer to Section 27.1 “DC Characteristics”

for more details.

EXAMPLE 10-1: PORT WRITE/READ EXAMPLE

Note: For easy identification, the pin diagrams at

the beginning of this data sheet also indi-

cate 5.5V tolerant pins with dark grey

shading.

TABLE 10-1: INPUT VOLTAGE LEVELS(1)

Port or Pin Tolerated

Input Description

PORTA<10:9> VDD Only VDD input

levels are tolerated.

PORTB<15:0>

PORTC<15:12>

PORTA<15:14> 5.5V Tolerates input

levels above VDD,

useful for most

standard logic.

PORTA<7:0>

PORTC<4:1>

PORTD<15:0>

PORTE<9:0>

PORTF<13:12>

PORTF<8:0>

PORTG<15:12>

PORTG<9:6>

PORTG<3:0>

Note 1: Not all port pins shown here are imple-

mented on 64-pin and 80-pin devices.

Refer to Sect ion 1.0 “Device Overv i ew”

to confirm which ports are available in

specific devices.

MOV 0xFF00, W0 ; Configure PORTB<1 5:8> as inputs

MOV W0, TRISBB ; and PORTB< 7:0> as output s

NOP ; Delay 1 cycle

btss PORTB, #13 ; Next Instruction

 2005-2012 Microchip Technology Inc. DS39747F-page 109

PIC24FJ128GA010 FAMILY

10.3 Input Change Notification

The input change notification function of the I/O ports

allows the PIC24FJ128GA010 family of devices to gen-

erate interrupt requests to the processor in response to

a Change-of-State (COS) on selected input pins. This

feature is capable of detecting input Change-of-States,

even in Sleep mode, when the clocks are disabled.

Depending on the device pin count, there are up to

22 external signals (CN0 through CN21) that may be

selected (enabled) for generating an interrupt request

on a Change-of-State.

There are four control registers associated with the CN

module. The CNEN1 and CNEN2 registers contain the

interrupt enable control bits for each of the CN input

pins. Setting any of these bits enables a CN interrupt

for the corresponding pins.

Each CN pin also has a weak pull-up connected to it.

The pull-ups act as a current source that is connected

to the pin and eliminate the need for external resistors

when push button or keypad devices are connected.

The pull-ups are enabled separately using the CNPU1

and CNPU2 registers, which contain the control bits for

each of the CN pins. Setting any of the control bits

enables the weak pull-ups for the corresponding pins.

When the internal pull-up is selected, the pin pulls up to

VDD – 0.7V (typical). Make sure that there is no external

pull-up source when the internal pull-ups are enabled, as

the voltage difference can cause a current path.

Note: Pull-ups on Change Notification (CN) pins

should always be disabled whenever the

port pin is configured as a digital output.

PIC24FJ128GA010 FAMILY

DS39747F-page 110  2005-2012 Microchip Technology Inc.

NOTES:

 2005-2012 Microchip Technology Inc. DS39747F-page 111

PIC24FJ128GA010 FAMILY

11.0 TIMER1

The Timer1 module is a 16-bit timer which can serve as

the time counter for the Real-Time Clock (RTC) or

operate as a free-running, interval timer/counter.

Timer1 can operate in three modes:

•16-Bit Timer

• 16-Bit Synchronous Counter

• 16-Bit Asynchronous Counter

Timer1 also supports these features:

• Timer gate operation

• Selectable prescaler settings

• Timer operation during CPU Idle and Sleep

modes

• Interrupt on 16-bit Period register match or falling

edge of the external gate signal

Figure 11-1 presents a block diagram of the 16-bit timer

module.

To configure Timer1 for operation:

1. Set the TON bit (= 1).

2. Select the timer prescaler ratio using the

TCKPS<1:0> bits.

3. Set the Clock and Gating modes using the TCS

and TGATE bits.

4. Set or clear the TSYNC bit to configure

synchronous or asynchronous operation.

5. Load the timer period value into the PR1

6. If interrupts are required, set the Timer1 Inter-

rupt Enable bit, T1IE. Use the priority bits,

T1IP<2:0>, to set the interrupt priority.

FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 14. “Timers”

(DS39704) in the “PIC24F Family

Reference Manual” for more information.

TON

Sync

SOSCI

SOSCO/

PR1

Set T1IF

Equal Comparator

TMR1

Reset

SOSCEN

TSYNC

TCKPS<1:0>

Prescaler

1, 8, 64, 256

TGATE

TCY

T1CK

TCS

TGATE

Gate

Sync

PIC24FJ128GA010 FAMILY

DS39747F-page 112  2005-2012 Microchip Technology Inc.

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

TON —TSIDL— — — — —

bit 15 bit 8

U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0

— TGATE TCKPS1 TCKPS0 — TSYNC TCS —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 TON: Timer1 On bit

1 = Starts 16-bit Timer1

0 = Stops 16-bit Timer1

bit 14 Unimplemented: Read as ‘0’

bit 13 TSIDL: Stop in Idle Mode bit

1 = Discontinues module operation when device enters Idle mode

0 = Continues module operation in Idle mode

bit 12-7 Unimplemented: Read as ‘0’

bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1 = Gated time accumulation is enabled

0 = Gated time accumulation is disabled

bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits

11 = 1:256

10 = 1:64

01 = 1:8

00 = 1:1

bit 3 Unimplemented: Read as ‘0’

bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit

When TCS = 1:

1 = Synchronizes external clock input

0 = Does not synchronize external clock input

When TCS = 0:

This bit is ignored.

bit 1 TCS: Timer1 Clock Source Select bit

1 = External clock from pin, T1CK (on the rising edge)

0 = Internal clock (FOSC/2)

bit 0 Unimplemented: Read as ‘0’

 2005-2012 Microchip Technology Inc. DS39747F-page 113

PIC24FJ128GA010 FAMILY

12.0 TIMER2/3 AND TIMER4/5

The Timer2/3 and Timer4/5 modules are 32-bit timers,

which can also be configured as four independent, 16-bit

timers with selectable operating modes.

As a 32-bit timer, Timer2/3 and Timer4/5 operate in

three modes:

• Two Independent 16-Bit Timers (Timer2 and

Timer3) with All 16-Bit Operating modes

• Single 32-Bit Timer

• Single 32-Bit Synchronous Counter

They also support these features:

• Timer Gate Operation

• Selectable Prescaler Settings

• Timer Operation During Idle and Sleep modes

• Interrupt on a 32-Bit Period Register Match

• A/D Event Trigger (Timer2/3 only)

Individually, all four of the 16-bit timers can function as

synchronous timers or counters. They also offer the

features listed above, except for the A/D Event Trigger;

this is implemented only with Timer3. The operating

modes and enabled features are determined by setting

the appropriate bit(s) in the T2CON, T3CON, T4CON

and T5CON registers. T2CON and T4CON are shown

in generic form in Register 12-1; T3CON and T5CON

are shown in Register 12-2.

For 32-bit timer/counter operation, Timer2 and Timer4

are the least significant word; Timer3 and Timer4 are

the most significant word of the 32-bit timers.

To configure Timer2/3 or Timer4/5 for 32-bit operation:

1. Set the T32 bit (T2CON<3> or T4CON<3> = 1).

2. Select the prescaler ratio for Timer2 or Timer4

using the TCKPS<1:0> bits.

3. Set the Clock and Gating modes using the TCS

and TGATE bits.

4. Load the timer period value. PR3 (or PR5) will

contain the most significant word of the value,

while PR2 (or PR4) contains the least significant

word.

5. If interrupts are required, set the interrupt enable

bit, T3IE or T5IE. Use the interrupt priority bits,

T3IP<2:0> or T5IP<2:0>, to set the interrupt pri-

ority. Note that while Timer2 or Timer4 controls

the timer, the interrupt appears as a Timer3 or

Timer5 interrupt.

6. Set the TON bit (= 1).

The timer value, at any point, is stored in the register

pair: TMR3:TMR2 (or TMR5:TMR4). TMR3 (TMR5)

always contains the most significant word of the count,

while TMR2 (TMR4) contains the least significant word.

To configure any of the timers for individual 16-bit

operation:

1. Clear the T32 bit corresponding to that timer

(T2CON<3> for Timer2 and Timer3 or

T4CON<3> for Timer4 and Timer5).

2. Select the timer prescaler ratio using the

TCKPS<1:0> bits.

3. Set the Clock and Gating modes using the TCS

and TGATE bits.

4. Load the timer period value into the PRx register.

5. If interrupts are required, set the interrupt enable

bit, TxIE; use the priority bits, TxIP<2:0>, to set

the interrupt priority.

6. Set the TON bit (TxCON<15> = 1).

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 14. “Timers”

(DS39704) in the “PIC24F Family

Reference Manual” for more information.

Note: For 32-bit operation, T3CON and T5CON

control bits are ignored. Only T2CON and

T4CON control bits are used for setup and

control. Timer2 and Timer4 clock and gate

inputs are utilized for the 32-bit timer

modules, but an interrupt is generated

with the Timer3 or Timer5 interrupt flags.

PIC24FJ128GA010 FAMILY

DS39747F-page 114  2005-2012 Microchip Technology Inc.

FIGURE 12-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM

TMR3 TMR2

Set T3IF (T5IF)

Equal Comparator

PR3 PR2

Reset

LSB MSB

Note: The 32-bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are

respective to the T2CON and T4CON registers.

* The A/D Event Trigger is only available on Timer2/3.

Data Bus<15:0>

TMR3HLD

Read TMR2 (TMR4)

Write TMR2 (TMR4)

TGATE

TON

TCKPS<1:0>

Prescaler

1, 8, 64, 256

TCY

TCS

TGATE

Gate

T2CK

A/D Event Trigger*

Sync

(T4CK)

(PR5) (PR4)

(TMR5HLD)

(TMR5) (TMR4) Sync

 2005-2012 Microchip Technology Inc. DS39747F-page 115

PIC24FJ128GA010 FAMILY

FIGURE 12-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM

FIGURE 12-3: TIMER3 AND TIMER5 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM

TON

TCKPS<1:0>

Prescaler

1, 8, 64, 256

TCY TCS

TGATE

Gate

T2CK

Sync

PR2 (PR4)

Set T2IF (T4IF)

Equal Comparator

TMR2 (TMR4)

Reset

TGATE

(T4CK)

Sync

TON

TCKPS<1:0>

TCY TCS

TGATE

T3CK

PR3 (PR5)

Set T3IF (T5IF)

Equal Comparator

TMR3 (TMR5)

Reset

TGATE

A/D Event Trigger*

(T5CK)

* The A/D Event Trigger is available only on Timer2/3.

Prescaler

1, 8, 64, 256

Sync

PIC24FJ128GA010 FAMILY

DS39747F-page 116  2005-2012 Microchip Technology Inc.

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

TON —TSIDL— — — — —

bit 15 bit 8

U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0

— TGATE TCKPS1 TCKPS0 T32(1)—TCS—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 TON: Timerx On bit

When TxCON<3> = 1:

1 = Starts 32-bit Timerx/y

0 = Stops 32-bit Timerx/y

When TxCON<3> = 0:

1 = Starts 16-bit Timerx

0 = Stops 16-bit Timerx

bit 14 Unimplemented: Read as ‘0’

bit 13 TSIDL: Stop in Idle Mode bit

1 = Discontinues module operation when the device enters Idle mode

0 = Continues module operation in Idle mode

bit 12-7 Unimplemented: Read as ‘0’

bit 6 TGATE: Timerx Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1 = Gated time accumulation is enabled

0 = Gated time accumulation is disabled

bit 5-4 TCKPS<1:0>: Timer2 Input Clock Prescale Select bits

11 = 1:256

10 = 1:64

01 = 1:8

00 = 1:1

bit 3 T32: 32-Bit Timer Mode Select bit(1)

1 = Timerx and Timery form a single 32-bit timer

0 = Timerx and Timery act as two 16-bit timers

bit 2 Unimplemented: Read as ‘0’

bit 1 TCS: Timerx Clock Source Select bit

1 = External clock from pin, TxCK (on the rising edge)

0 = Internal clock (FOSC/2)

bit 0 Unimplemented: Read as ‘0’

Note 1: In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation.

 2005-2012 Microchip Technology Inc. DS39747F-page 117

PIC24FJ128GA010 FAMILY

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

TON(1)—TSIDL

(1)— — — — —

bit 15 bit 8

U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0

—TGATE

(1)TCKPS1(1)TCKPS0(1)——TCS

(1)—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 TON: Timery On bit(1)

1 = Starts 16-bit Timery

0 = Stops 16-bit Timery

bit 14 Unimplemented: Read as ‘0’

bit 13 TSIDL: Stop in Idle Mode bit(1)

1 = Discontinues module operation when the device enters Idle mode

0 = Continues module operation in Idle mode

bit 12-7 Unimplemented: Read as ‘0’

bit 6 TGATE: Timery Gated Time Accumulation Enable bit(1)

When TCS = 1:

This bit is ignored.

When TCS = 0:

1 = Gated time accumulation is enabled

0 = Gated time accumulation is disabled

bit 5-4 TCKPS<1:0>: Timery Input Clock Prescale Select bits(1)

11 = 1:256

10 = 1:64

01 = 1:8

00 = 1:1

bit 3-2 Unimplemented: Read as ‘0’

bit 1 TCS: Timery Clock Source Select bit(1)

1 = External clock from pin, TyCK (on the rising edge)

0 = Internal clock (FOSC/2)

bit 0 Unimplemented: Read as ‘0’

Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer

functions are set through T2CON.

PIC24FJ128GA010 FAMILY

DS39747F-page 118  2005-2012 Microchip Technology Inc.

NOTES:

 2005-2012 Microchip Technology Inc. DS39747F-page 119

PIC24FJ128GA010 FAMILY

13.0 INPUT CAPTURE

The input capture module has multiple operating

modes, which are selected via the ICxCON register.

The operating modes include:

• Capture timer value on every falling edge of input,

applied at the ICx pin

• Capture timer value on every rising edge of input,

applied at the ICx pin

• Capture timer value on every fourth rising edge of

input, applied at the ICx pin

• Capture timer value on every 16th rising edge of

input, applied at the ICx pin

• Capture timer value on every rising and every

falling edge of input, applied at the ICx pin

• Device wake-up from capture pin during CPU

Sleep and Idle modes

The input capture module has a four-level FIFO buffer.

The number of capture events required to generate a

CPU interrupt can be selected by the user.

FIGURE 13-1: INPUT CAPTURE BLOCK DIAGRAM

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 15. “Input Cap-

ture” (DS39701) in the “PIC24F Family

Reference Manual” for more information.

ICxBUF

ICx Pin

ICM<2:0> (ICxCON<2:0>)

Mode Select

Set Flag ICxIF

(in IFSx Register)

TMRx

Edge Detection Logic

16 16

FIFO

R/W

Logic

ICI<1:0>

ICOV, ICBNE (ICxCON<4:3>)

ICxCON Interrupt

Logic

System Bus

From 16-Bit Timers

ICTMR

(ICxCON<7>)

Prescaler

Counter

(1, 4, 16) and

Clock Synchronizer

Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.

TMRy

PIC24FJ128GA010 FAMILY

DS39747F-page 120  2005-2012 Microchip Technology Inc.

13.1 Input Capture Registers

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

——ICSIDL— — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R-0, HC R/W-0, HC R/W-0 R/W-0 R/W-0

ICTMR(1)ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0

bit 7 bit 0

Legend: HC = Hardware Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 ICSIDL: Input Capture x Module Stop in Idle Control bit

1 = Input capture module will Halt in CPU Idle mode

0 = Input capture module will continue to operate in CPU Idle mode

bit 12-8 Unimplemented: Read as ‘0’

bit 7 ICTMR: Input Capture x Timer Select bit(1)

1 = TMR2 contents are captured on capture event

0 = TMR3 contents are captured on capture event

bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits

11 = Interrupt on every fourth capture event

10 = Interrupt on every third capture event

01 = Interrupt on every second capture event

00 = Interrupt on every capture event

bit 4 ICOV: Input Capture x Overflow Status Flag bit (read-only)

1 = Input capture overflow occurred

0 = No input capture overflow occurred

bit 3 ICBNE: Input Capture x Buffer Empty Status bit (read-only)

1 = Input capture buffer is not empty, at least one more capture value can be read

0 = Input capture buffer is empty

bit 2-0 ICM<2:0>: Input Capture x Mode Select bits

111 = Input capture functions as an interrupt pin only when the device is in Sleep or Idle mode (rising

edge detect only, all other control bits are not applicable)

110 = Unused (module is disabled)

101 = Capture mode, every 16th rising edge

100 = Capture mode, every 4th rising edge

011 = Capture mode, every rising edge

010 = Capture mode, every falling edge

001 = Capture mode, every edge (rising and falling); ICI<1:0> does not control interrupt generation

for this mode

000 = Input capture module is turned off

Note 1: Timer selections may vary. Refer to the specific device data sheet for details.

 2005-2012 Microchip Technology Inc. DS39747F-page 121

PIC24FJ128GA010 FAMILY

14.0 OUTPUT COMPARE

14.1 MODES OF OPERATION

Each output compare module has the following modes

of operation:

• Single Compare Match mode

• Dual Compare Match mode generating:

- Single Output Pulse mode

- Continuous Output Pulse mode

• Simple Pulse-Width Modulation mode:

- with Fault protection input

- without Fault protection input

14.2 Setup for Single Output Pulse

Generation

When the OCM control bits (OCxCON<2:0>) are set to

‘100’, the selected output compare channel initializes

the OCx pin to the low state and generates a single

output pulse.

FIGURE 14-1: OUT PUT COMPARE MODULE BLOCK DIAGRAM

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 16. “Output

Compare” (DS39706) in the “PIC24F

Family Reference Manual” for more

information.

Comparator

Output

Logic

OCM<2:0>

Output Enable

OCx(1)

Set Flag bit

OCxIF(1)

OCxRS(1)

Mode Select

Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels, 1

through 5.

2: OCFA pin controls OC1-OC4 channels; OCFB pin controls OC5.

3: Each output compare channel can use either Timer2 or Timer3.

OCTSEL 01

1616

OCFA or OCFB(2)

TMR Register Inputs

from Time Bases

(see Note 3)

Period Match Signals

from Time Bases

(see Note 3)

OCxR(1)

PIC24FJ128GA010 FAMILY

DS39747F-page 122  2005-2012 Microchip Technology Inc.

To generate a single output pulse, the following steps

are required (these steps assume the timer source is

initially turned off, but this is not a requirement for the

module operation):

1. Determine the instruction clock cycle time. Take

into account the frequency of the external clock

to the timer source (if one is used) and the timer

prescaler settings.

2. Calculate time to the rising edge of the output

pulse relative to the TMRy start value (0000h).

3. Calculate the time to the falling edge of the pulse

based on the desired pulse width and the time to

the rising edge of the pulse.

4. Write the values computed in Steps 2 and 3

above into the Compare register, OCxR, and the

Secondary Compare register, OCxRS,

respectively.

5. Set the Timer Period register, PRy, to a value

equal to or greater than the value in OCxRS, the

Secondary Compare register.

6. Set the OCM bits to ‘100’ and the OCTSEL

(OCxCON<3>) bit to the desired timer source.

The OCx pin state will now be driven low.

7. Set the TON (TyCON<15>) bit to ‘1’, which

enables the compare time base to count.

8. Upon the first match between TMRy and OCxR,

the OCx pin will be driven high.

9. When the incrementing timer, TMRy, matches the

Secondary Compare register, OCxRS, the

second and trailing edge (high-to-low) of the pulse

is driven onto the OCx pin. No additional pulses

are driven onto the OCx pin and it remains at low.

As a result of the second compare match event,

the OCxIF interrupt flag bit is set which will result

in an interrupt, if it is enabled, by setting the

OCxIE bit. For further information on periph-

eral interrupts, refer to Section 7.0 “Interrupt

Controller”.

10. To initiate another single pulse output, change the

Timer and Compare register settings, if needed,

and then issue a write to set the OCM bits to ‘100’.

Disabling and re-enabling of the timer, and clear-

ing the TMRy register are not required, but may

be advantageous for defining a pulse from a

known event time boundary.

The output compare module does not have to be dis-

abled after the falling edge of the output pulse. Another

pulse can be initiated by rewriting the value of the

OCxCON register.

14.3 Setup for Continuous Output

Pulse Generation

When the OCM control bits (OCxCON<2:0>) are set to

‘101’, the selected output compare channel initializes

the OCx pin to the low state, and generates output

pulses on each and every compare match event.

For the user to configure the module for the generation

of a continuous stream of output pulses, the following

steps are required (these steps assume the timer

source is initially turned off, but this is not a requirement

for the module operation):

1. Determine the instruction clock cycle time. Take

into account the frequency of the external clock

to the timer source (if one is used) and the timer

prescaler settings.

2. Calculate the time to the rising edge of the output

pulse relative to the TMRy start value (0000h).

3. Calculate the time to the falling edge of the pulse,

based on the desired pulse width and the time to

the rising edge of the pulse.

4. Write the values computed in Step 2 and 3

above, into the Compare register, OCxR, and

the Secondary Compare register, OCxRS,

respectively.

5. Set the Timer Period register, PRy, to a value,

equal to or greater than, the value in OCxRS, the

Secondary Compare register.

6. Set the OCM bits to ‘101’ and the OCTSEL bit to

the desired timer source. The OCx pin state will

now be driven low.

7. Enable the compare time base by setting the TON

(TyCON<15>) bit to ‘1’.

8. Upon the first match between TMRy and OCxR,

the OCx pin will be driven high.

9. When the compare time base, TMRy, matches

the Secondary Compare register, OCxRS, the

second and trailing edge (high-to-low) of the pulse

is driven onto the OCx pin.

10. As a result of the second compare match event,

the OCxIF interrupt flag bit is set.

11. When the compare time base and the value in its

respective Period register match, the TMRy

12. Steps 8 through 11 are repeated and a continuous

stream of pulses is generated indefinitely. The

OCxIF flag is set on each OCxRS-TMRy compare

match event.

 2005-2012 Microchip Technology Inc. DS39747F-page 123

PIC24FJ128GA010 FAMILY

14.4 Pulse-Width Modulation Mode

The following steps should be taken when configuring

the output compare module for PWM operation:

1. Set the PWM period by writing to the selected

Timer Period register (PRy).

2. Set the PWM duty cycle by writing to the OCxRS

3. Write the OCxR register with the initial duty

cycle.

4. Enable interrupts, if required, for the timer and

output compare modules. The output compare

interrupt is required for PWM Fault pin

utilization.

5. Configure the output compare module for one of

two PWM operation modes by writing to the

Output Compare mode bits, OCM<2:0>

(OCxCON<2:0>).

6. Set the TMRy prescale value and enable the

time base by setting TON (TxCON<15>) = 1.

14.4.1 PWM PERIOD

The PWM period is specified by writing to PRy, the

Timer Period register. The PWM period can be

calculated using Equation 14-1.

EQUATION 14-1: CALCULATING THE PWM

PERIOD(1)

14.4.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

OCxRS register. The OCxRS register can be written to

at any time, but the duty cycle value is not latched into

OCxR until a match between PRy and TMRy occurs

(i.e., the period is complete). This provides a double

buffer for the PWM duty cycle and is essential for glitch-

less PWM operation. In the PWM mode, OCxR is a

read-only register.

Some important boundary parameters of the PWM duty

cycle include:

• If the Duty Cycle register, OCxR, is loaded with

0000h, the OCx pin will remain low (0% duty cycle).

• If OCxR is greater than PRy (Timer Period register),

the pin will remain high (100% duty cycle).

• If OCxR is equal to PRy, the OCx pin will be low

for one time base count value and high for all

other count values.

See Example 14-1 for PWM mode timing details.

Table 14-1 shows example PWM frequencies and

resolutions for a device operating at 10 MIPS.

EQUATION 14-2: CALCULATION FOR MAXIMUM PWM RESOLUTION(1)

Note: The OCxR register should be initialized

before the output compare module is first

enabled. The OCxR register becomes a

Read-Only Duty Cycle register when the

module is operated in the PWM modes.

The value held in OCxR will become the

PWM duty cycle for the first PWM period.

The contents of the Duty Cycle Buffer

into OCxR until a time base period match

occurs.

Note: A PRy value of N will produce a PWM

period of N + 1 time base count cycles.

For example, a value of 7 written into the

PRy register will yield a period consisting

of 8 time base cycles.

PWM Period = [(PR y) + 1] • TCY • ( Timer Prescale Val ue)

PWM Frequenc y = 1/[PW M Period]

where:

Note 1: Based on T

CY = TOSC * 2; Doze mode and

PLL are disabled.

( )

Maximum PWM Resolution (bits) =

FCY

FPWM • (Timer Prescale Value)

log10

log10(2) bits

Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.

PIC24FJ128GA010 FAMILY

DS39747F-page 124  2005-2012 Microchip Technology Inc.

EXAMPLE 14-1: PW M PERIOD AND DUTY CYCLE CALCULATIONS(1)

TABLE 14-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1)

TABLE 14-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)(1)

PWM Frequency 7.6 Hz 61 Hz 122 Hz 977 Hz 3.9 kHz 31.3 kHz 125 kHz

Timer Prescaler Ratio 8111111

Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh

Resolution (bits) 16 16 15 12 10 7 5

Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled.

PWM Frequency 30.5 Hz 244 Hz 488 Hz 3.9 kHz 15.6 kHz 125 kHz 500 kHz

Timer Prescaler Ratio 8111111

Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh

Resolution (bits) 16 16 15 12 10 7 5

Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled.

1. Find the Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device clock

rate) and a Timer2 prescaler setting of 1:1.

TCY = 2/FOSC = 62.5 ns

PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s

PWM Period = (PR2 + 1) • TCY • (Timer2 Prescale Value)

19.2 s = (PR2 + 1) • 62.5 ns • 1

PR2 = 306

2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate:

PWM Resolution = log10(FCY/FPWM)/log102) bits

=(log

10(16 MHz/52.08 kHz)/log102) bits

= 8.3 bits

Note 1: Based on T

CY = TOSC * 2; Doze mode and PLL are disabled.

 2005-2012 Microchip Technology Inc. DS39747F-page 125

PIC24FJ128GA010 FAMILY

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

——OCSIDL— — — — —

bit 15 bit 8

U-0 U-0 U-0 R-0, HC R/W-0 R/W-0 R/W-0 R/W-0

— — —OCFLT

(1)OCTSEL(1)OCM2 OCM1 OCM0

bit 7 bit 0

Legend: HC = Hardware Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 OCSIDL: Stop Output Compare x Module Stop in Idle Control bit

1 = Output capture x will halt in CPU Idle mode

0 = Output capture x will continue to operate in CPU Idle mode

bit 12-5 Unimplemented: Read as ‘0’

bit 4 OCFLT: PWM Fault Condition Status bit(1)

1 = PWM Fault condition has occurred (cleared in HW only)

0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)

bit 3 OCTSEL: Output Compare x Timer Select bit(1)

1 = Timer3 is the clock source for output Compare x

0 = Timer2 is the clock source for output Compare x

bit 2-0 OCM<2:0>: Output Compare x Mode Select bits

111 = PWM mode on OCx, Fault pin is enabled(2)

110 = PWM mode on OCx, Fault pin is disabled(2)

101 = Initialize the OCx pin low, generate continuous output pulses on the OCx pin

100 = Initialize the OCx pin low, generate single output pulse on the OCx pin

011 = Compare event toggles OCx pin

010 = Initialize the OCx pin high, a compare event forces the OCx pin low

001 = Initialize the OCx pin low, a compare event forces the OCx pin high

000 = Output compare channel is disabled

Note 1: Refer to the device data sheet for specific time bases available to the output compare module.

2: The OCFA pin controls the OC1-OC4 channels; OCFB pin controls the OC5 channel.

PIC24FJ128GA010 FAMILY

DS39747F-page 126  2005-2012 Microchip Technology Inc.

NOTES:

 2005-2012 Microchip Technology Inc. DS39747F-page 127

PIC24FJ128GA010 FAMILY

15.0 SERIAL PER IPHERAL

INTERFACE (SPI)

The Serial Peripheral Interface (SPI) module is a

synchronous serial interface useful for communicating

with other peripheral or microcontroller devices. These

peripheral devices may be serial EEPROMs, shift reg-

isters, display drivers, A/D Converters, etc. The SPI

module is compatible with SPI and SIOP interfaces

from Motorola®.

The module supports operation in two buffer modes. In

Standard mode, data is shifted through a single serial

buffer. In Enhanced Buffer mode, data is shifted

through an 8-level FIFO buffer.

The module also supports a basic framed SPI protocol

while operating in either Master or Slave modes. A total

of four framed SPI configurations are supported.

The SPI serial interface consists of four pins:

• SDIx: Serial Data Input

• SDOx: Serial Data Output

• SCKx: Shift Clock Input or Output

• SSx: Active-Low Slave Select or Frame

Synchronization I/O Pulse

The SPI module can be configured to operate using

2, 3 or 4 pins. In the 3-pin mode, SSx is not used. In the

2-pin mode, both SDOx and SSx are not used.

A block diagram of the module is shown in Figure 15-1

and Figure 15-2.

To set up the SPI module for the Standard Master mode

of operation:

1. If using interrupts:

a) Clear the SPIxIF bit in the respective IFSx

b) Set the SPIxIE bit in the respective IECx

c) Write the SPIxIP bits in the respective IPCx

2. Write the desired settings to the SPIxCON

3. Clear the SPIROV bit (SPIxSTAT<6>).

4. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

5. Write the data to be transmitted to the SPIxBUF

as soon as data is written to the SPIxBUF

To set up the SPI module for the Standard Slave mode

of operation:

1. Clear the SPIxBUF register.

2. If using interrupts:

a) Clear the SPIxIF bit in the respective IFSx

b) Set the SPIxIE bit in the respective IECx

c) Write the SPIxIP bits in the respective IPCx

3. Write the desired settings to the SPIxCON1 and

SPIxCON2 registers with MSTEN

(SPIxCON1<5>) = 0.

4. Clear the SMP bit.

5. If the CKE bit is set, then the SSEN bit

(SPIxCON1<7>) must be set to enable the

SSx pin.

6. Clear the SPIROV bit (SPIxSTAT<6>).

7. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

Note: This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive refer-

ence source. Refer to Section 23. “ Serial

Peripheral I nterface (SPI)” (DS39699) in

the “PIC24F Family Reference Manual”

for more information.

Note: Do not perform read-modify-write opera-

tions (such as bit-oriented instructions) on

the SPIxBUF register, in either Standard

or Enhanced Buffer mode.

Note: In this section, the SPI modules are

referred to together as SPIx, or separately

as SPI1 and SPI2. Special Function Reg-

isters will follow a similar notation. For

example, SPIxCON refers to the control

PIC24FJ128GA010 FAMILY

DS39747F-page 128  2005-2012 Microchip Technology Inc.

To set up the SPI module for the Enhanced Buffer

Master mode of operation:

1. If using interrupts:

a) Clear the SPIxIF bit in the respective IFSx

b) Set the SPIxIE bit in the respective IECx

c) Write the SPIxIP bits in the respective IPCx

2. Write the desired settings to the SPIxCON1

and SPIxCON2 registers with MSTEN

(SPIxCON1<5>) = 1.

3. Clear the SPIROV bit (SPIxSTAT<6>).

4. Select Enhanced Buffer mode by setting the

SPIBEN bit (SPIxCON2<0>).

5. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

6. Write the data to be transmitted to the SPIxBUF

as soon as data is written to the SPIxBUF

To set up the SPI module for the Enhanced Buffer

Slave mode of operation:

1. Clear the SPIxBUF register.

2. If using interrupts:

• Clear the SPIxIF bit in the respective IFSx

• Set the SPIxIE bit in the respective IECx

• Write the SPIxIP bits in the respective IPCx

3. Write the desired settings to the SPIxCON1

and SPIxCON2 registers with MSTEN

(SPIxCON1<5>) = 0.

4. Clear the SMP bit.

5. If the CKE bit is set, then the SSEN bit must be

set, thus enabling the SSx pin.

6. Clear the SPIROV bit (SPIxSTAT<6>).

7. Select Enhanced Buffer mode by setting the

SPIBEN bit (SPIxCON2<0>).

8. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

FIGURE 15-1: SPIx MODULE BL OCK DIAGRAM (STANDARD MODE)

Internal Data Bus

SDIx

SDOx

SSx/FSYNCx

SCKx

SPIxSR

bit 0

Shift Control

Edge

Select

FCY

Primary

1:1/4/16/64

Enable

Prescaler

Sync

Clock

Control

SPIxBUF

Control

TransferTransfer

Write SPIxBUFRead SPIxBUF

SPIxCON1<1:0>

SPIxCON1<4:2>

Master Clock

Secondary

Prescaler

1:1 to 1:8

 2005-2012 Microchip Technology Inc. DS39747F-page 129

PIC24FJ128GA010 FAMILY

FIGURE 15-2: SPIx MODULE BL OCK DIAGRAM (ENHANCED MODE)

Internal Data Bus

SDIx

SDOx

SSx/FSYNCx

SCKx

SPIxSR

bit 0

Shift Control

Edge

Select

FCY

Primary

1:1/4/16/64

Enable

Prescaler

Secondary

Prescaler

1:1 to 1:8

Sync

SPIxBUF

Control

Transfer

Write SPIxBUFRead SPIxBUF

SPIxCON1<1:0>

SPIxCON1<4:2>

Master Clock

Clock

Control

Receive Buffer

8-Level FIFO

Transmit Buffer

8-Level FIFO

PIC24FJ128GA010 FAMILY

DS39747F-page 130  2005-2012 Microchip Technology Inc.

R/W-0 U-0 R/W-0 U-0 U-0 R-0 R-0 R-0

SPIEN — SPISIDL —— SPIBEC2 SPIBEC1 SPIBEC0

bit 15 bit 8

R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0

SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 SPIEN: SPIx Enable bit

1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins

0 = Disables module

bit 14 Unimplemented: Read as ‘0’

bit 13 SPISIDL: Stop in Idle Mode bit

1 = Discontinues module operation when device enters Idle mode

0 = Continues module operation in Idle mode

bit 12-11 Unimplemented: Read as ‘0’

bit 10-8 SPIBEC<2:0>: SPIx Buffer Element Count bits

Master mode:

Number of SPI transfers pending.

Slave mode:

Number of SPI transfers unread.

bit 7 SRMPT: Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)

1 = SPIx Shift register is empty and ready to send or receive

0 = SPIx Shift register is not empty; read as ‘0’

bit 6 SPIROV: Receive Overflow Flag bit

1 = A new byte/word is completely received and discarded; the user software has not read the previous

data in the SPIxBUF register

0 = No overflow has occurred

bit 5 SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode)

1 = Receive FIFO is empty

0 = Receive FIFO is not empty’

bit 4-2 SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)

111 = Interrupt when the SPIx transmit buffer is full (SPITBF bit is set)

110 = Interrupt when the last bit is shifted into SPIxSR, as a result, the TX FIFO is empty

101 = Interrupt when the last bit is shifted out of SPIxSR, now the transmit is complete

100 = Interrupt when one data is shifted into the SPIxSR, as a result, the TX FIFO has one open spot

011 = Interrupt when the SPIx receive buffer is full (SPIRBF bit is set)

010 = Interrupt when the SPIx receive buffer is 3/4 or more full

001 = Interrupt when data is available in the receive buffer (SRMPT bit is set)

000 = Interrupt when the last data in the receive buffer is read, and as a result, the buffer is empty

(SRXMPT bit set)

 2005-2012 Microchip Technology Inc. DS39747F-page 131

PIC24FJ128GA010 FAMILY

bit 1 SPITBF: SPIx Transmit Buffer Full Status bit

1 = Transmit not yet started, SPIxTXB is full

0 = Transmit started, SPIxTXB is empty

In Standard Buffer mode:

Automatically set in hardware when the CPU writes to the SPIxBUF location, loading SPIxTXB.

Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.

In Enhanced Buffer mode:

Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the last available

buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write.

bit 0 SPIRBF: SPIx Receive Buffer Full Status bit

1 = Receive complete, SPIxRXB is full

0 = Receive is not complete, SPIxRXB is empty

In Standard Buffer mode:

Automatically set in hardware when the SPIx transfers data from SPIxSR to SPIxRXB. Automatically

cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB.

In Enhanced Buffer mode:

Automatically set in hardware when the SPIx transfers data from SPIxSR to the buffer, filling the last

unread buffer location. Automatically cleared in hardware when a buffer location is available for a

transfer from SPIxSR.

PIC24FJ128GA010 FAMILY

DS39747F-page 132  2005-2012 Microchip Technology Inc.

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — DISSCK DISSDO MODE16 SMP CKE(1)

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12 DISSCK: Disable SCKx pin bit (SPI Master modes only)

1 = Internal SPI clock is disabled, the pin functions as an I/O

0 = Internal SPI clock is enabled

bit 11 DISSDO: Disable SDOx pin bit

1 = SDOx pin is not used by the module; the pin functions as an I/O

0 = SDOx pin is controlled by the module

bit 10 MODE16: Word/Byte Communication Select bit

1 = Communication is word-wide (16 bits)

0 = Communication is byte-wide (8 bits)

bit 9 SMP: SPIx Data Input Sample Phase bit

Master mode:

1 = Input data is sampled at the end of data output time

0 = Input data is sampled at the middle of data output time

Slave mode:

SMP must be cleared when SPIx is used in Slave mode.

bit 8 CKE: SPIx Clock Edge Select bit(1)

1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)

0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)

bit 7 SSEN: Slave Select Enable bit (Slave mode)

1 = SSx pin is used for Slave mode

0 = SSx pin is not used by module; pin is controlled by port function

bit 6 CKP: Clock Polarity Select bit

1 = Idle state for clock is a high level; active state is a low level

0 = Idle state for clock is a low level; active state is a high level

bit 5 MSTEN: Master Mode Enable bit

1 = Master mode

0 =Slave mode

bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)

111 = Secondary prescale 1:1

110 = Secondary prescale 2:1

...

000 = Secondary prescale 8:1

bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)

11 = Primary prescale 1:1

10 = Primary prescale 4:1

01 = Primary prescale 16:1

00 = Primary prescale 64:1

Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed

SPI modes (FRMEN = 1).

 2005-2012 Microchip Technology Inc. DS39747F-page 133

PIC24FJ128GA010 FAMILY

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0

FRMEN SPIFSD SPIFPOL — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — SPIFE SPIBEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 FRMEN: Framed SPIx Support bit

1 = Framed SPIx support is enabled

0 = Framed SPIx support is disabled

bit 14 SPIFSD: Frame Sync Pulse Direction Control on SSx Pin bit

1 = Frame sync pulse input (slave)

0 = Frame sync pulse output (master)

bit 13 SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only)

1 = Frame sync pulse is active-high

0 = Frame sync pulse is active-low

bit 12-2 Unimplemented: Read as ‘0’

bit 1 SPIFE: Frame Sync Pulse Edge Select bit

1 = Frame sync pulse coincides with the first bit clock

0 = Frame sync pulse precedes the first bit clock

bit 0 SPIBEN: Enhanced Buffer Enable bit

1 = Enhanced Buffer is enabled

0 = Enhanced Buffer is disabled (Legacy mode)

PIC24FJ128GA010 FAMILY

DS39747F-page 134  2005-2012 Microchip Technology Inc.

FIGURE 15-3: SPI MASTER/SLA VE CONNECTION (STANDARD MODE)

FIGURE 15-4: SP I MA STE R/S LAVE CONNECTION (ENHANCED BUFFER MODES)

Serial Receive Buffer

(SPIxRXB)

Shift Register

(SPIxSR)

LSb

MSb

SDIx

SDOx

PROCESSOR 2 (SPI Slave)

SCKx

SSx

Serial Transmit Buffer

(SPIxTXB)

Serial Receive Buffer

(SPIxRXB)

Shift Register

(SPIxSR)

MSb LSb

SDOx

SDIx

PROCESSO R 1 (SPI Master)

Serial Clock

(SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0)

Note 1: Using the SSx pin in the Slave mode of operation is optional.

2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory

mapped to SPIxBUF.

SCKx

Serial Transmit Buffer

(SPIxTXB)

(MSTEN (SPIxCON1<5> = 1))

SPIx Buffer

(SPIxBUF)

SPIx Buffer

(SPIxBUF)

Shift Register

(SPIxSR)

LSb

MSb

SDIx

SDOx

PROCESSOR 2 (SPI Enhanced Buffer Slave)

SCKx

SSx

Shift Register

(SPIxSR)

MSb LSb

SDOx

SDIx

PROCESSOR 1 (SPI Enhanced Buffer Master)

Serial Clock

SSEN (SPIxCON1<7>) = 1 and

Note 1: Using the SSx pin in Slave mode of operation is optional.

2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory

mapped to SPIxBUF.

SSx

SCKx

8-Level FIFO Buffer

MSTEN (SPIxCON1<5> = 1 and

SPIx Buffer

(SPIxBUF)

8-Level FIFO Buffer

SPIx Buffer

(SPIxBUF)

SPIBEN (SPIxCON2<0>) = 1MSTEN (SPIxCON1<5>) = 0 and

SPIBEN (SPIxCON2<0>) = 1

 2005-2012 Microchip Technology Inc. DS39747F-page 135

PIC24FJ128GA010 FAMILY

FIGURE 15-5: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM

FIGURE 15-6: SP I MASTE R, FRAME SLAVE CONNECTION DIAGRAM

FIGURE 15-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM

FIGURE 15-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM

SDOx

SDIx

PIC24F

Serial Clock

SSx

SCKx

Frame Sync

Pulse

SDIx

SDOx

PROCESSOR 2

SSx

SCKx

(SPI Slave, Frame Slave)

SDOx

SDIx

PIC24F

Serial Clock

SSx

SCKx

Frame Sync

Pulse

SDIx

SDOx

PROCESSOR 2

SSx

SCKx

SPI Master, Frame Slave)

SDOx

SDIx

PIC24F

Serial Clock

SSx

SCKx

Frame Sync.

Pulse

SDIx

SDOx

PROCESSOR 2

SSx

SCKx

(SPI Slave, Frame Slave)

SDOx

SDIx

PIC24F

Serial Clock

SSx

SCKx

Frame Sync

Pulse

SDIx

SDOx

PROCESSOR 2

SSx

SCKx

(SPI Master, Frame Slave)

PIC24FJ128GA010 FAMILY

DS39747F-page 136  2005-2012 Microchip Technology Inc.

EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1)

TABLE 15-1: SAMPLE SCK FREQUENCIES(1,2)

FCY = 16 MHz Secondary Prescaler Settings

1:12:14:16:18:1

Primary Prescaler Settings 1:1 Invalid 8000 4000 2667 2000

4:1 4000 2000 1000 667 500

16:1 1000 500 250 167 125

64:1 250 125 63 42 31

FCY = 5 MHz

Primary Prescaler Settings 1:1 5000 2500 1250 833 625

4:1 1250 625 313 208 156

16:1 313 156 78 52 39

64:17839201310

Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.

2: The SCKx frequencies are shown in kHz.

Primary Prescaler * Secondary Prescaler

FCY

FSCK =

Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.

 2005-2012 Microchip Technology Inc. DS39747F-page 137

PIC24FJ128GA010 FAMILY

16.0 INTER-INTEGRATED CIRCUIT

(I2C™)

The Inter-Integrated Circuit (I2C) module is a serial

interface useful for communicating with other periph-

eral or microcontroller devices. These peripheral

devices may be serial EEPROMs, display drivers, A/D

Converters, etc.

The I2C module supports these features:

• Independent master and slave logic

• 7-bit and 10-bit device addresses

• General call address, as defined in the I

C protocol

• Clock stretching to provide delays for the

processor to respond to a slave data request

• Both 100 kHz and 400 kHz bus specifications.

• Configurable address masking

• Multi-Master modes to prevent loss of messages

in arbitration

• Bus Repeater mode, allowing the acceptance of

all messages as a slave, regardless of the

address

• Automatic SCL

A block diagram of the module is shown in Figure 16-1.

16.1 Communicating as a Master in a

Single Master Environ ment

The details of sending a message in Master mode

depends on the communications protocol for the device

being communicated with. Typically, the sequence of

events is as follows:

1. Assert a Start condition on SDAx and SCLx.

2. Send the I2C device address byte to the slave

with a write indication.

3. Wait for and verify an Acknowledge from the

slave.

4. Send the first data byte (sometimes known as

the command) to the slave.

5. Wait for and verify an Acknowledge from the

slave.

6. Send the serial memory address low byte to the

slave.

7. Repeat Steps 4 and 5 until all data bytes are

sent.

8. Assert a Repeated Start condition on SDAx and

SCLx.

9. Send the device address byte to the slave with

a read indication.

10. Wait for and verify an Acknowledge from the

slave.

11. Enable master reception to receive serial

memory data.

12. Generate an ACK or NACK condition at the end

of a received byte of data.

13. Generate a Stop condition on SDAx and SCLx.

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 24. “Inter-

Integrated Circuit™ (I2C™)” (DS39702)

in the “PIC24F Family Reference Manual”

for more information.

PIC24FJ128GA010 FAMILY

DS39747F-page 138  2005-2012 Microchip Technology Inc.

FIGURE 16-1: I2C™ BLOCK DIAGRAM

I2CxRCV

Internal

Data Bus

SCLx

SDAx

Shift

Match Detect

I2CxADD

Start and Stop

Bit Detect

Clock

Address Match

Clock

Stretching

I2CxTRN

LSB

Shift Clock

BRG Down Counter

Reload

Control

TCY/2

Start and Stop

Bit Generation

Acknowledge

Generation

Collision

Detect

I2CxCON

I2CxSTAT

Control Logic

Read

LSB

Write

Read

I2CxBRG

I2CxRSR

Write

Read

Write

Read

Write

Read

Write

Read

Write

Read

I2CxMSK

 2005-2012 Microchip Technology Inc. DS39747F-page 139

PIC24FJ128GA010 FAMILY

16.2 Setting Baud Rate When

Operating as a Bus Master

To compute the Baud Rate Generator reload value, use

the following equation:

EQUATION 16-1:(1)

16.3 Slave Address Masking

The I2CxMSK register (Register 16-3) designates

address bit positions as “don’t care” for both 7-Bit and

10-Bit Addressing modes. Setting a particular bit loca-

tion (= 1) in the I2CxMSK register causes the slave

module to respond, whether the corresponding

address bit value is a ‘0’ or ‘1’. For example, when

I2CxMSK is set to ‘00100000’, the slave module will

detect both addresses, ‘0000000’ and ‘00100000’.

To enable address masking, the IPMI (Intelligent

Peripheral Management Interface) must be disabled by

clearing the IPMIEN bit (I2CxCON<11>).

TABLE 16-1: I2C™ CLOC K RATES(1,3,4)

As a result of changes in the I2C protocol, several I2C

addresses are reserved and will not be Acknowledged

in Slave mode.

Address masking does not affect behavior. Refer to

Table 16-2 for a summary of these reserved addresses.

Note 1: Based on FCY = FOSC/2; Doze mode and

PLL are disabled.

I2CxBRG = (FCY/FSCL – FCY/10,000,000) – 1

Required

System

FSCL FCY I2CxBRG Value Actual

FSCL

(Decimal) (Hexadecimal)

100 kHz 16 MHz 157 9D 100 kHz

100 kHz 8 MHz 78 4E 100 kHz

100 kHz 4 MHz 39 27 99 kHz

400 kHz 16 MHz 37 25 404 kHz

400 kHz 8 MHz 18 12 404 kHz

400 kHz 4 MHz 9 9 385 kHz(2)

400 kHz 2 MHz 4 4 385 kHz(2)

1 MHz 16 MHz 13 D 1,026 KHz

1MHz 8MHz 6 6 1,026KHz

1MHz 4MHz 3 3 909 KHz

Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled.

2: This is the closest value to 400 kHz for this value of FCY.

3: FCY = 2 MHz is the minimum input clock frequency to have FSCL = 1 MHz.

4: I2CxBRG cannot have a value of less than 2.

TABLE 16-2: RESER VED I2C™ ADDRESSES(1)

Slave Address R/W Bit Description

0000 000 0 General Call Address(2)

0000 000 1 Start Byte

0000 001 x CBUS Address

0000 010 x Reserved

0000 011 x Reserved

0000 1xx x HS Mode Master Code

1111 1xx x Reserved

1111 0xx x 10-Bit Slave Upper Byte(3)

Note 1: The above address bits will not cause an address match, independent of address mask settings.

2: The address will be Acknowledged only if GCEN = 1.

3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.

PIC24FJ128GA010 FAMILY

DS39747F-page 140  2005-2012 Microchip Technology Inc.

R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0

I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC

GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN

bit 7 bit 0

Legend: HC = Hardware Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 I2CEN: I2Cx Enable bit

1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins

0 = Disables I2Cx module; all I2C™ pins are controlled by port functions

bit 14 Unimplemented: Read as ‘0’

bit 13 I2CSIDL: Stop in Idle Mode bit

1 = Discontinues module operation when the device enters an Idle mode

0 = Continues module operation in Idle mode

bit 12 SCLREL: SCLx Release Control bit (when operating as an I2C™ slave)

1 = Releases SCLx clock

0 = Holds SCLx clock low (clock stretch)

If STREN = 1:

Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear

at the beginning of slave transmission. Hardware is clear at the end of slave reception.

If STREN = 0:

Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware is clear at the beginning of slave

transmission.

bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit

1 = IPMI Support mode is enabled; all addresses are Acknowledged

0 = IPMI mode is disabled

bit 10 A10M: 10-Bit Slave Address bit

1 = I2CxADD is a 10-bit slave address

0 = I2CxADD is a 7-bit slave address

bit 9 DISSLW: Disable Slew Rate Control bit

1 = Slew rate control is disabled

0 = Slew rate control is enabled

bit 8 SMEN: SMBus Input Levels bit

1 = Enables I/O pin thresholds compliant with the SMBus specification

0 = Disables SMBus input thresholds

bit 7 GCEN: General Call Enable bit (when operating as an I2C slave)

1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for

reception)

0 = General call address is disabled

bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as an I2C slave)

Used in conjunction with the SCLREL bit.

1 = Enables software or receives clock stretching

0 = Disables software or receives clock stretching

 2005-2012 Microchip Technology Inc. DS39747F-page 141

PIC24FJ128GA010 FAMILY

bit 5 ACKDT: Acknowledge Data bit (When operating as an I2C master; applicable during master receive.)

Value that will be transmitted when the software initiates an Acknowledge sequence.

1 = Sends NACK during Acknowledge

0 = Sends ACK during Acknowledge

bit 4 ACKEN: Acknowledge Sequence Enable bit

(When operating as an I2C master; applicable during master receive.)

1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits the ACKDT data bit.

Hardware is clear at the end of the master Acknowledge sequence.

0 = Acknowledge sequence is not in progress

bit 3 RCEN: Receive Enable bit (when operating as an I2C master)

1 = Enables Receive mode for I2C. Hardware is clear at the end of the eighth bit of the master receive

data byte.

0 = Receive sequence is not in progress

bit 2 PEN: Stop Condition Enable bit (when operating as an I2C master)

1 = Initiates Stop condition on SDAx and SCLx pins. Hardware is clear at the end of the master Stop

sequence.

0 = Stop condition is not in progress

bit 1 RSEN: Repeated Start Condition Enable bit (when operating as an I2C master)

1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware is clear at the end of the

master Repeated Start sequence.

0 = Repeated Start condition is not in progress

bit 0 SEN: Start Condition Enable bit (when operating as an I2C master)

1 = Initiates Start condition on SDAx and SCLx pins. Hardware is clear at the end of the master Start

sequence.

0 = Start condition is not in progress

PIC24FJ128GA010 FAMILY

DS39747F-page 142  2005-2012 Microchip Technology Inc.

R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HSC R-0, HSC R-0, HSC

ACKSTAT TRSTAT — — — BCL GCSTAT ADD10

bit 15 bit 8

R/C-0, HSC R/C-0, HSC R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC

IWCOL I2COV D/A PSR/WRBF TBF

bit 7 bit 0

Legend: HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ C = Clearable bit

R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ACKSTAT: Acknowledge Status bit

1 = NACK is received from slave

0 = ACK is received from slave

Hardware is set or clear at the end of slave Acknowledge.

bit 14 TRSTAT: Transmit Status bit (When operating as I2C master; applicable to master transmit operation.)

1 = Master transmit is in progress (8 bits + ACK)

0 = Master transmit is not in progress

Hardware is set at the beginning of master transmission. Hardware is clear at the end of slave Acknowledge.

bit 13-11 Unimplemented: Read as ‘0’

bit 10 BCL: Master Bus Collision Detect bit

1 = A bus collision has been detected during master operation

0 = No collision

Hardware is set at the detection of a bus collision.

bit 9 GCSTAT: General Call Status bit

1 = General call address was received

0 = General call address was not received

Hardware is set when an address matches a general call address. Hardware is clear at Stop detection.

bit 8 ADD10: 10-Bit Address Status bit

1 = 10-bit address was matched

0 = 10-bit address was not matched

Hardware is set at a match of the 2nd byte of a matched 10-bit address. Hardware is clear at Stop detection.

bit 7 IWCOL: Write Collision Detect bit

1 = An attempt to write the I2CxTRN register failed because the I2C module is busy

0 = No collision

Hardware is set at an occurrence of a write to I2CxTRN while busy (cleared by software).

bit 6 I2COV: Receive Overflow Flag bit

1 = A byte was received while the I2CxRCV register is still holding the previous byte

0 = No overflow

Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).

bit 5

D/A

: Data/Address bit (when operating as I2C slave)

1 = Indicates that the last byte received was data

0 = Indicates that the last byte received was device address

Hardware is clear at a device address match. Hardware is set after a transmission finishes or by

reception of a slave byte.

bit 4 P: Stop bit

1 = Indicates that a Stop bit has been detected last

0 = Stop bit was not detected last

Hardware is set or clear when a Start, Repeated Start or Stop is detected.

 2005-2012 Microchip Technology Inc. DS39747F-page 143

PIC24FJ128GA010 FAMILY

bit 3 S: Start bit

1 = Indicates that a Start (or Repeated Start) bit has been detected last

0 = Start bit was not detected last

Hardware is set or clear when Start, Repeated Start or Stop is detected.

bit 2 R/W: Read/Write bit Information (when operating as I2C slave)

1 = Read – indicates data transfer is output from slave

0 = Write – indicates data transfer is input to slave

Hardware is set or clear after reception of an I2C device address byte.

bit 1 RBF: Receive Buffer Full Status bit

1 = Receive is complete, I2CxRCV is full

0 = Receive is not complete, I2CxRCV is empty

Hardware is set when I2CxRCV is written with the received byte. Hardware is clear when the software reads

I2CxRCV.

bit 0 TBF: Transmit Buffer Full Status bit

1 = Transmit is in progress, I2CxTRN is full

0 = Transmit is complete, I2CxTRN is empty

Hardware is set when the software writes to I2CxTRN. Hardware is clear at the completion of

data transmission.

PIC24FJ128GA010 FAMILY

DS39747F-page 144  2005-2012 Microchip Technology Inc.

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — AMSK9 AMSK8

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-10 Unimplemented: Read as ‘0’

bit 9-0 AMSK<9:0>: Mask for Address Bit x Select bits

1 = Enables masking for bit x of incoming message address; bit match is not required in this position

0 = Disables masking for bit x; bit match is required in this position

 2005-2012 Microchip Technology Inc. DS39747F-page 145

PIC24FJ128GA010 FAMILY

17.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER

(UART)

The Universal Asynchronous Receiver Transmitter

(UART) module is one of the serial I/O modules available

in the PIC24F device family. The UARTx is a full-duplex,

asynchronous system that can communicate with

peripheral devices, such as personal computers,

LIN/J2602, RS-232 and RS-485 interfaces. The

module also supports a hardware flow control option

with the UxCTS and UxRTS pins, and also includes an

IrDA® encoder and decoder.

The primary features of the UARTx module are:

• Full-Duplex, 8 or 9-Bit Data Transmission

Through the UxTX and UxRX Pins

• Even, Odd or No Parity Options (for 8-bit data)

• One or Two Stop bits

• Hardware Flow Control Option with UxCTS and

UxRTS Pins

• Fully Integrated Baud Rate Generator with 16-Bit

Prescaler

• Baud Rates Ranging from 1 Mbps to 15 bps at

16 MIPS

• 4-Deep First-In-First-Out (FIFO) Transmit Data

Buffer

• 4-Deep FIFO Receive Data Buffer

• Parity, Framing and Buffer Overrun Error Detection

• Support for 9-bit mode with Address Detect

(9th bit = 1)

• Transmit and Receive Interrupts

• Loopback mode for Diagnostic Support

• Support for Sync and Break Characters

• Supports Automatic Baud Rate Detection

• IrDA Encoder and Decoder Logic

• 16x Baud Clock Output for IrDA Support

A simplified block diagram of the UARTx is shown in

Figure 17-1. The UARTx module consists of these key

important hardware elements:

• Baud Rate Generator

• Asynchronous Transmitter

• Asynchronous Receiver

FIGURE 17-1: UARTx SIMPLIFIED BLOCK DIAGRAM

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 21. “UART”

(DS39708) in the “PIC24F Family

Reference Manual” for more information.

UxRX

IrDA®

Hardware Flow Control

UARTx Receiver

UARTx Transmitter UxTX

UxCTS

UxRTS

BCLKx

Baud Rate Generator

PIC24FJ128GA010 FAMILY

DS39747F-page 146  2005-2012 Microchip Technology Inc.

17.1 UARTx Baud Rate Generator

(BRG)

The UARTx module includes a dedicated, 16-bit Baud

Rate Generator. The UBRGx register controls the

period of a free-running, 16-bit timer. Equation 17-1

shows the formula for computation of the baud rate

with BRGH = 0.

EQUATION 17-1: UARTx BAUD RATE WITH

BRGH = 0(1)

Example 17-1 shows the calculation of the baud rate

error for the following conditions:

•FCY = 4 MHz

• Desired Baud Rate = 9600

The maximum baud rate (BRGH = 0) possible is

FCY/16 (for UBRGx = 0) and the minimum baud rate

possible is FCY/(16 * 65536).

Equation 17-2 shows the formula for computation of

the baud rate with BRGH = 1.

EQUATION 17-2: UARTx BAUD RATE WITH

BRGH = 1(1)

The maximum baud rate (BRGH = 1) possible is FCY/4

(for UBRGx = 0) and the minimum baud rate possible

is FCY/(4 * 65536).

Writing a new value to the UBRGx register causes the

BRG timer to be reset (cleared). This ensures the BRG

does not wait for a timer overflow before generating the

new baud rate.

EXAMPLE 17-1: BAUD RATE ERROR CALCULATION (BRGH = 0)(1)

Note 1: Based on FCY = FOSC/2; Doze mode

and PLL are disabled.

Baud Rate = FCY

16 • (UBRGx + 1)

FCY

16 • Baud Rate

UBRGx = – 1

Baud Rate = FCY

4 • (UBRGx + 1)

FCY

4 • Baud Rate

UBRGx = – 1

Note 1: Based on FCY = FOSC/2; Doze mode

and PLL are disabled.

Desired B aud Rat e = FCY/(16 (UBR G x + 1))

Solving for UBRGx value:

BRGx = ((FCY/De sired Baud Rate)/16) – 1

BRGx = ((4000000/9600)/16) – 1

BRGx = 25

Calcula te d Ba ud Rate = 4000 000/(16 (25 + 1))

= 9615

Error = (Calculated Baud Rate – Desired Baud Rate)

Desired Baud Rate

= (9615 – 9600)/9600

= 0.16%

Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.

 2005-2012 Microchip Technology Inc. DS39747F-page 147

PIC24FJ128GA010 FAMILY

17.2 Transmitting in 8-Bit Data Mode

1. Set up the UARTx:

a) Write appropriate values for data, parity and

Stop bits.

b) Write appropriate baud rate value to the

UBRGx register.

c) Set up transmit and receive interrupt enable

and priority bits.

2. Enable the UARTx.

3. Set the UTXEN bit (causes a transmit interrupt).

4. Write data byte to lower byte of UTXxREG word.

The value will be immediately transferred to the

Transmit Shift Register (TSR) and the serial bit

stream will start shifting out with the next rising

edge of the baud clock.

5. Alternately, the data byte may be transferred

while UTXEN = 0 and then the user may set

UTXEN. This will cause the serial bit stream to

begin immediately because the baud clock will

start from a cleared state.

6. A transmit interrupt will be generated as per

interrupt control bit, UTXISELx.

17.3 Transmitting in 9-Bit Data Mode

1. Set up the UARTx (as described in Section 17.2

“Transmitting in 8-Bit Data Mode”).

2. Enable the UARTx.

3. Set the UTXEN bit (causes a transmit interrupt).

4. Write UxTXREG as a 16-bit value only.

5. A word write to UxTXREG triggers the transfer

of the 9-bit data to the TSR. Serial bit stream will

start shifting out with the first rising edge of the

baud clock.

6. A transmit interrupt will be generated as per the

setting of control bit, UTXISELx.

17.4 Break and Sync Transmit

Sequence

The following sequence will send a message frame

header, made up of a Break, followed by an auto-baud

Sync byte.

1. Configure the UARTx for the desired mode.

2. Set UTXEN and UTXBRK – sets up the Break

character,

3. Load the UxTXREG with a dummy character to

initiate transmission (value is ignored).

4. Write ‘55h’ to UxTXREG – loads the Sync

character into the transmit FIFO.

5. After the Break has been sent, the UTXBRK bit

is reset by hardware. The Sync character now

transmits.

17.5 Receiving in 8-Bit or 9-Bit Data

Mode

1. Set up the UARTx (as described in Section 17.2

“Transmitting in 8-Bit Data Mode”).

2. Enable the UARTx.

3. A receive interrupt will be generated when one

or more data characters have been received, as

per interrupt control bit, URXISELx.

4. Read the OERR bit to determine if an overrun

error has occurred. The OERR bit must be reset

in software.

5. Read UxRXREG.

The act of reading the UxRXREG character will move

the next character to the top of the receive FIFO,

including a new set of PERR and FERR values.

17.6 Operation of UxCTS and UxRTS

Control Pins

UARTx Clear-to-Send (UxCTS) and Request-to-Send

(UxRTS) are the two hardware controlled pins that are

associated with the UARTx modules. These two pins

allow the UARTx to operate in Simplex and Flow Con-

trol mode. They are implemented to control the

transmission and reception between the Data Terminal

Equipment (DTE). The UEN<1:0> bits in the UxMODE

17.7 Infrared Support

The UARTx module provides two types of infrared

UARTx support: one is the IrDA clock output to support

the external IrDA encoder and decoder device (legacy

module support), and the other is the full implementation

of the IrDA encoder and decoder.

17.8 External IrDA Support – IrDA

Clock Output

To support the external IrDA encoder and decoder

devices, the BCLKx pin (same as the UxRTS pin) can

be configured to generate the 16x baud clock. With

UEN<1:0> = 11, the BCLKx pin will output the

16x baud clock if the UARTx module is enabled. It can

be used to support the IrDA codec chip.

17.9 Built -in Ir DA Encoder and Deco der

The UARTx has full implementation of the IrDA

encoder and decoder as part of the UARTx module.

The built-in IrDA encoder and decoder functionality is

enabled using the IREN bit UxMODE<12>. When

enabled (IREN = 1), the receive pin (UxRX) acts as the

input from the infrared receiver. The transmit pin

(UxTX) acts as the output to the infrared transmitter.

PIC24FJ128GA010 FAMILY

DS39747F-page 148  2005-2012 Microchip Technology Inc.

R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

UARTEN — USIDL IREN(1)RTSMD — UEN1 UEN0

bit 15 bit 8

R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL

bit 7 bit 0

Legend: HC = Hardware Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 UARTEN: UARTx Enable bit

1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>

0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption is minimal

bit 14 Unimplemented: Read as ‘0’

bit 13 USIDL: Stop in Idle Mode bit

1 = Discontinues module operation when the device enters Idle mode

0 = Continues module operation in Idle mode

bit 12 IREN: IrDA® Encoder and Decoder Enable bit(1)

1 = IrDA encoder and decoder are enabled

0 = IrDA encoder and decoder are disabled

bit 11 RTSMD: Mode Selection for UxRTS Pin bit

1 =UxRTS pin is in Simplex mode

0 =UxRTS

pin is in Flow Control mode

bit 10 Unimplemented: Read as ‘0’

bit 9-8 UEN<1:0>: UARTx Enable bits

11 = UxTX, UxRX and BCLKx pins are enabled and used; the UxCTS pin is controlled by PORT latches

10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used

01 = UxTX, UxRX and UxRTS pins are enabled and used; the UxCTS pin is controlled by PORT latches

00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by PORT

latches

bit 7 WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit

1 = UARTx will continue to sample the UxRX pin; interrupt is generated on the falling edge, bit cleared in

hardware on the following rising edge

0 = No wake-up is enabled

bit 6 LPBACK: UARTx Loopback Mode Select bit

1 = Enables Loopback mode

0 = Loopback mode is disabled

bit 5 ABAUD: Auto-Baud Enable bit

1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h);

cleared in hardware upon completion

0 = Baud rate measurement is disabled or completed

bit 4 RXINV: Receive Polarity Inversion bit

1 = UxRX Idle state is ‘0’

0 = UxRX Idle state is ‘1’

Note 1: This feature is only available for the 16x BRG mode (BRGH = 0).

 2005-2012 Microchip Technology Inc. DS39747F-page 149

PIC24FJ128GA010 FAMILY

bit 3 BRGH: High Baud Rate Enable bit

1 = BRG generates 4 clocks per bit period (4x Baud Clock, High-Speed mode)

0 = BRG generates 16 clocks per bit period (16x Baud Clock, Standard mode)

bit 2-1 PDSEL<1:0>: Parity and Data Selection bits

11 = 9-bit data, no parity

10 = 8-bit data, odd parity

01 = 8-bit data, even parity

00 = 8-bit data, no parity

bit 0 STSEL: Stop Bit Selection bit

1 = Two Stop bits

0 = One Stop bit

Note 1: This feature is only available for the 16x BRG mode (BRGH = 0).

PIC24FJ128GA010 FAMILY

DS39747F-page 150  2005-2012 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0 R-1

UTXISEL1 TXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0

URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA

bit 7 bit 0

Legend: C = Clearable bit HC = Hardware Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits

11 = Reserved; do not use

10 = Interrupt when a character is transferred to the Transmit Shift Register and as a result, the transmit

buffer becomes empty

01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations

are completed

00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least

one character open in the transmit buffer)

bit 14 TXINV: Transmit Polarity Inversion bit

IREN = 0:

1 = TX Idle state is ‘0’

0 = TX Idle state is ‘1’

IREN = 1:

1 = IrDA® encoded TX Idle state is ‘1’

0 = IrDA encoded TX Idle state is ‘0’

bit 12 Unimplemented: Read as ‘0’

bit 11 UTXBRK: Transmit Break bit

1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;

cleared by hardware upon completion

0 = Sync Break transmission is disabled or completed

bit 10 UTXEN: Transmit Enable bit

1 = Transmit is enabled, UxTX pin controlled by UARTx

0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset. UxTX pin is controlled

by the PORT.

bit 9 UTXBF: Transmit Buffer Full Status bit (read-only)

1 = Transmit buffer is full

0 = Transmit buffer is not full, at least one more character can be written

bit 8 TRMT: Transmit Shift Register Empty bit (read-only)

1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)

0 = Transmit Shift Register is not empty, a transmission is in progress or queued

bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bits

11 = Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters)

10 = Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)

0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer;

receive buffer has one or more characters

bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)

1 = Address Detect mode is enabled. If 9-bit mode is not selected, this does not take effect.

0 = Address Detect mode is disabled

 2005-2012 Microchip Technology Inc. DS39747F-page 151

PIC24FJ128GA010 FAMILY

bit 4 RIDLE: Receiver Idle bit (read-only)

1 = Receiver is Idle

0 = Receiver is active

bit 3 PERR: Parity Error Status bit (read-only)

1 = Parity error has been detected for the current character (character at the top of the receive FIFO)

0 = Parity error has not been detected

bit 2 FERR: Framing Error Status bit (read-only)

1 = Framing error has been detected for the current character (character at the top of the receive FIFO)

0 = Framing error has not been detected

bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only)

1 = Receive buffer has overflowed

0 = Receive buffer has not overflowed (clearing a previously set OERR bit (10 transition) will reset

the receiver buffer and the RSR to the empty state)

bit 0 URXDA: Receive Buffer Data Available bit (read-only)

1 = Receive buffer has data, at least one more character can be read

0 = Receive buffer is empty

PIC24FJ128GA010 FAMILY

DS39747F-page 152  2005-2012 Microchip Technology Inc.

NOTES:

 2005-2012 Microchip Technology Inc. DS39747F-page 153

PIC24FJ128GA010 FAMILY

18.0 PARALLEL MASTER PORT

(PMP)

The Parallel Master Port (PMP) module is a parallel,

8-bit I/O module, specifically designed to communicate

with a wide variety of parallel devices, such as commu-

nication peripherals, LCDs, external memory devices

and microcontrollers. Because the interface to parallel

peripherals varies significantly, the PMP is highly

configurable.

Key features of the PMP module include:

• Up to 16 Programmable Address Lines

• Up to Two Chip Select Lines

• Programmable Strobe Options

- Individual Read and Write Strobes or;

- Read/Write Strobe with Enable Strobe

• Address Auto-Increment/Auto-Decrement

• Programmable Address/Data Multiplexing

• Programmable Polarity on Control Signals

• Legacy Parallel Slave Port Support

• Enhanced Parallel Slave Support

- Address Support

- 4-Byte Deep Auto-Incrementing Buffer

• Programmable Wait States

• Selectable Input Voltage Levels

FIGURE 18-1: PM P MO DUL E OV ER VIE W

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 13. “Parallel

Master Port (PMP)” (DS39713) in the

“PIC24F Family Reference Manual” for

more information.

PMA<0>

PMA<14>

PMA<15>

PMBE

PMRD

PMWR

PMD<7:0>

PMENB

PMRD/PMWR

PMCS1

PMA<1>

PMA<13:2>

PMALL

PMALH

PMA<7:0>

PMA<15:8>

PMCS2

EEPROM

Address Bus

Data Bus

Control Lines

PIC24F

LCD FIFO

Microcontroller

8-Bit Data

Up to 16-Bit Address

Parallel Master Port

Buffer

PIC24FJ128GA010 FAMILY

DS39747F-page 154  2005-2012 Microchip Technology Inc.

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN

bit 15 bit 8

R/W-0 R/W-0 R/W-0(1)R/W-0(1)R/W-0(1)R/W-0 R/W-0 R/W-0

CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 PMPEN: Parallel Master Port Enable bit

1 = PMP is enabled

0 = PMP is disabled, no off-chip access is performed

bit 14 Unimplemented: Read as ‘0’

bit 13 PSIDL: Stop in Idle Mode bit

1 = Discontinues module operation when device enters Idle mode

0 = Continues module operation in Idle mode

bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits

11 = Reserved

10 = All 16 bits of address are multiplexed on PMD<7:0> pins

01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 8 bits are on PMA<15:8>

00 = Address and data appear on separate pins

bit 10 PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode)

1 = PMBE port is enabled

0 = PMBE port is disabled

bit 9 PTWREN: Write Enable Strobe Port Enable bit

1 = PMWR/PMENB port is enabled

0 = PMWR/PMENB port is disabled

bit 8 PTRDEN: Read/Write Strobe Port Enable bit

1 = PMRD/PMWR port is enabled

0 = PMRD/PMWR port is disabled

bit 7-6 CSF<1:0>: Chip Select Function bits

11 = Reserved

10 = PMCS1 and PMCS2 function as chip select

01 = PMCS2 functions as chip select, PMCS1 functions as Address Bit 14

00 = PMCS1 and PMCS2 function as Address Bits 15 and 14

bit 5 ALP: Address Latch Polarity bit(1)

1 = Active-high (PMALL and PMALH)

0 = Active-low (PMALL and PMALH)

bit 4 CS2P: Chip Select 2 Polarity bit(1)

1 = Active-high (PMCS2)

0 =Active-low (PMCS2

)

bit 3 CS1P: Chip Select 1 Polarity bit(1)

1 = Active-high (PMCS1/PMCS)

0 =Active-low (PMCS1

/PMCS)

Note 1: These bits have no effect when their corresponding pins are used as address lines.

 2005-2012 Microchip Technology Inc. DS39747F-page 155

PIC24FJ128GA010 FAMILY

bit 2 BEP: Byte Enable Polarity bit

1 = Byte enable is active-high (PMBE)

0 = Byte enable is active-low (PMBE)

bit 1 WRSP: Write Strobe Polarity bit

For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10):

1 = Write strobe is active-high (PMWR)

0 = Write strobe is active-low (PMWR)

For Master mode 1 (PMMODE<9:8> = 11):

1 = Enable strobe is active-high (PMENB)

0 = Enable strobe is active-low (PMENB)

bit 0 RDSP: Read Strobe Polarity bit

For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10):

1 = Read strobe is active-high (PMRD)

0 = Read strobe is active-low (PMRD)

For Master mode 1 (PMMODE<9:8> = 11):

1 = Read/write strobe is active-high (PMRD/PMWR)

0 = Read/write strobe is active-low (PMRD/PMWR)

Note 1: These bits have no effect when their corresponding pins are used as address lines.

PIC24FJ128GA010 FAMILY

DS39747F-page 156  2005-2012 Microchip Technology Inc.

R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WAITB1(1)WAITB0(1)WAITM3 WAITM2 WAITM1 WAITM0 WAITE1(1)WAITE0(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 BUSY: Busy bit (Master mode only)

1 = Port is busy (not useful when the processor stall is active)

0 = Port is not busy

bit 14-13 IRQM<1:0>: Interrupt Request Mode bits

11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode), or

on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only)

10 = No interrupt is generated, processor stall activated

01 = Interrupt is generated at the end of the read/write cycle

00 = No interrupt is generated

bit 12-11 INCM<1:0>: Increment Mode bits

11 = PSP read and write buffers auto-increment (Legacy PSP mode only)

10 = Decrements ADDR<15,13:0> by 1 every read/write cycle

01 = Increments ADDR<15,13:0> by 1 every read/write cycle

00 = No increment or decrement of the address

bit 10 MODE16: 8/16-Bit Mode bit

1 = 16-bit mode: Data register is 16 bits, a read or write to the Data register invokes two 8-bit transfers

0 = 8-bit mode: Data register is 8 bits, a read or write to the Data register invokes one 8-bit transfer

bit 9-8 MODE<1:0>: Parallel Port Mode Select bits

11 = Master mode 1 (PMCSx, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)

10 = Master mode 2 (PMCSx, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)

01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0>)

00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>)

bit 7-6 WAITB<1:0>: Data Setup to Read/Write Wait State Configuration bits(1)

11 = Data Wait of 4 TCY; multiplexed address phase of 4 TCY

10 = Data Wait of 3 TCY; multiplexed address phase of 3 TCY

01 = Data Wait of 2 TCY; multiplexed address phase of 2 TCY

00 = Data Wait of 1 TCY; multiplexed address phase of 1 TCY

bit 5-2 WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits

1111 = Wait of additional 15 TCY

...

0001 = Wait of additional 1 TCY

0000 = No additional Wait cycles (operation forced into one TCY)

bit 1-0 WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits(1)

11 = Wait of 4 TCY

10 = Wait of 3 TCY

01 = Wait of 2 TCY

00 = Wait of 1 TCY

Note 1: WAITB and WAITE bits are ignored whenever WAITM<3:0> = 0000.

 2005-2012 Microchip Technology Inc. DS39747F-page 157

PIC24FJ128GA010 FAMILY

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CS2 CS1 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CS2: Chip Select 2 bit

1 = Chip Select 2 is active

0 = Chip Select 2 is inactive (pin functions as PMA<15>)

bit 14 CS1: Chip Select 1 bit

1 = Chip Select 1 is active

0 = Chip Select 1 is inactive (pin functions as PMA<14>)

bit 13-0 ADDR<13:0>: Parallel Port Destination Address bits

Note 1: PMADDR and PMDOUT1 share the same physical register. The register functions as PMDOUT1 only in

Slave modes and as PMADDR only in Master modes.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 PTEN<15:14>: PMCSx Strobe Enable bits

1 = PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1

0 = PMA15 and PMA14 function as port I/O

bit 13-2 PTEN<13:2>: PMP Address Port Enable bits

1 = PMA<13:2> function as PMP address lines

0 = PMA<13:2> function as port I/O

bit 1-0 PTEN<1:0>: PMALH/PMALL Strobe Enable bits

1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL

0 = PMA1 and PMA0 pads function as port I/O

PIC24FJ128GA010 FAMILY

DS39747F-page 158  2005-2012 Microchip Technology Inc.

R-0 R/W-0, HS U-0 U-0 R-0 R-0 R-0 R-0

IBF IBOV —— IB3F IB2F IB1F IB0F

bit 15 bit 8

R-1 R/W-0, HS U-0 U-0 R-1 R-1 R-1 R-1

OBE OBUF —— OB3E OB2E OB1E OB0E

bit 7 bit 0

Legend: HS = Hardware Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 IBF: Input Buffer Full Status bit

1 = All writable Input Buffer registers are full

0 = Some or all of the writable Input Buffer registers are empty

bit 14 IBOV: Input Buffer Overflow Status bit

1 = A write attempt to a full Input Byte register occurred (must be cleared in software)

0 = No overflow occurred

bit 13-12 Unimplemented: Read as ‘0’

bit 11-8 IB3F:IB0F: Input Buffer n Status Full bit

1 = Input buffer contains data that has not been read (reading the buffer will clear this bit)

0 = Input buffer does not contain any unread data

bit 7 OBE: Output Buffer Empty Status bit

1 = All readable Output Buffer registers are empty

0 = Some or all of the readable Output Buffer registers are full

bit 6 OBUF: Output Buffer Underflow Status bit

1 = A read occurred from an empty Output Byte register (must be cleared in software)

0 = No underflow occurred

bit 5-4 Unimplemented: Read as ‘0’

bit 3-0 OB3E:OB0E: Output Buffer n Status Empty bit

1 = Output buffer is empty (writing data to the buffer will clear this bit)

0 = Output buffer contains data that has not been transmitted

 2005-2012 Microchip Technology Inc. DS39747F-page 159

PIC24FJ128GA010 FAMILY

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — RTSECSEL(1)PMPTTL(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-2 Unimplemented: Read as ‘0’

bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1)

1 = RTCC Seconds Clock is selected for the RTCC pin

0 = RTCC Alarm Pulse is selected for the RTCC pin

bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit(2)

1 = PMP module uses TTL input buffers

0 = PMP module uses Schmitt input buffers

Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit needs to be set.

2: Refer to Table 1-2 for affected PMP inputs.

PIC24FJ128GA010 FAMILY

DS39747F-page 160  2005-2012 Microchip Technology Inc.

FIGURE 18-2: LEGACY PARALLEL SLAVE PORT EXAMPLE

FIGURE 18-3: ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE

TABLE 18-1: SLAVE MODE ADDRESS RESOLUTION

FIGURE 18-4: MASTER MODE, DEMULTIPLEXED ADDRESSING (SEPARATE READ AND

WRITE STROBES, TWO CHIP SELECTS)

PMA<1:0> Output Register (Buffer) Input Register (Buffer)

00 PMDOUT1<7:0> (0) PMDIN1<7:0> (0)

01 PMDOUT1<15:8> (1) PMDIN1<15:8> (1)

10 PMDOUT2<7:0> (2) PMDIN2<7:0> (2)

11 PMDOUT2<15:8> (3) PMDIN2<15:8> (3)

PMD<7:0>

PMRD

PMWR

Master Address Bus

Data Bus

Control Lines

PMCS

PMD<7:0>

PMRD

PMWR

PIC24F Slave

PMCS

PMD<7:0>

PMRD

PMWR

Master

PMCS

PMA<1:0>

Address Bus

Data Bus

Control Lines

PMRD

PMWR

PIC24F Slave

PMCS

PMDOUT1L (0)

PMDOUT1H (1)

PMDOUT2L (2)

PMDOUT2H (3)

PMDIN1L (0)

PMDIN1H (1)

PMDIN2L (2)

PMDIN2H (3)

PMD<7:0> Write

Address

Decode

Read

Address

Decode

PMA<1:0>

PMRD

PMWR

PMD<7:0>

PMCS1

PMA<13:0>

PMCS2

PIC24F

Address Bus

Data Bus

Control Lines

 2005-2012 Microchip Technology Inc. DS39747F-page 161

PIC24FJ128GA010 FAMILY

FIGURE 18-5: MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ

AND WRITE STROBES, TWO CHIP SELECTS)

FIGURE 18-6: MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND

WRITE S TROBES, TWO CHIP SELECTS)

FIGURE 18-7: EXAMPLE OF A MULTIPLEXED ADDRE SS ING APPLICA TION

FIGURE 18-8: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION

PMRD

PMWR

PMD<7:0>

PMCS1

PMA<13:8>

PMALL

PMA<7:0>

PMCS2

PIC24F

Address Bus

Multiplexed

Data and

Address Bus

Control Lines

PMRD

PMWR

PMD<7:0>

PMCS1

PMALH

PMA<13:8>

PMCS2

PIC24F

Multiplexed

Data and

Address Bus

Control Lines

PMALL

PMD<7:0>

PMALH

D<7:0>

373 A<15:0>

D<7:0>

A<7:0>

373

PMRD

PMWR

OE WR

PIC24F

Address Bus

Data Bus

Control Lines

PMCS1

PMALL

A<15:8>

PMA<14:7>

D<7:0>

373 A<14:0>

D<7:0>

A<7:0>

PMRD

PMWR

OE WR

PIC24F

Address Bus

Data Bus

Control Lines

PMCS1

PMALL

A<14:8>

PMD<7:0>

PIC24FJ128GA010 FAMILY

DS39747F-page 162  2005-2012 Microchip Technology Inc.

FIGURE 18-9: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION

FIGURE 18-10: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA)

FIGURE 18-11: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 16-BIT DATA)

FIGURE 18-12: LCD CONTROL EXAMPLE (BYTE MODE OPERATION)

ALE

PMRD

PMWR

PIC24F

Address Bus

Data Bus

Control Lines

PMCS1

PMALL

AD<7:0>

Parallel Peripheral

PMD<7:0>

A<n:0>

D<7:0>

CE Address Bus

Data Bus

Control Lines

Para ll el EEPROM

PMA<n:0>

PMRD

PMWR

PIC24F

PMCS1

PMD<7:0>

A<n:1>

D<7:0>

CE Address Bus

Data Bus

Control Lines

Para ll el EEPROM

PMA<n:0>

PMRD

PMWR

PIC24F

PMCS1

PMD<7:0>

PMBE

D<7:0>

Address Bus

Data Bus

Control Lines

R/W

LCD Controller

PMRD/PMWR

PIC24F

PMA0

PMCS1

PM<7:0>

 2005-2012 Microchip Technology Inc. DS39747F-page 163

PIC24FJ128GA010 FAMILY

19.0 REAL-TIME CLOCK AND

CALENDAR (RTCC)

The Real-Time Clock and Calendar hardware module

has the following features:

• Time: Hours, Minutes and Seconds

• 24-Hour Format (Military Time)

• Calendar: Weekday, Date, Month and Year

• Alarm Configurable

• Year Range: 2000 to 2099

• Leap Year Correction

• BCD Format for Compact Firmware

• Optimized for Low-Power Operation

• User Calibration with Auto-Adjust

• Calibration Range: ±2.64 Seconds Error per

Month

• Requirements: External 32.768 kHz Clock Crystal

• Alarm Pulse or Seconds Clock Output on RTCC Pin

FIGURE 19-1: RTCC BLOCK DIAGRAM

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 29. “Real-Time

Clock and Calendar (RTCC)” (DS39696)

in the “PIC24F Family Reference Manual”

for more information.

RTCC Prescalers

RTCC Timer

Comparator

Compare Registers

Repeat Counter

YEAR

MTHDAY

WKDYHR

MINSEC

ALMTHDY

ALWDHR

ALMINSEC

with Masks

RTCC Interrupt Logic

RCFGCAL

ALCFGRPT

Alarm

Event

32.768 kHz Input

from SOSC Oscillator

0.5s

RTCC Clock Domain

Alarm Pulse

RTCC Interrupt

CPU Clock Domain

RTCVAL

ALRMVAL

RTCC Pin

RTCOE

PIC24FJ128GA010 FAMILY

DS39747F-page 164  2005-2012 Microchip Technology Inc.

19.1 RTCC Module Registers

The RTCC module registers are organized into three

categories:

• RTCC Control Registers

• RTCC Value Registers

• Alarm Value Registers

19.1.1 REGISTER MAPPING

To limit the register interface, the RTCC Timer and

Alarm Time registers are accessed through corre-

sponding register pointers. The RTCC Value register

window (RTCVALH and RTCVALL) uses the RTCPTR

bits (RCFGCAL<9:8>) to select the desired Timer

byte, the RTCC Pointer value, RTCPTR<1:0>, decre-

ments by one until it reaches ‘00’. Once it reaches ‘00’,

the MINUTES and SECONDS value will be accessible

through RTCVALH and RTCVALL until the pointer

value is manually changed.

TABLE 19-1: RTCVAL REGISTER MAPPING

The Alarm Value register window (ALRMVALH and

ALRMVALL) uses the ALRMPTR bits

(ALCFGRPT<9:8>) to select the desired Alarm register

pair (see Table 19-2).

By writing the ALRMVALH byte, the Alarm Pointer

value, ALRMPTR<1:0>, decrements by one until it

reaches ‘00’. Once it reaches ‘00’, the ALRMMIN and

ALRMSEC value will be accessible through

ALRMVALH and ALRMVALL until the pointer value is

manually changed.

TABLE 19-2: ALRMVAL REGISTER

MAPPING

Considering that the 16-bit core does not distinguish

between 8-bit and 16-bit read operations, the user must

be aware that when reading either the ALRMVALH or

ALRMVALL bytes it will decrement the ALRMPTR<1:0>

value. The same applies to the RTCVALH or RTCVALL

bytes with the RTCPTR<1:0> being decremented.

19.1.2 WRITE LOCK

In order to perform a write to any of the RTCC Timer

registers, the RTCWREN bit (RCFGCAL<13>) must be

set (refer to Example 19-1).

EXAMPLE 19-1: SETTING THE RTCWREN BIT IN MPLAB® C30

RTCPTR

<1:0>

RTCC Value Register Window

RTCVAL<15:8> RTCVAL<7:0>

00 MINUTES SECONDS

01 WEEKDAY HOURS

10 MONTH DAY

11 — YEAR

ALRMPTR

<1:0>

Alarm Value Register Window

ALRMVAL<15:8> ALRMVAL<7:0>

00 ALRMMIN ALRMSEC

01 ALRMWD ALRMHR

10 ALRMMNTH ALRMDAY

11 ——

Note: This only applies to read operations and

not write operations.

Note: To avoid accidental writes to the timer, it is recommended that the RTCWREN bit (RCFGCAL<13>) is kept

clear at any other time. For the RTCWREN bit to be set, there is only 1 instruction cycle time window allowed

between the 55h/AA sequence and the setting of RTCWREN; therefore, it is recommended that the code in

Example 19-1 be followed.

asm volatile("disi #13");

asm volatile("push W1");

asm volatile("push W2");

asm volatile("push W3");

asm volatile("MOV #NVMKEY, W1"); //move the address of NVMKEY into W1

asm volatile("MOV #0x55, W2");

asm volatile("MOV #0xAA, W3");

asm volatile("MOV W2, [W1]"); //start 55/AA sequence

NOP(); //There must be an instruction between the two writes ( either a NOP or a MOV to W)

asm volatile("MOV W3, [W1]");

asm volatile("BSET RCFGCAL, #13"); //set the RTCWREN bit

asm volatile("pop W3");

asm volatile("pop W2");

asm volatile("pop W1");

 2005-2012 Microchip Technology Inc. DS39747F-page 165

PIC24FJ128GA010 FAMILY

19.1.3 RTCC CONTROL REGISTERS

R/W-0 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0

RTCEN(2)— RTCWREN RTCSYNC HALFSEC(3)RTCOE RTCPTR1 RTCPTR0

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 RTCEN: RTCC Enable bit(2)

1 = RTCC module is enabled

0 = RTCC module is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 RTCWREN: RTCC Value Registers Write Enable bit

1 = RTCVALH and RTCVALL registers can be written to by the user

0 = RTCVALH and RTCVALL registers are locked out from being written to by the user

bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit

1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple

resulting in an invalid data read. If the register is read twice and results in the same data, the data can

be assumed to be valid.

0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple

bit 11 HALFSEC: Half-Second Status bit(3)

1 = Second half period of a second

0 = First half period of a second

bit 10 RTCOE: RTCC Output Enable bit

1 = RTCC output is enabled

0 = RTCC output is disabled

bit 9-8 RTCPTR<1:0>: RTCC Value Register Window Pointer bits

Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers;

the RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.

RTCVAL<15:8>:

00 = MINUTES

01 = WEEKDAY

10 =MONTH

11 = Reserved

RTCVAL<7:0>:

00 = SECONDS

01 = HOURS

10 =DAY

11 = YEAR

Note 1: The RCFGCAL Reset value is dependent on the type of Reset.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.

3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.

PIC24FJ128GA010 FAMILY

DS39747F-page 166  2005-2012 Microchip Technology Inc.

bit 7-0 CAL<7:0>: RTC Drift Calibration bits

01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute

...

01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute

00000000 = No adjustment

11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute

...

10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute

Note 1: The RCFGCAL Reset value is dependent on the type of Reset.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.

3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — RTSECSEL(1)PMPTTL(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-2 Unimplemented: Read as ‘0’

bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1)

1 = RTCC seconds clock is selected for the RTCC pin

0 = RTCC alarm pulse is selected for the RTCC pin

bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit(2)

1 = PMP module uses TTL input buffers

0 = PMP module uses Schmitt input buffers

Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit needs to be set.

2: Refer to Table 1-2 for affected PMP inputs.

 2005-2012 Microchip Technology Inc. DS39747F-page 167

PIC24FJ128GA010 FAMILY

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ALRMEN: Alarm Enable bit

1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00 and

CHIME = 0)

0 = Alarm is disabled

bit 14 CHIME: Chime Enable bit

1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh

0 = Chime is disabled; ARPT<7:0> bits stop once they reach 00h

bit 13-10 AMASK<3:0>: Alarm Mask Configuration bits

0000 = Every half second

0001 = Every second

0010 = Every 10 seconds

0011 = Every minute

0100 = Every 10 minutes

0101 = Every hour

0110 = Once a day

0111 = Once a week

1000 = Once a month

1001 = Once a year (except when configured for February 29th, once every 4 years)

101x = Reserved – do not use

11xx = Reserved – do not use

bit 9-8 ALRMPTR<1:0>: Alarm Value Register Window Pointer bits

Points to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers;

the ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’.

ALRMVAL<15:8>:

00 = ALRMMIN

01 =ALRMWD

10 = ALRMMNTH

11 = Unimplemented

ALRMVAL<7:0>:

00 = ALRMSEC

01 =ALRMHR

10 =ALRMDAY

11 = Unimplemented

bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits

11111111 = Alarm will repeat 255 more times

...

00000000 = Alarm will not repeat

The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh

unless CHIME = 1.

PIC24FJ128GA010 FAMILY

DS39747F-page 168  2005-2012 Microchip Technology Inc.

19.1.4 RTCVAL REGISTER MAPPINGS

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’

bit 7-4 YRTEN<3:0:> Binary Coded Decimal Value of Year’s Tens Digit; Contains a value from 0 to 9

bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit; Contains a value from 0 to 9

Note 1: A write to the YEAR register is only allowed when RTCWREN = 1.

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0

bit 15 bit 8

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

—— DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; Contains a value of 0 or 1

bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit; Contains a value from 0 to 9

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit; Contains a value from 0 to 3

bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit; Contains a value from 0 to 9

Note 1: A write to this register is only allowed when RTCWREN = 1.

 2005-2012 Microchip Technology Inc. DS39747F-page 169

PIC24FJ128GA010 FAMILY

U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x

— — — — — WDAY2 WDAY1 WDAY0

bit 15 bit 8

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

—— HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit; Contains a value from 0 to 6

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit; Contains a value from 0 to 2

bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit; Contains a value from 0 to 9

Note 1: A write to this register is only allowed when RTCWREN = 1.

U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0

bit 15 bit 8

U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit; Contains a value from 0 to 5

bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit; Contains a value from 0 to 9

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit; Contains a value from 0 to 5

bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit; Contains a value from 0 to 9

PIC24FJ128GA010 FAMILY

DS39747F-page 170  2005-2012 Microchip Technology Inc.

19.1.5 ALRMVAL REGISTER MAPPINGS

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0

bit 15 bit 8

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

—— DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; Contains a value of 0 or 1

bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit; Contains a value from 0 to 9

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit; Contains a value from 0 to 3

bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit; Contains a value from 0 to 9

Note 1: A write to this register is only allowed when RTCWREN = 1.

U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x

— — — — — WDAY2 WDAY1 WDAY0

bit 15 bit 8

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

—— HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit; Contains a value from 0 to 6

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit; Contains a value from 0 to 2

bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit; Contains a value from 0 to 9

Note 1: A write to this register is only allowed when RTCWREN = 1.

 2005-2012 Microchip Technology Inc. DS39747F-page 171

PIC24FJ128GA010 FAMILY

U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0

bit 15 bit 8

U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit; Contains a value from 0 to 5

bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit; Contains a value from 0 to 9

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit; Contains a value from 0 to 5

bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit; Contains a value from 0 to 9

PIC24FJ128GA010 FAMILY

DS39747F-page 172  2005-2012 Microchip Technology Inc.

19.2 Calibration

The real-time crystal input can be calibrated using the

periodic auto-adjust feature. When properly calibrated,

the RTCC can provide an error of less than 3 seconds

per month. This is accomplished by finding the number

of error clock pulses and storing the value into the

lower half of the RCFGCAL register. The 8-bit signed

value loaded into the lower half of RCFGCAL is multi-

plied by four and will either be added or subtracted from

the RTCC timer, once every minute. Refer to the steps

below for RTCC calibration:

1. Using another timer resource on the device, the

user must find the error of the 32.768 kHz

crystal.

2. Once the error is known, it must be converted to

the number of error clock pulses per minute.

EQUATION 19-1:

3. a) If the oscillator is faster then ideal (negative

result form Step 2), the RCFGCAL register value

needs to be negative. This causes the specified

number of clock pulses to be subtracted from

the timer counter, once every minute.

b) If the oscillator is slower then ideal (positive

result from Step 2), the RCFGCAL register value

needs to be positive. This causes the specified

number of clock pulses to be subtracted from

the timer counter, once every minute.

4. Divide the number of error clocks per minute by

4 to get the correct CAL value and load the

RCFGCAL register with the correct value. (Each

1-bit increment in CAL adds or subtracts

4 pulses). Load the RCFGCAL register with the

correct value.

Writes to the lower half of the RCFGCAL register

should only occur when the timer is turned off or

immediately after the rising edge of the seconds pulse.

19.3 Alarm

• Configurable from half second to one year

• Enabled using the ALRMEN bit

(ALCFGRPT<15>, Register 19-3)

• One-time alarm and repeat alarm options are

available

19.3.1 CONFIGURING THE ALARM

The alarm feature is enabled using the ALRMEN bit.

This bit is cleared when an alarm is issued. Writes to

ALRMVALH:ALRMVALL should only take place when

ALRMEN = 0.

As shown in Figure 19-2, the interval selection of the

alarm is configured through the AMASK bits

(ALCFGRPT<13:10>). These bits determine which and

how many digits of the alarm must match the clock value

for the alarm to occur. The alarm can also be configured

to repeat, based on a preconfigured interval. The

amount of times this occurs, once the alarm is enabled,

is stored in the lower half of the ALCFGRPT register.

When ALCFGRPT = 00 and the CHIME

(ALCFGRPT<14>) bit = 0, the repeat function is

disabled and only a single alarm will occur. The alarm

can be repeated up to 255 times by loading the lower

half of the ALCFGRPT register with FFh.

After each alarm is issued, the ALCFGRPT register is

decremented by one. Once the register has reached

‘00’, the alarm will be issued one last time, after which,

the ALRMEN bit will be cleared automatically and the

alarm will turn off. Indefinite repetition of the alarm can

occur if the CHIME bit = 1. Instead of the alarm being

disabled when the ALCFGRPT register reaches ‘00’, it

will roll over to FF and continue counting indefinitely

when CHIME = 1.

19.3.2 ALARM INTERRUPT

At every alarm event an interrupt is generated. In addi-

tion, an alarm pulse output is provided that operates at

half the frequency of the alarm. This output is

completely synchronous to the RTCC clock and can be

used as a trigger clock to other peripherals.

Note: It is up to the user to include in the error

value, the initial error of the crystal drift

due to temperature and drift due to crystal

aging.

(Ideal Freq uency

†

– Measured Frequ ency) * 60 = Clocks per Minute

† Ideal Frequency = 32,768 Hz

Note: Changing any of the registers, other then

the RCFGCAL and ALCFGRPT registers,

and the CHIME bit while the alarm is

enabled (ALRMEN = 1), can result in a

false alarm event leading to a false alarm

interrupt. To avoid a false alarm event, the

timer and alarm values should only be

changed while the alarm is disabled

(ALRMEN = 0). It is recommended that

the ALCFGRPT register and CHIME bit be

changed when RTCSYNC = 0.

 2005-2012 Microchip Technology Inc. DS39747F-page 173

PIC24FJ128GA010 FAMILY

FIGURE 19-2: ALARM MASK SETTINGS

Note 1: Annually, except when configured for February 29.

mss

mm s s

hh mm ss

dhhmmss

dd hh mm ss

mm d d h h mm s s

Day of

the

Week Month Day Hours Minutes Seconds

Alarm Mask Setting

(AMASK<3:0>)

0000 – Every half second

0001 – Every second

0010 – Every 10 seconds

0011 – Every minute

0100 – Every 10 minutes

0101 – Every hour

0110 – Every day

0111 – Every week

1000 – Every month

1001 – Every year(1)

PIC24FJ128GA010 FAMILY

DS39747F-page 174  2005-2012 Microchip Technology Inc.

NOTES:

 2005-2012 Microchip Technology Inc. DS39747F-page 175

PIC24FJ128GA010 FAMILY

20.0 PROGRAMMABLE CYCLIC

REDUNDANCY CHECK (CRC)

GENERATOR

The programmable CRC generator offers the following

features:

• User-programmable polynomial CRC equation

• Interrupt output

• Data FIFO

20.1 Registers

There are four registers used to control programmable

CRC operation:

• CRCCON

• CRCXOR

• CRCDAT

• CRCWDAT

20.2 Overview

The module implements a software configurable CRC

generator. The terms of the polynomial and its length

can be programmed using the CRCXOR (X<15:1>) bits

and the CRCCON (PLEN<3:0>) bits, respectively.

Consider the following equation:

EQUATION 20-1: CRC POLYNOMIAL

To program this polynomial into the CRC generator,

the CRC register bits should be set, as shown in

Table 20-1.

TABLE 20-1: EXAMPLE CRC SETUP

Note that for the value of X<15:1>, the 12th bit and the

5th bit are set to ‘1’, as required by the equation. The

0 bit, required by the equation, is always XORed. For a

16-bit polynomial, the 16th bit is also always assumed to

be XORed; therefore, the X<15:1> bits do not have the

0 bit or the 16th bit.

The topology of a standard CRC generator is shown in

Figure 20-2.

FIGURE 20-1: CRC SHIFTER DETAILS

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 30. “Program-

mable Cyclic Redundancy Check

(CRC)” (DS39714) in the “PIC24F Family

Reference Manual” for more information.

Bit Name Bit Va lue

PLEN<3:0> 1111

X<15:1> 000100000010000

x16 + x12 + x5 + 1

OUT

BIT 0

p_clk

OUT

BIT 1

p_clk

OUT

BIT 2

p_clk

OUT

BIT 15

p_clk

X15

XOR

DOUT

01 2 15

PLEN<3:0>

Hold Hold Hold Hold

CRC Read Bus

CRC Write Bus

CRC Shift Register

PIC24FJ128GA010 FAMILY

DS39747F-page 176  2005-2012 Microchip Technology Inc.

FIGURE 20-2: CRC GENERATOR RECONFIGURED FOR x16 + x12 + x5 + 1

20.3 User Interface

20.3.1 DATA INTERFACE

To start serial shifting, a ‘1’ must be written to the

CRCGO bit.

The module incorporates a FIFO that is 8-deep when

PLEN<3:0> (CRCCON<3:0>) > 7 and 16-deep other-

wise. The data for which the CRC is to be calculated

must first be written into the FIFO. The smallest data

element that can be written into the FIFO is one byte.

For example, if PLEN = 5, then the size of the data is

PLEN + 1 = 6. The data must be written as follows:

data[5:0] = crc_input[5:0]

data[7:6] = ‘bxx

Once data is written into the CRCWDAT MSb (as

defined by PLEN), the value of the VWORD<4:0> bits

(CRCCON<12:8>) increment by one. The serial shifter

starts shifting data into the CRC engine when

CRCGO = 1 and VWORD > 0. When the MSb is

shifted out, VWORD decrements by one. The serial

shifter continues shifting until the VWORD reaches 0.

Therefore, for a given value of PLEN, it will take

(PLEN<3:0> + 1)/2 x VWORD number of clock cycles

to complete the CRC calculations.

When VWORD reaches 8 (or 16), the CRCFUL bit will

be set. When VWORD reaches 0, the CRCMPT bit will

be set.

To continually feed data into the CRC engine, the rec-

ommended mode of operation is to initially “prime” the

FIFO with a sufficient number of words, so no interrupt

is generated before the next word can be written. Once

that is done, start the CRC by setting the CRCGO bit to

‘1’. From that point onward, the VWORD bits should be

polled. If they read less than 8 or 16, another word can

be written into the FIFO.

To empty words already written into a FIFO, the

CRCGO bit must be set to ‘1’ and the CRC shifter

allowed to run until the CRCMPT bit is set.

Also, to get the correct CRC reading, it will be

necessary to wait for the CRCMPT bit to go high before

reading the CRCWDAT register.

If a word is written when the CRCFUL bit is set, the

VWORD Pointer will roll over to 0. The hardware will

then behave as if the FIFO is empty. However, the con-

dition to generate an interrupt will not be met; therefore,

no interrupt will be generated (see Section 20.3.2

“Interrupt Operation”).

At least one instruction cycle must pass after a write to

CRCWDAT before a read of the VWORD bits is done.

20.3.2 INTERRUPT OPERATION

When VWORD<4:0> make a transition from a value of

‘1’ to ‘0’, an interrupt will be generated.

BIT 0

p_clk

BIT 4

p_clk

BIT 5

p_clk

BIT 12

p_clk

XOR

SDOx

CRC Read Bus

CRC Write Bus

BIT 15

p_clk

 2005-2012 Microchip Technology Inc. DS39747F-page 177

PIC24FJ128GA010 FAMILY

20.4 Operation in Power Save Modes

20.4.1 SLEEP MODE

If Sleep mode is entered while the module is operating,

the module will be suspended in its current state until

clock execution resumes.

20.4.2 IDLE MODE

To continue full module operation in Idle mode, the

CSIDL bit must be cleared prior to entry into the mode.

If CSIDL = 1, the module will behave the same way as

it does in Sleep mode. Pending interrupt events will be

passed on, even though the module clocks are not

available.

U-0 U-0 R/W-0 R-0 R-0 R-0 R-0 R-0

—— CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0

bit 15 bit 8

R-0 R-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CRCFUL CRCMPT — CRCGO PLEN3 PLEN2 PLEN1 PLEN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 CSIDL: CRC Stop in Idle Mode bit

1 = Discontinues module operation when the device enters Idle mode

0 = Continues module operation in Idle mode

bit 12-8 VWORD<4:0>: Pointer Value bits

Indicates the number of valid words in the FIFO. It has a maximum value of 8 when PLEN<3:0> > 7

or 16 when PLEN<3:0> 7.

bit 7 CRCFUL: FIFO Full bit

1 = FIFO is full

0 = FIFO is not full

bit 6 CRCMPT: FIFO Empty bit

1 = FIFO is empty

0 = FIFO is not empty

bit 5 Unimplemented: Read as ‘0’

bit 4 CRCGO: Start CRC bit

1 = Starts CRC serial shifter

0 = CRC serial shifter is turned off

bit 3-0 PLEN<3:0>: Polynomial Length bits

Denotes the length of the polynomial to be generated minus 1.

PIC24FJ128GA010 FAMILY

DS39747F-page 178  2005-2012 Microchip Technology Inc.

NOTES:

 2005-2012 Microchip Technology Inc. DS39747F-page 179

PIC24FJ128GA010 FAMILY

21.0 10-BIT HIGH-SPEED A/D

CONVERTER

The 10-bit A/D Converter has the following key

features:

• Successive Approximation (SAR) conversion

• Conversion speeds of up to 500 ksps

• Up to 16 analog input pins

• External voltage reference input pins

• Automatic Channel Scan mode

• Selectable conversion trigger source

• 16-word conversion result buffer

• Selectable Buffer Fill modes

• Four result alignment options

• Operation during CPU Sleep and Idle modes

Depending on the particular device pinout, the 10-bit

A/D Converter can have up to 16 analog input pins,

designated AN0 through AN15. In addition, there are

two analog input pins for external voltage reference

connections. These voltage reference inputs may be

shared with other analog input pins. The actual number

of analog input pins and external voltage reference

input configuration will depend on the device. Refer to

the specific device data sheet for further details.

A block diagram of the A/D Converter is shown in

Figure 21-1.

To perform an A/D conversion:

1. Configure the A/D module:

a) Select the port pins as analog inputs

(AD1PCFG<15:0>).

b) Select a voltage reference source to match

the expected range on the analog inputs

(AD1CON2<15:13>).

c) Select the analog conversion clock to match

the desired data rate with the processor clock

(AD1CON3<7:0>).

d) Select the appropriate sample/conver-

sion sequence (AD1CON1<7:0> and

AD1CON3<12:8>).

e) Select how conversion results are

presented in the buffer (AD1CON1<9:8>).

f) Select the interrupt rate (AD1CON2<5:2>).

g) Turn on the A/D module (AD1CON1<15>).

2. Configure the A/D interrupt (if required):

a) Clear the AD1IF bit.

b) Select the A/D interrupt priority.

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 17. “10-Bit A/D

Converter” (DS39705) in the “PIC24F

Family Reference Manual” for more

information.

Note: A/D results should be read with the ADON

bit = 1. If the A/D is disabled before

reading the buffer, it is possible to lose

data.

PIC24FJ128GA010 FAMILY

DS39747F-page 180  2005-2012 Microchip Technology Inc.

Figure 21-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM

Comparator

10-Bit SAR Conversion Logic

VREF+

DAC

AN12

AN13

AN14

AN15

AN8

AN9

AN10

AN11

AN4

AN5

AN6

AN7

AN0

AN1

AN2

AN3

VREF-

Sample Control

S/H

AVSS

AVDD

ADC1BUF0:

ADC1BUFF

AD1CON1

AD1CON2

AD1CON3

AD1CHS

AD1PCFG

AD1CSSL

Control Logic

Data Formatting

Input MUX Control

Conversion Control

Pin Config. Control

Internal Data Bus

VR+VR-

MUX A

MUX B

VINH

VINL

VINH

VINL

VR+

VR-

VR Select

 2005-2012 Microchip Technology Inc. DS39747F-page 181

PIC24FJ128GA010 FAMILY

R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

ADON(1)—ADSIDL— — —FORM1FORM0

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0, HCS R/C-0, HCS

SSRC2 SSRC1 SSRC0 —— ASAM SAMP DONE

bit 7 bit 0

Legend: C = Clearable bit HCS = Hardware Clearable/Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ADON: A/D Operating Mode bit(1)

1 = A/D Converter module is operating

0 = A/D Converter is off

bit 14 Unimplemented: Read as ‘0’

bit 13 ADSIDL: Stop in Idle Mode bit

1 = Discontinues module operation when the device enters Idle mode

0 = Continues module operation in Idle mode

bit 12-10 Unimplemented: Read as ‘0’

bit 9-8 FORM<1:0>: Data Output Format bits

11 = Signed fractional (sddd dddd dd00 0000)

10 = Fractional (dddd dddd dd00 0000)

01 = Signed integer (ssss sssd dddd dddd)

00 = Integer (0000 00dd dddd dddd)

bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits

111 = Internal counter ends sampling and starts conversion (auto-convert)

110 = Reserved

10x = Reserved

011 = Reserved

010 = Timer3 compare ends sampling and starts conversion

001 = Active transition on the INT0 pin ends sampling and starts conversion

000 = Clearing the SAMP bit ends sampling and starts conversion

bit 4-3 Unimplemented: Read as ‘0’

bit 2 ASAM: A/D Sample Auto-Start bit

1 = Sampling begins immediately after the last conversion completes; SAMP bit is auto-set

0 = Sampling begins when the SAMP bit is set

bit 1 SAMP: A/D Sample Enable bit

1 = A/D Sample-and-Hold amplifier is sampling input

0 = A/D Sample-and-Hold amplifier is holding

bit 0 DONE: A/D Conversion Status bit

1 = A/D conversion is done

0 = A/D conversion is NOT done

Note 1: The values of the ADC1BUFx registers will not retain their values once the ADON bit is cleared. Read out

the conversion values from the buffer before disabling the module.

PIC24FJ128GA010 FAMILY

DS39747F-page 182  2005-2012 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0

VCFG2 VCFG1 VCFG0 r— CSCNA — —

bit 15 bit 8

R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS

bit 7 bit 0

Legend: r = Reserved bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits:

bit 12 Reserved

bit 11 Unimplemented: Read as ‘0’

bit 10 CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexor Setting bit

1 = Scan inputs

0 = Do not scan inputs

bit 9-8 Unimplemented: Read as ‘0’

bit 7 BUFS: Buffer Fill Status bit (valid only when BUFM = 1)

1 = A/D is currently filling Buffer 08-0F, user should access data in 00-07

0 = A/D is currently filling Buffer 00-07, user should access data in 08-0F

bit 6 Unimplemented: Read as ‘0’

bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits

1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence

1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence

.....

0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence

0000 = Interrupts at the completion of conversion for each sample/convert sequence

bit 1 BUFM: Buffer Mode Select bit

1 = Buffer configured as two 8-word buffers (ADC1BUFx<15:8> and ADC1BUFx<7:0>)

0 = Buffer configured as one 16-word buffer (ADC1BUFx<15:0>)

bit 0 ALTS: Alternate Input Sample Mode Select bit

1 = Uses MUX A input multiplexor settings for the first sample, then alternates between the MUX B and

MUX A input multiplexor settings for all subsequent samples

0 = Always uses MUX A input multiplexor settings

VCFG<2:0> VR+VR-

000 AVDD AVSS

001 External VREF+ pin AVSS

010 AVDD External VREF- pin

011 External VREF+ pin External VREF- pin

1xx AVDD AVSS

 2005-2012 Microchip Technology Inc. DS39747F-page 183

PIC24FJ128GA010 FAMILY

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADRC —— SAMC4 SAMC3 SAMC2 SAMC1 SAMC0

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ADRC: A/D Conversion Clock Source bit

1 = A/D internal RC clock

0 = Clock is derived from the system clock

bit 14-13 Unimplemented: Read as ‘0’

bit 12-8 SAMC<4:0>: Auto-Sample Time bits

11111 = 31 TAD

·····

00001 = 1 TAD

00000 = 0 TAD (not recommended)

bit 7-0 ADCS<7:0:> A/D Conversion Clock Select bits

11111111

····· = Reserved

01000000

00111111 = 64 * TCY

·····

00000001 = 2 * TCY

00000000 = TCY

PIC24FJ128GA010 FAMILY

DS39747F-page 184  2005-2012 Microchip Technology Inc.

R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

CH0NB — — — CH0SB3 CH0SB2 CH0SB1 CH0SB0

bit 15 bit 8

R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

CH0NA — — — CH0SA3 CH0SA2 CH0SA1 CH0SA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexor Setting bit

1 = Channel 0 negative input is AN1

0 = Channel 0 negative input is VR-

bit 14-12 Unimplemented: Read as ‘0’

bit 11-8 CH0SB<3:0>: Channel 0 Positive Input Select for MUX B Multiplexor Setting bits

1111 = Channel 0 positive input is AN15

1110 = Channel 0 positive input is AN14

·····

0001 = Channel 0 positive input is AN1

0000 = Channel 0 positive input is AN0

bit 7 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexor Setting bit

1 = Channel 0 negative input is AN1

0 = Channel 0 negative input is VR-

bit 6-4 Unimplemented: Read as ‘0’

bit 3-0 CH0SA<3:0>: Channel 0 Positive Input Select for MUX A Multiplexor Setting bits

1111 = Channel 0 positive input is AN15

1110 = Channel 0 positive input is AN14

·····

0001 = Channel 0 positive input is AN1

0000 = Channel 0 positive input is AN0

 2005-2012 Microchip Technology Inc. DS39747F-page 185

PIC24FJ128GA010 FAMILY

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 PCFG<15:0>: Analog Input Pin Configuration Control bits

1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read is enabled

0 = Pin configured in Analog mode; I/O port read is disabled, A/D samples pin voltage

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 CSSL<15:0>: A/D Input Pin Scan Selection bits

1 = Corresponding analog channel is selected for input scan

0 = Analog channel is omitted from input scan

PIC24FJ128GA010 FAMILY

DS39747F-page 186  2005-2012 Microchip Technology Inc.

EQUATION 21-1: A/D CONVERSION CLOCK PERIOD(1)

FIGURE 21-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL

TAD = TCY(ADCS + 1)

ADCS = TAD

TCY – 1

Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled.

CPIN

Rs ANx VT = 0.6V

VT = 0.6V ILEAKAGE

RIC  250Sampling

Switch

RSS

CHOLD

= DAC Capacitance

VSS

VDD

= 4.4 pF (Typical)

500 nA

Legend: CPIN

ILEAKAGE

RIC

RSS

CHOLD

= Input Capacitance

= Threshold Voltage

= Leakage Current at the pin due to

= Interconnect Resistance

= Sampling Switch Resistance

= Sample/Hold Capacitance (from DAC)

various junctions

Note: CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs  5 k.

RSS  5 k(Typical)

6-11 pF

(Typical)

 2005-2012 Microchip Technology Inc. DS39747F-page 187

PIC24FJ128GA010 FAMILY

FIGURE 21-3: A/D TRANSFER FUNCTION

10 0000 0001 (513)

10 0000 0010 (514)

10 0000 0011 (515)

01 1111 1101 (509)

01 1111 1110 (510)

01 1111 1111 (511)

11 1111 1110 (1022)

11 1111 1111 (1023)

00 0000 0000 (0)

00 0000 0001 (1)

Output Code

10 0000 0000 (512)

(VINH – VINL)

VR-

VR+ – VR-

1024

512*(VR+ – VR-)

1024

VR+

VR- +

1023*(VR+ – VR-)

1024

VR- +

(Binary (Decimal))

Voltage Le vel

PIC24FJ128GA010 FAMILY

DS39747F-page 188  2005-2012 Microchip Technology Inc.

NOTES:

 2005-2012 Microchip Technology Inc. DS39747F-page 189

PIC24FJ128GA010 FAMILY

22.0 COMPARATOR MODULE The analog comparator module contains two

comparators that can be configured in a variety of

ways. The inputs can be selected from the analog

inputs, multiplexed with I/O pins, as well as the on-chip

voltage reference. Block diagrams of the various

comparator configurations are shown in Figure 22-1.

FIGURE 22-1: COMPARATOR I/O OPERATING MODES

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 19. “Comparator

Module” (DS39710) in the “PIC24F Family

Reference Manual” for more information.

C2IN- VIN-

VIN+

C2IN+

CVREF

C2IN+

C2OUT

CMCON<7>

C1IN- VIN-

VIN+

C1IN+

CVREF

C1IN+

C1OUT

CMCON<6>

C1NEG

C1POS

C2NEG

C2POS

C1INV

C2INV

C1OUTEN

C2OUTEN

C1EN

C2EN

PIC24FJ128GA010 FAMILY

DS39747F-page 190  2005-2012 Microchip Technology Inc.

R/W-0 U-0 R/C-0 R/C-0 R/W-0 R/W-0 R/W-0 R/W-0

CMIDL — C2EVT C1EVT C2EN C1EN C2OUTEN C1OUTEN

bit 15 bit 8

R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

C2OUT C1OUT C2INV C1INV C2NEG C2POS C1NEG C1POS

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CMIDL: Stop in Idle Mode bit

1 = When the device enters Idle mode, the module does not generate interrupts; module is still enabled

0 = Continues normal module operation in Idle mode

bit 14 Unimplemented: Read as ‘0’

bit 13 C2EVT: Comparator 2 Event bit

1 = Comparator output changed states

0 = Comparator output did not change states

bit 12 C1EVT: Comparator 1 Event bit

1 = Comparator output changed states

0 = Comparator output did not change states

bit 11 C2EN: Comparator 2 Enable bit

1 = Comparator is enabled

0 = Comparator is disabled

bit 10 C1EN: Comparator 1 Enable bit

1 = Comparator is enabled

0 = Comparator is disabled

bit 9 C2OUTEN: Comparator 2 Output Enable bit

1 = Comparator output is driven on the output pad

0 = Comparator output is not driven on the output pad

bit 8 C1OUTEN: Comparator 1 Output Enable bit

1 = Comparator output is driven on the output pad

0 = Comparator output is not driven on the output pad

bit 7 C2OUT: Comparator 2 Output bit

When C2INV = 0:

1 =C2 VIN+ > C2 VIN-

0 =C2 V

IN+ < C2 VIN-

When C2INV = 1:

0 =C2 VIN+ > C2 VIN-

1 =C2 V

IN+ < C2 VIN-

bit 6 C1OUT: Comparator 1 Output bit

When C1INV = 0:

1 =C1 VIN+ > C1 VIN-

0 =C1 V

IN+ < C1 VIN-

When C1INV = 1:

0 =C1 VIN+ > C1 VIN-

1 =C1 V

IN+ < C1 VIN-

 2005-2012 Microchip Technology Inc. DS39747F-page 191

PIC24FJ128GA010 FAMILY

bit 5 C2INV: Comparator 2 Output Inversion bit

1 = C2 output is inverted

0 = C2 output is not inverted

bit 4 C1INV: Comparator 1 Output Inversion bit

1 = C1 output is inverted

0 = C1 output is not inverted

bit 3 C2NEG: Comparator 2 Negative Input Configure bit

1 = C2IN+ is connected to VIN-

0 = C2IN- is connected to VIN-

See Figure 22-1 for the Comparator modes.

bit 2 C2POS: Comparator 2 Positive Input Configure bit

1 = C2IN+ is connected to VIN+

0 =CV

REF is connected to VIN+

See Figure 22-1 for the Comparator modes.

bit 1 C1NEG: Comparator 1 Negative Input Configure bit

1 = C1IN+ is connected to VIN-

0 = C1IN- is connected to VIN-

See Figure 22-1 for the Comparator modes.

bit 0 C1POS: Comparator 1 Positive Input Configure bit

1 = C1IN is connected to VIN+

0 =CV

REF is connected to VIN+

See Figure 22-1 for the Comparator modes.

PIC24FJ128GA010 FAMILY

DS39747F-page 192  2005-2012 Microchip Technology Inc.

NOTES:

 2005-2012 Microchip Technology Inc. DS39747F-page 193

PIC24FJ128GA010 FAMILY

23.0 COMPARATOR VO LTAGE

REFERENCE

23.1 Configuring the Comparator

Voltage Reference

The voltage reference module is controlled through the

CVRCON register (Register 23-1). The comparator

voltage reference provides two ranges of output

voltage, each with 16 distinct levels. The range to be

used is selected by the CVRR bit (CVRCON<5>). The

primary difference between the ranges is the size of the

steps selected by the CVREF Selection bits

(CVR<3:0>), with one range offering finer resolution.

The comparator reference supply voltage can come

from either VDD and VSS, or the external VREF+ and

VREF-. The voltage source is selected by the CVRSS

bit (CVRCON<4>).

The settling time of the comparator voltage reference

must be considered when changing the CVREF

output.

CVRR: Comparator VREF Range Selection bit 1 = 0

to 0.625 CVRSRC, with CVRSRC/24 step size.

0 = 0.25 CVRSRC to 0.72 CVRSRC, with CVRSRC/32

step size

FIGURE 23-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

Note: This data sheet summarizes features of

PIC24F group of devices and is not

intended to be a comprehensive reference

source. Refer to Section 20. “Comparator

Voltage Reference Module” (DS39709)

in the “PIC24F Family Reference Manual”

for more information.

16-to-1 MUX

CVR<3:0>

CVREN

CVRSS = 0

AVDD

VREF+CVRSS = 1

CVRSS = 0

VREF-CVRSS = 1

16 Steps

CVRR

CVREF

AVSS

PIC24FJ128GA010 FAMILY

DS39747F-page 194  2005-2012 Microchip Technology Inc.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’

bit 7 CVREN: Comparator Voltage Reference Enable bit

1 =CV

REF circuit is powered on

0 =CV

REF circuit is powered down

bit 6 CVROE: Comparator VREF Output Enable bit

1 =CVREF voltage level is output on the CVREF pin

0 =CV

REF voltage level is disconnected from the CVREF pin

bit 5 CVRR: Comparator VREF Range Selection bit

1 = 0 to 0.625 CVRSRC, with CVRSRC/24 step size

0 = 0.25 CVRSRC to 0.72 CVRSRC, with CVRSRC/32 step size

bit 4 CVRSS: Comparator VREF Source Selection bit

1 = Comparator reference source: CVRSRC = VREF+ – VREF-

0 = Comparator reference source: CVRSRC = AVDD – AVSS

bit 3-0 CVR<3:0>: Comparator VREF Value Selection 0  CVR<3:0>  15 bits

When CVRR = 1:

CVREF = (CVR<3:0>/ 24)  (CVRSRC)

When CVRR = 0:

CVREF = 1/4  (CVRSRC) + (CVR<3:0>/32)  (CVRSRC)

 2005-2012 Microchip Technology Inc. DS39747F-page 195

PIC24FJ128GA010 FAMILY

24.0 SPECIAL FEATURES

PIC24FJ128GA010 devices include several features

intended to maximize application flexibility and reliabil-

ity, and minimize cost through elimination of external

components. These are:

• Flexible Configuration

• Watchdog Timer (WDT)

• Code Protection

• JTAG Boundary Scan Interface

• In-Circuit Serial Programming™ (ICSP™)

• In-Circuit Emulation

24.1 Configur ation Bits

The Configuration bits can be programmed (read as

‘0’) or left unprogrammed (read as ‘1’) to select various

device configurations. These bits are mapped, starting

at program memory location, F80000h. A complete list

is shown in Table 24-1. A detailed explanation of the

various bit functions is provided in Register 24-1

through Register 24-4.

Note that address, F80000h, is beyond the user program

memory space. In fact, it belongs to the configuration

memory space (800000h-FFFFFFh), which can only be

accessed using table reads and table writes.

24.1.1 CONSIDERATIONS FOR

CONFIGURING PIC24FJ128GA010

FAMILY DEVICES

In PIC24FJ128GA010 family devices, the configuration

bytes are implemented as volatile memory. This means

that configuration data must be programmed each time

the device is powered up. Configuration data is stored

in the two words at the top of the on-chip program

memory space, known as the Flash Configuration

Words. Their specific locations are shown in

Table 24-1. These are packed representations of the

actual device Configuration bits, whose actual

locations are distributed among five locations in config-

uration space. The configuration data is automatically

loaded from the Flash Configuration Words to the

proper Configuration registers during device Resets.

TABLE 24-1: FLASH CONFIGURATION

WORD LOCATIONS

When creating applications for these devices, users

should always specifically allocate the location of the

Flash Configuration Word for configuration data. This is

to make certain that program code is not stored in this

address when the code is compiled.

The Configuration bits are reloaded from the Flash

Configuration Word on any device Reset.

The upper byte of both Flash Configuration Words in

program memory should always be ‘1111 1111 ’. This

makes them appear to be NOP instructions in the

remote event that their locations are ever executed by

accident. Since Configuration bits are not implemented

in the corresponding locations, writing ‘1’s to these

locations has no effect on device operation.

Note: This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive refer-

ence source. Refer to Section 32.

“High-Level Device Integration”

(DS39719) in the “PIC24F Family

Reference Ma nual” for more information.

Note: Configuration data is reloaded on all types

of device Resets.

Device

Configuration Word

Addresses

PIC24FJ64GA 00ABFEh 00ABFCh

PIC24FJ96GA 00FFFEh 00FFFCh

PIC24FJ128GA 0157FEh 0157FCh

PIC24FJ128GA010 FAMILY

DS39747F-page 196  2005-2012 Microchip Technology Inc.

U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1

— — — — — — — —

bit 23 bit 16

r-x R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 U-1 R/PO-1

rJTAGEN

(1)GCP GWRP DEBUG r—ICS

bit 15 bit 8

R/PO-1 R/PO-1 U-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1

FWDTEN WINDIS — FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0

bit 7 bit 0

Legend: x = Bit is unknown r = Reserved

R = Readable bit PO = Program Once bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 23-16 Unimplemented: Read as ‘1’

bit 15 Reserved: Program as ‘0’. Read value is unknown.

bit 14 JTAGEN: JTAG Port Enable bit(1)

1 = JTAG port is enabled

0 = JTAG port is disabled

bit 13 GCP: General Segment Program Memory Code Protection bit

1 = Code protection is disabled

0 = Code protection is enabled for the entire program memory space

bit 12 GWRP: General Segment Code Flash Write Protection bit

1 = Writes to program memory are allowed

0 = Writes to program memory are disabled

bit 11 DEBUG: Background Debugger Enable bit

1 = Device resets into Operational mode

0 = Device resets into Debug mode

bit 10 Reserved: Program as ‘1’

bit 9 Unimplemented: Read as ‘1’

bit 8 ICS: Emulator Pin Placement Select bit

1 = Emulator/debugger uses EMUC2/EMUD2

0 = Emulator/debugger uses EMUC1/EMUD1

bit 7 FWDTEN: Watchdog Timer Enable bit

1 = Watchdog Timer is enabled

0 = Watchdog Timer is disabled

bit 6 WINDIS: Windowed Watchdog Timer Disable bit

1 = Standard Watchdog Timer is enabled

0 = Windowed Watchdog Timer is enabled; FWDTEN must be ‘1’

bit 5 Unimplemented: Read as ‘1’

bit 4 FWPSA: WDT Prescaler Ratio Select bit

1 = Prescaler ratio of 1:128

0 = Prescaler ratio of 1:32

Note 1: JTAGEN bit can not be modified using JTAG programming. It can only change using In-Circuit Serial

Programming™ (ICSP™).

 2005-2012 Microchip Technology Inc. DS39747F-page 197

PIC24FJ128GA010 FAMILY

bit 3-0 WDTPS<3:0>: Watchdog Timer Postscaler Select bits

1111 = 1:32,768

1110 = 1:16,384

1101 = 1:8,192

1100 = 1:4,096

1011 = 1:2,048

1010 = 1:1,024

1001 = 1:512

1000 = 1:256

0111 = 1:128

0110 = 1:64

0101 = 1:32

0100 = 1:16

0011 = 1:8

0010 = 1:4

0001 = 1:2

0000 = 1:1

Note 1: JTAGEN bit can not be modified using JTAG programming. It can only change using In-Circuit Serial

Programming™ (ICSP™).

PIC24FJ128GA010 FAMILY

DS39747F-page 198  2005-2012 Microchip Technology Inc.

U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1

— — — — — — — —

bit 23 bit 16

R/PO-1 U-1 U-1 U-1 U-1 R/PO-1 R/PO-1 R/PO-1

IESO — — — — FNOSC2 FNOSC1 FNOSC0

bit 15 bit 8

R/PO-1 R/PO-1 R/PO-1 U-1 U-1 U-1 R/PO-1 R/PO-1

FCKSM1 FCKSM0 OSCIOFCN — — — POSCMD1 POSCMD0

bit 7 bit 0

Legend: x = Bit is unknown

R = Readable bit PO = Program Once bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 23-16 Unimplemented: Read as ‘1’

bit 15 IESO: Internal External Switchover bit

1 = IESO mode (Two-Speed Start-up) is enabled

0 = IESO mode (Two-Speed Start-up) is disabled

bit 14-11 Unimplemented: Read as ‘1’

bit 10-8 FNOSC<2:0>: Initial Oscillator Select bits

111 = Fast RC Oscillator with Postscaler (FRCDIV)

110 = Reserved

101 = Low-Power RC Oscillator (LPRC)

100 = Secondary Oscillator (SOSC)

011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)

010 = Primary Oscillator (XT, HS, EC)

001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL)

000 = Fast RC Oscillator (FRC)

bit 7-6 FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Configuration bits

1x = Clock switching and Fail-Safe Clock Monitor are disabled

01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled

00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled

bit 5 OSCIOFCN: OSC2 Pin Configuration bit

If POSCMD<1:0> = 11 or 00:

1 = OSC2/CLKO/RC15 functions as CLKO (FOSC/2)

0 = OSC2/CLKO/RC15 functions as port I/O (RC15)

If POSCMD<1:0> = 10 or 01:

OSCIOFCN has no effect on OSC2/CLKO/RC15.

bit 4-2 Unimplemented: Read as ‘1’

bit 1-0 POSCMD<1:0>: Primary Oscillator Configuration bits

11 = Primary oscillator is disabled

10 = HS Oscillator mode is selected

01 = XT Oscillator mode is selected

00 = EC Oscillator mode is selected

 2005-2012 Microchip Technology Inc. DS39747F-page 199

PIC24FJ128GA010 FAMILY

UU U U U U U U

— — — — — — — —

bit 23 bit 16

UU R R R R R R

—— FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2

bit 15 bit 8

RR R R R R R R

FAMID1 FAMID0 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0

bit 7 bit 0

Legend: x = Bit is unknown

R = Readable bit PO = Program Once bit U = Unimplemented bit, read as ‘1’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 23-14 Unimplemented: Read as ‘0’

bit 13-6 FAMID<7:0>: Device Family Identifier bits

00010000 = PIC24FJ128GA010 family

bit 5-0 DEV<5:0>: Individual Device Identifier bits

000101 = PIC24FJ64GA006

000110 = PIC24FJ96GA006

000111 = PIC24FJ128GA006

001000 = PIC24FJ64GA008

001001 = PIC24FJ96GA008

001010 = PIC24FJ128GA008

001011 = PIC24FJ64GA010

001100 = PIC24FJ96GA010

001101 = PIC24FJ128GA010

PIC24FJ128GA010 FAMILY

DS39747F-page 200  2005-2012 Microchip Technology Inc.

UU U U U U U U

— — — — — — — —

bit 23 bit 16

R-0 R-0 R-1 R-1 U U U R

r r r r — — —MAJRV2

bit 15 bit 8

RR U U U R R R

MAJRV1 MAJRV0 — — — DOT2 DOT1 DOT0

bit 7 bit 0

Legend: x = Bit is unknown r = Reserved

R = Readable bit PO = Program Once bit U = Unimplemented bit, read as ‘1’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 23-16 Unimplemented: Read as ‘0’

bit 15-12 Reserved: Read as ‘0011’

bit 11-9 Unimplemented: Read as ‘0’

bit 8-6 MAJRV<2:0>: Major Revision Identifier bits

bit 5-3 Unimplemented: Read as ‘0’

bit 2-0 DOT<2:0>: Minor Revision Identifier bits

 2005-2012 Microchip Technology Inc. DS39747F-page 201

PIC24FJ128GA010 FAMILY

24.2 On-Chip Voltage Regulator

All of the PIC24FJ128GA010 family devices power

their core digital logic at a nominal 2.5V. This may

create an issue for designs that are required to operate

at a higher typical voltage, such as 3.3V. To simplify

system design, all devices in the PIC24FJ128GA010

family incorporate an on-chip regulator that allows the

device to run its core logic from VDD.

The regulator is controlled by the ENVREG pin. Tying

VDD to the pin enables the regulator, which in turn,

provides power to the core from the other VDD pins.

When the regulator is enabled, a low-ESR capacitor

(such as tantalum) must be connected to the

VDDCORE/VCAP pin (Figure 24-1). This helps to main-

tain the stability of the regulator. The recommended

value for the filter capacitor, CEFC, is provided in

Section 27.1 “DC Characteristics”.

If ENVREG is tied to VSS, the regulator is disabled. In

this case, separate power for the core logic, at a nomi-

nal 2.5V, must be supplied to the device on the

VDDCORE/VCAP pin to run the I/O pins at higher voltage

levels, typically 3.3V. Alternatively, the VDDCORE/VCAP

and VDD pins can be tied together to operate at a lower

nominal voltage. Refer to Figure 24-1 for possible

configurations.

24.2.1 ON-CHIP REGULATOR AND POR

When the voltage regulator is enabled, it takes approxi-

mately 20 s for it to generate output. During this time,

designated as TSTARTUP, code execution is disabled.

STARTUP is applied every time the device resumes

operation after any power-down, including Sleep mode.

If the regulator is disabled, a separate Power-up Timer

(PWRT) is automatically enabled. The PWRT adds a

fixed delay of 64 ms nominal delay at device start-up.

24.2.2 ON-CHIP REGULATOR AND BOR

When the on-chip regulator is enabled,

PIC24FJ128GA010 devices also have a simple

brown-out capability. If the voltage supplied to the reg-

ulator is inadequate to maintain a regulated level, the

regulator Reset circuitry will generate a Brown-out

Reset. This event is captured by the BOR flag bit

(RCON<0>). The brown-out voltage specifications can

be found in the “PIC24F Family Reference Manual” in

Section 7. “Reset” (DS39712).

24.2.3 POWER-UP REQUIREMENTS

The on-chip regulator is designed to meet the power-up

requirements for the device. If the application does not

use the regulator, then strict power-up conditions must

be adhered to. While powering up, VDDCORE must

never exceed VDD by 0.3 volts.

FIGURE 24-1: CONNECTIONS FOR THE

ON-CHIP REGULATOR

VDD

ENVREG

VDDCORE/VCAP

VSS

PIC24FJ128GA010

3.3V(1)

2.5V(1)

VDD

ENVREG

VDDCORE/VCAP

VSS

PIC24FJ128GA010

CEFC

3.3V

Regulator Enabled (ENVRE G tied to VDD):

Regulator Disabled (ENVREG tied to ground):

VDD

ENVREG

VDDCORE/VCAP

VSS

PIC24FJ128GA010

2.5V(1)

Regulator Disabled (VDD tied to VDDCORE):

Note 1: These are typical operating voltages. Refer

Se ction 2 7.1 “D C Ch ar ac ter istic s”

for

the full operating ranges of VDD and

VDDCORE.

(10 F typ)

PIC24FJ128GA010 FAMILY

DS39747F-page 202  2005-2012 Microchip Technology Inc.

24.3 Watchdog Timer (WDT)

For PIC24FJ128GA010 family devices, the WDT is

driven by the LPRC oscillator. When the WDT is

enabled, the clock source is also enabled.

The nominal WDT clock source from LPRC is 32 kHz.

This feeds a prescaler that can be configured for either

5-bit (divide-by-32) or 7-bit (divide-by-128) operation.

The prescaler is set by the FWPSA Configuration bit.

With a 32 kHz input, the prescaler yields a nominal

WDT time-out period (TWDT) of 1 ms in 5-bit mode or

4 ms in 7-bit mode.

A variable postscaler divides down the WDT prescaler

output and allows for a wide range of time-out periods.

The postscaler is controlled by the WDTPS<3:0> Con-

figuration bits (Flash Configuration Word 1<3:0>),

which allow the selection of a total of 16 settings, from

1:1 to 1:32,768. Using the prescaler and postscaler,

time-out periods, ranging from 1 ms to 131 seconds,

can be achieved.

The WDT, prescaler and postscaler are reset:

• On any device Reset

• On the completion of a clock switch, whether

invoked by software (i.e., setting the OSWEN bit

after changing the NOSC bits) or by hardware

(i.e., Fail-Safe Clock Monitor)

• When a PWRSAV instruction is executed (i.e.,

Sleep or Idle mode is entered)

• When the device exits Sleep or Idle mode to

resume normal operation

•By a CLRWDT instruction during normal execution

If the WDT is enabled, it will continue to run during

Sleep or Idle modes. When the WDT time-out occurs,

the device will wake-up and code execution will con-

tinue from where the PWRSAV instruction was executed.

The corresponding SLEEP or IDLE bits (RCON<3:2>)

will need to be cleared in software after the device

wakes up.

The WDT Flag bit, WDTO (RCON<4>), is not auto-

matically cleared following a WDT time-out. To detect

subsequent WDT events, the flag must be cleared in

software.

24.3.1 CONTROL REGISTER

The WDT is enabled or disabled by the FWDTEN

Configuration bit. When the FWDTEN Configuration bit

is set, the WDT is always enabled.

The WDT can be optionally controlled in software when

the FWDTEN Configuration bit has been programmed

to ‘0’. The WDT is enabled in software by setting the

SWDTEN control bit (RCON<5>). The SWDTEN con-

trol bit is cleared on any device Reset. The software

WDT option allows the user to enable the WDT for crit-

ical code segments and disables the WDT during

non-critical segments for maximum power savings.

FIGURE 24-2: WATCHDOG TIMER (WDT) BLOCK DIAGRAM

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 9. “Watchdog

Timer (WDT)” (DS39697) in the “PIC24F

Family Reference Manual” for more

information.

Note: The CLRWDT and PWRSAV instructions

clear the prescaler and postscaler counts

when executed.

LPRC Input WDT Overflow

Wake from Sleep

32 kHz

Prescaler Postscaler

FWPSA

SWDTEN

FWDTEN

Reset

All Device Resets

Sleep or Idle Mode

LPRC Control

CLRWDT Instr.

PWRSAV Instr.

(5-bit/7-bit) 1:1 to 1:32.768

WDTPS<3:0>

1 ms/4 ms

Exit Sleep or

Idle Mode

WDT

Counter

Transition to

New Clock Source

 2005-2012 Microchip Technology Inc. DS39747F-page 203

PIC24FJ128GA010 FAMILY

24.4 JTAG Interface

PIC24FJ128GA010 family devices implement a JTAG

interface, which supports boundary scan device testing

as well as In-Circuit Serial Programming™ (ICSP™).

Refer to the Microchip web site (www.microchip.com)

for JTAG support files and additional information.

24.5 Program Verification and

Code Protection

For all devices in the PIC24FJ128GA010 family, the

on-chip program memory space is treated as a single

block. Code protection for this block is controlled by

one Configuration bit, GCP (Flash Configuration

Word 1<13>. This bit inhibits external reads and writes

to the program memory space. It has no direct effect in

normal execution mode.

Write protection is controlled by the GWRP bit (Flash

Configuration Word 1<12>. When GWRP is pro-

grammed to ‘0’, internal write and erase operations to

the program memory are blocked.

24.5.1 CONFIGURATION REGISTER

PROTECTION

The Configuration registers are protected against

inadvertent or unwanted changes, or reads in two

ways. The primary protection method is the same as

that of the shadow registers, which contain a compli-

mentary value that is constantly compared with the

actual value. To safeguard against unpredictable

events, Configuration bit changes resulting from indi-

vidual cell level disruptions (such as ESD events) will

cause a parity error and trigger a device Configuration

Word Mismatch Reset.

The data for the Configuration registers is derived from

the Flash Configuration Words in program memory. As

a consequence, when the GCP bit is set, the source

data for the device configuration is also protected.

24.6 In-Cir cuit Serial Programming

PIC24FJ128GA010 family microcontrollers can be

serially programmed while in the end application circuit.

This is simply done with two lines for clock (PGCx) and

data (PGDx), and three other lines for power, ground

and the programming voltage. This allows customers to

manufacture boards with unprogrammed devices and

then program the microcontroller just before shipping

the product. This also allows the most recent firmware

or a custom firmware to be programmed.

24.7 In-Circuit Debugger

When MPLAB® ICD 2 is selected as a debugger, the

In-Circuit Debugging functionality is enabled. This

function allows simple debugging functions when used

with MPLAB IDE. Debugging functionality is controlled

through the EMUCx (Emulation/Debug Clock) and

EMUDx (Emulation/Debug Data) pins.

To use the In-Circuit Debugger function of the device, the

design must implement ICSP connections to MCLR,

VDD, VSS, PGCx, PGDx and the EMUDx/EMUCx pin

pair. In addition, when the feature is enabled, some of the

resources are not available for general use. These

resources include the first 80 bytes of data RAM and two

I/O pins.

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 33. “Program-

ming and Diagnostics” (DS39716) in the

“PIC24F Family Reference Manual” for

more information.

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 33. “Program-

ming and Diagnostics” (DS39716) in the

“PIC24F Family Reference Manual” for

more information.

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 33. “Program-

ming and Diagnostics” (DS39716) in the

“PIC24F Family Reference Manual” for

more information.

PIC24FJ128GA010 FAMILY

DS39747F-page 204  2005-2012 Microchip Technology Inc.

NOTES:

 2005-2012 Microchip Technology Inc. DS39747F-page 205

PIC24FJ128GA010 FAMILY

25.0 INSTRUCTION SET SUMMARY

The PIC24F instruction set adds many enhancements

to the previous PIC® MCU instruction sets, while main-

taining an easy migration from previous PIC MCU

instruction sets. Most instructions are a single program

memory word. Only three instructions require two

program memory locations.

Each single-word instruction is a 24-bit word divided

into an 8-bit opcode, which specifies the instruction

type and one or more operands, which further specify

the operation of the instruction. The instruction set is

highly orthogonal and is grouped into four basic

categories:

• Word or byte-oriented operations

• Bit-oriented operations

• Literal operations

• Control operations

Table 25-1 shows the general symbols used in

describing the instructions. The PIC24F instruction set

summary in Table 25-2 lists all the instructions, along

with the status flags affected by each instruction.

Most word or byte-oriented W register instructions

(including barrel shift instructions) have three

operands:

• The first source operand which is typically a

• The second source operand which is typically a

• The destination of the result which is typically a

However, word or byte-oriented file register instructions

have two operands:

• The file register specified by the value, ‘f’

• The destination, which could either be the file

‘WREG’

Most bit-oriented instructions (including simple rotate/

shift instructions) have two operands:

• The W register (with or without an address

modifier) or file register (specified by the value of

‘Ws’ or ‘f’)

• The bit in the W register or file register

(specified by a literal value or indirectly by the

contents of register, ‘Wb’)

The literal instructions that involve data movement may

use some of the following operands:

• A literal value to be loaded into a W register or file

• The W register or file register where the literal

value is to be loaded (specified by ‘Wb’ or ‘f’)

However, literal instructions that involve arithmetic or

logical operations use some of the following operands:

• The first source operand which is a register, ‘Wb’,

without any address modifier

• The second source operand which is a literal

value

• The destination of the result (only if not the same

as the first source operand) which is typically a

The control instructions may use some of the following

operands:

• A program memory address

• The mode of the table read and table write

instructions

All instructions are a single word, except for certain

double-word instructions, which were made double-

word instructions so that all of the required information

is available in these 48 bits. In the second word, the

8MSbs are ‘0’s. If this second word is executed as an

instruction (by itself), it will execute as a NOP.

Most single-word instructions are executed in a single

instruction cycle, unless a conditional test is true or the

Program Counter (PC) is changed as a result of the

instruction. In these cases, the execution takes two

instruction cycles, with the additional instruction

cycle(s) executed as a NOP. Notable exceptions are the

BRA (unconditional/computed branch), indirect CALL/

GOTO, all table reads and writes, and RETURN/RETFIE

instructions, which are single-word instructions but take

two or three cycles.

Certain instructions that involve skipping over the sub-

sequent instruction require either two or three cycles if

the skip is performed, depending on whether the

instruction being skipped is a single-word or two-word

instruction. Moreover, double-word moves require two

cycles. The double-word instructions execute in two

instruction cycles.

PIC24FJ128GA010 FAMILY

DS39747F-page 206  2005-2012 Microchip Technology Inc.

TABLE 25-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field Description

#text Means literal defined by “text”

(text) Means “content of text”

[text] Means “the location addressed by text”

{ } Optional field or operation

<n:m> Register bit field

.b Byte mode selection

.d Double-Word mode selection

.S Shadow register select

.w Word mode selection (default)

bit4 4-bit bit selection field (used in word addressed instructions) {0...15}

C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero

Expr Absolute address, label or expression (resolved by the linker)

f File register address {0000h...1FFFh}

lit1 1-bit unsigned literal {0,1}

lit4 4-bit unsigned literal {0...15}

lit5 5-bit unsigned literal {0...31}

lit8 8-bit unsigned literal {0...255}

lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode

lit14 14-bit unsigned literal {0...16384}

lit16 16-bit unsigned literal {0...65535}

lit23 23-bit unsigned literal {0...8388608}; LSB must be ‘0’

None Field does not require an entry, may be blank

PC Program Counter

Slit10 10-bit signed literal {-512...511}

Slit16 16-bit signed literal {-32768...32767}

Slit6 6-bit signed literal {-16...16}

Wb Base W register {W0..W15}

Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }

Wdo Destination W register 

{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }

Wm,Wn Dividend, Divisor working register pair (Direct Addressing)

Wn One of 16 working registers {W0..W15}

Wnd One of 16 destination working registers {W0..W15}

Wns One of 16 source working registers {W0..W15}

WREG W0 (working register used in file register instructions)

Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }

Wso Source W register 

{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }

 2005-2012 Microchip Technology Inc. DS39747F-page 207

PIC24FJ128GA010 FAMILY

TABLE 25-2: INSTRUCTION SET OVERVIEW

Assembly

Mnemonic Assembly Syntax Description # of

Words # of

Cycles Status Flags

Affected

ADD ADD f f = f + WREG 1 1 C, DC, N, OV, Z

ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z

ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z

ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z

ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z

ADDC ADDC f f = f + WREG + (C) 1 1 C, DC, N, OV, Z

ADDC f,WREG WREG = f + WREG + (C) 1 1 C, DC, N, OV, Z

ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C, DC, N, OV, Z

ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C, DC, N, OV, Z

ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C, DC, N, OV, Z

AND AND f f = f .AND. WREG 1 1 N, Z

AND f,WREG WREG = f .AND. WREG 1 1 N, Z

AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N, Z

AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N, Z

AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N, Z

ASR ASR f f = Arithmetic Right Shift f 1 1 C, N, OV, Z

ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C, N, OV, Z

ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C, N, OV, Z

ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N, Z

ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N, Z

BCLR BCLR f,#bit4 Bit Clear f 1 1 None

BCLR Ws,#bit4 Bit Clear Ws 1 1 None

BRA BRA C,Expr Branch if Carry 1 1 (2) None

BRA GE,Expr Branch if Greater than or Equal 1 1 (2) None

BRA GEU,Expr Branch if Unsigned Greater than or Equal 1 1 (2) None

BRA GT,Expr Branch if Greater than 1 1 (2) None

BRA GTU,Expr Branch if Unsigned Greater than 1 1 (2) None

BRA LE,Expr Branch if Less than or Equal 1 1 (2) None

BRA LEU,Expr Branch if Unsigned Less than or Equal 1 1 (2) None

BRA LT,Expr Branch if Less than 1 1 (2) None

BRA LTU,Expr Branch if Unsigned Less than 1 1 (2) None

BRA N,Expr Branch if Negative 1 1 (2) None

BRA NC,Expr Branch if Not Carry 1 1 (2) None

BRA NN,Expr Branch if Not Negative 1 1 (2) None

BRA NOV,Expr Branch if Not Overflow 1 1 (2) None

BRA NZ,Expr Branch if Not Zero 1 1 (2) None

BRA OV,Expr Branch if Overflow 1 1 (2) None

BRA Expr Branch Unconditionally 1 2 None

BRA Z,Expr Branch if Zero 1 1 (2) None

BRA Wn Computed Branch 1 2 None

BSET BSET f,#bit4 Bit Set f 1 1 None

BSET Ws,#bit4 Bit Set Ws 1 1 None

BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None

BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None

BTG BTG f,#bit4 Bit Toggle f 1 1 None

BTG Ws,#bit4 Bit Toggle Ws 1 1 None

BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1

(2 or 3)

None

BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1

(2 or 3)

None

PIC24FJ128GA010 FAMILY

DS39747F-page 208  2005-2012 Microchip Technology Inc.

BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1

(2 or 3)

None

BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1

(2 or 3)

None

BTST BTST f,#bit4 Bit Test f 1 1 Z

BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C

BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z

BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C

BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z

BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z

BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C

BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z

CALL CALL lit23 Call Subroutine 2 2 None

CALL Wn Call Indirect Subroutine 1 2 None

CLR CLR f f = 0x0000 1 1 None

CLR WREG WREG = 0x0000 1 1 None

CLR Ws Ws = 0x0000 1 1 None

CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO, Sleep

COM COM f f = f 11N, Z

COM f,WREG WREG = f 11N, Z

COM Ws,Wd Wd = Ws 11N, Z

CP CP f Compare f with WREG 1 1 C, DC, N, OV, Z

CP Wb,#lit5 Compare Wb with lit5 1 1 C, DC, N, OV, Z

CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C, DC, N, OV, Z

CP0 CP0 f Compare f with 0x0000 1 1 C, DC, N, OV, Z

CP0 Ws Compare Ws with 0x0000 1 1 C, DC, N, OV, Z

CPB CPB f Compare f with WREG, with Borrow 1 1 C, DC, N, OV, Z

CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C, DC, N, OV, Z

CPB Wb,Ws Compare Wb with Ws, with Borrow

(Wb – Ws – C)

1 1 C, DC, N, OV, Z

CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, Skip if = 1 1

(2 or 3)

None

CPSGT CPSGT Wb,Wn Compare Wb with Wn, Skip if > 1 1

(2 or 3)

None

CPSLT CPSLT Wb,Wn Compare Wb with Wn, Skip if < 1 1

(2 or 3)

None

CPSNE CPSNE Wb,Wn Compare Wb with Wn, Skip if 11

(2 or 3)

None

DAW DAW.B Wn Wn = Decimal Adjust Wn 1 1 C

DEC DEC f f = f –1 1 1 C, DC, N, OV, Z

DEC f,WREG WREG = f –1 1 1 C, DC, N, OV, Z

DEC Ws,Wd Wd = Ws – 1 1 1 C, DC, N, OV, Z

DEC2 DEC2 f f = f – 2 1 1 C, DC, N, OV, Z

DEC2 f,WREG WREG = f – 2 1 1 C, DC, N, OV, Z

DEC2 Ws,Wd Wd = Ws – 2 1 1 C, DC, N, OV, Z

DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None

DIV DIV.SW Wm,Wn Signed 16/16-Bit Integer Divide 1 18 N, Z, C, OV

DIV.SD Wm,Wn Signed 32/16-Bit Integer Divide 1 18 N, Z, C, OV

DIV.UW Wm,Wn Unsigned 16/16-Bit Integer Divide 1 18 N, Z, C, OV

DIV.UD Wm,Wn Unsigned 32/16-Bit Integer Divide 1 18 N, Z, C, OV

EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None

FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C

FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C

TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic Assembly Syntax Description # of

Words # of

Cycles Status Flags

Affected

 2005-2012 Microchip Technology Inc. DS39747F-page 209

PIC24FJ128GA010 FAMILY

GOTO GOTO Expr Go to Address 2 2 None

GOTO Wn Go to Indirect 1 2 None

INC INC f f = f + 1 1 1 C, DC, N, OV, Z

INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z

INC Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z

INC2 INC2 f f = f + 2 1 1 C, DC, N, OV, Z

INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z

INC2 Ws,Wd Wd = Ws + 2 1 1 C, DC, N, OV, Z

IOR IOR f f = f .IOR. WREG 1 1 N, Z

IOR f,WREG WREG = f .IOR. WREG 1 1 N, Z

IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N, Z

IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N, Z

IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N, Z

LNK LNK #lit14 Link Frame Pointer 1 1 None

LSR LSR f f = Logical Right Shift f 1 1 C, N, OV, Z

LSR f,WREG WREG = Logical Right Shift f 1 1 C, N, OV, Z

LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C, N, OV, Z

LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N, Z

LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N, Z

MOV MOV f,Wn Move f to Wn 1 1 None

MOV [Wns+Slit10],Wnd Move [Wns+Slit10] to Wnd 1 1 None

MOV f Move f to f 1 1 N, Z

MOV f,WREG Move f to WREG 1 1 N, Z

MOV #lit16,Wn Move 16-Bit Literal to Wn 1 1 None

MOV.b #lit8,Wn Move 8-Bit Literal to Wn 1 1 None

MOV Wn,f Move Wn to f 1 1 None

MOV Wns,[Wns+Slit10] Move Wns to [Wns+Slit10] 1 1

MOV Wso,Wdo Move Ws to Wd 1 1 None

MOV WREG,f Move WREG to f 1 1 N, Z

MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None

MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None

MUL MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 None

MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) 1 1 None

MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) 1 1 None

MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) 1 1 None

MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) 1 1 None

MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) 1 1 None

MUL f W3:W2 = f * WREG 1 1 None

NEG NEG f f = f + 1 1 1 C, DC, N, OV, Z

NEG f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z

NEG Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z

NOP NOP No Operation 1 1 None

NOPR No Operation 1 1 None

POP POP f Pop f from Top-of-Stack (TOS) 1 1 None

POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None

POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) 1 2 None

POP.S Pop Shadow Registers 1 1 All

PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None

PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None

PUSH.D Wns Push W(ns):W(ns+1) to Top-of-Stack (TOS) 1 2 None

PUSH.S Push Shadow Registers 1 1 None

TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic Assembly Syntax Description # of

Words # of

Cycles Status Flags

Affected

PIC24FJ128GA010 FAMILY

DS39747F-page 210  2005-2012 Microchip Technology Inc.

PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep

RCALL RCALL Expr Relative Call 1 2 None

RCALL Wn Computed Call 1 2 None

REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None

REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None

RESET RESET Software Device Reset 1 1 None

RETFIE RETFIE Return from Interrupt 1 3 (2) None

RETLW RETLW #lit10,Wn Return with Literal in Wn 1 3 (2) None

RETURN RETURN Return from Subroutine 1 3 (2) None

RLC RLC f f = Rotate Left through Carry f 1 1 C, N, Z

RLC f,WREG WREG = Rotate Left through Carry f 1 1 C, N, Z

RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C, N, Z

RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N, Z

RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N, Z

RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N, Z

RRC RRC f f = Rotate Right through Carry f 1 1 C, N, Z

RRC f,WREG WREG = Rotate Right through Carry f 1 1 C, N, Z

RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C, N, Z

RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N, Z

RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N, Z

RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N, Z

SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C, N, Z

SETM SETM f f = FFFFh 1 1 None

SETM WREG WREG = FFFFh 1 1 None

SETM Ws Ws = FFFFh 1 1 None

SL SL f f = Left Shift f 1 1 C, N, OV, Z

SL f,WREG WREG = Left Shift f 1 1 C, N, OV, Z

SL Ws,Wd Wd = Left Shift Ws 1 1 C, N, OV, Z

SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N, Z

SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N, Z

SUB SUB f f = f – WREG 1 1 C, DC, N, OV, Z

SUB f,WREG WREG = f – WREG 1 1 C, DC, N, OV, Z

SUB #lit10,Wn Wn = Wn – lit10 1 1 C, DC, N, OV, Z

SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C, DC, N, OV, Z

SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C, DC, N, OV, Z

SUBB SUBB f f = f – WREG – (C) 1 1 C, DC, N, OV, Z

SUBB f,WREG WREG = f – WREG – (C) 1 1 C, DC, N, OV, Z

SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C, DC, N, OV, Z

SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C, DC, N, OV, Z

SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C, DC, N, OV, Z

SUBR SUBR f f = WREG – f 1 1 C, DC, N, OV, Z

SUBR f,WREG WREG = WREG – f 1 1 C, DC, N, OV, Z

SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C, DC, N, OV, Z

SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C, DC, N, OV, Z

SUBBR SUBBR f f = WREG – f – (C) 1 1 C, DC, N, OV, Z

SUBBR f,WREG WREG = WREG – f – (C) 1 1 C, DC, N, OV, Z

SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C, DC, N, OV, Z

SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C, DC, N, OV, Z

SWAP SWAP.b Wn Wn = Nibble Swap Wn 1 1 None

SWAP Wn Wn = Byte Swap Wn 1 1 None

TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None

TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic Assembly Syntax Description # of

Words # of

Cycles Status Flags

Affected

 2005-2012 Microchip Technology Inc. DS39747F-page 211

PIC24FJ128GA010 FAMILY

TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None

TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None

TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None

ULNK ULNK Unlink Frame Pointer 1 1 None

XOR XOR f f = f .XOR. WREG 1 1 N, Z

XOR f,WREG WREG = f .XOR. WREG 1 1 N, Z

XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N, Z

XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N, Z

XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N, Z

ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C, Z, N

TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic Assembly Syntax Description # of

Words # of

Cycles Status Flags

Affected

PIC24FJ128GA010 FAMILY

DS39747F-page 212  2005-2012 Microchip Technology Inc.

NOTES:

 2005-2012 Microchip Technology Inc. DS39747F-page 213

PIC24FJ128GA010 FAMILY

26.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers and dsPIC® digital signal

controllers are supported with a full range of software

and hardware development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Compilers/Assemblers/Linkers

- MPLAB C Compiler for Various Device

Families

- HI-TECH C® for Various Device Families

- MPASMTM Assembler

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers

- MPLAB ICD 3

- PICkit™ 3 Debug Express

• Device Programmers

- PICkit™ 2 Programmer

- MPLAB PM3 Device Programmer

• Low-Cost Demonstration/Development Boards,

Evaluation Kits, and Starter Kits

26.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16/32-bit

microcontroller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- In-Circuit Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Extensive on-line help

• Integration of select third party tools, such as

IAR C Compilers

The MPLAB IDE allows you to:

• Edit your source files (either C or assembly)

• One-touch compile or assemble, and download to

emulator and simulator tools (automatically

updates all project information)

• Debug using:

- Source files (C or assembly)

- Mixed C and assembly

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

PIC24FJ128GA010 FAMILY

DS39747F-page 214  2005-2012 Microchip Technology Inc.

26.2 MPLAB C Compilers for Various

Device Families

The MPLAB C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC18,

PIC24 and PIC32 families of microcontrollers and the

dsPIC30 and dsPIC33 families of digital signal control-

lers. These compilers provide powerful integration

capabilities, superior code optimization and ease of

use.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

26.3 HI-TECH C for Vario u s Device

Families

The HI-TECH C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC

family of microcontrollers and the dsPIC family of digital

signal controllers. These compilers provide powerful

integration capabilities, omniscient code generation

and ease of use.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The compilers include a macro assembler, linker, pre-

processor, and one-step driver, and can run on multiple

platforms.

26.4 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel® standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

source files

• Directives that allow complete control over the

assembly process

26.5 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

26.6 MPLAB Assembler, Linker and

Librarian for Various Device

Families

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC devices. MPLAB C Compiler uses

the assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directive set

• Flexible macro language

• MPLAB IDE compatibility

 2005-2012 Microchip Technology Inc. DS39747F-page 215

PIC24FJ128GA010 FAMILY

26.7 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC® DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

26.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC® Flash MCUs and dsPIC® Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated Development Environment (IDE),

included with each kit.

The emulator is connected to the design engineer’s PC

using a high-speed USB 2.0 interface and is connected

to the target with either a connector compatible with in-

circuit debugger systems (RJ11) or with the new high-

speed, noise tolerant, Low-Voltage Differential Signal

(LVDS) interconnection (CAT5).

The emulator is field upgradable through future firmware

downloads in MPLAB IDE. In upcoming releases of

MPLAB IDE, new devices will be supported, and new

features will be added. MPLAB REAL ICE offers

significant advantages over competitive emulators

including low-cost, full-speed emulation, run-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

26.9 MPLAB ICD 3 In-Circuit Debugger

System

MPLAB ICD 3 In-Circuit Debugger System is Micro-

chip's most cost effective high-speed hardware

debugger/programmer for Microchip Flash Digital Sig-

nal Controller (DSC) and microcontroller (MCU)

devices. It debugs and programs PIC® Flash microcon-

trollers and dsPIC® DSCs with the powerful, yet easy-

to-use graphical user interface of MPLAB Integrated

Development Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is con-

nected to the design engineer’s PC using a high-speed

USB 2.0 interface and is connected to the target with a

connector compatible with the MPLAB ICD 2 or MPLAB

REAL ICE systems (RJ-11). MPLAB ICD 3 supports all

MPLAB ICD 2 headers.

26.10 PICkit 3 In-Circuit Debugger/

Programmer and

PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and program-

ming of PIC® and dsPIC® Flash microcontrollers at a

most affordable price point using the powerful graphical

user interface of the MPLAB Integrated Development

Environment (IDE). The MPLAB PICkit 3 is connected

to the design engineer's PC using a full speed USB

interface and can be connected to the target via an

Microchip debug (RJ-11) connector (compatible with

MPLAB ICD 3 and MPLAB REAL ICE). The connector

uses two device I/O pins and the reset line to imple-

ment in-circuit debugging and In-Circuit Serial

Programming™.

The PICkit 3 Debug Express include the PICkit 3, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

PIC24FJ128GA010 FAMILY

DS39747F-page 216  2005-2012 Microchip Technology Inc.

26.11 PICkit 2 Development

Programmer/Debugger and

PICkit 2 Debug Express

The PICkit™ 2 Development Programmer/Debugger is

a low-cost development tool with an easy to use inter-

face for programming and debugging Microchip’s Flash

families of microcontrollers. The full featured

Windows® programming interface supports baseline

(PIC10F, PIC12F5xx, PIC16F5xx), midrange

(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,

dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit

microcontrollers, and many Microchip Serial EEPROM

products. With Microchip’s powerful MPLAB Integrated

Development Environment (IDE) the PICkit™ 2

enables in-circuit debugging on most PIC® microcon-

trollers. In-Circuit-Debugging runs, halts and single

steps the program while the PIC microcontroller is

embedded in the application. When halted at a break-

point, the file registers can be examined and modified.

The PICkit 2 Debug Express include the PICkit 2, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

26.12 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an MMC card for file

storage and data applications.

26.13 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

for analog filter design, KEELOQ® security ICs, CAN,

IrDA®, PowerSmart battery management, SEEVAL®

evaluation system, Sigma-Delta A/D, flow rate sensing,

plus many more.

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

 2005-2012 Microchip Technology Inc. DS39747F-page 217

PIC24FJ128GA010 FAMILY

27.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of the PIC24FJ128GA010 electrical characteristics. Additional information will be

provided in future revisions of this document as it becomes available.

Absolute maximum ratings for the PIC24FJ128GA010 are listed below. Exposure to these maximum rating conditions

for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions

above the parameters indicated in the operation listings of this specification, is not implied.

Absolute Maximum Ratings(†)

Ambient temperature under bias...............................................................................................................-40°C to +85°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V

Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)

Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +6.0V

Voltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +2.8V

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin (Note 1)................................................................................................................ 250 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by all ports .......................................................................................................................200 mA

Maximum current sourced by all ports (Note 1).................................................................................................... 200 mA

Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 27 -2 ).

FIGURE 27-1: FREQUENCY/VOLTAGE GRAPH

†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those, or any other conditions above those

indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Frequency

Voltage VDDCORE(1)

3.00V

2.75V

2.25V

2.00V

32 MHz

2.50V

16 MHz

2.75V

Note 1: When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCORE  VDD 3.6V.

PIC24FJ128GA010 FAMILY

DS39747F-page 218  2005-2012 Microchip Technology Inc.

27.1 DC Characteristics

TABLE 27-1: OPERATING MIPS vs. VOLTAGE

VDD Range

(in Volts) Temp Range

(in °C)

Max MIPS

PIC24FJ128GA010 Family

2.0-3.6V -40°C to +85°C 16

TABLE 27-2: THERMAL OPERATING CONDITIONS

Rating Symbol Min Typ Max Unit

PIC24FJ128GA010 Family:

Operating Junction Temperature Range TJ-40 — +125 °C

Operating Ambient Temperature Range TA-40 — +85 °C

Power Dissipation:

Internal Chip Power Dissipation:

PINT = VDD x (IDD –  IOH)PDPINT + PI/OW

I/O Pin Power Dissipation:

PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL)

Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W

TABLE 27-3: THERMAL PACKAGING CHARACTERISTICS

Characteristic Symbol Typ Max Unit Notes

Package Thermal Resistance, 14x14x1 mm TQFP JA 50 — °C/W (Note 1)

Package Thermal Resistance, 12x12x1 mm TQFP JA 69.4 — °C/W (Note 1)

Package Thermal Resistance, 10x10x1 mm TQFP JA 76.6 — °C/W (Note 1)

Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.

TABLE 27-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

DC CHARACTERISTICS St andard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  T

A  +85°C for Industrial

Param

No. Sym Characteristic Min Typ(1)Max Units Conditions

Operating Voltage

DC10 Supply V oltage

VDD VBOR — 3.6 V Regulator is enabled

VDD VDDCORE — 3.6 V Regulator is disabled

VDDCORE 2.0 — 2.75 V Regulator is disabled

DC12 VDR RAM Data Retention

Voltage(2)1.5 — — V

DC16 VPOR VDD Start Voltage

to Ensure Internal

Power-on Reset Signal

——V

SS V

DC17 SVDD VDD Rise Rate

to Ensure Internal

Power-on Reset Signal

0.05 — — V/ms 0-3.3V in 0.1s

0-2.5V in 60 ms

DC18 VBOR Brown-out Reset

Voltage(3)1.9 2.2 2.5 V Regulator must be enabled

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: This is the limit to which VDD can be lowered without losing RAM data.

3: Device will operate normally until Brown-out reset occurs even though VDD may be below VDDMIN.

 2005-2012 Microchip Technology Inc. DS39747F-page 219

PIC24FJ128GA010 FAMILY

TABLE 27-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

DC CHARACTERISTICS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

Parameter

No. Typical(1)Max Units Conditions

Operating Current (IDD)(2)

DC20 1.6 4.0 mA -40°C

2.5V(3)

1 MIPS

DC20a 1.6 4.0 mA +25°C

DC20b 1.6 4.0 mA +85°C

DC20d 1.6 4.0 mA -40°C

3.6V(4)

DC20e 1.6 4.0 mA +25°C

DC20f 1.6 4.0 mA +85°C

DC23 6.0 12 mA -40°C

2.5V(3)

4 MIPS

DC23a 6.0 12 mA +25°C

DC23b 6.0 12 mA +85°C

DC23d 6.0 12 mA -40°C

3.6V(4)

DC23e 6.0 12 mA +25°C

DC23f 6.0 12 mA +85°C

DC24 20 32 mA -40°C

2.5V(3)

16 MIPS

DC24a 20 32 mA +25°C

DC24b 20 32 mA +85°C

DC24d 20 32 mA -40°C

3.6V(4)

DC24e 20 32 mA +25°C

DC24f 20 32 mA +85°C

DC31 70 150 A -40°C

2.5V(3)

LPRC (31 kHz)

DC31a 100 200 A+25°C

DC31b 200 400 A+85°C

DC31d 70 150 A -40°C

3.6V(4)

DC31e 100 200 A+25°C

DC31f 200 400 A+85°C

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have

an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1

driven with external square wave from rail-to-rail. All I/O pins are configured as inputs and pulled to VDD.

MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are

operational. No peripheral modules are operating and PMD bits are set.

3: On-chip voltage regulator is disabled (ENVREG tied to VSS).

4: On-chip voltage regulator is enabled (ENVREG tied to VDD).

PIC24FJ128GA010 FAMILY

DS39747F-page 220  2005-2012 Microchip Technology Inc.

TABLE 27-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

DC CHARACTERISTICS S tandard Ope rating C on dit ion s: 2.0 V to 3 .6V (unless otherwis e stated)

Operating temperature -40°C  TA  +85°C for Industrial

Parameter

No. Typical(1)Max Units Conditions

Idle Current (IIDLE): Core Off, Clock On Base Current(2)

DC40 0.7 2 mA -40°C

2.5V(3)

1 MIPS

DC40a 0.7 2 mA +25°C

DC40b 0.7 2 mA +85°C

DC40d 0.7 2 mA -40°C

3.6V(4)

DC40e 0.7 2 mA +25°C

DC40f 0.7 2 mA +85°C

DC43 2.1 4 mA -40°C

2.5V(3)

4 MIPS

DC43a 2.1 4 mA +25°C

DC43b 2.1 4 mA +85°C

DC43d 2.1 4 mA -40°C

3.6V(4)

DC43e 2.1 4 mA +25°C

DC43f 2.1 4 mA +85°C

DC47 6.8 8 mA -40°C

2.5V(3)

16 MIPS

DC47a 6.8 8 mA +25°C

DC47b 6.8 8 mA +85°C

DC47c 6.8 8 mA -40°C

3.6V(4)

DC47d 6.8 8 mA +25°C

DC47e 6.8 8 mA +85°C

DC51 70 150 A-40°C

2.5V(3)

LPRC (31 kHz)

DC51a 100 200 A+25°C

DC51b 150 400 A+85°C

DC51d 70 150 A-40°C

3.6V(4)

DC51e 100 200 A+25°C

DC51f 150 400 A+85°C

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: Base IIDLE current is measured with core off, clock on, PMD bits set and all modules turned off.

3: On-chip voltage regulator is disabled (ENVREG tied to VSS).

4: On-chip voltage regulator is enabled (ENVREG tied to VDD).

 2005-2012 Microchip Technology Inc. DS39747F-page 221

PIC24FJ128GA010 FAMILY

TABLE 27-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

DC CHARACTERISTICS Standard Operating Conditions: 2.0V t o 3 .6V (u nless oth erw is e stated)

Operating temperature -40°C  TA  +85°C for Industrial

Parameter

No. Typical(1)Max Units Conditions

Power-Down Current (IPD)(2)

DC60 3 25 A-40°C

2.0V(3)

Base Power-Down Current(5)

DC60a 3 45 A+25°C

DC60b 100 600 A+85°C

DC60f 20 40 A-40°C

3.6V(4)

DC60g 27 60 A+25°C

DC60h 120 600 A+85°C

Module Differential Current

DC61 10 25 A-40°C

2.0V(3)

Watchdog Timer Current: IWDT(5)

DC61a 10 25 A+25°C

DC61b 10 25 A+85°C

DC61f 10 25 A-40°C

3.6V(4)

DC61g 10 25 A+25°C

DC61h 10 25 A+85°C

DC62 8 15 A-40°C

2.0V(3)

RTCC + Timer1 w/32 kHz Crystal:

IRTCC(5)

DC62a 8 15 A+25°C

DC62b 8 15 A+85°C

DC62f 8 15 A-40°C

3.6V(4)

DC62g 8 15 A+25°C

DC62h 8 15 A+85°C

Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and

pulled high. WDT, etc., are all switched off. Unused PMD bits are set. VREGS bit is clear.

3: On-chip voltage regulator is disabled (ENVREG tied to VSS).

4: On-chip voltage regulator is enabled (ENVREG tied to VDD).

5: The  current is the additional current consumed when the module is enabled. This current should be

added to the base IPD current.

PIC24FJ128GA010 FAMILY

DS39747F-page 222  2005-2012 Microchip Technology Inc.

TABLE 27-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

DC CHARACTERISTICS St andard Operating Conditions: 2.0V to 3.6V (unless otherwise st ated)

Operating temperature -40°C  T

A  +85°C for Industrial

Param

No. Sym Characteristic Min Typ(1)Max Units Conditions

VIL Input Low Voltage(4)

DI10 I/O Pins with ST Buffer VSS —0.2VDD V

DI11 I/O Pins with TTL Buffer VSS —0.15 VDD V

DI15 MCLR VSS —0.2VDD V

DI16 OSC1 (XT mode) VSS —0.2VDD V

DI17 OSC1 (HS mode) VSS —0.2VDD V

DI18 I/O Pins with I2C™ Buffer VSS —0.3VDD V

DI19 I/O Pins with SMBus Buffer VSS — 0.8 V SMBus enabled

VIH Input High Voltage(4)

DI20 I/O Pins with ST Buffer:

with Analog Functions

Digital Only

0.8 VDD

—

VDD

5.5

DI21 I/O Pins with TTL Buffer:

with Analog Functions,

Digital Only

0.25 VDD + 0.8

—

VDD

5.5

DI25 MCLR 0.8 VDD —VDD V

DI26 OSC1 (XT mode) 0.7 VDD —VDD V

DI27 OSC1 (HS mode) 0.7 VDD —VDD V

DI28 I/O Pins with I2C Buffer:

with Analog Functions

Digital Only

0.7 VDD

—

VDD

5.5

DI29 I/O Pins with SMBus Buffer:

with Analog Functions

Digital Only

2.1

VDD

5.5

V2.5V  VPIN  VDD

DI30 ICNPU CNxx Pull-up Current 50 250 400 AVDD = 3.3V, VPIN = VSS

DI31 IPU Maximum Load Current

for Digital High Detection

w/Internal Pull-up

——30AV

DD = 2.0V

——100AVDD = 3.3V

IIL Inpu t Leakage Current(2,3)

DI50 I/O Ports:

with Analog Functions

Digital Only

—

1000

Pin at high-impedance

VSS  VPIN  VDD

VSS  VPIN  5.5V

DI51 Analog Input Pins — 50 1000 nA VSS  VPIN  VDD,

Pin at high-impedance

DI55 MCLR — 50 1000 nA VSS VPIN VDD

DI56 OSC1 — 50 1000 nA VSS VPIN VDD,

XT and HS modes

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: Refer to Table 1-2 for I/O pins buffer types.

 2005-2012 Microchip Technology Inc. DS39747F-page 223

PIC24FJ128GA010 FAMILY

TABLE 27-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

DC CHARACTERISTICS St andard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  T

A  +85°C for Industrial

Param

No. Sym Characteristic Min Typ(1)Max Units Conditions

VOL Output Low Volt ag e

DO10 I/O Ports — — 0.4 V IOL = 8.5 mA, VDD = 3.6V

——0.4VI

OL = 6.0 mA, VDD = 2.0V

DO16 OSC2/CLKO — — 0.4 V IOL = 8.5 mA, VDD = 3.6V

——0.4VIOL = 6.0 mA, VDD = 2.0V

VOH Output High Volta ge

DO20 I/O Ports 3.0 — — V IOH = -3.0 mA, VDD = 3.6V

2.4 — — V IOH = -6.0 mA, VDD = 3.6V

1.65 — — V IOH = -1.0 mA, VDD = 2.0V

1.4 — — V IOH = -3.0 mA, VDD = 2.0V

DO26 OSC2/CLKO 2.4 — — V IOH = -6.0 mA, VDD = 3.6V

1.4 — — V IOH = -3.0 mA, VDD = 2.0V

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

PIC24FJ128GA010 FAMILY

DS39747F-page 224  2005-2012 Microchip Technology Inc.

TABLE 27-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise sta ted)

Operating temperature -40°C  TA  +85°C for Industrial

Param. Symbol Characteristic Min. Typ(1)Max. Units Conditions

IICL Input Low Injection Current

DI60a

0—-5

(2,5)mA

All pins except VDD, VSS,

AVDD, AVSS, MCLR, VCAP,

RB11, SOSCI, SOSCO, D+,

D-, VUSB and VBUS

IICH Input High Injection Current

DI60b

0—+5

(3,4,5)mA

All pins except VDD, VSS,

AVDD, AVSS, MCLR, VCAP,

RB11, SOSCI, SOSCO, D+,

D-, VUSB and VBUS, and all

5V tolerant pins(4)

IICT Total Input Injection Current

DI60c (sum of all I/O and control

pins) -20(6)—+20

(6)mA Absolute instantaneous sum

of all ± input injection cur-

rents from all I/O pins

(| I

ICL + | IICH |)  IICT

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

2: Characterized but not tested.

3: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not

tested.

4: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.

5: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.

6: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted

provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not

exceed the specified limit. Characterized but not tested.

 2005-2012 Microchip Technology Inc. DS39747F-page 225

PIC24FJ128GA010 FAMILY

TABLE 27-12: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

TABLE 27-11: DC CHARACTERISTICS: PROGRAM MEMORY

DC CHAR ACTE RISTI CS S tandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  T

A  +85°C for Industrial

Param

No. Sym Characteristic Min Typ(1)Max Units Conditions

Program Flash Memory

D130 EPCell Endurance 100 1K — E/W -40C to +85C

D131 VPR VDD for Read VMIN —3.6VVMIN = Minimum operating

voltage

D132B VPEW VDD for Self-Timed

Erase/Write

2.25 — 3.6 V

D133A TIW Self-Timed Write Cycle Time — 3 — ms

D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications

are violated

D135 IDDP Supply Current During

Programming

—10 —mA

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

Operating Conditions: -40°C < T

A < +85°C (unless otherwise stated)

Param

No. Sym Characteristics Min Typ Max Units Comments

VRGOUT Regulator Output Voltage — 2.5 — V

CEFC External Filter Capacitor Value 4.7 10 — F Series resistance < 3 Ohm recommended;

< 5 Ohm required.

TVREG Voltage Regulator Start-up Time — 500 — s ENVREG = VDD

TPWRT Power-up Timer Period — 64 — ms ENVREG = VSS

TBG Band Gap Reference Start-up Time — — 1 ms

PIC24FJ128GA010 FAMILY

DS39747F-page 226  2005-2012 Microchip Technology Inc.

TABLE 27-13: COMPARATOR SPECIFICATIONS

TABLE 27-14: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS

Operating Condit ions : 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)

Param

No. Symbol Characteristic Min Typ Max Units Comments

D300 VIOFF Input Offset Voltage*—10 30mV

D301 VICM Input Common Mode Voltage*0—VDD V

D302 CMRR Common Mode Rejection

Ratio*

55 — — dB

300 TRESP Response Time*(1)— 150 400 ns

301 TMC2OV Comparator Mode Change to

Output Valid*

—— 10s

* Parameters are characterized but not tested.

Note 1: Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions

from VSS to VDD.

Operating Condit ions : 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)

Param

No. Symbol Characteristic Min Typ Max Units Comments

VRD310 CVRES Resolution VDD/24 — VDD/32 LSb

VRD311 CVRAA Absolute Accuracy — — AVDD – 1.5 LSb

VRD312 CVRUR Unit Resistor Value (R) — 2k — 

VR310 TSET Settling Time(1)—— 10s

Note 1: Settling time measured while CVRR = 1 and CVR<3:0> bits transition from ‘0000’ to ‘1111’.

 2005-2012 Microchip Technology Inc. DS39747F-page 227

PIC24FJ128GA010 FAMILY

27.2 AC Characteristics and Ti ming Parameters

The information contained in this section defines the PIC24FJ128GA010 AC characteristics and timing parameters.

TABLE 27-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

FIGURE 27-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

TABLE 27-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

AC CHARACTERISTICS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

Operating voltage VDD range as described in Sectio n 27.1 “ DC Charac teristics”.

Param

No. Symbol Characteristic Min Typ(1)Max Units Conditions

DO50 COSC2 OSC2/CLKO Pin — — 15 pF In XT and HS modes when

external clock is used to drive

OSC1

DO56 CIO All I/O Pins and OSC2 — — 50 pF EC mode

DO58 CBSCLx, SDAx — — 400 pF In I2C™ mode

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

VDD/2

VSS

RL= 464

CL= 50 pF for all pins except OSC2

15 pF for OSC2 output

Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2

PIC24FJ128GA010 FAMILY

DS39747F-page 228  2005-2012 Microchip Technology Inc.

FIGURE 27-3: EXTERNAL CLOCK TIMING

OSC1

CLKO

Q4 Q1 Q2 Q3 Q4 Q1

OS20

OS25

OS30 OS30

OS40 OS41

OS31OS31

Q1 Q2 Q3 Q4 Q2 Q3

TABLE 27-17: EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

Param

No. Sym Characteristic Min Typ(1)Max Units Conditions

OS10 FOSC External CLKI Frequency

(external clocks allowed

only in EC mode)

—

MHz

EC mode

ECPLL mode

Oscillator Frequency 3.5

3.5

—

MHz

kHz

XT mode

XTPLL mode

HS mode

SOSC

OS20 T

OSC TOSC = 1/FOSC — — — — See Parameter OS10

for FOSC value

OS25 T

CY Instruction Cycle Time(2)62.5 — DC ns

OS30 TosL,

To s H

External Clock in (OSC1)

High or Low Time

0.45 x TOSC ——nsEC mode

OS31 TosR,

To s F

External Clock in (OSC1)

Rise or Fall Time

— — 20 ns EC mode

OS40 TckR CLKO Rise Time(3) — 6 10 ns

OS41 TckF CLKO Fall Time(3)— 6 10 ns

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: Instruction cycle period (T

CY) equals two times the input oscillator time base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with

the device executing code. Exceeding these specified limits may result in an unstable oscillator operation

and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an

external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “Max.” cycle time

limit is “DC” (no clock) for all devices.

3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. CLKO is low for the

Q1-Q2 period (1/2 T

CY) and high for the Q3-Q4 period (1/2 TCY).

 2005-2012 Microchip Technology Inc. DS39747F-page 229

PIC24FJ128GA010 FAMILY

TABLE 27-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V)

AC CHARACTERISTICS St andard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

Param

No. Sym Characteristic(1)Min Typ(2)Max Units Conditions

OS50 FPLLI PLL Input Frequency

Range

3 — 8 MHz ECPLL, HSPLL, XTPLL

modes

OS51 FSYS PLL Output Frequency

Range

12 — 32 MHz

OS52 TLOCK PLL Start-up Time

(Lock Time)

—— 2ms

OS53 DCLK CLKO Stability (Jitter) -2 1 +2 %

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

TABLE 27-19: INTERNAL RC OSCILLATOR SPECIFICATIONS

AC CHARACTERISTICS

Industrial

Standard O pe rati ng Conditions: 2 .0V to 3. 6V (unless other wise stated)

Operating temperature -40°C  T

A +85°C for Industrial

Param

No. Sym Characteristic(1)Min Typ Max Units Conditions

TFRC FRC Start-up Time —15—µs

TLPRC LPRC Start-up Time — 500 — µs

Note 1: These parameters are characterized but not tested in manufacturing.

TABLE 27-20: INTERNAL RC OSCILLATOR ACCURACY

AC CHARACTERISTICS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  T

A  +85°C for Industrial

Param

No. Characteristic Min Typ Max Units Conditions

Internal FRC Accuracy @ 8 MHz(1)

F20 FRC -2 — +2 % +25°C VDD = 3.0 - 3.6V

-5 — +5 % -40°C  TA +85°C VDD = 3.0 - 3.6V

F21 LPR C @ 31 kH z(1)-15 — +15 % -40°C  TA +85°C VDD = 3.0 - 3.6V

Note 1: Change of LPRC frequency as VDD changes.

PIC24FJ128GA010 FAMILY

DS39747F-page 230  2005-2012 Microchip Technology Inc.

FIGURE 27-4: CLKO AND I/O TIMING CHARACTERISTICS

Note: Refer to Figure 27-2 for load conditions.

I/O Pin

(Input)

I/O Pin

(Output)

DI35

Old Value New Value

DI40

DO31

DO32

TABLE 27-21: CLKO AND I/O TIMING REQUIREMENTS

AC CHARACTERISTICS St andard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  T

A  +85°C for Industrial

Param

No. Sym Characteristic Min Typ(1)Max Units Conditions

DO31 TIOR Port Output Rise Time — 10 25 ns

DO32 TIOF Port Output Fall Time — 10 25 ns

DI35 TINP INTx Pin High or Low

Time (output)

20 — — ns

DI40 TRBP CNx High or Low Time

(input)

2——TCY

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

 2005-2012 Microchip Technology Inc. DS39747F-page 231

PIC24FJ128GA010 FAMILY

TABLE 27-22: A/D MODULE SPECIFICATIONS

AC CHARACTERISTICS Stan dard O perat ing Condit ions: 2.0V t o 3.6V (unl ess otherwise stated)

Operating temperature -40°C  TA  +85°C

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

Device Sup p ly

AD01 AVDD Module VDD Supply Greater of

VDD – 0.3

or 2.0

— Lesser of

VDD + 0.3

or 3.6

AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V

Reference Inputs

AD05 VREFH Reference Voltage High AVSS + 1.7 — AVDD V

AD06 VREFL Reference Voltage Low AVSS —AVDD – 1.7 V

AD07 VREF Absolute Reference

Voltage

AVSS – 0.3 — AVDD + 0.3 V

AD08 IVREF Reference Voltage Input

Current

——1.25mA

AD09 ZVREF Reference Input

Impedance

—10K—

Analog Input

AD10 VINH-VINL Full-Scale Input Span(2)VREFL VREFH V

AD11 VIN Absolute Input Voltage AVSS – 0.3 AVDD + 0.3 V

AD12 — Leakage Current — ±0.001 ±0.610 AVINL = AVSS = VREFL = 0V,

AVDD = VREFH = 5V,

Source Impedance = 2.5 k

AD14 VINL Absolute VINL Input Voltage AVSS – 0.3 AVDD/2 V

AD17 RIN Recommended

Impedance of Analog Voltage

— — 2.5K

A/D Accuracy

AD20a Nr Resolution 10 data bits bits

AD21a INL Integral Nonlinearity(2)—+1<±2LSbVINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

AD22a DNL Differential Nonlinearity(2)—+0.5 <±1 LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

AD23a GERR Gain Error(2)—+1±3LSbVINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

AD24a EOFF Offset Error(2)—+1±2LSbVINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

AD25a — Monotonicity(1)— — — — Guaranteed

Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

2: Measurements are taken with external VREF+ and VREF- used as the A/D voltage reference.

PIC24FJ128GA010 FAMILY

DS39747F-page 232  2005-2012 Microchip Technology Inc.

TABLE 27-23: A/D CONVERSION TIMING REQUIREMENTS(1)

AC CHARACTERISTICS St andard Operating Conditions: 2.0V to 3.6V (unless

otherwise stated)

Operating temperature -40°C  T

A  +85°C for Industrial

Param

No. Sym Characteristic Min Typ Max Units Conditions

AD50 TAD A/D Clock Period 75 — — ns TCY = 75 ns, ADxCON3

is in default state

AD51 tRC A/D Internal RC Oscillator

Period

—250—ns

Conversion Rate

AD55 tCONV Conversion Time — 12 — TAD

AD56 FCNV Throughput Rate — — 500 ksps AVDD > 2.7V

AD57 tSAMP Sample Time — 1 — TAD

Clock Parameters

AD61 tPSS Sample Start Delay from

Setting Sample bit (SAMP)

2—3TAD

Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

 2005-2012 Microchip Technology Inc. DS39747F-page 233

PIC24FJ128GA010 FAMILY

28.0 PACKAGING INFORMATION

28.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

64-Lead TQFP (10x10x1 mm)

XXXXXXXXXX

YYWWNNN

Example

PIC24FJ128

GA006-I/

1110017

80-Lead TQFP (12x12x1 mm)

XXXXXXXXXXXX

YYWWNNN

Example

PIC24FJ128GA

008-I/PT

1110017

100-Lead TQFP (12x12x1 mm)

XXXXXXXXXXXX

YYWWNNN

Example

PIC24FJ128GA

010-I/PT

1110017

100-Lead TQFP (14x14x1 mm)

XXXXXXXXXXXX

YYWWNNN

Example

PIC24FJ128GA

010-I/PF

1110017

PIC24FJ128GA010 FAMILY

DS39747F-page 234  2005-2012 Microchip Technology Inc.

XXXXXXXXXXX

64-Lead QFN (9x9x0.9 mm)

XXXXXXXXXXX

YYWWNNN

PIC24FJ128

Example

GA010-I/MR

1150017

 2005-2012 Microchip Technology Inc. DS39747F-page 235

PIC24FJ128GA010 FAMILY

28.2 Package Details

The following sections give the technical details of the packages.

/HDG3ODVWLF7KLQ4XDG)ODWSDFN37±[[PP%RG\PP>74)3@

1RWHV

 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD

 &KDPIHUVDWFRUQHUVDUHRSWLRQDOVL]HPD\YDU\

 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH

 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV 0,//,0(7(56

'LPHQVLRQ/LPLWV 0,1 120 0$;

1XPEHURI/HDGV 1 

/HDG3LWFK H %6&

2YHUDOO+HLJKW $ ± ± 

0ROGHG3DFNDJH7KLFNQHVV $   

6WDQGRII $  ± 

)RRW/HQJWK /   

)RRWSULQW / 5()

)RRW$QJOH   

2YHUDOO:LGWK ( %6&

2YHUDOO/HQJWK ' %6&

0ROGHG3DFNDJH:LGWK ( %6&

0ROGHG3DFNDJH/HQJWK ' %6&

/HDG7KLFNQHVV F  ± 

/HDG:LGWK E   

0ROG'UDIW$QJOH7RS   

0ROG'UDIW$QJOH%RWWRP   

NOTE 1 123 NOTE 2

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

PIC24FJ128GA010 FAMILY

DS39747F-page 236  2005-2012 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2005-2012 Microchip Technology Inc. DS39747F-page 237

PIC24FJ128GA010 FAMILY

80-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Chamfers at corners are optional; size may vary.

3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Leads N 80

Lead Pitch e 0.50 BSC

Overall Height A – – 1.20

Molded Package Thickness A2 0.95 1.00 1.05

Standoff A1 0.05 – 0.15

Foot Length L 0.45 0.60 0.75

Footprint L1 1.00 REF

Foot Angle φ0° 3.5° 7°

Overall Width E 14.00 BSC

Overall Length D 14.00 BSC

Molded Package Width E1 12.00 BSC

Molded Package Length D1 12.00 BSC

Lead Thickness c 0.09 – 0.20

Lead Width b 0.17 0.22 0.27

Mold Draft Angle Top α11° 12° 13°

Mold Draft Angle Bottom β11° 12° 13°

NOTE 1123 NOTE 2

βφ

Microchip Technology Drawing C04-092B

PIC24FJ128GA010 FAMILY

DS39747F-page 238  2005-2012 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2005-2012 Microchip Technology Inc. DS39747F-page 239

PIC24FJ128GA010 FAMILY

100-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Chamfers at corners are optional; size may vary.

3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Leads N 100

Lead Pitch e 0.40 BSC

Overall Height A – – 1.20

Molded Package Thickness A2 0.95 1.00 1.05

Standoff A1 0.05 – 0.15

Foot Length L 0.45 0.60 0.75

Footprint L1 1.00 REF

Foot Angle φ0° 3.5° 7°

Overall Width E 14.00 BSC

Overall Length D 14.00 BSC

Molded Package Width E1 12.00 BSC

Molded Package Length D1 12.00 BSC

Lead Thickness c 0.09 – 0.20

Lead Width b 0.13 0.18 0.23

Mold Draft Angle Top α11° 12° 13°

Mold Draft Angle Bottom β11° 12° 13°

123

NOTE 1NOTE 2

A1 L1

Microchip Technology Drawing C04-100B

PIC24FJ128GA010 FAMILY

DS39747F-page 240  2005-2012 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2005-2012 Microchip Technology Inc. DS39747F-page 241

PIC24FJ128GA010 FAMILY

/HDG3ODVWLF7KLQ4XDG)ODWSDFN3)±[[PP%RG\PP>74)3@

1RWHV

 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD

 &KDPIHUVDWFRUQHUVDUHRSWLRQDOVL]HPD\YDU\

 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH

 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV 0,//,0(7(56

'LPHQVLRQ/LPLWV 0,1 120 0$;

1XPEHURI/HDGV 1 

/HDG3LWFK H %6&

2YHUDOO+HLJKW $ ± ± 

0ROGHG3DFNDJH7KLFNQHVV $   

6WDQGRII $  ± 

)RRW/HQJWK /   

)RRWSULQW / 5()

)RRW$QJOH   

2YHUDOO:LGWK ( %6&

2YHUDOO/HQJWK ' %6&

0ROGHG3DFNDJH:LGWK ( %6&

0ROGHG3DFNDJH/HQJWK ' %6&

/HDG7KLFNQHVV F  ± 

/HDG:LGWK E   

0ROG'UDIW$QJOH7RS   

0ROG'UDIW$QJOH%RWWRP   

NOTE 1 NOTE 2

123

LA1 L1

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

PIC24FJ128GA010 FAMILY

DS39747F-page 242  2005-2012 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2005-2012 Microchip Technology Inc. DS39747F-page 243

PIC24FJ128GA010 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC24FJ128GA010 FAMILY

DS39747F-page 244  2005-2012 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2005-2012 Microchip Technology Inc. DS39747F-page 245

PIC24FJ128GA010 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC24FJ128GA010 FAMILY

DS39747F-page 246  2005-2012 Microchip Technology Inc.

NOTES:

 2005-2012 Microchip Technology Inc. DS39747F-page 247

PIC24FJ128GA010 FAMILY

APPENDIX A: REVISION HISTORY

Revision A (September 2005)

Original data sheet for PIC24FJ128GA010 family

devices.

Revision B (March 2006)

Update of electrical specifications.

Revision C (June 2006)

Update of electrical specifications.

Revision D (September 2007)

Minor changes in the overall data sheet

Revision E (October 2009)

Updated to remove Preliminary status.

Revision F (January 2012)

Added Section 2.0 “Guidelines for Getting Started

with 16-bit Microcontrollers”. In Section 28.0

“Packaging Information”, Land Patterns of all the

packaging have been added. Minor edits to text

throughout the document.

PIC24FJ128GA010 FAMILY

DS39747F-page 248  2005-2012 Microchip Technology Inc.

NOTES:

 2005-2012 Microchip Technology Inc. DS39747F-page 249

PIC24FJ128GA010 FAMILY

INDEX

A/D

Conversion Timing Requirements............................. 232

Module Specifications ............................................... 231

Characteristics .......................................................... 227

Load Conditions ........................................................ 227

Temperature and Voltage Specifications .................. 227

Alternate Interrupt Vector Table (AIVT) .............................. 63

Arithmetic Logic Unit (ALU)................................................. 30

Assembler

MPASM Assembler................................................... 214

Block Diagrams

10-Bit High-Speed A/D Converter............................. 180

16-Bit Timer1 Module................................................ 111

8-Bit Multiplexed Address and Data Application ....... 162

Accessing Program Memory with

Table Instructions ............................................... 48

Addressable Parallel Slave Port ............................... 160

Comparator I/O Operating Modes............................. 189

Comparator Voltage Reference ................................ 193

Connections for On-Chip Voltage Regulator............. 201

Device Clock............................................................... 97

I2C............................................................................. 138

Input Capture ............................................................ 119

LCD Control, Byte Mode........................................... 162

Legacy Parallel Slave Port........................................ 160

Master Mode, Demultiplexed Addressing ................. 160

Master Mode, Fully Multiplexed Addressing ............. 161

Master Mode, Partially Multiplexed Addressing ........ 161

Multiplexed Addressing Application .......................... 161

Output Compare Module........................................... 121

Parallel EEPROM (Up to 15-Bit Address, 16-Bit Data)...

162

Parallel EEPROM (Up to 15-Bit Address, 8-Bit Data).....

162

Partially Multiplexed Addressing Application ............ 161

PIC24F CPU Core ...................................................... 26

PIC24FJ128GA010 Family (General) ......................... 10

PMP Module ............................................................. 153

Program Space Visibility Operation ............................ 49

Reset System.............................................................. 57

RTCC ........................................................................ 163

Shared Port Structure ............................................... 107

SPI Master, Frame Master Connection..................... 135

SPI Master, Frame Slave Connection....................... 135

SPI Master/Slave Connection (Enhanced

Buffer Modes) ................................................... 134

SPI Master/Slave Connection (Standard Mode) ....... 134

SPI Slave, Frame Master Connection....................... 135

SPI Slave, Frame Slave Connection......................... 135

SPIx Module (Enhanced Mode) ................................ 129

SPIx Module (Standard Mode).................................. 128

Timer2 and Timer4 (16-Bit Synchronous)................. 115

Timer2/3 and Timer4/5 (32-Bit)................................. 114

Timer3 and Timer5 (16-Bit Synchronous)................. 115

UARTx ...................................................................... 145

Watchdog Timer (WDT) ............................................ 202

C Compilers

MPLAB C18.............................................................. 214

Clock Switching

Enabling.................................................................... 103

Operation.................................................................. 103

Oscillator Sequence ................................................. 103

Code Examples

Basic Code Sequence for Clock Switching .............. 104

Erasing a Program Memory Block.............................. 54

Initiating a Programming Sequence ........................... 55

Loading Write Buffers ................................................. 55

Port Write/Read ........................................................ 108

Programming a Single Word of Flash

Program Memory................................................ 56

PWRSAV Instruction Syntax .................................... 105

Comparator Module .......................................................... 189

Comparator Voltage Reference ........................................ 193

Configuring ............................................................... 193

Configuration Bits ............................................................. 195

Configuration Register Protection..................................... 203

Core Features....................................................................... 7

16-Bit Architecture ........................................................ 7

Easy Migration .............................................................. 8

Oscillator Options, Features ......................................... 7

PIC24FJ128GA010 Family Devices ............................. 9

Power-Saving Technology............................................ 7

CPU .................................................................................... 25

Control Registers ........................................................ 28

Programmer’s Model .................................................. 27

CPU Clocking Scheme ....................................................... 98

CRC

Example Setup ......................................................... 175

Operation in Power Save Modes.............................. 177

Overview................................................................... 175

Registers .................................................................. 175

User Interface ........................................................... 176

Customer Change Notification Service............................. 253

Customer Notification Service .......................................... 253

Customer Support............................................................. 253

CVRR

CVrsrc....................................................................... 193

Data Memory

Address Space ........................................................... 33

Width .................................................................. 33

Memory Map for PIC24F128GA010

Family Devices ................................................... 33

Near Data Space ........................................................ 34

Organization and Alignment ....................................... 34

SFR Space ................................................................. 34

Software Stack ........................................................... 46

PIC24FJ128GA010 FAMILY

DS39747F-page 250  2005-2012 Microchip Technology Inc.

DC Characteristics ............................................................ 218

Comparator Voltage Reference

Specifications.................................................... 226

I/O Pin Input Specifications............................... 222, 224

I/O Pin Output Specifications .................................... 223

Idle Current (IIDLE) .................................................... 220

Operating Current (IDD)............................................. 219

Operating MIPS vs. Voltage...................................... 218

Power-Down Current (IPD) ........................................ 221

Program Memory ......................................................225

Temperature and Voltage Specifications .................. 218

Thermal Operating Conditions .................................. 218

Thermal Packaging ...................................................218

Development Support ....................................................... 213

Electrical Characteristics................................................... 217

Absolute Maximum Ratings ......................................217

ENVREG Pin.....................................................................201

Equations

A/D Conversion Clock Period ................................... 186

Calculating the PWM Period ..................................... 123

Calculation for Maximum PWM Resolution...............123

CRC Polynomial........................................................ 175

Relationship Between Device and SPI

Clock Speed...................................................... 136

UARTx Baud Rate with BRGH = 0............................146

UARTx Baud Rate with BRGH = 1............................146

Errata .................................................................................... 6

Examples

Baud Rate Error Calculation (BRGH = 0) ................. 146

PWM Period and Duty Cycle Calculations................ 124

Setting RTCWREN Bit in MPLAB C30...................... 164

Flash Configuration Words.......................................... 32, 195

Flash Program Memory....................................................... 51

Control Registers ........................................................ 52

Enhanced ICSP .......................................................... 52

JTAG Operation ..........................................................52

Operations .................................................................. 52

Programming a Single Word....................................... 56

Programming Algorithm .............................................. 54

RTSP Operation.......................................................... 52

Table Instructions........................................................ 51

FSCM

and Device Resets...................................................... 61

Delay for Crystal and PLL Clock Sources................... 61

I/O Ports ............................................................................ 107

Configuring Analog Pins ........................................... 108

Voltage Considerations..................................... 108

Input Change Notification.......................................... 109

Open-Drain Configuration ......................................... 108

Parallel I/O (PIO).......................................................107

Write/Read Timing .................................................... 108

I2C

Clock Rates............................................................... 139

Communicating as Master in a Single

Master Environment.......................................... 137

Setting Baud Rate When Operating as

Bus Master........................................................ 139

Slave Address Masking ............................................ 139

Implemented Interrupt Vectors (table)................................. 65

In-Circuit Debugger........................................................... 203

In-Circuit Serial Programming (ICSP)............................... 203

Input Capture.................................................................... 119

Registers .................................................................. 120

Instruction Set

Overview................................................................... 207

Summary .................................................................. 205

Inter-Integrated Circuit (I2C) ............................................. 137

Internal RC Oscillator

Use with WDT........................................................... 202

Internet Address ............................................................... 253

Interrupt

Setup Procedures

Initialization......................................................... 96

Interrupt Control and Status Registers ............................... 66

IECx ............................................................................ 66

IFSx ............................................................................ 66

INTCON1, INTCON2 .................................................. 66

IPCx ............................................................................ 66

Interrupt Controller.............................................................. 63

Interrupt Vector Table (IVT) ................................................ 63

Interrupts

Setup Procedure,

Interrupt Disable ................................................. 96

Setup Procedures ....................................................... 96

Interrupt Service Routine (ISR) .......................... 96

Trap Service Routine (TSR) ............................... 96

Memory Organization ......................................................... 31

Microchip Internet Web Site.............................................. 253

MPLAB ASM30 Assembler, Linker, Librarian ................... 214

MPLAB Integrated Development

Environment Software .............................................. 213

MPLAB PM3 Device Programmer .................................... 216

MPLAB REAL ICE In-Circuit Emulator System ................ 215

MPLINK Object Linker/MPLIB Object Librarian ................ 214

On-Chip Voltage Regulator............................................... 201

Brown-out Reset (BOR)............................................ 201

Power-on Reset (POR)............................................. 201

Power-up Requirements ........................................... 201

Oscillator Configuration ...................................................... 97

Clock Switching Mode Configuration Bits ................... 98

Control Registers ........................................................ 99

CLKDIV............................................................... 99

OSCCON............................................................ 99

OSCTUN ............................................................ 99

Output Compare ............................................................... 121

Continuous Output Pulse Generation Setup............. 122

Modes of Operation .................................................. 121

Pulse-Width Modulation.................................... 123

Pulse-Width Modulation

Duty Cycle ........................................................ 123

PWM Period ..................................................... 123

Single Output Pulse Generation Setup..................... 121

 2005-2012 Microchip Technology Inc. DS39747F-page 251

PIC24FJ128GA010 FAMILY

Packaging ......................................................................... 233

Details ....................................................................... 235

Marking ..................................................................... 233

Parallel Master Port (PMP) ............................................... 153

PIC24FJ128GA010 Family

Pinout Descriptions ..................................................... 11

Pin Diagrams ........................................................................ 2

POR and Long Oscillator Start-up Times............................ 61

Power-Saving Features .................................................... 105

Clock Switching, Clock Frequency............................ 105

Doze Modes.............................................................. 106

Instruction-Based Modes .......................................... 105

Idle .................................................................... 106

Sleep................................................................. 105

Interrupts, Coincident with Power-Save

Instructions ....................................................... 106

Selective Peripheral Control ..................................... 106

Program Address Space..................................................... 31

Memory Map for PIC24FJ128GA010

Family Devices ................................................... 31

Program and Data Memory Spaces

Interfacing ................................................................... 46

Program Memory

Data Access Using Table Instructions ........................ 48

Hard Memory Vectors................................................. 32

Interrupt Vector ........................................................... 32

Organization................................................................ 32

Reading Data Using Program Space Visibility............ 49

Reset Vector ............................................................... 32

Table Instructions

TBLRDH ............................................................. 48

TBLRDL .............................................................. 48

Program Space

Address Construction.................................................. 47

Addressing .................................................................. 46

Data Access from, Address Generation...................... 47

Program Verification and Code Protection........................ 203

Programmer’s Model........................................................... 25

Reader Response ............................................................. 254

A/D .............................................................................. 41

CRC ............................................................................ 45

Dual Comparator......................................................... 44

I2C1 ............................................................................ 39

I2C2 ............................................................................ 39

ICN.............................................................................. 37

Input Capture .............................................................. 38

Interrupt Controller...................................................... 36

NVM ............................................................................ 45

Output Compare ......................................................... 38

Pad Configuration ....................................................... 43

Parallel Master/Slave Port .......................................... 44

PMD ............................................................................ 45

PORTA........................................................................ 41

PORTB........................................................................ 42

PORTC ....................................................................... 42

PORTD ....................................................................... 42

PORTE........................................................................ 43

PORTF........................................................................ 43

PORTG ....................................................................... 43

Real-Time Clock and Calendar (RTCC) ..................... 44

SPI1 ............................................................................ 40

SPI2............................................................................ 40

System........................................................................ 45

Timer .......................................................................... 37

UART1........................................................................ 40

UART2........................................................................ 40

Registers

AD1CHS (A/D Input Select)...................................... 184

AD1CON1 (A/D Control 1)........................................ 181

AD1CON2 (A/D Control 2)........................................ 182

AD1CON3 (A/D Control 3)........................................ 183

AD1CSSL (A/D Input Scan Select)........................... 185

AD1PCFG (A/D Port Configuration) ......................... 185

ALCFGRPT (Alarm Configuration) ........................... 167

ALMINSEC (Alarm Minutes and

Seconds Value) ................................................ 171

ALMTHDY (Alarm Month and Day Value) ................ 170

ALWDHR (Alarm Weekday and Hours Value) ......... 170

CLKDIV (Clock Divider) ............................................ 101

CMCON (Comparator Control) ................................. 190

CORCON (Core Control) ...................................... 29, 67

CRCCON (CRC Control) .......................................... 177

CVRCON (Comparator Voltage

Reference Control) ........................................... 194

DEVID (Device ID).................................................... 199

DEVREV (Device Revision)...................................... 200

Flash Configuration Word 1...................................... 196

Flash Configuration Word 2...................................... 198

I2CxCON (I2Cx Control)........................................... 140

I2CxMSK (I2Cx Slave Mode Address Mask)............ 144

I2CxSTAT (I2Cx Status) ........................................... 142

ICxCON (Input Capture x Control)............................ 120

IEC0 (Interrupt Enable Control 0) ............................... 75

IEC1 (Interrupt Enable Control 1) ............................... 76

IEC2 (Interrupt Enable Control 2) ............................... 77

IEC3 (Interrupt Enable Control 3) ............................... 78

IEC4 (Interrupt Enable Control 4) ............................... 79

IFS0 (Interrupt Flag Status 0) ..................................... 70

IFS1 (Interrupt Flag Status 1) ..................................... 71

IFS2 (Interrupt Flag Status 2) ..................................... 72

IFS3 (Interrupt Flag Status 3) ..................................... 73

IFS4 (Interrupt Flag Status 4) ..................................... 74

INTCON1 (Interrupt Control 1) ................................... 68

INTCON2 (Interrupt Control 2) ................................... 69

INTTREG (Interrupt Control and Status) .................... 95

IPC0 (Interrupt Priority Control 0) ............................... 80

IPC1 (Interrupt Priority Control 1) ............................... 81

IPC10 (Interrupt Priority Control 10) ........................... 90

IPC11 (Interrupt Priority Control 11) ........................... 90

IPC12 (Interrupt Priority Control 12) ........................... 91

IPC13 (Interrupt Priority Control 13) ........................... 92

IPC15 (Interrupt Priority Control 15) ........................... 93

IPC16 (Interrupt Priority Control 16) ........................... 94

IPC2 (Interrupt Priority Control 2) ............................... 82

IPC3 (Interrupt Priority Control 3) ............................... 83

IPC4 (Interrupt Priority Control 4) ............................... 84

IPC5 (Interrupt Priority Control 5) ............................... 85

IPC6 (Interrupt Priority Control 6) ............................... 86

IPC7 (Interrupt Priority Control 7) ............................... 87

IPC8 (Interrupt Priority Control 8) ............................... 88

IPC9 (Interrupt Priority Control 9) ............................... 89

MINSEC (Minutes and Seconds Value) ................... 169

MTHDY (Month and Day Value)............................... 168

NVMCON (Flash Memory Control)............................. 53

OCxCON Output Compare x Control) ...................... 125

OSCCON (Oscillator Control)..................................... 99

PIC24FJ128GA010 FAMILY

DS39747F-page 252  2005-2012 Microchip Technology Inc.

OSCTUN (FRC Oscillator Tune) ............................... 102

PADCFG1 (Pad Configuration Control) .................... 166

PMADDR (Parallel Port Address) .............................157

PMAEN (Parallel Port Enable) .................................. 157

PMCON (Parallel Port Control) ................................. 154

PMMODE (Parallel Port Mode)................................. 156

PMSTAT (Parallel Port Status) ................................. 158

RCFGCAL (RTCC Calibration

and Configuration) ............................................ 165

RCON (Reset Control) ................................................ 58

SPIxCON1 (SPIx Control 1)...................................... 132

SPIxCON2 (SPIx Control 2)...................................... 133

SPIxSTAT (SPIx Status and Control) ....................... 130

SR (CPU STATUS)............................................... 28, 67

T1CON (Timer1 Control)........................................... 112

TxCON (Timer2/4 Control)........................................ 116

TyCON (Timer3/5 Control)........................................ 117

UxMODE (UARTx Mode).......................................... 148

UxSTA (UARTx Status and Control)......................... 150

WKDYHR (Weekday and Hours Value) .................... 169

YEAR (Year Value) ................................................... 168

Registers Map

CPU Core....................................................................35

Reset Sequence.................................................................. 63

Resets ................................................................................. 57

Clock Source Selection............................................... 59

Device Times .............................................................. 59

Revision History ................................................................ 247

RTCC

Alarm......................................................................... 172

Configuring........................................................ 172

Interrupt............................................................. 172

ALRMVAL Register Mappings .................................. 170

Calibration................................................................. 172

Control Registers ......................................................165

Module Registers ...................................................... 164

Mapping ............................................................ 164

RTCVAL Register Mapping....................................... 168

Serial Peripheral Interface (SPI) ....................................... 127

Software Simulator (MPLAB SIM)..................................... 215

Software Stack Pointer, Frame Pointer

CALL Stack Frame...................................................... 46

Special Features ...............................................................195

Code Protection ........................................................ 195

Flexible Configuration ...............................................195

In-Circuit Emulation...................................................195

In-Circuit Serial Programming (ICSP) .......................195

JTAG Boundary Scan Interface ................................ 195

Watchdog Timer (WDT) ............................................ 195

Special Function Register Reset States..............................61

Symbols Used in Opcode Descriptions.............................206

Table of Contents ................................................................. 5

Timer1 Module.................................................................. 111

Timer2/3 Module............................................................... 113

Timer4/5 Module............................................................... 113

Timing Diagrams

CLKO and I/O ........................................................... 230

External Clock........................................................... 228

Timing Requirements

Capacitive Loading on Output Pin ............................ 227

CLKO and I/O ........................................................... 230

External Clock........................................................... 228

Timing Specifications

Internal RC Oscillator................................................ 229

Internal RC Oscillator Accuracy................................ 229

PLL Clock ................................................................. 229

UARTx

Baud Rate Generator (BRG) .................................... 146

Break and Sync Transmit Sequence ........................ 147

Infrared Support........................................................ 147

IrDA

Built-in Encoder and Decoder........................... 147

External Support, Clock Output ........................ 147

Operation of UxCTS and UxRTS Control Pins ......... 147

Receiving in

8-Bit or 9-Bit Data Mode ................................... 147

Transmitting

8-Bit Data Mode................................................ 147

Transmitting in

9-Bit Data Mode................................................ 147

Universal Asynchronous Receiver Transmitter (UART) ... 145

VDDCORE/VCAP Pin ........................................................... 201

Watchdog Timer (WDT).................................................... 202

Control Register........................................................ 202

Programming Considerations ................................... 202

WWW Address ................................................................. 253

WWW, On-Line Support ....................................................... 6

 2005-2012 Microchip Technology Inc. DS39747F-page 253

PIC24FJ128GA010 FAMILY

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com. Under “Support”, click on

“Customer Change Notification” and follow the

registration instructions.

CUSTOMER SUPP ORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line

Customers should contact their distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technic al suppo rt is avail able throug h the we b site

at: http://microchip.com/support

PIC24FJ128GA010 FAMILY

DS39747F-page 254  2005-2012 Microchip Technology Inc.

READER RESP ONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip

product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our

documentation can better serve you, please FAX your comments to the Technical Publications Manager at

(480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

TO: Technical Publications Manager

RE: Reader Response

Total Pages Sent ________

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS39747FPIC24FJ128GA010 family

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

 2005-2012 Microchip Technology Inc. DS39747F-page 255

PIC24FJ128GA010 FAMILY

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Architecture 24 = 16-bit modified Harvard without DSP

Flash Memory Family FJ = Flash program memory

Product Group GA0 = General purpose microcontrollers

Pin Count 06 = 64-pin

08 = 80-pin

10 = 100-pin

Temperature Range I = -40C to +85C (Industrial)

Package PT = 64-Lead, 80-Lead, 100-Lead (12x12x1 mm)

TQFP (Thin Quad Flatpack)

PF = 100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack)

MR = 64-lead (9x9x0.9 mm) QFN (Quad Flatpack, No Lead)

Pattern Three-digit QTP, SQTP, Code or Special Requirements

(blank otherwise)

ES = Engineering Sample

Examples:

a) PIC24FJ128GA008-I/PT 301:

General purpose PIC24F, 96 Kbyte program

memory, 80-pin, Industrial temp.,

TQFP package, QTP pattern #301.

b) PIC24FJ128GA010-I/PT:

General purpose PIC24F, 128 Kbyte program

memory, 100-pin, Industrial temp.,

TQFP package.

Microchip T rademark

Architecture

Flash Memory Family

Program Memory Size (KB)

Product Group

Pin Coun t

Temperature Range

Package

Pattern

PIC 24 FJ 128 GA0 10 T - I / PT - X XX

Tape and Reel Flag (if applicable)

PIC24FJ128GA010 FAMILY

DS39747F-page 256  2005-2012 Microchip Technology Inc.

NOTES:

 2005-2012 Microchip Technology Inc. DS39747F-page 257

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient Code Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,

rfLAB, Select Mode, Total Endurance, TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN:978-1-61341-955-7

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code ho pping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS39747F-page 258  2005-2012 Microchip Technology Inc.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Web Address:

www.microchip.com

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Cleveland

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Los A n ge les

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

China - Hangzhou

Tel: 86-571-2819-3187

Fax: 86-571-2819-3189

China - Hong K ong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

ASIA/PACIFIC

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Japan - Osaka

Tel: 81-66-152-7160

Fax: 81-66-152-9310

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Taiwan - Ka ohs iung

Tel: 886-7-536-4818

Fax: 886-7-330-9305

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Cop e nha gen

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Worldwide Sales and Service

11/29/11