© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 8 1Publication Order Number:
MC74AC74/D
MC74AC74, MC74ACT74
Dual D-Type Positive
Edge-Triggered Flip-Flop
The MC74AC74/74ACT74 is a dual D−type flip−flop with
Asynchronous Clear and Set inputs and complementary (Q,Q)
outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage
level of the clock pulse and is not directly related to the transition time
of the positive-going pulse. After the Clock Pulse input threshold
voltage has been passed, the Data input is locked out and information
present will not be transferred to the outputs until the next rising edge
of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
Features
Outputs Source/Sink 24 mA
ACT74 Has TTL Compatible Inputs
These are Pb−Free Devices
CP1CD2
CP2
1314 12 11 10 9 8
21 34567
VCC
CD1 D1CP1SD1 Q1Q1
CD2 D2CP2SD2 Q2Q2
CD1
SD1
Q1
D1
SD2Q2
Q2
D2
GND
Q1
Figure 1. Pinout: 14−Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN FUNCTION
D1, D2Data Inputs
CP1, CP2Clock Pulse Inputs
CD1, CD2 Direct Clear Inputs
SD1, SD2 Direct Set Inputs
Q1, Q1, Q2,
Q2Outputs
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
www.onsemi.com
MARKING
DIAGRAMS
xxx = AC or ACT
A = Assembly Location
WL or L = Wafer Lot
Y = Year
WW or W = Work Week
G or G= Pb−Free Package
TSSOP−14
DT SUFFIX
CASE 948G
xxx
74
ALYWG
G
1
14
SOIC−14
D SUFFIX
CASE 751A
1
14
1
14
xxx74G
AWLYWW
1
14
(Note: Microdot may be in either location)
MC74AC74, MC74ACT74
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2
TRUTH TABLE (Each Half)
Inputs Outputs
SDCDCP D Q Q
L H X X H L
H L X X L H
L L X X H H
H H H H L
H H L L H
H H L X Q0Q0
NOTE: H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial;
= LOW-to-HIGH Clock Transition
Q0(Q0) = Previous Q(Q) before LOW-to-HIGH
Transition of Clock Figure 2. Logic Symbol
SD1
Q1
CP1
Q1
CD1
SD2
Q2
D2CP2
Q2
CD2
D1
SD
D
CP
CD
Q
Q
Figure 3. Logic Diagram
NOTE: This diagram is provided only for the understanding of
logic operations and should not be used to estimate
propagation delays.
MC74AC74, MC74ACT74
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3
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC DC Supply Voltage *0.5 to )7.0 V
VIDC Input Voltage *0.5 v VI v VCC )0.5 V
VODC Output Voltage (Note 1) *0.5 v VO v VCC )0.5 V
IIK DC Input Diode Current $20 mA
IOK DC Output Diode Current $50 mA
IODC Output Sink/Source Current $50 mA
ICC DC Supply Current per Output Pin $50 mA
IGND DC Ground Current per Output Pin $50 mA
TSTG Storage Temperature Range *65 to )150 °C
TLLead temperature, 1 mm from Case for 10 Seconds 260 °C
TJJunction temperature under Bias )150 °C
qJA Ther mal Resista nce (Note 2) SOIC
TSSOP 125
170 °C/W
PDPower Dissipation in Still Air at 85°C SOIC
TSSOP 125
170 mW
MSL Moisture Sensitivity Level 1
FRFlammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in
VESD ESD Withstand Voltage Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
> 2000
> 200
> 1000
V
ILatch−Up Latch−Up Performance Above VCC and Below GND at 85°C (Note 6) $100 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. IO absolute maximum rating must be observed.
2. The package thermal impedance is calculated in accordance with JESD51−7.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage AC 2.0 5.0 6.0 V
ACT 4.5 5.0 5.5
Vin, Vout DC Input V oltage, Output Voltage (Ref. to GND) 0 VCC V
tr, tfInput Rise and Fall Time (Note )
AC Devices except Schmitt Inputs
VCC @ 3.0 V 150
VCC @ 4.5 V 40 ns/V
VCC @ 5.5 V 25
tr, tfInput Rise and Fall Time (Note )
ACT Devices except Schmitt Inputs VCC @ 4.5 V 10 ns/V
VCC @ 5.5 V 8.0
TJJunction Temperature (PDIP) 140 °C
TAOperating Ambient Temperature Range −40 25 85 °C
IOH Output Current − High −24 mA
IOL Output Current − Low 24 mA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
MC74AC74, MC74ACT74
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4
DC CHARACTERISTICS
Symbol Parameter VCC
(V)
74AC 74AC
Unit Conditions
TA = +25°CTA =
−40°C to
+85°C
Typ Guaranteed Limits
VIH Minimum High Level
Input Voltage 3.0 1.5 2.1 2.1 VOUT = 0.1 V
4.5 2.25 3.15 3.15 V or VCC − 0.1 V
5.5 2.75 3.85 3.85
VIL Maximum Low Level
Input Voltage 3.0 1.5 0.9 0.9 VOUT = 0.1 V
4.5 2.25 1.35 1.35 V or VCC − 0.1 V
5.5 2.75 1.65 1.65
VOH Minimum High Level
Output Voltage 3.0 2.99 2.9 2.9 IOUT = −50 mA
4.5 4.49 4.4 4.4 V
5.5 5.49 5.4 5.4
V
*VIN = VIL or VIH
3.0 2.56 2.46 −12 mA
4.5 3.86 3.76 IOH −24 mA
5.5 4.86 4.76 −24 mA
VOL Maximum Low Level
Output Voltage 3.0 0.002 0.1 0.1 IOUT = 50 mA
4.5 0.001 0.1 0.1 V
5.5 0.001 0.1 0.1
V
*VIN = VIL or VIH
3.0 0.36 0.44 12 mA
4.5 0.36 0.44 IOL 24 mA
5.5 0.36 0.44 24 mA
IIN Maximum Input
Leakage Current 5.5 ±0.1 ±1.0 mAVI = VCC, GND
IOLD †Minimum Dynamic
Output Current 5.5 75 mA VOLD = 1.65 V Max
IOHD 5.5 −75 mA VOHD = 3.85 V Min
ICC Maximum Quiescent
Supply Current 5.5 4.0 40 mAVIN = VCC or GND
*All outputs loaded; thresholds on input associated with output under test.
Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
AC CHARACTERISTICS
Symbol Parameter VCC*
(V)
74AC 74AC
Unit Fig.
No.
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Min Typ Max Min Max
fmax Maximum Clock
Frequency 3.3 100 125 95 MHz 3−3
5.0 140 160 125
tPLH Propagation Delay
CDn or SDn to Qn or Qn
3.3 5.0 8.0 12.5 4.0 13.0 ns 3−6
5.0 3.5 6.0 9.0 3.0 10.0
tPHL Propagation Delay
CDn or SDn to Qn or Qn
3.3 4.0 10.5 12.0 3.5 13.5 ns 3−6
5.0 3.0 8.0 9.5 2.5 10.5
tPLH Propagation Delay
CPn to Qn or Qn
3.3 4.5 8.0 13.5 4.0 16.0 ns 3−6
5.0 3.5 6.0 10.0 3.0 10.5
tPHL Propagation Delay
CPn to Qn or Qn
3.3 3.5 8.0 14.0 3.5 14.5 ns 3−6
5.0 2.5 6.0 10.0 2.5 10.5
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
MC74AC74, MC74ACT74
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5
AC OPERATING REQUIREMENTS
Symbol Parameter VCC*
(V)
74AC 74AC
Unit Fig.
No.
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Typ Guaranteed Minimum
tsSet-up Time, HIGH or LOW 3.3 1.5 4.0 4.5 ns 3−9
Dn to CPn5.0 1.0 3.0 3.0
thHold Time, HIGH or LOW 3.3 −2.0 0.5 0.5 ns 3−9
Dn to CPn5.0 −1.5 0.5 0.5
twCPn or CDn or SDn 3.3 3.0 5.5 7.0 ns 3−6
Pulse Width 5.0 2.5 4.5 5.0
trec Recovery TIme 3.3 −2.5 0 0 ns 3−9
CDn or SDn to CP 5.0 −2.0 0 0
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
MC74AC74, MC74ACT74
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6
DC CHARACTERISTICS
Symbol Parameter VCC
(V)
74ACT 74ACT
Unit Conditions
TA = +25°CTA =
−40°C to
+85°C
Typ Guaranteed Limits
VIH Minimum High Level
Input Voltage 4.5 1.5 2.0 2.0 VVOUT = 0.1 V
5.5 1.5 2.0 2.0 or VCC − 0.1 V
VIL Maximum Low Level
Input Voltage 4.5 1.5 0.8 0.8 VVOUT = 0.1 V
5.5 1.5 0.8 0.8 or VCC − 0.1 V
VOH Minimum High Level
Output Voltage 4.5 4.49 4.4 4.4 VIOUT = −50 mA
5.5 5.49 5.4 5.4
*VIN = VIL or VIH
4.5 3.86 3.76 V IOH −24 mA
5.5 4.86 4.76 −24 mA
VOL Maximum Low Level
Output Voltage 4.5 0.001 0.1 0.1 VIOUT = 50 mA
5.5 0.001 0.1 0.1
*VIN = VIL or VIH
4.5 0.36 0.44 V IOL 24 mA
5.5 0.36 0.44 24 mA
IIN Maximum Input
Leakage Current 5.5 ±0.1 ±1.0 mAVI = VCC, GND
DICCT Additional Max. ICC/Input 5.5 0.6 1.5 mA VI = VCC 2.1 V
IOLD †Minimum Dynamic
Output Current 5.5 75 mA VOLD = 1.65 V Max
IOHD 5.5 −75 mA VOHD = 3.85 V Min
ICC Maximum Quiescent
Supply Current 5.5 4.0 40 mAVIN = VCC or GND
*All outputs loaded; thresholds on input associated with output under test.
Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS
Symbol Parameter VCC*
(V)
74ACT 74ACT
Unit Fig.
No.
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Min Typ Max Min Max
fmax Maximum Clock
Frequency 5.0 145 210 125 MHz 3−3
tPLH Propagation Delay
CDn or SDn to Qn or Qn5.0 3.0 5.5 9.5 2.5 10.5 ns 3−6
tPHL Propagation Delay
CDn or SDn to Qn or Qn5.0 3.0 6.0 10.0 3.0 11.5 ns 3−6
tPLH Propagation Delay
CPn to Qn or Qn5.0 4.0 7.5 11.0 4.0 13.0 ns 3−6
tPHL Propagation Delay
CPn to Qn or Qn5.0 3.5 6.0 10.0 3.0 11.5 ns 3−6
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
MC74AC74, MC74ACT74
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7
AC OPERATING REQUIREMENTS
Symbol Parameter VCC*
(V)
74ACT 74ACT
Unit Fig.
No.
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Typ Guaranteed Minimum
tsSet-up Time, HIGH or LOW 5.0 1.0 3.0 3.5 ns 3−9
Dn to CPn
thHold Time, HIGH or LOW 5.0 −0.5 1.0 1.0 ns 3−9
Dn to CPn
twCPn or CDn or SDn 5.0 3.0 5.0 6.0 ns 3−6
Pulse Width
trec Recovery TIme 5.0 −2.5 0 0 ns 3−9
CDn or SDn to CP
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
Symbol Parameter Value
Typ Unit Test Conditions
CIN Input Capacitance 4.5 pF VCC = 5.0 V
CPD Power Dissipation Capacitance 35 pF VCC = 5.0 V
ORDERING INFORMATION
Device Package Shipping
MC74AC74DG SOIC−14
(Pb−Free) 55 Units/Rail
MC74AC74DR2G SOIC−14
(Pb−Free) 2500/Tape & Reel
MC74AC74DTR2G TSSOP−14
(Pb−Free) 2500/Tape & Reel
MC74ACT74DG SOIC−14
(Pb−Free) 55 Units/Rail
MC74ACT74DR2G SOIC−14
(Pb−Free) 2500/Tape & Reel
MC74ACT74DTR2G TSSOP−14
(Pb−Free) 2500/Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC74AC74, MC74ACT74
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8
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
H
14 8
71
M
0.25 B M
C
h
X 45
SEATING
PLANE
A1
A
M
_
S
A
M
0.25 B S
C
b
13X
B
A
E
D
e
DET AIL A
L
A3
DET AIL A
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
D8.55 8.75 0.337 0.344
E3.80 4.00 0.150 0.157
A1.35 1.75 0.054 0.068
b0.35 0.49 0.014 0.019
L0.40 1.25 0.016 0.049
e1.27 BSC 0.050 BSC
A3 0.19 0.25 0.008 0.010
A1 0.10 0.25 0.004 0.010
M0 7 0 7
H5.80 6.20 0.228 0.244
h0.25 0.50 0.010 0.019
__ __
6.50
14X
0.58
14X
1.18
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC74AC74, MC74ACT74
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9
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−− 1.20 −− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.50 0.60 0.020 0.024
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25
(0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
____
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V S
T
L−U−
SEATING
PLANE
0.10 (0.004)
−T−
ÇÇÇ
ÇÇÇ
SECTION N−N
DETAIL E
JJ1
K
K1
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
−W−
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
−V−
14X REFK
N
N
7.06
14X
0.36 14X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC74AC74, MC74ACT74
www.onsemi.com
10
P
UBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
MC74AC74/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your loc
al
Sales Representative
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