74LVC07A
Hex buffer with open-drain outputs
Rev. 7 — 3 August 2020 Product data sheet
1. General description
The 74LVC07A is a hex buffer with open-drain outputs. Inputs can be driven from either 3.3 V or
5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V
environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
2. Features and benefits
5 V tolerant inputs and outputs (open-drain) for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Overvoltage tolerant inputs to 5.5 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
PackageType number
Temperature range Name Description Version
74LVC07AD -40 °C to +125 °C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LVC07APW -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LVC07ABQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
SOT762-1
Nexperia 74LVC07A
Hex buffer with open-drain outputs
4. Functional diagram
mna535
21 1A 1Y
43 2A 2Y
65 3A 3Y
89 4A 4Y
1011 5A 5Y
1213 6A 6Y
Fig. 1. Logic symbol
mna534
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
2
11
4
3
6
5
8
9
10
11
12
13
1
1
1
1
1
Fig. 2. IEC logic symbol
mna533
GND
A
Y
Fig. 3. Logic diagram for one gate
5. Pinning information
5.1. Pinning
74LVC07A
1A VCC
1Y 6A
2A 6Y
2Y 5A
3A 5Y
3Y 4A
GND 4Y
001aad066
1
2
3
4
5
6
7 8
10
9
12
11
14
13
Fig. 4. Pin configuration for SOT108-1 (SO14) and
SOT402-1 (TSSOP14)
001aad067
74LVC07A
GND(1)
Transparent top view
3Y 4A
3A 5Y
2Y 5A
2A 6Y
1Y 6A
GND
4Y
1
A
V
C
C
6 9
5 10
4 11
3 12
2 13
7
8
1
14
terminal 1
index area
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
Fig. 5. Pin configuration for SOT762-1 (DHVQFN14)
5.2. Pin description
Table 2. Pin description
Symbol Pin Description
1A, 2A, 3A, 4A, 5A, 6A 1, 3, 5, 9, 11, 13 data input
1Y, 2Y, 3Y, 4Y, 5Y, 6Y 2, 4, 6, 8, 10, 12 data output
GND 7 ground (0 V)
VCC 14 supply voltage
74LVC07A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved
Product data sheet Rev. 7 — 3 August 2020 2 / 12
Nexperia 74LVC07A
Hex buffer with open-drain outputs
6. Functional description
Table 3. Function selection
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state
Input Output
nA nY
L L
H Z
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage -0.5 +6.5 V
IIK input clamping current VI < 0 V -50 - mA
VIinput voltage [1] -0.5 +6.5 V
IOK output clamping current VO < 0 V -50 - mA
active mode [2] -0.5 +6.5 VVOoutput voltage
high-impedance mode [2] -0.5 +6.5 V
IOoutput current VO = 0 V to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current -100 - mA
Ptot total power dissipation Tamb = -40 °C to +125 °C [3] - 500 mW
Tstg storage temperature -65 +150 °C
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C.
For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C.
For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
1.65 - 5.5 VVCC supply voltage
functional 1.2 - - V
VIinput voltage 0 - 5.5 V
active mode 0 - 5.5 VVOoutput voltage
high-impedance mode 0 - 5.5 V
Tamb ambient temperature -40 - +125 °C
VCC = 1.65 V to 2.7 V 0 - 20 ns/VΔt/ΔV input transition rise and fall rate
VCC = 2.7 V to 5.5 V 0 - 10 ns/V
74LVC07A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved
Product data sheet Rev. 7 — 3 August 2020 3 / 12
Nexperia 74LVC07A
Hex buffer with open-drain outputs
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions
Min Typ[1] Max Min Max
Unit
VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65VCC - - 0.65VCC - V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIH HIGH-level input
voltage
VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC - V
VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35VCC - 0.35VCC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VIL LOW-level input
voltage
VCC = 4.5 V to 5.5 V - - 0.30VCC - 0.30VCC V
VI = VIH or VIL
IO = 100 μA;
VCC = 1.65 V to 5.5 V
- - 0.20 - 0.3 V
IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.6 V
IO = 8 mA; VCC = 2.3 V - - 0.3 - 0.75 V
IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V
IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V
VOL LOW-level output
voltage
IO = 32 mA; VCC = 4.5 V - - 0.55 - 0.8 V
IIinput leakage
current
VI = 5.5 V or GND;
VCC = 1.65 V to 5.5 V
- ±0.1 ±5 - ±20 μA
IOZ OFF-state output
current
VI = VIH; VO = 5.5 V or GND;
VCC = 1.65 V to 5.5 V
- ±0.1 ±10 - ±20 μA
IOFF power-off leakage
current
VI or VO = 5.5 V; VCC = 0 V - ±0.1 ±10 - ±20 μA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
- 0.1 10 - 40 μA
ΔICC additional supply
current
per input pin; VI = VCC - 0.6 V;
IO = 0 A; VCC = 2.7 V to 5.5 V
- 5 500 - 5000 μA
CIinput capacitance VCC = 0 V to 5.5 V;
VI = GND to VCC
- 5.0 - - - pF
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
74LVC07A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved
Product data sheet Rev. 7 — 3 August 2020 4 / 12
Nexperia 74LVC07A
Hex buffer with open-drain outputs
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 7.
-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions
Min Typ [1] Max Min Max
Unit
nA to nY; see Fig. 6
VCC = 1.2 V - 8.0 - - - ns
VCC = 1.65 V to 1.95 V 0.5 1.7 5.5 0.5 6.5 ns
VCC = 2.3 V to 2.7 V 0.5 1.2 2.8 0.5 3.5 ns
VCC = 2.7 V 0.5 1.8 3.3 0.5 4.5 ns
VCC = 3.0 V to 3.6 V 0.5 1.2 3.6 0.5 4.5 ns
tPZL OFF-state to LOW
propagation delay
VCC = 4.5 V to 5.5 V 0.5 1.6 2.6 0.5 3.5 ns
nA to nY; see Fig. 6
VCC = 1.2 V - 10 - - - ns
VCC = 1.65 V to 1.95 V 0.5 3.0 5.5 0.5 6.5 ns
VCC = 2.3 V to 2.7 V 0.5 1.7 2.8 0.5 3.5 ns
VCC = 2.7 V 0.5 2.1 3.3 0.5 4.5 ns
VCC = 3.0 V to 3.6 V 0.5 2.5 3.6 0.5 4.5 ns
tPLZ LOW to OFF-state
propagation delay
VCC = 4.5 V to 5.5 V 0.5 1.6 2.6 0.5 3.5 ns
per buffer; VI = GND to VCC [2]
VCC = 1.65 V to 1.95 V - 6.5 - - - pF
VCC = 2.3 V to 2.7 V - 6.9 - - - pF
CPD power dissipation
capacitance
VCC = 3.0 V to 3.6 V - 7.2 - - - pF
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD x VCC 2 x fi x N + Σ(CL x VCC 2 x fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL x VCC 2 x fo) = sum of the outputs
10.1. Waveforms and test circuit
mna528
tPLZ
VX
nY output
nA input
VI
VCC
VMVM
VOL
GND
tPZL
VM
Measurements points are given in Table 8.
Logic level: VOL is a typical output voltage level that occurs with the output load.
Fig. 6. The input (nA) to output (nY) propagation delays
74LVC07A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved
Product data sheet Rev. 7 — 3 August 2020 5 / 12
Nexperia 74LVC07A
Hex buffer with open-drain outputs
Table 8. Measurement points
Supply voltage Input Output
VCC VMVX
< 2.7 V 0.5 × VCC VOL + 0.15 V
≥ 2.7 V to 3.6 V 1.5 V VOL + 0.3 V
≥ 4.5 V to 5.5 V 0.5 × VCC VOL + 0.3 V
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aae331
VEXT
VCC
VIVO
DUT
CL
RT
RL
RL
G
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 7. Test circuit for measuring switching times
Table 9. Test data
Input Load VEXT
Supply voltage
VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH
1.2 V VCC ≤ 2 ns 30 pF 1 kΩ open 2 × VCC GND
1.65 V to 1.95 V VCC ≤ 2 ns 30 pF 1 kΩ open 2 × VCC GND
2.3 V to 2.7 V VCC ≤ 2 ns 30 pF 500 Ω open 2 × VCC GND
2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND
3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND
4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND
74LVC07A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved
Product data sheet Rev. 7 — 3 August 2020 6 / 12
Nexperia 74LVC07A
Hex buffer with open-drain outputs
11. Package outline
UNIT A
max. A
1 A
2 A
3 b
p c D
(1) E
(1) (1)
e H
E L L
p Q Z y w v θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10
1.45
1.25 0.25 0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8 1.27 6.2
5.8
0.7
0.6
0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
w M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M A
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004
0.057
0.049 0.01 0.019
0.014
0.0100
0.0075
0.35
0.34
0.16
0.15 0.05
1.05
0.041
0.244
0.228
0.028
0.024
0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
Fig. 8. Package outline SOT108-1 (SO14)
74LVC07A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved
Product data sheet Rev. 7 — 3 August 2020 7 / 12
Nexperia 74LVC07A
Hex buffer with open-drain outputs
UNIT A
1 A
2 A
3 b
p c D
(1) E (2) (1)
e H
E L L
p Q Z y w v θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3 0.65 6.6
6.2
0.4
0.3
0.72
0.38
8
0
o
o
0.13 0.1 0.2 1
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
w M
b
p
D
Z
e
0.25
1 7
14 8
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v M A
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index
Fig. 9. Package outline SOT402-1 (TSSOP14)
74LVC07A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved
Product data sheet Rev. 7 — 3 August 2020 8 / 12
Nexperia 74LVC07A
Hex buffer with open-drain outputs
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT762-1 MO-241
sot762-1_po
15-04-10
15-05-05
Unit
mm
max
nom
min
1 0.05 3.1 1.65 2.6
0.5 2 0.4
A(1)
Dimensions (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1
A1b
0.30
c D(1) DhE(1) Eh
1.00
e e1k
k
L v
0.1
w y
0.02 0.2 3.0 1.50 2.5 0.10.25 0.05 0.05
y1
0.30.85 0.20.00 2.9 1.35 2.40.18
0.51.15
0 4 mm2
scale
terminal 1
index area
AA1
c
L
Eh
Dh
k
b
2 6
13 9
8
7
1
14
D
E
terminal 1
index area
e1
e
e
C
y
C
y1
AC B
v
C
w
detail X
AB
X
Fig. 10. Package outline SOT762-1 (DHVQFN14)
74LVC07A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved
Product data sheet Rev. 7 — 3 August 2020 9 / 12
Nexperia 74LVC07A
Hex buffer with open-drain outputs
12. Abbreviations
Table 10. Abbreviations
Acronym Description
CDM Charged Device Model
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
13. Revision history
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC07A v.7 20200803 Product data sheet - 74LVC07A v.6
Modifications: Section 1 and Section 2 updated.
Table 4: Derating values for Ptot total power dissipation updated.
74LVC07A v.6 20181214 Product data sheet - 74LVC07A v.5
Modifications: The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
Legal texts have been adapted to the new company name where appropriate.
Table 5: Maximum output voltage (active mode) changed from VCC to 5.5 V
74LVC07A v.5 20111027 Product data sheet - 74LVC07A v.4
Modifications: Table 7: values added for lower voltage ranges.
74LVC07A v.4 20110810 Product data sheet - 74LVC07A v.3
Modifications: The format of this data sheet has been redesigned to comply with the new identity
guidelines
of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
Table 4, Table 5, Table 6 and Table 7: values added for lower voltage ranges.
74LVC07A v.3 20031111 Product specification - 74LVC07A v.2
74LVC07A v.2 20030225 Product specification - 74LVC07A v.1
74LVC07A v.1 20000307 Product specification - -
74LVC07A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved
Product data sheet Rev. 7 — 3 August 2020 10 / 12
Nexperia 74LVC07A
Hex buffer with open-drain outputs
14. Legal information
Data sheet status
Document status
[1][2]
Product
status [3]
Definition
Objective [short]
data sheet
Development This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification This document contains data from
the preliminary specification.
Product [short]
data sheet
Production This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
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detailed and full information. For detailed and full information see the relevant
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product data given in the Limiting values and Characteristics sections of this
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or warranty that such applications will be suitable for the specified use
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
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given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
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accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
74LVC07A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved
Product data sheet Rev. 7 — 3 August 2020 11 / 12
Nexperia 74LVC07A
Hex buffer with open-drain outputs
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................2
5.1. Pinning.........................................................................2
5.2. Pin description............................................................. 2
6. Functional description................................................. 3
7. Limiting values............................................................. 3
8. Recommended operating conditions..........................3
9. Static characteristics....................................................4
10. Dynamic characteristics............................................ 5
10.1. Waveforms and test circuit........................................ 5
11. Package outline.......................................................... 7
12. Abbreviations............................................................ 10
13. Revision history........................................................10
14. Legal information......................................................11
© Nexperia B.V. 2020. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 3 August 2020
74LVC07A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. All rights reserved
Product data sheet Rev. 7 — 3 August 2020 12 / 12