General Description
The MAX1067/MAX1068 low-power, multichannel, 14-
bit analog-to-digital converters (ADCs) feature a suc-
cessive-approximation ADC, integrated +4.096V
reference, a reference buffer, an internal oscillator,
automatic power-down, and a high-speed SPI™/
QSPI™/MICROWIRE™-compatible interface. The
MAX1067/MAX1068 operate with a single +5V analog
supply and feature a separate digital supply, allowing
direct interfacing with +2.7V to +5.5V digital logic.
The MAX1067/MAX1068 consume only 3.6mA (AVDD =
DVDD = +5V) at 200ksps when using an external refer-
ence. AutoShutdown™ reduces the supply current to
185µA at 10ksps and to less than 10µA at reduced sam-
pling rates.
The MAX1067 includes a 4-channel input multiplexer, and
the MAX1068 accepts up to eight analog inputs.
In addition, digital signal processor (DSP)-initiated con-
versions are simplified with the DSP frame-sync input and
output featured in the MAX1068. The MAX1068 includes a
data-bit transfer input to select between 8-bit-wide or 16-
bit-wide data-transfer modes. Both devices feature a scan
mode that converts each channel sequentially or one
channel continuously.
Excellent dynamic performance and low power, com-
bined with ease of use and an integrated reference,
make the MAX1067/MAX1068 ideal for control and data-
acquisition operations or for other applications with
demanding power consumption and space require-
ments. The MAX1067 is available in a 16-pin QSOP
package, and the MAX1068 is available in a 24-pin
QSOP package. Both devices are guaranteed over the
commercial (0°C to +70°C) and extended (-40°C to
+85°C) temperature ranges. Use the MAX1168 evalua-
tion kit to evaluate the MAX1068.
Applications
Motor Control
Industrial Process Control
Industrial I/O Modules
Data-Acquisition Systems
Thermocouple Measurements
Accelerometer Measurements
Features
♦14-Bit Resolution, ±0.5 LSB INL and
±1 LSB DNL (max)
♦+5V Single-Supply Operation
♦Adjustable Logic Level (+2.7V to +5.25V)
♦Input Voltage Range: 0 to VREF
♦Internal (+4.096V) or External (+3.8V to AVDD)
Reference
♦Internal Track/Hold, 4MHz Input Bandwidth
♦Internal or External Clock
♦SPI/QSPI/MICROWIRE-Compatible Serial
Interface, MAX1068 Performs DSP-Initiated
Conversions
♦8-Bit-Wide or 16-Bit-Wide Data-Transfer Mode
(MAX1068 Only)
♦4-Channel (MAX1067) or 8-Channel (MAX1068)
Input Mux
Scan Mode Sequentially Converts Multiple
Channels or One Channel Continuously
♦Low Power
3.6mA at 200ksps
1.85mA at 100ksps
185µA at 10ksps
0.6µA in Full Power-Down Mode
♦Small Package Size
16-Pin QSOP (MAX1067)
24-Pin QSOP (MAX1068)
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2955; Rev 1; 8/07
For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-
PACKAGE
INL
(LSB)
MAX1067ACEE
0°C to +70°C
16 QSOP
±0.5
MAX1067BCEE 0°C to +70°C
16 QSOP
±1
MAX1067CCEE
0°C to +70°C
16 QSOP
±2
MAX1067AEEE -40°C to +85°C
16 QSOP
±0.5
MAX1067BEEE -40°C to +85°C
16 QSOP
±1
MAX1067CEEE -40°C to +85°C
16 QSOP
±2
Ordering Information continued at end of data sheet.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
Pin Configurations appear at end of data sheet.
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND .........................................................-0.3V to +6V
DVDD to DGND.........................................................-0.3V to +6V
DGND to AGND.....................................................-0.3V to +0.3V
AIN_, REF, REFCAP to AGND..................-0.3V to (AVDD + 0.3V)
SCLK, CS, DSEL, DSPR, DIN to DGND ...................-0.3V to +6V
DOUT, DSPX, EOC to DGND...................-0.3V to (DVDD + 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
24-Pin QSOP (derate 9.5mW/°C above +70°C)...........762mW
Operating Temperature Ranges
MAX106_ _ CE_ ..................................................0°C to +70°C
MAX106_ _ EE_ ...............................................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF
= +4.096V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
DC ACCURACY (Note 1)
Resolution 14 Bits
MAX106_A
±0.5
±1
MAX106_B
±1.0
±2
Relative Accuracy (Note 2) INL
MAX106_C
±1.5
±3
LSB
MAX106_A ±1
MAX106_B +1.5
-1.0
Differential Nonlinearity DNL No missing codes
over temperature
MAX106_C +1.5
-1.0
LSB
External reference
0.33
Transition Noise RMS noise Internal reference
0.35
LSBRMS
Offset Error
±0.1 ±10
mV
Gain Error (Note 3)
±0.01 ±0.2
%FSR
Offset Drift 1
ppm/°C
Gain Drift (Note 3)
±1.2
ppm/°C
DYNAMIC SPECIFICATIONS (1kHz sine wave, 4.096VP-P) (Note 1)
Signal-to-Noise Plus Distortion SINAD 81 84 dB
Signal-to-Noise Ratio SNR 82 84 dB
Total Harmonic Distortion THD -98 -86 dB
Spurious-Free Dynamic Range SFDR 86 99 dB
Full-Power Bandwidth -3dB point 4
MHz
Full-Linear Bandwidth SINAD > 81dB 10 kHz
Channel-to-Channel Isolation (Note 4) 85 dB
CONVERSION RATE
Internal clock, no data transfer,
single conversion (Note 5)
5.52 7.07
Conversion Time tCONV
External clock
3.75
µs
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF
= +4.096V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Acquisition Time tACQ (Note 6)
729
ns
External clock, data transfer and conversion
0.1 4.8
Serial Clock Frequency fSCLK External clock, data transfer only 9
MHz
Internal Clock Frequency
fINTCLK
Internal clock 3.2 4.0
MHz
Aperture Delay tAD 15 ns
Aperture Jitter tAJ
<50
ps
8-bit-wide data-transfer mode
4.17 200.00
16-bit-wide data-transfer mode
3.125 150.000
Internal clock, single conversion, 8-bit-wide
data-transfer mode 89
Internal clock, single conversion, 16-bit-
wide data-transfer mode 68
Internal clock, scan mode, 8-bit-wide data-
transfer mode (four conversions)
103
Sample Rate (Note 7) fS
External clock, scan mode, 16-bit-wide
data-transfer mode (four conversions) 82
ksps
Duty Cycle 45 55 %
ANALOG INPUT (AIN_)
Input Range VAIN_0
VREF
V
Input Capacitance CAIN_45pF
EXTERNAL REFERENCE
Input Voltage Range VREF (Note 8) 3.8
AVDD – 0.2
V
VAIN_ = 0 34
SCLK idle 0.1
Input Current IREF
CS = DVDD, SCLK idle 0.1
µA
INTERNAL REFERENCE
Reference Voltage VREFIN
4.042 4.096 4.136
V
Reference Short-Circuit Current IREFSC 13 mA
Reference Temperature
Coefficient
±25
ppm/°C
Reference Wake-Up Time
tRWAKE
VREF = 0 5 ms
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF
= +4.096V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
DIGITAL INPUTS (SCLK, CS, DSEL, DSPR, DIN) (DVDD = +2.7V to +5.25V)
Input High Voltage VIH 0.7 ×
DVDD
V
Input Low Voltage VIL 0.3 ×
DVDD
V
Input Leakage Current IIN Digital inputs = 0 to DVDD
±0.1
±1 µA
Input Hysteresis VHYST 0.2 V
Input Capacitance CIN 15 pF
DIGITAL OUTPUT (DOUT, DSPX, EOC) (DVDD = +2.7V to +5.25V)
Output High Voltage VOH ISOURCE = 0.5mA DVDD -
0.4 V
ISINK = 10mA, DVDD = +4.75V to +5.25V 0.8
Output Low Voltage VOL ISINK = 1.6mA, DVDD = +2.7V to +5.25V 0.4 V
ILCS = DVDD
±0.1 ±10
µA
Tri-State Output Capacitance COUT CS = DVDD 15 pF
POWER SUPPLIES
Analog Supply AVDD
4.75 5.25
V
Digital Supply DVDD
2.70 5.25
V
External reference 2.7 3.3
200ksps Internal reference 3.6 4.2
External reference 1.4
100ksps Internal reference 2.7
External reference
0.14
10ksps Internal reference 1.8
External reference
0.014
Analog Supply Current (Note 9) IAVDD
1ksps Internal reference 1.7
mA
200ksps
0.87
1.3
100ksps
0.45
10ksps
0.045
Digital Supply Current IDVDD DOUT =
all zeros
1ksps
0.005
mA
Internal reference and
reference buffer on
between conversions
0.66
Power-Down Supply Current IAVDD +
IDVDD
CS = DVDD,
SCLK = 0,
DIN = 0,
DSPR = DVDD
Internal reference on,
reference buffer off
between conversions
0.20
mA
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF
= +4.096V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Shutdown Supply Current IAVDD +
IDVDD
CS = DVDD, SCLK = 0, DIN = 0,
DSPR = DVDD, full power-down 0.6 10 µA
Power-Supply Rejection Ratio PSRR AVDD = DVDD = 4.75V to 5.25V, full-scale
input (Note 10) 63 dB
TIMING CHARACTERISTICS (Figures 1, 2, 8, and 16)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF
= +4.096V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Acquisition Time tACQ External clock (Note 6)
729
ns
SCLK to DOUT Valid tDO CDOUT = 30pF 50 ns
CS Fall to DOUT Enable tDV CDOUT = 30pF 80 ns
CS Rise to DOUT Disable tTR CDOUT = 30pF 80 ns
CS Pulse Width tCSW
100
ns
SCLK rise
CS to SCLK Setup tCSS SCLK fall (DSP)
100
ns
SCLK rise
CS to SCLK Hold tCSH SCLK fall (DSP) 0ns
Conversion 93
SCLK High Pulse Width tCH Duty cycle 45% to 55% Data transfer 50 ns
Conversion 93
SCLK Low Pulse Width tCL Duty cycle 45% to 55% Data transfer 50 ns
SCLK Period tCP
209
ns
SCLK rise
DIN to SCLK Setup tDS SCLK fall (DSP) 50 ns
SCLK rise
DIN to SCLK Hold tDH SCLK fall (DSP) 0ns
CS Falling to DSPR Rising tDF
100
ns
DSPR to SCLK Falling Setup tFSS
100
ns
DSPR to SCLK Falling Hold tFSH 0ns
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
6 _______________________________________________________________________________________
TIMING CHARACTERISTICS (Figures 1, 2, 8, and 16)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion
(200ksps), external VREF = +4.096V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Acquisition Time tACQ External clock (Note 6) 729 ns
SCLK to DOUT Valid tDO CDOUT = 30pF 100 ns
CS Fall to DOUT Enable tDV CDOUT = 30pF 100 ns
CS Rise to DOUT Disable tTR CDOUT = 30pF 80 ns
CS Pulse Width tCSW 100 ns
SCLK rise
CS to SCLK Setup tCSS SCLK fall (DSP) 100 ns
SCLK rise
CS to SCLK Hold tCSH SCLK fall (DSP) 0ns
Conversion 93
SCLK High Pulse Width tCH Duty cycle 45% to 55% Data transfer 93 ns
Conversion 93
SCLK Low Pulse Width tCL Duty cycle 45% to 55% Data transfer 93 ns
SCLK Period tCP 209 ns
SCLK rise
DIN to SCLK Setup tDS SCLK fall (DSP) 100 ns
SCLK rise
DIN to SCLK Hold tDH SCLK fall (DSP) 0ns
CS Falling to DSPR Rising tDF 100 ns
DSPR to SCLK Falling Setup tFSS 100 ns
DSPR to SCLK Falling Hold tFSH 0ns
Note 1: AVDD = DVDD = +5.0V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
calibrated.
Note 3: Offset and reference errors nulled.
Note 4: DC voltage applied to on channel, and a full-scale 1kHz sine wave applied to off channels.
Note 5: Conversion time is measured from the rising edge of the 8th external SCLK pulse to EOC transition minus tACQ in 8-bit
data-transfer mode.
Note 6: See Figures 10 and 17.
Note 7: fSCLK = 4.8MHz, fINTCLK = 4.0MHz. Sample rate is calculated with the formula fs= n1(n2 / fSCLK + n3 / fINTCLK)-1 where: n1
= number of scans, n2= number of SCLK cycles, and n3= number of internal clock cycles (see Figures 11–14).
Note 8: Guaranteed by design, not production tested.
Note 9: Internal reference and buffer are left on between conversions.
Note 10: Defined as the change in the positive full scale caused by a ±5% variation in the nominal supply voltage.
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
_______________________________________________________________________________________ 7
-1.0
-0.6
-0.4
-0.8
0.2
0
0.4
-0.2
0.6
0.8
1.0
0 81924096 12,288 16,384
INL vs. CODE
MAX1067/68 toc01
CODE
INL (LSB)
-1.0
-0.6
-0.4
-0.8
0.2
0
0.4
-0.2
0.6
0.8
1.0
0 81924096 12,288 16,384
DNL vs. CODE
MAX1067/68 toc02
CODE
DNL (LSB)
-160
-120
-100
-140
-40
-60
-20
-80
0
20
0608020 40 100
FFT AT fAIN = 1kHz
MAX1067/68 toc03
FREQUENCY (kHz)
AMPLITUDE (dB)
SINAD vs. FREQUENCY
MAX1067/68 toc04
FREQUENCY (kHz)
SINAD (dB)
101
10
20
30
40
50
60
70
80
90
0
0.1 100
fSAMPLE = 200kbps
SFDR vs. FREQUENCY
MAX1067/68 toc05
FREQUENCY (kHz)
SFDR (dB)
101
20
40
60
80
100
120
0
0.1 100
fSAMPLE = 200ksps
THD vs. FREQUENCY
MAX1067/68 toc06
FREQUENCY (kHz)
THD (dB)
101
-100
-80
-60
-40
-20
0
-120
0.1 100
fSAMPLE = 200kbps
SUPPLY CURRENT vs. CONVERSION RATE
(EXTERNAL CLOCK)
MAX1067/68 toc07
CONVERSION RATE (ksps)
SUPPLY CURRENT (mA)
18016014012010080604020
0
0.5
1.0
1.5
2.0
2.5
3.0
-0.5
0 200
IAVDD, INT REF
IAVDD, EXT REF
DVDD = AVDD = +5V
DOUT = ALL ZEROS
EXTERNAL CLOCK
SPI MODE
IDVDD
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
(INTERNAL REFERENCE)
MAX1067/68 toc08
AVDD (V)
IAVDD (mA)
5.155.054.954.85
2.75
2.80
2.85
2.90
2.95
2.70
4.75 5.25
DVDD = +5V
fS = 200ksps
TA = 0°C
TA = -40°C
TA = +85°C
TA = +70°C
TA = +25°C
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
(EXTERNAL REFERENCE)
MAX1067/68 toc09
AVDD (V)
IAVDD (mA)
5.155.054.954.85
1.80
1.85
1.90
1.95
2.00
1.75
4.75 5.25
TA = 0°C
TA = -40°C
TA = +85°C
TA = +70°C
TA = +25°C
DVDD = +5V
fS = 200ksps
Typical Operating Characteristics
(AVDD = DVDD = +5V, fSCLK = 4.8MHz, CDOUT = 30pF, external VREF = +4.096V, TA= +25°C, unless otherwise noted.)
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
8 _______________________________________________________________________________________
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
MAX1067/68 toc10
DVDD (V)
IDVDD (mA)
4.744.233.723.21
0.6
1.0
1.4
1.8
2.2
2.6
0.2
2.70 5.25
AVDD = +5V
VIL = 0
fS = 200ksps
DOUT = 1010...1010
DOUT = 0000...0000
POWER-DOWN SUPPLY CURRENT
vs. AVDD SUPPLY VOLTAGE
(INTERNAL REFERENCE)
MAX1067/68 toc11
AVDD (V)
IDVDD (µA)
IAVDD (mA)
5.155.054.954.85
0.53
0.54
0.55
0.56
0.57
0.58
0.52
0.99
1.00
1.01
1.02
1.03
1.04
0.98
4.75 5.25
DVDD = +5V
IAVDD
IDVDD
POWER-DOWN SUPPLY CURRENT
vs. DVDD SUPPLY VOLTAGE
(INTERNAL REFERENCE)
MAX1067/68 toc12
DVDD (V)
IDVDD (µA)
IAVDD (mA)
4.744.233.723.21
0.2
0.3
0.4
0.5
0.6
0.7
0.1
1.00
1.01
1.02
1.03
0.99
2.70 5.25
DVDD = +5VAVDD = +5V
IAVDD
IDVDD
SHUTDOWN SUPPLY CURRENT
vs. AVDD SUPPLY VOLTAGE
(EXTERNAL REFERENCE)
MAX1067/68 toc13
AVDD (V)
IDVDD (µA)
IAVDD (nA)
5.155.054.954.85
0.53
0.54
0.55
0.56
0.57
0.58
0.52
0.34
0.38
0.42
0.46
0.50
0.54
0.30
4.75 5.25
DVDD = +5V
IAVDD
IDVDD
SHUTDOWN SUPPLY CURRENT
vs. DVDD SUPPLY VOLTAGE
(EXTERNAL REFERENCE)
MAX1067/68 toc14
DVDD (V)
IDVDD (µA)
IAVDD (nA)
4.744.233.723.21
0.2
0.3
0.4
0.5
0.6
0.7
0.1
0.38
0.39
0.40
0.41
0.42
0.43
0.37
2.70 5.25
DVDD = +5VAVDD = +5V
IAVDD
IDVDD
POWER-DOWN SUPPLY CURRENT
vs. TEMPERATURE (INTERNAL REFERENCE)
MAX1067/68 toc15
TEMPERATURE (°C)
IDVDD (µA)
IAVDD (mA)
603510-15
0.53
0.54
0.55
0.56
0.57
0.58
0.52
0.99
1.00
1.01
1.02
1.03
1.04
0.98
-40 85
DVDD = AVDD = +5V
IAVDD
IDVDD
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE (EXTERNAL REFERENCE)
MAX1067/68 toc16
TEMPERATURE (°C)
IDVDD (µA)
IAVDD (nA)
603510-15
0.53
0.54
0.55
0.56
0.57
0.58
0.52
0.37
0.39
0.41
0.43
0.45
0.35
-40 85
DVDD = AVDD = +5V
IAVDD
IDVDD
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5V, fSCLK = 4.8MHz, CDOUT = 30pF, external VREF = +4.096V, TA= +25°C, unless otherwise noted.)
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1067/68 toc17
AVDD (V)
OFFSET ERROR (µV)
5.154.85 5.054.95
-150
-100
-50
0
50
100
150
200
-200
4.75 5.25
VREF = +4.096V
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1067/68 toc18
AVDD (V)
GAIN ERROR (%FSR)
5.154.85 5.054.95
-0.025
-0.020
-0.015
-0.010
-0.005
0
0.005
0.010
0.015
0.020
-0.030
4.75 5.25
VREF = +4.096V
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
_______________________________________________________________________________________ 9
OFFSET ERROR vs. TEMPERATURE
MAX1067/68 toc19
TEMPERATURE (°C)
OFFSET ERROR (µV)
603510-15
-400
-300
-200
0
-100
100
200
300
400
500
-500
-40 85
VREF = +4.096V
GAIN ERROR vs. TEMPERATURE
MAX1067/68 toc20
TEMPERATURE (°C)
GAIN ERROR (%FSR)
603510-15
-0.020
-0.015
-0.010
-0.005
0
0.005
0.010
0.015
-0.025
-40 85
VREF = +4.096V
CHANNEL-TO-CHANNEL ISOLATION
vs. FREQUENCY
MAX1067/68 toc21
FREQUENCY (kHz)
ISOLATION (dB)
908060 7020 30 40 5010
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
0100
VREF = +4.096V
INTERNAL +4.096V REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1067/68 toc22
AVDD (V)
VREF (V)
5.155.054.954.85
4.092
4.096
4.100
4.104
4.088
4.75 5.25
DVDD = +5V
TA = 0°C
TA = -40°C
TA = +85°C
TA = +25°C
TA = +70°C
EXTERNAL REFERENCE INPUT CURRENT
vs. EXTERNAL REFERENCE VOLTAGE
MAX1067/68 toc23
VREF (V)
IREF (µA)
5.04.52.5 3.0 3.5 4.0
20
40
60
80
100
120
140
160
0
2.0 5.5
VAIN = 0
fSCLK = 4.8MHz
AVDD = DVDD = +5V
199ksps, EXTERNAL CLOCK
87.19ksps, INTERNAL CLOCK
INTERNAL REFERENCE VOLTAGE
vs. REF LOAD
MAX1067/68 toc24
IREF (mA)
VREF (V)
12106 842
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
014
fSCLK = 0
INTERNAL REFERENCE MODE
LOAD APPLIED TO REF
CREF = 1µF
INTERNAL CLOCK CONVERSION TIME
(8th RISING SCLK TO FALLING EOC)
MAX1067/68 toc25
NUMBER OF SCAN-MODE CONVERSIONS
tCONV(ms)
8765432
10
20
30
40
50
60
70
0
1
fSCLK = 4.8MHz
8-BIT DATA-TRANSFER MODE
16-BIT DATA-TRANSFER MODE
610 12
17 17
24 22
31
28
39
33
46
38
53
44
60
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5V, fSCLK = 4.8MHz, CDOUT = 30pF, external VREF = +4.096V, TA= +25°C, unless otherwise noted.)
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
10 ______________________________________________________________________________________
Pin Description
PIN
MAX1067
MAX1068 NAME
FUNCTION
13
DOUT
Serial Data Output. Data changes state on SCLK’s falling edge in SPI/QSPI/MICROWIRE
mode and on SCLK’s rising edge in DSP mode (MAX1068 only). DOUT is high impedance
when CS is high.
24
SCLK
Serial Clock Input. SCLK drives the conversion process in external clock mode and clocks
data out.
3 5 DIN
Serial Data Input. Use DIN to communicate with the command/configuration/control register.
In SPI/QSPI/MICROWIRE mode, the rising edge of SCLK clocks in data at DIN. In DSP
mode, the falling edge of SCLK clocks in data at DIN.
46EOC End-of-Conversion Output. In internal clock mode, a logic low at EOC signals the end of a
conversion with the result available at DOUT. In external clock mode, EOC remains high.
5 7 AIN0 Analog Input 0
6 8 AIN1 Analog Input 1
7 9 AIN2 Analog Input 2
8 10 AIN3 Analog Input 3
9 15 REF Reference Voltage Input/Output. VREF sets the analog voltage range. Bypass to AGND with
a 10µF capacitor. Bypass with a 1µF (min) capacitor when using the internal reference.
10 16
REFCAP
Refer ence Byp ass C ap aci tor C onnecti on. Byp ass to AG N D w i th a 0.1µF cap aci tor w hen usi ng
i nter nal r efer ence. Inter nal r efer ence and b uffer shut d ow n i n exter nal r efer ence m od e.
11 17
AGND
Analog Ground. Connect to pin 18 (MAX1068) or pin 12 (MAX1067).
12 18
AGND
Primary Analog Ground (Star Ground). Power return for AVDD.
13 19
AVDD
Analog Supply Voltage. Bypass to AGND with a 0.1µF capacitor.
14 20 CS
Active-Low Chip-Select Input. Forcing CS high places the MAX1067/MAX1068 in shutdown
with a typical supply current of 0.6µA. In SPI/QSPI/MICROWIRE mode, a high-to-low
transition on CS activates normal operating mode. In DSP mode, after the initial CS transition
from high to low, CS can remain low for the entire conversion process (see the Operating
Modes section).
15 21
DGND
Digital Ground
16 22
DVDD
Digital Supply Voltage. Bypass to DGND with a 0.1µF capacitor.
—1
DSPR
DSP Frame-Sync Receive Input. A frame-sync pulse received at DSPR initiates a
conversion. Connect to logic high when using SPI/QSPI/MICROWIRE mode.
—2
DSEL
Data-Bit Transfer-Select Input. Logic low on DSEL places the device in 8-bit-wide data-
transfer mode. Logic high places the device in 16-bit-wide data-transfer mode. Do not leave
DSEL unconnected.
— 11 AIN4 Analog Input 4
— 12 AIN5 Analog Input 5
Detailed Description
The MAX1067/MAX1068 low-power, multichannel, 14-
bit ADCs feature a successive-approximation ADC,
automatic power-down, integrated +4.096V reference,
and a high-speed SPI/QSPI/MICROWIRE-compatible
interface. A DSPR input and DSPX output allow the
MAX1068 to communicate with DSPs with no external
glue logic. The MAX1067/MAX1068 operate with a sin-
gle +5V analog supply and feature a separate digital
supply allowing direct interfacing with +2.7V to +5.5V
digital logic.
Figures 3 and 4 show the functional diagrams of the
MAX1067/MAX1068, and Figures 5 and 6 show the
MAX1067/MAX1068 in a typical operating circuit. The
serial interface simplifies communication with micro-
processors (µPs).
In external reference mode, the MAX1067/MAX1068
have two power modes: normal mode and shutdown
mode. Driving CS high places the MAX1067/MAX1068
in shutdown mode, reducing the supply current to
0.6µA (typ). Pull CS low to place the MAX1067/
MAX1068 in normal operating mode. The internal refer-
ence mode offers software-programmable, power-down
options as shown in Table 5.
In SPI/QSPI/MICROWIRE mode, a falling edge on CS
wakes the analog circuitry and allows SCLK to clock in
data. Acquisition and conversion are initiated by SCLK.
The conversion result is available at DOUT in unipolar
serial format. DOUT is held low until data becomes
available (MSB first) on the 8th falling edge of SCLK
when in 8-bit transfer mode, and on the 16th falling
edge when in 16-bit transfer mode. See the Operating
Modes section. Figure 8 shows the detailed SPI/QSPI/
MICROWIRE serial-interface timing diagram.
In external clock mode, the MAX1068 also interfaces
with DSPs. In DSP mode, a frame-sync pulse from the
DSP initiates a conversion that is driven by SCLK. The
MAX1068 formats a frame-sync pulse to notify the DSP
that the conversion results are available at DOUT in
MSB-first, unipolar, serial-data format. Figure 16 shows
the detailed DSP serial-interface timing diagram (see the
Operating Modes section).
Analog Input
Figure 7 illustrates the input-sampling architecture of
the ADC. The voltage applied at REF or the internal
+4.096V reference sets the full-scale input voltage.
Track/Hold (T/H)
In track mode, the analog signal is acquired on the
internal hold capacitor. In hold mode, the T/H switches
open and the capacitive digital-to-analog converter
(DAC) samples the analog input.
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 11
Pin Description (continued)
PIN
MAX1067
MAX1068
NAME
FUNCTION
— 13 AIN6 Analog Input 6
— 14 AIN7 Analog Input 7
—23
DSPX
DSP Frame-Sync Transmit Output. A frame-sync pulse at DSPX notifies the DSP that the
MSB data is available at DOUT. Leave DSPX unconnected when not in DSP mode.
— 24 N.C. No Connection. Not internally connected.
DGND
1mA CLOAD = 30pF
DOUT DOUT
CLOAD = 30pF
1mA
DGND
DVDD
a) VOL TO VOH b) HIGH-Z TO VOL AND VOH TO VOL
Figure 1. Load Circuits for DOUT Enable Time and SCLK-to-
DOUT Delay Time
DGND
1mA CLOAD = 30pF
DOUT DOUT
CLOAD = 30pF
1mA
DGND
DVDD
a) VOH TO HIGH-Z b) VOL TO HIGH-Z
Figure 2. Load Circuits for DOUT Disable Time
MAX1067/MAX1068
During the acquisition, the analog input (AIN_) charges
capacitor CDAC. At the end of the acquisition interval
the T/H switches open. The retained charge on CDAC
represents a sample of the input.
In hold mode, the capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to zero within the limits of 14-bit resolution. At the
end of the conversion, force CS high and then low to
reset the T/H switches back to track mode (AIN_),
where CDAC charges to the input signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(tACQ) is the maximum time the device takes to acquire
the signal. Use the following formula to calculate acqui-
sition time:
tACQ = 11(RS+ RIN + RDS(ON)) ✕45pF + 0.3µs
where RIN = 340Ω, RS= the input signal’s source
impedance, RDS(ON) = 60Ω, and tACQ is never less
than 729ns. A source impedance less than 200Ωdoes
not significantly affect the ADC’s performance. The
MAX1068 features a 16-bit-wide data-transfer mode
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
12 ______________________________________________________________________________________
REFERENCE
REF
REFCAP AVDD DVDD
AGND
AGND DGND
AIN0
AIN1
AIN2
AIN3
SCLK
CS
DIN
ANALOG-INPUT
MULTIPLEXER
MULTIPLEXER
CONTROL
ACCUMULATOR
MEMORY
INPUT REGISTER
BIAS
OSCILLATOR
OUTPUT DOUT
EOC
ANALOG-SWITCH FINE TIMING
SUCCESSIVE-APPROXIMATION
REGISTER
MAX1067
DAC
BUFFER
AZ
RAIL
COMPARATOR
Figure 3. MAX1067 Functional Diagram
that includes a longer acquisition time (11.5 clock
cycles). Longer acquisition times are useful in applica-
tions with input source resistances greater than 1kΩ.
Noise increases when using large source resistances. To
improve the input signal bandwidth under AC conditions,
drive AIN_ with a wideband buffer (>10MHz) that can
drive the ADC’s input capacitance and settle quickly.
Input Bandwidth
The ADC’s input-tracking circuitry has a 4MHz small-
signal bandwidth, making possible the digitization of
high-speed transient events and the measurement of
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid aliasing of unwanted, high-frequency signals into
the frequency band of interest, use anti-alias filtering.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to AVDD or AGND, allow the input to swing from
(AGND - 0.3V) to (AVDD + 0.3V) without damaging the
device. If the analog input exceeds 300mV beyond the
supplies, limit the input current to 10mA.
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 13
REFERENCE
REF
REFCAP AVDD DVDD
AGND
AGND DGND
AIN0
AIN1
AIN2
AIN3
SCLK
CS
DIN
ANALOG-INPUT
MULTIPLEXER
MULTIPLEXER
CONTROL
ACCUMULATOR
MEMORY
INPUT REGISTER
BIAS
OSCILLATOR
OUTPUT DOUT
EOC
ANALOG-SWITCH FINE TIMING
SUCCESSIVE-APPROXIMATION
REGISTER
MAX1068
DAC
BUFFER
AIN4
AIN5
AIN6
AIN7
AZ
RAIL
COMPARATOR
DSPX
DSEL
DSPR
Figure 4. MAX1068 Functional Diagram
MAX1067/MAX1068
Digital Interface
The MAX1067/MAX1068 feature an SPI/QSPI/
MICROWIRE-compatible 3-wire serial interface. The
MAX1067 digital interface consists of digital inputs CS,
SCLK, and DIN; and outputs DOUT and EOC. The
MAX1067 operates in the following modes:
• SPI interface with external clock
• SPI interface with internal clock
• SPI interface with internal clock and scan mode
In addition to the standard 3-wire serial interface modes,
the MAX1068 includes a DSPR input and a DSPX output
for communicating with DSPs in external clock mode
and a DSEL input to determine 8-bit-wide or 16-bit-wide
data-transfer mode. When not using the MAX1068 in the
DSP interface mode, connect DSPR to DVDD and leave
DSPX unconnected.
Command/Configuration/Control Register
Table 1 shows the contents of the command/configura-
tion/control register and the state of each bit after initial
power-up. Tables 2–6 define the control and configura-
tion of the device for each bit. Cycling the power sup-
plies resets the command/configuration/control register
to the power-on-reset default state.
Initialization After Power-Up
A logic high on CS places the MAX1067/MAX1068 in the
shutdown mode chosen by the power-down bits, and
places DOUT in a high-impedance state. Drive CS low to
power-up and enable the MAX1067/MAX1068 before
starting a conversion. In internal reference mode, allow
5ms for the shutdown internal reference and/or buffer to
wake and stabilize before starting a conversion. In exter-
nal reference mode (or if the internal reference is already
on), no reference settling time is needed after power-up.
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
14 ______________________________________________________________________________________
SCLK
DOUT
AGND
DGND
AIN0
REF
AVDD
DVDD
DOUT
SCLK
CS
+5V
DIN
ANALOG
INPUTS
+5V
1µF
0.1µF
0.1µF
GND
MAX1067
0.1µF
AIN1
AIN2
AIN3
DIN
EOC EOC
AGND
REFCAP
CS
Figure 5. MAX1067 Typical Operating Circuit
SCLK
DOUT
AGND
DGND
AIN0
REF
AVDD
DVDD
DOUT
SCLK
CS
+5V
16
8
DIN
ANALOG
INPUTS
+5V
1µF
0.1µF
0.1µF
GND
MAX1068
0.1µF
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
DIN
DSEL
DSPR
DSPX DSPX
EOC
AGND
REFCAP
EOC
CS
Figure 6. MAX1068 Typical Operating Circuit
AUTO-ZERO
RAIL
CAPACITIVE
DAC
CDAC
REF
AGND
TRACK
HOLD
HOLD TRACK
ZERO
MUX
RIN
RDSON
AIN_
CMUX
CSWITCH
Figure 7. Equivalent Input Circuit
BIT7 (MSB)
BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 (LSB)
COMMAND
CH SEL2 CH SEL1 CH SEL0 SCAN1 SCAN0 REF/PD_SEL1 REF/PD SEL0
INT/EXT CLK
POWER-UP
STATE 00000110
Table 1. Command/Configuration/Control Register
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 15
BIT7 BIT6 BIT5
CH SEL2 CH SEL1 CH SEL0
CHANNEL
AIN_
000 0
001 1
010 2
011 3
100 4
101 5
110 6
111 7
Table 2. Channel Select
BIT4
BIT3
ACTION
SCAN1
SCAN0
Single channel, no scan 0 0
Sequentially scan channels 0 through N
(N ≤ 3) 01
Sequentially scan channels 2 through N
(2 ≤ N ≤ 3) 10
Scan channel N 4 times 1 1
Table 3. MAX1067 Scan Mode, Internal
Clock Only
BIT4
BIT3
ACTION
SCAN1
SCAN0
Single channel, no scan 0 0
Sequentially scan channels 0 through N
(N ≤ 7) 01
Sequentially scan channels 4 through N
(4 ≤ N ≤ 7) 10
Scan channel N 8 times 1 1
Table 4. MAX1068 Scan Mode, Internal
Clock Only (Not for DSP Mode)
BIT2 BIT1
REF/PD_
SEL1
REF/PD
SEL0
REFERENCE
REFERENCE MODE
(INTERNAL REFERENCE)
TYPICAL
SUPPLY
CURRENT
TYPICAL WAKE-
UP TIME
(CREF = 1µF)
0 0 Internal Internal reference and reference buffer stay
on between conversions 1mA NA
0 1 Internal Internal reference and reference buffer off
between conversions 0.6µA 5ms
1 0 Internal Internal reference on, reference buffer off
between conversions 0.43mA 5ms
1 1 External Internal reference and buffer always off 0.6µA NA
Table 5. Power-Down Modes
BIT0
INT/EXT
CLK
CLOCK MODE
0 External clock
1 Internal clock
Table 6. Clock Modes
MAX1067/MAX1068
Power-Down Modes
Table 5 shows the MAX1067/MAX1068 power-down
modes. Three internal reference modes and one exter-
nal reference mode are available. Select power-down
modes by writing to bits 2 and 1 in the command/con-
figuration/control register. The MAX1067/MAX1068
enter the selected power-down mode on the rising
edge of CS.
The internal reference stays on when CS is pulled high,
if bits 2 and 1 are set to zero. This mode allows for the
fastest turn-on time.
Setting bit 2 = 0 and bit 1 = 1 turns both the reference
and reference buffer off when CS is brought high. This
mode achieves the lowest supply current. The refer-
ence and buffer wake up on the falling edge of CS
when in SPI/QSPI/MICROWIRE mode and on the falling
edge of DSPR when in DSP mode. Allow 5ms for the
internal reference to rise and settle when powering up
from a complete shutdown (VREF = 0, CREF = 1µF).
The internal reference stays on and the buffer is shut off
on the rising edge of CS when bit 2 = 1 and bit 1 = 0.
The MAX1067/MAX1068 enter this mode on the rising
edge of CS. The buffer wakes up on the falling edge of
CS when in SPI/QSPI/MICROWIRE mode and on the
falling edge of DSPR when in DSP mode. Allow 5ms for
VREF to settle when powering up from a complete shut-
down (VREF = 0, CREF = 1µF). VREFCAP is always equal
to +4.096V in this mode.
Set both bit 2 and bit 1 to 1 to turn off the reference and
reference buffer to allow connection of an external ref-
erence. Using an external reference requires no extra
wake-up time.
Operating Modes
External Clock 8-Bit-Wide Data-Transfer Mode
(MAX1067 and MAX1068)
Force DSPR high and DSEL low (MAX1068) for SPI/
QSPI/MICROWIRE-interface mode. The falling edge of CS
wakes the analog circuitry and allows SCLK to clock in
data. Ensure the duty cycle on SCLK is between 45% and
55% when operating at 4.8MHz (the maximum clock fre-
quency). For lower clock frequencies, ensure the
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
16 ______________________________________________________________________________________
CS
SCLK
DIN
DOUT
tCSW
tCSS
tCL
tDS
tDH
tDV
tCH
tDO tTR
tCSH
tCP
• • •
• • •
• • •
• • •
Figure 8. Detailed SPI Interface Timing
COMPLETE CONVERSION SEQUENCE
CONVERSION 0 CONVERSION 1
POWERED UP
POWERED UP POWERED DOWN
DOUT
CS
Figure 9. Shutdown Sequence
minimum high and low times are at least 93ns. External
clock-mode conversions with SCLK rates less than
125kHz can reduce accuracy due to leakage of the sam-
pling capacitor. DOUT changes from high-Z to logic low
after CS is brought low. Input data latches on the rising
edge of SCLK. The first SCLK rising edge begins loading
data into the command/configuration/control register from
DIN. The devices select the proper channel for conver-
sion on the rising edge of the 3rd SCLK cycle. Acquisition
begins immediately thereafter and ends on the falling
edge of the 6th clock cycle. The MAX1067/MAX1068
sample the input and begin conversion on the falling
edge of the 6th clock cycle. Setup and configuration of
the MAX1067/MAX1068 complete on the rising edge of
the 8th clock cycle. The conversion result is available
(MSB first) at DOUT on the falling edge of the 8th SCLK
cycle. To read the entire conversion result, 16 SCLK
cycles are needed. Extra clock pulses, occurring after the
conversion result has been clocked out and prior to the
rising edge of CS, cause zeros to be clocked out of
DOUT. The MAX1067/MAX1068 external clock 8-bit-wide
data-transfer mode requires 24 SCLK cycles for comple-
tion (Figure 10).
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified mini-
mum time (tCSW). Forcing CS high in the middle of a
conversion immediately aborts the conversion and
places the MAX1067/MAX1068 in shutdown.
External Clock 16-Bit-Wide Data-Transfer Mode
(MAX1068 Only)
Force DSPR high and DSEL high for SPI/QSPI/
MICROWIRE-interface mode. Logic high at DSEL allows
the MAX1068 to transfer data in 16-bit-wide words. The
acquisition time is extended an extra eight SCLK cycles
in the 16-bit-wide data-transfer mode. The falling edge
of CS wakes the analog circuitry and allows SCLK to
clock in data. Ensure the duty cycle on SCLK is
between 45% and 55% when operating at 4.8MHz (the
maximum clock frequency). For lower clock frequen-
cies, ensure that the minimum high and low times are at
least 93ns. External-clock-mode conversions with SCLK
rates less than 125kHz can reduce accuracy due to
leakage of the sampling capacitor. DOUT changes from
high-Z to logic low after CS is brought low. Input data
latches on the rising edge of SCLK. The first SCLK rising
edge begins loading data into the command/configura-
tion/control register from DIN. The devices select the
proper channel for conversion and begin acquisition on
the rising edge of the 3rd SCLK cycle. Setup and con-
figuration of the MAX1068 completes on the rising edge
of the 8th clock cycle. Acquisition ends on the falling
edge of the 14th SCLK cycle. The MAX1068 samples
the input and begins conversion on the falling edge of
the 14th clock cycle. The conversion result is available
(MSB first) at DOUT on the falling edge of the 16th
SCLK cycle. To read the entire conversion result, 16
SCLK cycles are needed. Extra clock pulses, occurring
after the conversion result has been clocked out and
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 17
DOUT
CS
SCLK
DIN
DSPR*
*MAX1068 ONLY
0
MSB LSB
MSB LSB
S1 S0
tACQ IDLE
tCONV
ADC
STATE
1816 24
DSEL*
Figure 10. SPI External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing
MAX1067/MAX1068
prior to the rising edge of CS, cause zeros to be
clocked out of DOUT. The MAX1068 external clock 16-
bit-wide data-transfer mode requires 32 SCLK cycles for
completion (Figure 11).
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified mini-
mum time (tCSW). Forcing CS high in the middle of a
conversion immediately aborts the conversion and
places the MAX1068 in shutdown.
Internal Clock 8-Bit-Wide Data-Transfer and
Scan Mode (MAX1067 and MAX1068)
Force DSPR high and DSEL low (MAX1068) for the SPI/
QSPI/MICROWIRE-interface mode. The falling edge of
CS wakes the analog circuitry and allows SCLK to
clock in data (Figure 12). DOUT changes from high-Z
to logic low after CS is brought low. Input data latches
on the rising edge of SCLK. The command/configura-
tion/control register begins reading DIN on the first
SCLK rising edge and ends on the rising edge of the
8th SCLK cycle. The MAX1067/MAX1068 select the
proper channel for conversion on the rising edge of the
3rd SCLK cycle. The internal oscillator activates 125ns
after the rising edge of the 8th SCLK cycle. Turn off the
external clock while the internal clock is on. Turning off
SCLK ensures the lowest noise performance during
acquisition. Acquisition begins on the 2nd rising edge
of the internal clock and ends on the falling edge of the
6th internal clock cycle. Each bit of the conversion
result shifts into memory as it becomes available. The
conversion result is available (MSB first) at DOUT on
the falling edge of EOC. The internal oscillator and ana-
log circuitry are shut down on the high-to-low EOC tran-
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
18 ______________________________________________________________________________________
DOUT
CS
SCLK
DIN
DSPR
DSEL
0
MSB LSB
MSB LSB
S1 S0
ADC
STATE
16 24 32
18
XXXXX
X
XX
X = DON,T CARE
tACQ IDLE
tCONV
Figure 11. SPI External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1068 Only)
DOUT
CS
SCLK
DIN
EOC
1
MSB LSB
LSB
S1 S0 X
tACQ IDLE
tCONV POWER-DOWN
ADC
STATE
X = DON,T CARE
DSPR = DVDD, DSEL = GND (MAX1068 ONLY)
INTERNAL
CLK
18
26 25
16924
• • •
MSB
Figure 12. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing
sition. Use the EOC high-to-low transition as the signal
to restart the external clock (SCLK). To read the entire
conversion result, 16 SCLK cycles are needed. Extra
clock pulses, occurring after the conversion result has
been clocked out and prior to the rising edge of CS,
cause the conversion result to be shifted out again. The
MAX1067/MAX1068 internal clock 8-bit-wide data-
transfer mode requires 24 external clock cycles and 25
internal clock cycles for completion.
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified mini-
mum time (tCSW). Forcing CS high in the middle of a
conversion immediately aborts the conversion and
places the MAX1067/MAX1068 in shutdown.
Scan mode allows multiple channels to be scanned
consecutively or one channel to be scanned eight
times. Scan mode can only be enabled when using the
MAX1067/MAX1068 in the internal clock mode. Enable
scanning by setting bits 4 and 3 in the command/con-
figuration/control register (see Tables 3 and 4). In scan
mode, conversion results are stored in memory until the
completion of the last conversion in the sequence.
Upon completion of the last conversion in the
sequence, EOC transitions from high to low to indicate
the end of the conversion and shuts down the internal
oscillator. Use the EOC high-to-low transition as the sig-
nal to restart the external clock (SCLK). DOUT provides
the conversion results in the same order as the channel
conversion process. The MSB of the first conversion is
available at DOUT on the falling edge of EOC (Figure 14).
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 19
DOUT
CS
SCLK
DIN
EOC
X X X X X X X X
DATA
LSB
S1 S0 X
tACQ
CONFIGURATION
X = DON,T CARE
DSPR = DSEL = DVDD
tCONV POWER-DOWN
ADC
STATE
INTERNAL
CLK
189 16
21332
2417 32
• • •• • •
• • • • • •
MSB
Figure 13. SPI Internal Clock Mode,16-Bit Data-Transfer Mode, Conversion Timing (MAX1068 Only)
DOUT
CS
SCLK
DIN
EOC
ADC
STATE
INTERNAL
CLK
18940
• • •
• • •
2624 48
3026
• • • • • •
1
MSB LSB
LSB
S1 S0 X
MSB
tACQ
CONFIGURATION POWER-DOWN
tCONV tACQ tCONV
X = DON,T CARE
DSPR = DVDD, DSEL = GND (MAX1068 ONLY)
Figure 14. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing
MAX1067/MAX1068
Internal Clock 16-Bit-Wide Data-Transfer and
Scan Mode (MAX1068 Only)
Force DSPR high and DSEL low for the SPI/QSPI/
MICROWIRE-interface mode. The falling edge of CS
wakes the analog circuitry and allows SCLK to clock in
data (see Figure 13). DOUT changes from high-Z to logic
low after CS is brought low. Input data latches on the ris-
ing edge of SCLK. The command/configuration/control
register begins reading DIN on the first SCLK rising
edge and ends on the rising edge of the 8th SCLK
cycle. The MAX1068 selects the proper channel for
conversion on the rising edge of the 3rd SCLK cycle.
The internal oscillator activates 125ns after the rising
edge of the 16th SCLK cycle. Turn off the external
clock while the internal clock is on. Turning off SCLK
ensures lowest noise performance during acquisition.
Acquisition begins on the 2nd rising edge of the inter-
nal clock and ends on the falling edge of the 18th inter-
nal clock cycle. Each bit of the conversion result shifts
into memory as it becomes available. The conversion
result is available (MSB first) at DOUT on the falling
edge of EOC. The internal oscillator and analog circuit-
ry are shut down on the EOC high-to-low transition. Use
the EOC high-to-low transition as the signal to restart
the external clock (SCLK). To read the entire conver-
sion result, 16 SCLK cycles are needed. Extra clock
pulses, occurring after the conversion result has been
clocked out and prior to the rising edge of CS, cause
the conversion result to be shifted out again. The
MAX1068 internal-clock 16-bit-wide data-transfer mode
requires 32 external clock cycles and 32 internal clock
cycles for completion.
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified mini-
mum time (tCSW). Forcing CS high in the middle of a
conversion immediately aborts the conversion and
places the MAX1068 in shutdown.
Scan mode allows multiple channels to be scanned
consecutively or one channel to be scanned eight
times. Scan mode can only be enabled when using the
MAX1068 in internal clock mode. Enable scanning by
setting bits 4 and 3 in the command/configuration/con-
trol register (see Tables 3 and 4). In scan mode, conver-
sion results are stored in memory until the completion of
the last conversion in the sequence. Upon completion of
the last conversion in the sequence, EOC transitions
from high to low to indicate the end of the conversion
and shuts down the internal oscillator. Use the EOC
high-to-low transition as the signal to restart the external
clock (SCLK). DOUT provides the conversion results in
the same order as the channel conversion process. The
MSB of the first conversion is available at DOUT on the
falling edge of EOC. Figure 15 shows the timing dia-
gram for 16-bit-wide data transfer in scan mode.
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
20 ______________________________________________________________________________________
DOUT
CS
SCLK
DIN
EOC
ADC
STATE
INTERNAL
CLK
189 16
• • • • • •• • • • • •
X = DON,T CARE
213
17
45
48
64
32 34
• • • • • •
X X X X X X X X
DATA
LSB
S1 S0 X
• • •
• • •
tACQ POWER-DOWNtCONV tACQ tCONV
MSB
Figure 15. SPI Internal Clock Mode, 16-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing (MAX1068 Only)
DSP 8-Bit-Wide Data-Transfer Mode (External Clock
Mode, MAX1068 Only)
Figure 16 shows the DSP-interface timing diagram.
Logic low at DSPR on the falling edge of CS enables
DSP interface mode. After the MAX1068 enters DSP
mode, CS can remain low for the duration of the con-
version process and each subsequent conversion.
Drive DSEL low to select the 8-bit data-transfer mode.
A sync pulse from the DSP at DSPR wakes the analog
circuitry and allows SCLK to clock in data (Figure 17).
The frame sync pulse alerts the MAX1068 that incom-
ing data is about to be sent to DIN. Ensure the duty
cycle on SCLK is between 45% and 55% when operat-
ing at 4.8MHz (the maximum clock frequency). For
lower clock frequencies, ensure the minimum high and
low times are at least 93ns. External clock mode con-
versions with SCLK rates less than 125kHz can reduce
accuracy due to leakage of the sampling capacitor.
The input data latches on the falling edge of SCLK. The
command/configuration/control register starts reading
data in on the falling edge of the first SCLK cycle imme-
diately following the falling edge of the frame sync
pulse and ends on the falling edge of the 8th SCLK
cycle. The MAX1068 selects the proper channel for
conversion on the falling edge of the 3rd clock cycle
and begins acquisition. Acquisition continues until the
rising edge of the 7th clock cycle. The MAX1068 sam-
ples the input on the rising edge of the 7th clock cycle.
On the rising edge of the 8th clock cycle, the MAX1068
outputs a frame sync pulse at DSPX. The frame sync
pulse alerts the DSP that the conversion results are
about to be output at DOUT (MSB first) starting on the
rising edge of the 9th clock pulse. To read the entire
conversion results, 16 SCLK cycles are needed. Extra
clock pulses, occuring after the conversion result has
been clocked out, and prior to the next rising edge of
DSPR, cause zeros to be clocked out of DOUT. The
MAX1068 external-clock, DSP 8-bit-wide data-transfer
mode requires 24 clock cycles to complete.
Begin a new conversion by sending a new frame sync
pulse to DSPR followed by new configuration data.
Send the new DSPR pulse immediately after reading
the conversion result to realize maximum throughput.
Sending a new frame sync pulse in the middle of a con-
version immediately aborts the current conversion and
begins a new one. A rising edge on CS in the middle of
a conversion aborts the current conversion and places
the MAX1068 in shutdown.
DSP 16-Bit-Wide Data-Transfer Mode (External
Clock Mode, MAX1068 Only)
Figure 16 shows the DSP-interface timing diagram. Logic
low at DSPR on the falling edge of CS enables DSP inter-
face mode. After the MAX1068 enters DSP mode, CS
can remain low for the duration of the conversion
process and each subsequent conversion. The acquisi-
tion time is extended an extra eight SCLK cycles in the
16-bit-wide data-transfer mode. Drive DSEL high to
select the 16-bit-wide data-transfer mode. A sync pulse
from the DSP at DSPR wakes the analog circuitry and
allows SCLK to clock in data (Figure 18). The frame
sync pulse also alerts the MAX1068 that incoming data
is about to be sent to DIN. Ensure the duty cycle on
SCLK is between 45% and 55% when operating at
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 21
CS
SCLK
DSPR
DIN
DOUT
tCSS
tCL
tDS
tDH
tDV
tCH
tDO tTR
tFSH
tCSH
tDF
tCP
tCSW
tFSS
...
...
...
...
...
Figure 16. Detailed DSP-Interface Timing (MAX1068 Only)
MAX1067/MAX1068
4.8MHz (the maximum clock frequency). For lower
clock frequencies, ensure the minimum high and low
times are at least 93ns. External-clock-mode conver-
sions with SCLK rates less than 125kHz can reduce
accuracy due to leakage of the sampling capacitor.
The input data latches on the falling edge of SCLK. The
command/configuration/control register starts reading
data in on the falling edge of the first SCLK cycle imme-
diately following the falling edge of the frame sync
pulse and ends on the falling edge of the 16th SCLK
cycle. The MAX1068 selects the proper channel for
conversion on the falling edge of the 3rd clock cycle
and begins acquisition. Acquisition continues until the
rising edge of the 15th clock cycle. The MAX1068 sam-
ples the input on the rising edge of the 15th clock cycle.
On the rising edge of the 16th clock cycle, the MAX1068
outputs a frame sync pulse at DSPX. The frame sync
pulse alerts the DSP that the conversion results are
about to be output at DOUT (MSB first) starting on the
rising edge of the 17th clock pulse. To read the entire
conversion result, 16 SCLK cycles are needed. Extra
clock pulses, occuring after the conversion result has
been clocked out and prior to the next rising edge of
DSPR, cause zeros to be clocked out of DOUT. The
MAX1068 external clock, DSP 16-bit-wide data-transfer
mode requires 32 clock cycles to complete.
Begin a new conversion by sending a new frame sync
pulse to DSPR followed by new configuration data.
Send the new DSPR pulse immediately after reading
the conversion result to realize maximum throughput.
Sending a new frame sync pulse in the middle of a con-
version immediately aborts the current conversion and
begins a new one. A rising edge on CS in the middle of
a conversion aborts the current conversion and places
the MAX1068 in shutdown.
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
22 ______________________________________________________________________________________
DOUT
CS
DSPR
SCLK
DIN
DSPX
0
MSB LSB
MSB LSB
S1 S0
tACQ IDLE
tCONV
ADC
STATE
1816 24
Figure 17. DSP External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing (MAX1068 Only)
DOUT
CS
SCLK
DIN 0
MSB LSB
MSB LSB
S1
ADC
STATE
16 24 32
18
XXXXX
X
XX
X = DON,T CARE
tACQ IDLE
tCONV
DSPR
DSPX
S0
Figure 18. DSP External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1068 Only)
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 23
Output Coding and Transfer Function
The data output from the MAX1067/MAX1068 is
straight binary. Figure 19 shows the nominal transfer
function. Code transitions occur halfway between suc-
cessive integer LSB values (VREF = +4.096V, and
1 LSB = +250µV or 4.096V / 16,384V).
Applications Information
Internal Reference
The internal bandgap reference provides a buffered
+4.096V. Bypass REFCAP with a 0.1µF capacitor to
AGND and REF with a 1µF capacitor to AGND. For best
results, use low-ESR, X5R/X7R ceramic capacitors.
Allow 5ms for the reference and buffer to wake up from
full power-down (see Table 5).
External Reference
The MAX1067/MAX1068 accept an external reference
with a voltage range between +3.8V and AVDD.
Connect the external reference directly to REF. Bypass
REF to AGND with a 10µF capacitor. When not using a
low-ESR bypass capacitor, use a 0.1µF ceramic capac-
itor in parallel with the 10µF capacitor. Noise on the ref-
erence degrades conversion accuracy.
The input impedance at REF is 37kΩfor DC currents.
During a conversion, the external reference at REF
must deliver 118µA of DC load current and have an
output impedance of 10Ωor less.
For optimal performance, buffer the reference through
an op amp and bypass the REF input. Consider the
equivalent input noise (82µVRMS) of the MAX1067/
MAX1068 when choosing a reference.
Internal/External Oscillator
Select either an external (0.1MHz to 4.8MHz) or the
internal 4MHz (typ) clock to perform conversions
(Table 6). The external clock shifts data in and out of
the MAX1067/MAX1068 in either clock mode.
When using the internal clock mode, the internal oscil-
lator controls the acquisition and conversion process-
es, while the external oscillator shifts data in and out of
the MAX1067/MAX1068. Turn off the external clock
(SCLK) when the internal clock is on to realize lowest
noise performance. The internal clock remains off in
external clock mode.
Input Buffer
Most applications require an input-buffer amplifier to
achieve 14-bit accuracy. The input amplifier must have
a slew rate of at least 2V/µs and a unity-gain bandwidth
of at least 10MHz to complete the required output-volt-
age change before the end of the acquisition time.
At the beginning of the acquisition, the internal sam-
pling capacitor array connects to AIN_ (the amplifier
input), causing some disturbance on the output of the
buffer. Ensure the sampled voltage has settled before
the end of the acquisition time.
Digital Noise
Digital noise can couple to AIN_ and REF. The conver-
sion clock (SCLK) and other digital signals active during
input acquisition contribute noise to the conversion
result. Noise signals, synchronous with the sampling
interval, result in an effective input offset. Asynchronous
signals produce random noise on the input, whose high-
frequency components can be aliased into the frequen-
cy band of interest. Minimize noise by presenting a low
impedance (at the frequencies contained in the noise
signal) at the inputs. This requires bypassing AIN_ to
AGND, or buffering the input with an amplifier that has a
small-signal bandwidth of several megahertz (doing both
is preferable). AIN has a typical bandwidth of 4MHz.
OUTPUT CODE
FULL-SCALE
TRANSITION
11...111
123
0FS
FS - 3/2 LSB
FS = VREF
INPUT VOLTAGE (LSB)
1 LSB = VREF
16,384
11...110
11...101
00...011
00...010
00...001
00...000
Figure 19. Unipolar Transfer Function, Full Scale (FS) = VREF,
Zero Scale (ZS) = GND
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
24 ______________________________________________________________________________________
Distortion
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the total harmonic
distortion of the MAX1067/MAX1068 at the frequencies of
interest (THD = -98db at 1kHz). If the chosen amplifier
has insufficient common-mode rejection, which results in
degraded THD performance, use the inverting configura-
tion (positive input grounded) to eliminate errors from this
source. Low-temperature-coefficient, gain-setting resis-
tors reduce linearity errors caused by resistance
changes due to self-heating. To reduce linearity errors
due to finite amplifier gain, use amplifier circuits with suf-
ficient loop gain at the frequencies of interest..
DC Accuracy
To improve DC accuracy, choose a buffer with an offset
much less than the MAX1067/MAX1068s’ offset (±10mV
max for +5V supply), or whose offset can be trimmed
while maintaining stability over the required tempera-
ture range.
Serial Interfaces
SPI and MICROWIRE Interfaces
When using the SPI (Figure 20a) or MICROWIRE (Figure
20b) interfaces, set CPOL = 0 and CPHA = 0. Drive CS
low to power on the MAX1067/MAX1068 before starting a
conversion (Figure 20c). Three consecutive 8-bit-wide
readings are necessary to obtain the entire 14-bit result
from the ADC. DOUT data transitions on the serial clock’s
falling edge. The first 8-bit-wide data stream contains all
leading zeros. The 2nd 8-bit-wide data stream contains
the MSB through D6. The 3rd 8-bit-wide data stream con-
tains D5 through D0 followed by S1 and S0.
CS
SCLK
DOUT
I/O
SCK
MISO
SPI VDD
SS
MAX1067
MAX1068
Figure 20a. SPI Connections
MAX1067
MAX1068
CS
MICROWIRE
SCLK
DOUT
I/O
SK
SI
Figure 20b. MICROWIRE Connections
DOUT*
CS
SCLK
1ST BYTE READ 2ND BYTE READ
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
HIGH-Z
3RD BYTE READ
LSB
S1 S0D5 D4 D3 D2 D1 D0
2420
1612
8
641
D13 D12 D11 D10 D9 D8 D7 D6 D5
00000000
Figure 20c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 25
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX1067/MAX1068 support a
maximum fSCLK of 4.8MHz. Figure 21a shows the
MAX1067/MAX1068 connected to a QSPI master and
Figure 21b shows the associated interface timing.
PIC16 with SSP Module and PIC17
Interface
The MAX1067/MAX1068 are compatible with a PIC16/
PIC17 controller (µC), using the synchronous serial-port
(SSP) module.
To establish SPI communication, connect the controller
as shown in Figure 22a and configure the PIC16/PIC17
as system master by initializing its synchronous serial-
port control register (SSPCON) and synchronous serial-
port status register (SSPSTAT) to the bit patterns shown
in Tables 7 and 8.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data to
be synchronously transmitted and received simultane-
ously. Three consecutive 8-bit-wide readings (Figure
22b) are necessary to obtain the entire 14-bit result from
the ADC. DOUT data transitions on the serial clock’s
falling edge and is clocked into the µC on SCLK’s rising
edge. The first 8-bit-wide data stream contains all zeros.
The 2nd 8-bit-wide data stream contains the MSB
through D6. The 3rd 8-bit-wide data stream contains bits
D5 through D0 followed by S1 and S0.
DOUT*
CS
SCLK
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
2016
D13 D12 D11 D10 D9 D8 D7 HIGH-Z
S1 S0
24
1214 86
D6 D3 D2 D1
LSB
D5 D4
SAMPLING INSTANT
D0
Figure 21b. QSPI Interface Timing Sequence (External Clock, 8-Bit Data Transfer, CPOL = CPHA = 0)
CONTROL BIT SETTINGS SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL BIT7 X Write Collision Detection Bit
SSPOV BIT6 X Receive Overflow Detection Bit
SSPEN BIT5 1
Synchronous Serial-Port Enable Bit:
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial
port pins.
CKP BIT4 0 Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection.
SSPM3 BIT3 0
SSPM2 BIT2 0
SSPM1 BIT1 0
SSPM0 BIT0 1
Synchronous Serial-Port Mode Select Bit. Sets SPI master-mode and
selects fCLK = fOSC / 16.
Table 7. Detailed SSPCON Register Contents
X = Don’t care.
QSPI
SCLK
DOUT
CS
SCK
MISO
VDD
SS
CS
MAX1067
MAX1068
Figure 21a. QSPI Connections
DSP Interface
The DSP mode of the MAX1068 only operates in exter-
nal clock mode. Figure 23 shows a typical DSP interface
connection to the MAX1068. Use the same oscillator as
the DSP to provide the clock signal for the MAX1068.
The DSP provides the falling edge at CS to wake the
MAX1068. The MAX1068 detects the state of DSPR on
the falling edge of CS (Figure 17). Logic low at DSPR
places the MAX1068 in DSP mode. After the MAX1068
enters DSP mode, CS can be left low. A frame sync
pulse from the DSP to DSPR initiates a conversion. The
MAX1068 sends a frame sync pulse from DSPX to the
DSP signaling that the MSB is available at DOUT. Send
another frame sync pulse from the DSP to DSPR to
begin the next conversion. The MAX1068 does not
operate in scan mode when using DSP mode.
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
26 ______________________________________________________________________________________
DOUT*
CS
SCLK
1ST BYTE READ 2ND BYTE READ
*WHEN CS IS HIGH, DOUT = HIGH-Z MSB
HIGH-Z
3RD BYTE READ
LSB
S1 S0D5 D4 D3 D2 D1 D0
24
20
16128641
D13 D12 D11 D10 D9 D8 D7 D6
00000000
Figure 22b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
SCK
SDI
GND
PIC16/17
I/O
SCLK
DOUT
CS
VDD VDD
MAX1067
MAX1068
Figure 22a. SPI Interface Connection for a PIC16/PIC17
CONTROL BIT SETTINGS SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
SMP BIT7 0 SPI Data-Input Sample Phase. Input data is sampled at the middle of
the data output time.
CKE BIT6 1 SPI Clock Edge-Select Bit. Data is transmitted on the rising edge of the
serial clock.
D/A BIT5 X Data Address Bit
P BIT4 X Stop Bit
S BIT3 X Start Bit
R/W BIT2 X Read/Write Bit Information
UA BIT1 X Update Address
BF BIT0 X Buffer-Full Status Bit
Table 8. Detailed SSPSTAT Register Contents
X = Don’t care.
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 27
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1067/MAX1068
are measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step-width and the ideal value of ±1 LSB. A
DNL error specification of ±1 LSB guarantees no miss-
ing codes and a monotonic transfer function.
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between samples. Aperture delay (tAD) is the
time between the falling edge of the sampling clock
and the instant when the actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADC’s res-
olution (N bits):
SNR = (6.02 ✕N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals:
SINAD (dB) = 20 ✕log [SignalRMS / (Noise +
Distortion)RMS]
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the ENOB as follows:
ENOB = (SINAD - 1.76) / 6.02
Figure 24 shows the ENOB as a function of the MAX1067/
MAX1068s’ input frequency.
DSP
EXTERNAL
CLOCK
SCLK
DSPR
DSPX
DIN
DOUT
SCLK
TFS
RFS
DT
DR
FL1 CS
MAX1068
Figure 23. DSP Interface Connection
0.1 10 100
FREQUENCY (kHz)
EFFECTIVE BITS
1
14
16
0
2
4
6
8
12
10
fSAMPLE = 200ksps
EFFECTIVE NUMBER OF BITS (ENOB)
Figure 24. Effective Bits vs. Frequency
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V1is the fundamental amplitude and V2through
V5are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next-largest fre-
quency component.
Supplies, Layout, Grounding, and
Bypassing
Use printed circuit (PC) boards with separate analog
and digital ground planes. Do not use wire-wrap
boards. Connect the two ground planes together at the
MAX1067/MAX1068 AGND terminal. Isolate the digital
supply from the analog with a low-value resistor (10Ω)
or ferrite bead when the analog and digital supplies
come from the same source (Figure 25).
Constraints on sequencing the power supplies and
inputs are as follows:
• Apply AGND before DGND.
• Apply AIN_ and REF after AVDD and AGND are
present.
•DV
DD is independent of the supply sequencing.
Ensure that digital return currents do not pass through
the analog ground and that return-current paths are low
impedance. A 5mA current flowing through a PC board
ground trace impedance of only 0.05Ωcreates an error
voltage of about 250µV and a 1 LSB error with a +4.096V
full-scale system.
The board layout should ensure that digital and analog
signal lines are kept separate. Do not run analog and dig-
ital lines (especially the SCLK and DOUT) parallel to one
another. If one must cross another, do so at right angles.
The ADC’s high-speed comparator is sensitive to high-
frequency noise on the AVDD power supply. Bypass an
excessively noisy supply to the analog ground plane
with a 0.1µF capacitor in parallel with a 1µF to 10µF
low-ESR capacitor. Keep capacitor leads short for best
supply-noise rejection.
T
+V +V +V
23
24252
1
HD
V
V
=×
⎛
⎝⎞
⎠
⎡
⎣
⎢
⎢
⎢
⎢
⎤
⎦
⎥
⎥
⎥
⎥
20
2
log
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
28 ______________________________________________________________________________________
SCLK
DOUT
AGND
DGND
AIN_
REF
AVDD
DVDD
DOUT
SCLK
CS
AIN_
+5V
10Ω
1µF
0.1µF
0.1µF
GND
MAX1067
MAX1068
AGND
CS
Figure 25. Powering AVDD and DVDD from a Single Supply
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 29
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
DOUT DVDD
DGND
CS
AVDD
AGND
AGND
REFCAP
REF
TOP VIEW
MAX1067
QSOP
QSOP
SCLK
DIN
AIN1
EOC
AIN0
AIN2
AIN3
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
N.C.
DSPX
DVDD
DGNDSCLK
DOUT
DSEL
DSPR
CS
AVDD
AGND
AGNDAIN1
AIN0
EOC
DIN
16
15
14
13
9
10
11
12
REFCAP
REF
AIN7
AIN6AIN5
AIN4
AIN3
AIN2
MAX1068
Pin Configurations
Chip Information
TRANSISTOR COUNT: 20,760
PROCESS: BiCMOS
Ordering Information (continued)
PART TEMP RANGE PIN-
PACKAGE
INL
(LSB)
MAX1068ACEG
0°C to +70°C
24 QSOP
±0.5
MAX1068BCEG
0°C to +70°C
24 QSOP
±1
MAX1068CCEG
0°C to +70°C
24 QSOP
±2
MAX1068AEEG*
-40°C to +85°C
24 QSOP
±0.5
MAX1068BEEG*
-40°C to +85°C
24 QSOP
±1
MAX1068CEEG*
-40°C to +85°C
24 QSOP
±2
*Future product—contact factory for availability.
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
QSOP.EPS
F11
21-0055
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Revision History
Pages changed at Rev 1: 1–6, 30