MIEGE 10.000 LOGIC DIAGRAMS Numbers in parenthesis dencte pin numbers for F package (Case 650). FUNCTIONS AND CHARACTERISTICS (continued) Type 0) Propagation Power Dissipation Delay mW Function -30 to +85C | -55 to +125C ns typ typ/pkg* Case Universal Decade Counter MC10137 MC10537 f= 150 MHz 625 620,650 Bi-Quinary Counter MC10138 _ f= 150 MHz 370 620 64-Bit Random Access Memory (90 2) MCM10140 - taccess = 15 (max) 420 620,690 Four-Bit Universal Shift Register MC10141 MC 10541 # = 200 MHz 425 620,648 650 64 Bit Random Access Memory (50 $2) MCM10142 ~ taAccess = 10 (max) 420 620 8 x 2 Muitiport Register File (RAM} MCM10143 - taccess = 10 610 623 256-Bit Random Access Memory MCM10144 - taccess = 30 (max) 420 620,690 64-Bit Register File (RAM) MCM10145 - taccess = 10 625 620 128-Bit Random Access Memory MCM10147 - taccess = 12 (max) 420 620 64-Bit Random Access Memory (50 92) MCM10148 _ taccess = 15 (max) 420 620 1024-Bit Programmable Read Only Memory MCM10150 _ taccess = 20 = 690 Quad Latch MC10153 _ 4.0 310 620 12-Bit Parity Generator-Checker MC10160 MC10560 5.0 320 620,648 650 Binary to 1-8 Decoder (Low) MC10161 Mc10561 4.0 315 620,648,650 Binary to 1-8 Decoder (High) MC 10162 MC10562 4.0 315 620,648 ,650 Error Detection-Correction Circuit MC10163 _ 5.0 520 620 8-Line Multiplexer MC10164 MC 10564 3.0 310 620,648,650 8-Input Priority Encoder MC10165 _ 7.0 545 620,648 5-Bit Magnitude Comparator MC10166 - 6.0 440 620 Quad Latch MC 10168 - 3.0 310 620 Oual Binary To t-4 Decoder (Low) MC10171 Mc10571 4.0 32S 620,648,650 Dual Binary To 1-4 Decoder (High) MC10172 MC10572 4.0 325 620,648,650 Quad 2-Input Multiplexer/Latch MC10173 - 2.5 278 620,648 Dual 4 To 1 Multiplexer MC10174 McC 10574 3.5 305 620,650 Quint Latch MC10175 MC10575 2.5 400 620 Hex D" Master-Slave Flip-Flop mMC10176 - f = 250 MHz 460 620 Triple MECL to NMOS Translator MC10177 _ - 1.0W 620 Binary Counter MC 10178 _ f = 150 MHz 370 620 Look-Ahead Carry Block MC10179 Mc 10579 3,0 (Cn,P} 4.0 (G) 300 620,648,650 Dua! High Speed Adder/Subtractor MC 70180 Mc 10580 4.5 360 620,648,650 4-Bit Arithmetic Logic Unit/Function Generator MC10181 McC10581 See Logic Diag. 600 623,649,652 2-Bit Arithmetic Logic Unit/Function Generator MC10182 - See Logic Diag. 575 620 Error Detection-Correction Circuit MC10193 _ 7.5 520 620 Hex inverter/Buffer MC10195 - 2.0 200 620 Hex AND Gate MC10197 - 2.8 200 620 High Speed Dual 3-Input 3-Output OR Gate MC10210 _ 1.5 160 620 High Speed Oual 3-input 3-Output NOR Gate MC10211 =_ 1.5 160 620 High Speed Dual 3-Input 3-Output OR/NOR Gate MCc10212 _ 1.5 160 620 High Speed Tripie Line Receiver MC 10216 Mc 10616 1.8 100 620,648,650 High Speed Dual Type D Master-Slave Flip-Flop Mc10231 mMc10631 f = 225 MHz 270 620,648,650 High Speed 2 x 1 Bit Array Multiplier Block MC 10287 - ~ 400 620 q@ L suffix denotes Dual In-Line Ceramic Package, P suffix denotes Dual In-Line Plastic Package, F suffix denotes flat package {i.e., MC101001. = Ceramic Dual In-Line Package, MC10100P = Plastic Dual !n-Line Package and MC 10S500F = Ceramic Flat Package.) *Load Power not includedMEMORIES LOGIC DIAGRAMS (continued) [M10143 MCM 10145 8 x 2 Multiport Register 64-Bit Register File File (RAM) (RAM) Read Enable l4 a: 7 0 B Chip Enable +B 2 Ls 5 1 QB, } = 2 a, 10 cE 2 9 i Ao ao Write Enable WEg Stad 10 3 Address 7 Data 14 Do QB9 Lines A2 1 Ao Data s AZ aa Data Address < 15 A 5 Output Lines 3 1 Output IDO 15 Lines Lines 4 A2- ac, b 22. D1 a2 8 Data inputs Write Enable 1 WE 4 Lines 41 D2 Data 7 Dy 12 D3 a3 14 Co Qty |?! WE 16 C4 13 | 18 ~ Clock Write Enable 4 2 REC 20; 19 Read Enable Clock - Voc = Pin 16 tod: Vee =Pin8 Clock to Data out = 5 ns (typ) Veco= Pin 1 (Read Selected) Veer = Pin 23 Address to Data out = 10ns (typ) Voc = Pin 24 Pp = 625 mW typ/pkg (No Load) (Clock High) Veg = Pin 12 Access Time = 10 ns typ Read Enable to Data out = 3.5 ns (typ) {Clock high, Addresses present) Pp = 610 mW typ/pkg (No Load) MCM 10140 (90 2) MCM10142 (50 22) MCM10148 (50 2} 64-Bit Random Access Memory Address Inputs Al A2 AZ A4& AS AG 2] al ol 7 j ol rol Address Buffer/ 1/16 Decoder Decoder The Chip is enabled [TTI | === == J aes are ae eositive Column Pp = 420 mW typ/pkg logic "0" Select taccess = 15 ns (max) MCM10140, MCM10148 Gates [| = 10 ns (max) MCM10142 rt 16x 4 Array 4 . oo Chip CEN 5 Enabie CE2 Buffer Data Out 15 Output Sense Amplifier ata Ouro Buffer } Data tn of Write . and Write O-_ Data Input Buffer 2-26MECL 10,000 series 8 x 2 MULTIPORT REGISTER FILE (RAM) MCM10143 8 x 2MULTIPORT REGISTER FILE (RAM) The MC10143 is an 8 word. by 2 bit multiport register file (RAM) capable of reading two locations and writing one location simuita- neously. Two sets of eight latches are used for data storage in this L SUFFIX ircui CERAMIC PACKAGE LSI circuit. Se Ba WRITE The word to be written is selected by addresses AgAQ. Each bit of the word has a separate write enable to allow more flexibility in system design. A write occurs on the positive transition of the clock. Data is enabled by having the write enables at a low level when the clock makes the transition. To inhibit a bit from being written, the bit enable must be at a high level when the clock goes low and not change until the clock goes high. Operation of the clock and the bit enables can be reversed. While the clock is low a positive transition of the bit enable will write that bit into the address selected by AgA2. PIN ASSIGNMENT READ When the clock is high any two words may be read out simulta- neously, as selected by addresses BgB2 and CgCo, including the word written during the preceding half clock cycle. When the clock 1) Veco Vec goes low the addressed data is stored in the slaves. Level changes on the read address lines have no effect on the output until the clock NN Oo & 2] 0B, Yec1 again goes high. Read out is accomplished at any time by enabling 3 CJ aB9 Qc, 22 output gates (BgB1), (CgC}). 4) REg Qcg 21 5 CI B2 REc 6 CC] Bo Clock 19 7B, C2 18 tpd: 8 CI We, Co Clock to Data out = 5 ns (t oe (Read Selected) ye) oT WEo 1 Address to Data out = 10 ns (typ) 10 = Po At (Clock High) W Dy Ao Read Enable to Data out = 2.8 ns (typ) 12 (J Vee A2 (Clock high, Addresses present) Pp = 610 mW/pkg (typ no load) 15 14 HVUUUUUUOCUUUU 43 Veco = Pin 1 Vec1 = Pin 23 Vec= Pin 24 Veg = Pin 12 See General Information section for packaging. 3-374MCM10143 (continued) BLOCK DIAGRAM __ 4 RE O Multi- output | 9 at Slave 6 plexer B-bit 1 Gate Lo 2B; BO O-j__ Read B-bitt Bit 1 By ad Decoder - B2 B Multi- Output 3 Stave plexer Le] B-bItO Gate tO OBg B-bit 0 B-bit 0 J bm Write L 9 if; 8x WEg o Amplifier 10 i Master Latches Po o Bir 0 (| Bit oO Clock o~ 24 4 Ao os Write a OTs Decod A2 O A __ o> Write . 8x1 Ey o Amplitier Master Latches D104 Bit 1 | Bit 1 Mult be} Slave Output | 95 pet Cit 4 Gate bo acy Chit o Chit 1 Co ott a Read cy Ld Decoder 18 ' ct tLe] Lia sa | ana C-bit 0 te }-~o acg C-bit 0 C-rit O 3-375MCM10143 (continued) Aead Enable ELECTRICAL CHARACTERISTICS Each MECL 10,000 series circuit has been designed to meet the dc specifications 7 shown in the test table, after thermal Write Enable equilibrium has been established. The cir- Dera cuit board and transverse air flow greater Address 1S Data than 500 tinear fpm is maintained. Out- Lines < output puts are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are Write Enable shown only for selected inputs and out- Data VOLTAGE VALUES . L puts. Other inputs and outputs are tested TEST VOLT + we fh in a similar manner. (Volts) @ Test Temperature "| ViHmax |Vitmin | ViHAmin| ViLAmex | VEE Aead Enable -30c [| -0.890 | -1.890 | -1.205 | -1.500 | -5.2 Clock +26c [| -0.810 | -1,850 | -1.105 | -1475 | -5.2 +85c | -0.700 | -1.825 | -1.035 | -1.440_| -52 MCM10143L Fest Limits TEST VOLTAGE APPLIED TO P : ae 0c 25 75% PINS LISTED BELOW (Vee) Characteristic Symbol Test Min Max Min Typ Max Min Max Unit | Yidmax | itmin | Vinamin|ViLtAmax | VEE Gnd Power Supply Dra Current le 12 - - 118 147 ~ - mAdc | 4.5.6.7.8, - - 12) 1,23,24 9.13.14, 15.16.17 18,19,20 Input Current lin H 4 ~ - = 200 wAde 4 - - 12 | 1,23,24 5 - - - - 5 - 6 - - 6 - - 7 - - - 7 8 - - 8 - 9 - - - - - 9 - - 13 - - - - - 13 - 14 - = = - - 18 - ~ 15 - - - 15 - 16 - - - 16 7 - - - 7 - 18 - - - 18 - - 20 - - - 20 10 - - - 245 - - 10 - "1 - - - 245 Mi - 19 : = - 245 - 19 - = lin L . = 05 - - - #Ade = . - ~ 12 | 1,23,24 Logic 1 Output Voltage VOH 2 -1.060 | -0.890 | -0.960 = -o.8to0 | -0.890 | -0.700 [ vae | 10,114) ~ 12 | 1,23,24 3 - 21 t 1 - - t 22 - - Logic 0 Output Voltage Vou 2 -1.890 | -1.675 | -1.850 - -1.650 | -1.825 | -1.615 | vae | 420@] - - 12 | 4.23.24 3 - - 2 ' tt iva 22 - = - Logic 1" Threshold Voltage VOHA 2 -1,080 -0.980 ~ -0.910 vde | 11) - 4 12 | 1,23,24 3 - - 10 4 21 - - 10 { 20 22 = - WW = 20 Logic 0 Threshotd Voltage VoLa 2 1.655 - -1,630 - -1.595 | vde | 11 @ 4 - 12 | 1,23,24 3 - - - j 10 4s 21 - - - 10 ' 20 22 = = = "4 20 = Switching Times (2) Figure | Pulse tn Pulse Out | -3.2V | +2.0V Access Time Address input tg-08 2 - - - 10 - ns - 1 5 2 12 | 1,23,24 1g+OB- 2 - - 10 - 1 5 2 Read Enable tHE-OB+ 2 - - 28 - 2 4 2 Data tClock+OB- 2 - - 5.0 - 3 19 2 Setup Address "setup(B -Clack -) 19 - - 5.5 - - 4 5 19 Hold Address thoid(Clock-B+) 5 - -4.5 - 4 19 5 Write Time (2) Setup Write Enable tsetup(WE-Clock+) | 19 2.0 5 8 19 Tsetup(WE +Clack-} 19 - 2.0 - 6 8 19 Address teetuptAClock+) 19 - - 3.0 - - - 8 14 19 Data tsetup(D-C-ock+) 19 - - 2.0 8 10 19 Hold Write Enable thold(Clock HWE +) 8 - - -2.0 - 5 19 8 thold{Clock FWE-) 8 - - -2.0 - ~ - - 6 19 8 Address tholdiClock +A 4} 5 - -3.0 - - 8 19 14 Data thold(Clock +0+) 10 - - 12.6 - 8 19 10 Write Pulse Width PWT 19 - 50 - - 7 8 19 Rise Time t+ 2 - - 20 - 8 2 (20% to 80%) Fall Time t 2 - - 20 - 5 2 1 (20% to 80%) *Limit applies for all inputs, individually apply V)Lrmn to pin under test @ Data has to be clocked in JT -0.810V @ ac timing figures do not show ail the necessary pre-se(ting conditions -1.85 V 3-376MCM10143 (continued) SWITCHING TIME TEST CIRCUIT @ 25C Vee = Veco = Vec1 = 2.0 Vde Vin Vout @) Coax Coax Co | | i | oI WE | 2 o- Jo, | QBg }__-o Input 5 oF Ao | $< o_ AI (9) oF), | 42, ac 6 Pulse Generator z ot WE, 1 | : ot 1 | Input Pulse o Co QCog | O te =t- = 2.00.2 ns oO C4 Clock | (20% to 80%) o C2 REc on | PRR = 1 MHz ' { W 2 20ns | | Ee 1 ' | 50-ohm termination to ground lo- cated in each scope channel input. All input and output cables to the scope are equal lengths of 50-ohm coaxial cable. Wire length should be < 1/4 inch from TPip to input pin and TP out to output pin. Unused outputs connected to a 50-ohm resistor to ground. 3-377MCM10143 (continued) READ TIMING DIAGRAMS Access (Clock High}. 3 _. FIGURE 1 aB Enable __ RE FIGURE 2 tRE+aB- Data (Address Selected) g FIGURE 3 Clock Setup and Hold B FIGURE 4 Clock . WRITE TIMING DIAGRAMS Enabie We FIGURE S Tsetup thold Ciock Disable \ FIGURE 6 WE a tgatup tho ld +| Clock a Pulse Width WE FIGURE 7 \ _f K +t >> tratup -t >> thald Ctock . . Addi ress FIGURE 8 Oo Clock _____ 3-378