D a ta S he e t , V 1 .0 , Ap r . 2 0 0 8 TC1796 y 3 2 - B i t S i n g l e - C h i p M i c ro c o n t r o ll e r P re li m in ar TriCore M i c r o c o n t r o l l e rs Edition 2008-04 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D a ta S he e t , V 1 .0 , Ap r . 2 0 0 8 TC1796 y 3 2 - B i t S i n g l e - C h i p M i c ro c o n t r o ll e r P re li m in ar TriCore M i c r o c o n t r o l l e rs TC1796 Preliminary TC1796 Data Sheet Preliminary Revision History: V1.0, 2008-04 Previous Version: V0.7, 2006-03 Page Subjects (major changes since last revision) 32 The list of not connected pins (N.C.) improved by adding several formerly as VSS labeled pins. 69 Watchdog timer, double reset detection, description corrected. 80 RTID register updated for the design step BE. 85 The description of the inactive device current improved. 96 ADC parameters sample and conversion time moved to a dedicated table. 107 The description of the power supply sequence improved.. 115 BFCLKO clock, duty cycle description extended. 126 MLI timing, maximum operating frequency limit extended, t31 added. 131 The drawing of the package updated. Green package variant included. 133 Example of a temperature profile corrected. Trademarks TriCore(R) is a trademark of Infineon Technologies AG. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Data Sheet V1.0, 2008-04 TC1796 Preliminary Table of Contents Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 2.1 2.2 2.3 2.4 2.5 2.5.1 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TC1796 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pad Driver and Input Classes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pull-Up/Pull-Down Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . 10 10 11 12 13 13 35 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.14.1 3.14.2 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24 3.25 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Architecture and On-Chip Bus Systems . . . . . . . . . . . . . . . . . . . . On-Chip Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architectural Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Protection System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Control Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Controller and Memory Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1) . . . . . . . . . . High-Speed Synchronous Serial Interfaces (SSC0, SSC1) . . . . . . . . . . . . Micro Second Bus Interfaces (MSC0, MSC1) . . . . . . . . . . . . . . . . . . . . . . MultiCAN Controller (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Micro Link Serial Bus Interface (MLI0, MLI1) . . . . . . . . . . . . . . . . . . . . . . . General Purpose Timer Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functionality of GPTA0/GPTA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functionality of LTCA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter (ADC0, ADC1) . . . . . . . . . . . . . . . . . . . . . . . . Fast Analog-to-Digital Converter Unit (FADC) . . . . . . . . . . . . . . . . . . . . . . System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Identification Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 36 37 39 40 41 42 44 46 48 50 52 54 57 59 60 62 63 65 67 69 70 70 73 74 76 79 80 4 4.1 4.1.1 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Data Sheet 5 V1.0, 2008-04 TC1796 Preliminary Table of Contents 4.1.2 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.1.4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.2.1 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.2.2 Analog to Digital Converters (ADC0/ADC1) . . . . . . . . . . . . . . . . . . . . . 92 4.2.3 Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . . . 99 4.2.4 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.2.5 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.2.6 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.3.2 Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4.3.3 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.3.4 Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.3.5 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.3.6 BFCLKO Output Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.3.7 Debug Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.3.8 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.3.9 EBU Demultiplexed Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.3.9.1 Demultiplexed Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.3.9.2 Demultiplexed Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.3.10 EBU Burst Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.3.11 EBU Arbitration Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.3.12 Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.3.12.1 Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.3.12.2 Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . . 128 4.3.12.3 Synchronous Serial Channel (SSC) Master Mode Timing . . . . . . . . 129 5 5.1 5.2 5.3 5.4 Data Sheet Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters (P/PG-BGA-416-4) . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 130 130 131 132 133 V1.0, 2008-04 TC1796 Preliminary 1 * * * * * * * * * Summary of Features Summary of Features High-performance 32-bit super-scalar TriCore V1.3 CPU with 4-stage pipeline - Superior real-time performance - Strong bit handling - Fully integrated DSP capabilities - Single precision Floating Point Unit (FPU) - 150 MHz operation at full temperature range 32-bit Peripheral Control Processor with single cycle instruction (PCP2) - 16 Kbyte Parameter Memory (PRAM) - 32 Kbyte Code Memory (CMEM) Multiple on-chip memories - 2 Mbyte Program Flash Memory (PFLASH) with ECC - 128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation - 136 Kbyte Data Memory (LDRAM, SRAM, SBRAM) - 8 Kbyte Dual-Ported Memory (DPRAM) - 48 Kbyte Code Scratchpad Memory (SPRAM) - 16 Kbyte Instruction Cache (ICACHE) - 16 Kbyte BootROM (BROM) 16-Channel DMA Controller 32-bit External Bus Interface Unit (EBU) with - 75 dedicated address/data bus, clock, and control lines - Synchronous burst Flash access capability Sophisticated interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on-chip bus structure - Two 64-bit Local Memory Buses between EBU, Flash and Data Memory - 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units - 32-bit Remote Peripheral Bus (RPB) for high-speed on-chip peripheral units - Two bus bridges (LFI Bridge, DMA Controller) Peripheral Control Processor with single cycle instruction (PCP2) - 16 Kbyte Parameter Memory (PRAM) - 32 Kbyte Code Memory (CMEM) Versatile On-chip Peripheral Units - Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection - Two High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction - Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices - Two High-Speed Micro Link interfaces (MLI) for serial inter-processor communication Data Sheet 7 V1.0, 2008-04 TC1796 Preliminary * * * * * * * * * * * Summary of Features - One MultiCAN Module with four CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer (one CAN node supports TTCAN functionality) - Two General Purpose Timer Array Modules (GPTA) with additional Local Timer Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management - Two 16-channel Analog-to-Digital Converter units (ADC) with selectable 8-bit, 10bit, or 12-bit resolution - One 4-channel Fast Analog-to-Digital Converter unit (FADC) with concatenated comb filters for hardware data reduction: supporting 10-bit resolution, min. conversion time of 280ns 44 analog input lines for ADC and FADC 123 digital general purpose I/O lines, 4 input lines Digital I/O ports with 3.3 V capability On-chip debug support for OCDS Level 1 and 2 (CPU, PCP3, DMA) Dedicated Emulation Device chip for multi-core debugging, tracing, and calibration via USB V1.1 interface available (TC1796ED) Power Management System Clock Generation Unit with PLL Core supply voltage of 1.5 V I/O voltage of 3.3 V Full automotive temperature range: -40 to +125C P/PG-BGA-416-4 package Data Sheet 8 V1.0, 2008-04 TC1796 Preliminary Summary of Features Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: * * The derivative itself, i.e. its function set, the temperature range, and the supply voltage The package and the type of delivery. For the available ordering codes for the TC1796 please refer to the "Product Catalog Microcontrollers", which summarizes all available microcontroller variants. This document describes the derivatives of the device.The Table 1 enumerates these derivatives and summarizes the differences. Table 1 TC1796 Derivative Synopsis Derivative Ambient Temperature Range SAK-TC1796-256F150E TA = -40oC to +125oC Data Sheet 9 V1.0, 2008-04 TC1796 Preliminary General Device Information 2 General Device Information 2.1 TC1796 Block Diagram FPU DMI TriCore (TC1M) 56 KB LDRAM 48 KB SPRAM 16 KB ICACHE SPRAM: ICACHE: LDRAM DPRAM: BROM: PFLASH: DFLASH: SBRAM: SRAM: PRAM: CMEM: PLMB: DLMB: RPB: SPB: shaded: 8 KB DPRAM CPS Program Local Memory Bus Data Local Memory Bus P LMB DBCU DLMB PMU LMI Emulation Memory Interface OCDS Debug Interface /JTAG 32 KB CMEM SCU PLL SSC1 SBCU ADC0 S PB fCPU SSC0 RP B STM Ports fFPI LTCA2 DMA ADC1 BI1 F PI-Bus Interface PCP2 Core BI0 GPTA1 System Peripheral Bus GPTA0 LFI Bridge 16 KB PRAM ASC0 ASC1 64 KB SRAM 16 KB SBRAM Interrupts EBU DMU 16 KB BROM 2 MB PFLASH 128 KB DFLASH Remote Peripheral Bus PBCU Scratch-Pad RAM Instruction cache Local data RAM Dual-port RAM Boot ROM Program Flash Memory Data Flash Memory Stand-by Data Memory Data Memory PCP Parameter Memory PCP Code Memory Program Local Memory Bus Data Local Memory Bus Remote Peripheral Bus System Peripheral Bus only available in TC1796ED FADC Analog Input Assignment PMI SMIF RBCU MultiCAN (with 4 CAN Nodes) MSC 0 MSC 1 MLI 0 MLI 1 MEM CHK MCB05573_mod Figure 1 Data Sheet TC1796 Block Diagram 10 V1.0, 2008-04 TC1796 Preliminary 2.2 General Device Information Logic Symbol TSTRES D[31:0] TESTMODE General Control A[23:0] HDRST 5 PORST NMI 13 BYPASS BFLCKO XTAL2 16 VD D OSC VD DOSC3 VSSOSC 16 14 TRST JTAG / OCDS TCK 16 TDI TDO 16 TMS 8 BRKIN TC1796 BRKOUT 8 TRCLK 9 VD DEBU 11 VD D P 13 VD D 2 VD D FL3 9 4 Figure 2 Data Sheet Port 1 Port 2 2 2 10 Alternate Functions : MLI0 / SCU SSC0 / SSC1 / GPTA Port 3 GPTA Port 4 Port 5 Port 6 ASC0 / ASC1 / MSC0 / MSC1 /MLI0 ASC0 / ASC1 / SSC1 / CAN Port 7 ADC0 / ADC1 Port 8 MLI 1 / GPTA MSC0 / MSC1 / GPTA Port 9 Port 10 HWCFG Dedicated SSC0 I/O Lines 8 V FAR EF VFAGN D VD D MF VSSMF VDD AF VSSAF N.C. Port 0 6 VD D SBRAM 62 VSS FADC Analog Power Supply 12 8 TR[15:0] Digital Circuitry Power Supply External Bus Unit Interface BFCLKI XTAL1 Oscillator Chip Select Control LVDS MSC Outputs AN[43:0] ADC Analog Inputs VAR EFx VAGND x VD D M VSSM ADC0 /ADC1 Analog Power Supply MCA05583_mod TC1796 Logic Symbol 11 V1.0, 2008-04 TC1796 Preliminary 2.3 Pin Configuration 1 A B C D E F General Device Information N.C. P2.6 P2.5 P2.4 2 3 4 5 6 P2.9 P2.13 P2.15 P0.14 P0.5 P2.7 P2.10 P2.14 P0.9 P0.6 7 P0.2 P0.4 P2.8 P2.11 P2.12 P0.12 P0.10 P0.8 P2.3 P2.2 P0.15 P0.13 P0.11 VDDP P6.12 P6.11 P6.6 P6.14 P6.10 P6.4 8 P0.1 9 10 P0.0 P3.14 P3.5 P0.3 P3.15 P3.6 P0.7 VSS 11 P3.3 P3.7 P3.10 P3.9 VDD 12 P3.1 P3.0 P3.4 13 P5.1 P5.0 P3.2 14 P5.2 P5.3 P5.5 P3.8 P3.12 P3.13 P3.11 VDDP 15 16 P5.7 SO N1 FCL V DDFL3 P9.0 P1A P9.3 P10.0 P5.6 SO P1A FCL V DDFL3 P9.1 N1 PO TEST V P9.2 P10.1 RST MODE DDP P5.4 SO P0A FCL N0 VDD SO N0 VSS 17 18 FCL P0A P9.4 19 P9.6 P9.5 20 21 22 NMI P9.8 P10.2 N.C. P9.7 P10.3 VDDP P6.8 P6.15 P6.13 P6.7 P6.5 H P8.1 P8.0 N.C. VDD J P8.4 P8.3 P8.2 VSS K P8.7 P8.5 P8.6 VDDP L 24 25 26 VSS A VSS VDD B VDD BRK IN C TDO BRK OUT D TCK TDI VDD E TRST TMS VSS VDD OSC OSC VDDP VSS VDD P6.9 G 23 HD BY VDDP RST PASS VSS VDD OSC3 F TST XTAL XTAL RES 2 1 G VDDEBU VDDEBU VDDEBU VDDEBU H N.C. A5 A0 A1 A2 J TR12 TR13 TR15 VSS VSS VSS VSS VSS A9 A6 A3 A4 K P1.15 P1.14 P1.13 P1.11 TR11 TR10 TR14 VSS VSS VSS VSS VSS VSS A13 A7 A8 L M P1.10 P1.9 P1.8 P1.5 TR9 TR8 VSS VSS VSS VSS VSS VSS VDDEBU A12 A11 A10 M N P1.3 P1.7 P1.6 P1.4 VSS VSS VSS VSS VSS VSS VSS VSS A15 A16 A17 A14 N P P1.2 P1.1 P1.0 P1.12 VSS VSS VSS VSS VSS VSS VSS VSS VDD A19 A20 A18 P R VDD P7.1 P7.0 VDD TR6 TR7 TR5 VSS VSS VSS VSS VSS VSS A21 A23 A22 R SBRAM T P7.6 P7.5 P7.4 VSS TR CLK TR3 TR1 VSS VSS VSS VSS VSS VDDEBU D1 D3 D0 T U AN23 P7.7 P7.3 P7.2 TR4 TR2 TR0 VSS VSS VSS VSS VSS D6 D9 D5 D2 U V AN22 AN21 AN19 AN16 VDD D13 D8 D4 V W AN20 AN17 AN13 VDDM VSS D16 D12 D7 W Y AN18 AN14 AN10 VSSM VDDEBU D18 D14 D10 Y AA AN15 AN11 AN5 AN2 AB AN12 AN3 AN7 AN9 SLSO VDDP P4.8 P4.12 1 AC AN8 AN4 AN32 AN38 AN42 VAGND1 AN26 AN24 VDDAF VSS VDD P4.4 AD AN6 AN1 AN34 AN40 AN35 VAREF1 AN27 AN25 VSSAF P4.0 P4.2 P4.5 P4.11 P4.15 SLSI0 VDDP AN33 AN36 AN41 VAREF0 AN28 AN30 VFAGND VDDMF P4.1 P4.3 SLSO MRST VDDP P4.7 P4.13 0 0 AN37 AN39 AN43 VAGND0 AN29 AN31 VFAREF VSSMF SCLK MTSR VDDP HOLD BC2 MR/W P4.9 P4.10 P4.14 0 0 AE AF AN0 N.C. 1 2 3 4 5 6 7 8 9 P4.6 10 11 12 13 14 15 16 VSS D19 D22 D17 D11 AA VDD D21 D20 D15 AB VDDEBU VSS VDD N.C. VDDEBU VSS D28 D25 D23 AC BC1 HLDA CS3 CS2 CS1 BREQ N.C. D31 D27 D24 AD CS0 N.C. D30 D29 D26 AE BF BF CLKI CLKO N.C. AF BC0 17 CS BC3 WAIT COMB 18 19 N.C. RD RD/ WR ADV BAA 20 21 22 23 24 25 26 MCA05584 Figure 3 Data Sheet TC1796 Pinning for P/PG-BGA-416-4 Package (Top view) 12 V1.0, 2008-04 TC1796 Preliminary 2.4 General Device Information Pad Driver and Input Classes Overview The TC1796 provides different types and classes of input and output lines. For understanding of the abbreviations in Table 2 starting at the next page, Table 4 gives an overview on the pad type and class types. 2.5 Data Sheet Pin Definitions and Functions 13 V1.0, 2008-04 TC1796 Preliminary Table 2 Symbol General Device Information Pin Definitions and Functions Pins I/O Pad Class Power Functions Supply External Bus Interface Lines (EBU) D[31:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Data Sheet I/O B1 T26 T24 U26 T25 V26 U25 U23 W26 V25 U24 Y26 AA26 W25 V24 Y25 AB26 W24 AA25 Y24 AA23 AB25 AB24 AA24 AC26 AD26 AC25 AE26 AD25 AC24 AE25 AE24 AD24 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDDEBU EBU Data Bus Lines The EBU Data Bus Lines D[31:0] serve as external data bus. Data bus line 0 Data bus line 1 Data bus line 2 Data bus line 3 Data bus line 4 Data bus line 5 Data bus line 6 Data bus line 7 Data bus line 8 Data bus line 9 Data bus line 10 Data bus line 11 Data bus line 12 Data bus line 13 Data bus line 14 Data bus line 15 Data bus line 16 Data bus line 17 Data bus line 18 Data bus line 19 Data bus line 20 Data bus line 21 Data bus line 22 Data bus line 23 Data bus line 24 Data bus line 25 Data bus line 26 Data bus line 27 Data bus line 28 Data bus line 29 Data bus line 30 Data bus line 31 14 V1.0, 2008-04 TC1796 Preliminary Table 2 Symbol General Device Information Pin Definitions and Functions (cont'd) Pins A[23:0] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 J24 J25 J26 K25 K26 J23 K24 L25 L26 K23 M26 M25 M24 L24 N26 N23 N24 N25 P26 P24 P25 R24 R26 R25 I/O Pad Class Power Functions Supply O B1 VDDEBU EBU Address Bus Lines A[23:0] The EBU Address Bus Lines serve as external address bus. Address bus line 0 Address bus line 1 Address bus line 2 Address bus line 3 Address bus line 4 Address bus line 5 Address bus line 6 Address bus line 7 Address bus line 8 Address bus line 9 Address bus line 10 Address bus line 11 Address bus line 12 Address bus line 13 Address bus line 14 Address bus line 15 Address bus line 16 Address bus line 17 Address bus line 18 Address bus line 19 Address bus line 20 Address bus line 21 Address bus line 22 Address bus line 23 B1 VDDEBU Chip Select Output Lines Chip select output line 0 Chip select output line 1 Chip select output line 2 Chip select output line 3 B1 VDDEBU Combined Chip Select Output for Global Select / Emulator Memory Region/Emulator Overlay Memory O O O O O O O O O O O O O O O O O O O O O O O O CS0 CS1 CS2 CS3 AE21 AD21 AD20 AD19 O O O O CS COMB AE19 O Data Sheet 15 V1.0, 2008-04 TC1796 Preliminary Table 2 Symbol General Device Information Pin Definitions and Functions (cont'd) Pins I/O Pad Class Power Functions Supply BFCLKO AF25 O B2 VDDEBU BFCLKI AF24 I B1 Burst Mode Flash Clock Input (feedback clock) RD AF20 O B1 Read Control Line RD/WR AF21 O B1 Write Control Line ADV AF22 O B1 Address Valid Output MR/W AF19 O B1 Motorola-style Read/Write Control Signal B1 Byte Control Lines Byte control line 0 Byte control line 1 Byte control line 2 Byte control line 3 Burst Mode Flash Clock Output (nondifferential) BC0 BC1 BC2 BC3 AE17 AD17 AF18 AE18 O O O O WAIT AE20 I B1 Wait Input for inserting Wait-States BAA AF23 O B1 Burst Address Advance Output HOLD AF17 I B1 Hold Request Input HLDA AD18 O B1 Hold Acknowledge Output BREQ AD22 O B1 Bus Request Output Data Sheet 16 V1.0, 2008-04 TC1796 Preliminary Table 2 Symbol General Device Information Pin Definitions and Functions (cont'd) Pins I/O Pad Class Power Functions Supply I/O A1 VDDP Parallel Ports P0 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 Data Sheet A9 A8 A7 B8 B7 A6 B6 C8 C7 B5 C6 D6 C5 D5 A5 D4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Port 0 Port 0 is a 16-bit bidirectional generalpurpose I/O port. Port 0 I/O line 0 Port 0 I/O line 1 Port 0 I/O line 2 Port 0 I/O line 3 Port 0 I/O line 4 Port 0 I/O line 5 Port 0 I/O line 6 Port 0 I/O line 7 Port 0 I/O line 8 Port 0 I/O line 9 Port 0 I/O line 10 Port 0 I/O line 11 Port 0 I/O line 12 Port 0 I/O line 13 Port 0 I/O line 14 Port 0 I/O line 15 The states of the Port 0 pins are latched into the software configuration input register SCU_SCILR at the rising edge of HDRST. Therefore, Port 0 pins can be used for operating mode selections by software. 17 V1.0, 2008-04 TC1796 Preliminary Table 2 Symbol General Device Information Pin Definitions and Functions (cont'd) Pins P1 I/O Pad Class Power Functions Supply I/O A1/A2 VDDP Port 1 Port 1 is a 16-bit bi-directional generalpurpose I/O port which can be alternatively used for the MLI0 interface or as external trigger input lines. P1.0 P1.1 P1.2 P1.3 P3 P2 P1 N1 I I I I I A1 A1 A1 A1 A1 REQ0 REQ1 REQ2 REQ3 TREADY0B P1.4 N4 O A2 TCLK0 P1.5 M4 I A1 TREADY0A P1.6 N3 O A2 TVALID0A P1.7 N2 O A2 TDATA0 P1.8 M3 I A1 RCLK0A P1.9 M2 O A2 RREADY0A P1.10 M1 I A1 RVALID0A P1.11 L4 I A1 RDATA0A P1.12 P1.13 P4 L3 O I A2 A1 SYSCLK RCLK0B P1.14 L2 I A1 RVALID0B P1.15 L1 I A1 RDATA0B Data Sheet 18 External trigger input 0 External trigger input 1 External trigger input 3 External trigger input 2 MLI0 transmit channel ready input B MLI0 transmit channel clock output MLI0 transmit channel ready input A MLI0 transmit channel valid output A MLI0 transmit channel data output MLI0 receive channel clock input A MLI0 receive channel ready output A MLI0 receive channel valid input A MLI0 receive channel data input A System clock output MLI0 receive channel clock input B MLI0 receive channel valid input B MLI0 receive channel data input B V1.0, 2008-04 TC1796 Preliminary Table 2 Symbol General Device Information Pin Definitions and Functions (cont'd) Pins P2 I/O Pad Class Power Functions Supply I/O A1/A2 VDDP Port 2 Port 2 is a 14-bit bi-directional generalpurpose I/O port which can be used alternatively for the six upper SSC slave select outputs or for GPTA I/O lines. P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 D3 D2 D1 C1 B1 B2 O O O O O O A2 A2 A2 A2 A2 A2 SLSO2 SLSO3 SLSO4 SLSO5 SLSO6 SLSO7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 C2 A2 B3 C3 C4 A3 B4 A4 I/O I/O I/O I/O I/O I/O I/O I/O A1 A1 A1 A1 A1 A1 A1 A1 IN0 / OUT0 line of GPTA IN1 / OUT1 line of GPTA IN2 / OUT2 line of GPTA IN3 / OUT3 line of GPTA IN4 / OUT4 line of GPTA IN5 / OUT5 line of GPTA IN6 / OUT6 line of GPTA IN7 / OUT7 line of GPTA Data Sheet 19 Slave select output line 2 Slave select output line 3 Slave select output line 4 Slave select output line 5 Slave select output line 6 Slave select output line 7 V1.0, 2008-04 TC1796 Preliminary Table 2 Symbol General Device Information Pin Definitions and Functions (cont'd) Pins P3 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.9 P3.8 P3.10 P3.11 P3.12 P3.13 P3.14 P3.15. Data Sheet B12 A12 C13 B11 C12 A11 B10 C9 D10 C11 C10 D13 D11 D12 A10 B9 I/O Pad Class Power Functions Supply I/O A1 VDDP Port 3 Port 3 is a 16-bit bi-directional generalpurpose I/O port which can be alternatively used for GPTA I/O lines. IN8 / OUT8 line of GPTA IN9 / OUT9 line of GPTA IN10 / OUT10 line of GPTA IN11 / OUT11 line of GPTA IN12 / OUT12 line of GPTA IN13 / OUT13 line of GPTA IN14 / OUT14 line of GPTA IN15 / OUT15 line of GPTA IN16 / OUT16 line of GPTA IN17 / OUT17 line of GPTA IN18 / OUT18 line of GPTA IN19 / OUT19 line of GPTA IN20 / OUT20 line of GPTA IN21 / OUT21 line of GPTA IN22 / OUT22 line of GPTA IN23 / OUT23 line of GPTA 20 V1.0, 2008-04 TC1796 Preliminary Table 2 Symbol General Device Information Pin Definitions and Functions (cont'd) Pins P4 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P4.8 P4.9 P4.10 P4.11 P4.12 P4.13 P4.14 P4.15 Data Sheet AD10 AE10 AD11 AE11 AC12 AD12 AF10 AE12 AC13 AF11 AF12 AD13 AC14 AE13 AF13 AD14 I/O Pad Class Power Functions Supply I/O A1/A2 VDDP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A21) A21) A21) A21) A21) A21) A21) A21) A1 A1 A1 A1 A1 A1 A1 A1 Port 4 Port 4 is a 16-bit bi-directional generalpurpose I/O port which can be alternatively used for GPTA I/O lines. IN24 / OUT24 line of GPTA IN25 / OUT25 line of GPTA IN26 / OUT26 line of GPTA IN27 / OUT27 line of GPTA IN28 / OUT28 line of GPTA IN29 / OUT29 line of GPTA IN30 / OUT30 line of GPTA IN31 / OUT31 line of GPTA IN32 / OUT32 line of GPTA IN33 / OUT33 line of GPTA IN34 / OUT34 line of GPTA IN35 / OUT35 line of GPTA IN36 / OUT36 line of GPTA IN37 / OUT37 line of GPTA IN38 / OUT38 line of GPTA IN39 / OUT39 line of GPTA 21 V1.0, 2008-04 TC1796 Preliminary Table 2 Symbol General Device Information Pin Definitions and Functions (cont'd) Pins P5 I/O Pad Class Power Functions Supply I/O A2 VDDP Port 5 Port 5 is an 8-bit bi-directional generalpurpose I/O port which can be alternatively used for ASC0/1 or MSC0/1 lines. P5.0 B13 I/O RXD0A P5.1 P5.2 A13 A14 O I/O TXD0A RXD1A P5.3 B14 O TXD1A P5.4 C15 O EN00 O RREADY0B I O SDI0 EN10 O TVALID0B I SDI1 P5.5 P5.6 P5.7 Data Sheet C14 B15 A15 22 ASC0 receiver input / output A ASC0 transmitter output A ASC1 receiver input / output A ASC1 transmitter output A P5.3 is latched with the rising edge of PORST if BYPASS = 1 and stored in inverted state as bit OSC_CON.MOSC. MSC0 device select output 0 MLI0 receive channel ready output B MSC0 serial data input MSC1 device select output 0 MLI0 transmit channel valid output B MSC1 serial data input V1.0, 2008-04 TC1796 Preliminary Table 2 Symbol General Device Information Pin Definitions and Functions (cont'd) Pins P6 I/O Pad Class Power Functions Supply I/O A2 VDDP Port 6 Port 6 is a 12-bit bi-directional generalpurpose I/O port which can be alternatively used for SSC1, ASC0/1, and CAN I/O lines. P6.4 F3 O I MTSR1 P6.5 G4 MRST1 P6.6 P6.7 P6.8 E3 G3 F4 I O I/O I I I/O P6.9 E4 O TXDCAN0 P6.10 F2 O I I/O TXD0B RXDCAN1 RXD1B P6.11 E2 O TXDCAN1 P6.12 P6.13 E1 G2 O I O TXD1B RXDCAN2 TXDCAN2 P6.14 P6.15 F1 G1 I O RXDCAN3 TXDCAN3 Data Sheet SCLK1 SLSI1 RXDCAN0 RXD0B 23 SSC1 master transmit output / SSC1 slave receive input SSC1 master receive input / SSC1 slave transmit output SSC1 clock input / output SSC1 slave select input CAN node 0 receiver input ASC0 receiver input / output B CAN node 0 transmitter output ASC0 transmitter output B CAN node 1 receiver input ASC1 receiver input / output B CAN node 1 transmitter output ASC1 transmitter output B CAN node 2 receiver input CAN node 2 transmitter output CAN node 3 receiver input CAN node 3 transmitter output V1.0, 2008-04 TC1796 Preliminary Table 2 Symbol General Device Information Pin Definitions and Functions (cont'd) Pins P7 I/O Pad Class Power Functions Supply I/O A1 VDDP Port 7 Port 7 is an 8-bit bi-directional generalpurpose I/O port which can be alternatively used as external trigger input lines and for ADC0/1 external multiplexer control. P7.0 P7.1 R3 R2 I I O REQ4 REQ5 AD0EMUX2 P7.2 U4 O AD0EMUX0 P7.3 U3 O AD0EMUX2 P7.4 P7.5 P7.6 T3 T2 T1 I I O REQ6 REQ7 AD1EMUX0 P7.7 U2 O AD1EMUX1 Data Sheet 24 External trigger input 4 External trigger input 5 ADC0 external multiplexer control output 2 ADC0 external multiplexer control output 0 ADC0 external multiplexer control output 1 External trigger input 6 External trigger input 7 ADC1 external multiplexer control output 0 ADC1 external multiplexer control output 1 V1.0, 2008-04 TC1796 Preliminary Table 2 Symbol Pin Definitions and Functions (cont'd) Pins P8 P8.0 General Device Information I/O Pad Class Power Functions Supply I/O A1/A2 VDDP H2 O H1 I/O A2 I A1 IN40/OUT40 TREADY1A J3 I/O A1 O A2 IN41/OUT41 TVALID1A J2 I/O A2 O A2 IN42/OUT42 TDATA1 J1 I/O A2 I A1 IN43/OUT43 RCLK1A K2 I/O A1 O A2 IN44/OUT44 RREADY1A P8.6 K3 I/O A2 I A1 IN45/OUT45 RVALID1A P8.7 K1 I/O A1 I A1 IN46/OUT46 RDATA1A I/O A1 IN47/OUT47 P8.1 P8.2 P8.3 P8.4 P8.5 Data Sheet A2 Port 8 Port 8 is an 8-bit bi-directional generalpurpose I/O port which can be alternatively used for the MLI1 interface or as GPTA I/O lines. TCLK1 25 MLI1 transmit channel clock output I/O line of GPTA MLI1 transmit channel ready input A I/O line of GPTA MLI1 transmit channel valid output A I/O line of GPTA MLI1 transmit channel data output I/O line of GPTA MLI1 receive channel clock input A I/O line of GPTA MLI1 receive channel ready output A I/O line of GPTA MLI1 receive channel validinput A I/O line of GPTA MLI1 receive channel data input A I/O line of GPTA V1.0, 2008-04 TC1796 Preliminary Table 2 Symbol General Device Information Pin Definitions and Functions (cont'd) Pins P9 I/O Pad Class Power Functions Supply I/O A2 VDDP Port 9 Port 9 is a 9-bit bi-directional generalpurpose I/O port which can be alternatively used as GPTA or MSC0/1 I/O lines. P9.0 A19 I/O O IN48/OUT48 EN12 P9.1 B19 I/O O IN49/OUT49 EN11 P9.2 B20 P9.3 A20 P9.4 D18 I/O O I/O O I/O O IN50/OUT50 SOP1B IN51/OUT51 FCLP1 IN52/OUT52 EN03 P9.5 D19 I/O O IN53/OUT53 EN02 P9.6 C19 I/O O IN54/OUT54 EN01 P9.7 D20 P9.8 C20 I/O O O IN55/OUT55 SOP0B FCLP0B Data Sheet 26 I/O line of GPTA MSC1 device select output 2 I/O line of GPTA MSC1 device select output 1 I/O line of GPTA MSC1 serial data output I/O line of GPTA MSC1 clock output I/O line of GPTA MSC0 device select output 3 I/O line of GPTA MSC0 device select output 2 I/O line of GPTA MSC0 device select output 1 I/O line of GPTA MSC0 serial data output MSC0 clock output V1.0, 2008-04 TC1796 Preliminary Table 2 Symbol General Device Information Pin Definitions and Functions (cont'd) Pins P10 P10.0 P10.1 P10.2 P10.3 A21 B21 C21 D21 I/O Pad Class Power Functions Supply I VDDP Hardware Configuration Inputs / Port 10 These inputs are boot mode (hardware configuration) control inputs. They are latched with the rising edge of HDRST. Port 10 input line 0 / HWCFG0 Port 10 input line 1 / HWCFG1 Port 10 input line 2 / HWCFG2 Port 10 input line 3 / HWCFG3 After reset (HDRST = 1) the state of the Port 10 input pins may be modified from the reset configuration state. There actual state can be read via software (P10_IN register). During normal operation input HWCFG1 serves as emergency shut-off control input for certain I/O lines (e.g. GPTA related outputs). VDDP SSC0 Slave Select Output Line 0 A1 I I I I Dedicated Peripheral I/Os SLSO0 AE14 O SLSO1 AC15 O SSC0 Slave Select Output Line 1 MTSR0 AF15 O I SSC0 Master Transmit Output / SSC0 Slave Receive Input MRST0 AE15 I O SSC0 Master Receive Input / SSC0 Slave Transmit Output SCLK0 AF14 I/O SSC0 Clock Input/Output SLSI0 AD15 I SSC0 Slave Select Input Data Sheet A2 27 V1.0, 2008-04 TC1796 Preliminary Table 2 Symbol General Device Information Pin Definitions and Functions (cont'd) Pins I/O Pad Class Power Functions Supply MSC Outputs C FCLP0A C18 O FCLN0 C17 O SOP0A C16 O SON0 D17 O FCLP1A A17 O FCLN1 B17 O SOP1A B16 O SON1 A16 O Data Sheet VDDP LVDS MSC Clock and Data Outputs2) MSC0 differential driver clock output positive A MSC0 differential driver clock output negative MSC0 differential driver serial data output positive A MSC0 differential driver serial data output negative MSC1 differential driver clock output positive A MSC1 differential driver clock output negative MSC1 differential driver serial data output positive A MSC1 differential driver serial data output negative 28 V1.0, 2008-04 TC1796 Preliminary Table 2 Symbol General Device Information Pin Definitions and Functions (cont'd) Pins I/O Pad Class Power Functions Supply I - Analog Inputs AN[43:0] AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 Data Sheet AE1 AD2 AA4 AB3 AC2 AA3 AD1 AB4 AC1 AB2 Y3 AA2 AB1 W3 Y2 AA1 V4 W2 Y1 V3 W1 V2 V1 U1 AC8 AD8 AC7 AD7 AE6 AF6 AE7 AF7 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I D ADC Analog Input Port The ADC Analog Input Port provides 44 analog input lines for the A/D converters ADC0, ADC1, and FADC. Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 Analog input 6 Analog input 7 Analog input 8 Analog input 9 Analog input 10 Analog input 11 Analog input 12 Analog input 13 Analog input 14 Analog input 15 Analog input 16 Analog input 17 Analog input 18 Analog input 19 Analog input 20 Analog input 21 Analog input 22 Analog input 23 Analog input 24 Analog input 25 Analog input 26 Analog input 27 Analog input 28 Analog input 29 Analog input 30 Analog input 31 29 V1.0, 2008-04 TC1796 Preliminary Table 2 Symbol AN32 AN33 AN34 AN35 AN36 AN37 AN38 AN39 AN40 AN41 AN42 AN43 General Device Information Pin Definitions and Functions (cont'd) Pins AC3 AE2 AD3 AD5 AE3 AF2 AC4 AF3 AD4 AE4 AC5 AF4 TR[15:0] I/O Pad Class D - ADC Analog Input Port (cont'd) Analog input 32 Analog input 33 Analog input 34 Analog input 35 Analog input 36 Analog input 37 Analog input 38 Analog input 39 Analog input 40 Analog input 41 Analog input 42 Analog input 43 A3 VDDP OCDS Level 2 Debug Trace Lines2) (located on center balls) Trace output line 0 Trace output line 1 Trace output line 2 Trace output line 3 Trace output line 4 Trace output line 5 Trace output line 4 Trace output line 7 Trace output line 8 Trace output line 9 Trace output line 10 Trace output line 11 Trace output line 12 Trace output line 13 Trace output line 14 Trace output line 15 I I I I I I I I I I I I O TR0 TR1 TR2 TR3 TR4 TR5 TR6 TR7 TR8 TR9 TR10 TR11 TR12 TR13 TR14 TR15 U12 T12 U11 T11 U10 R12 R10 R11 M11 M10 L11 L10 K10 K11 L12 K12 O O O O O O O O O O O O O O O O TRCLK T10 O Data Sheet Power Functions Supply A4 Trace Clock for OCDS Level 2 Debug Trace Lines1) (located on a center ball) 30 V1.0, 2008-04 TC1796 Preliminary Table 2 Symbol General Device Information Pin Definitions and Functions (cont'd) Pins I/O Pad Class Power Functions Supply VDDP System I/O JTAG Module Reset/Enable Input2) TRST F23 I A2 TCK E24 I A2 JTAG Module Clock Input2) TDI E25 I A1 JTAG Module Serial Data Input TDO D25 O A2 JTAG Module Serial Data Output TMS F24 I A1 JTAG Module State Machine Control Input BRKIN C26 I/O A3 OCDS Break Input (Alternate Output)2) BRK OUT D26 I/O A3 OCDS Break Output (Alternate Input)2) NMI A22 I Non-Maskable Interrupt Input (input pad with input spike-filter.) HDRST A23 I/O A2 Hardware Reset Input / Reset Indication Output (open drain pad with input spike-filter.) PORST B22 I - Power-on Reset Input (input pad with input spike-filter.) BYPASS A24 I A1 PLL Bypass Select Input This input has to be held stable between to power-on resets. With BYPASS = 1 the spike filters in the HDRST, PORST, and NMI inputs are switched off. TEST MODE B23 I - Test Mode Select Input For normal operation of the TC1796, this pin should be connected to high level. (input pad, test function only, without input spike-filter.) TSTRES G24 I - Test Reset Input For normal operation of the TC1796, this pin should be connected to low level. Otherwise an unpredictable reset behavior may occur. (input pad, test function only, without input spike-filter.) Data Sheet - 31 V1.0, 2008-04 TC1796 Preliminary Table 2 General Device Information Pin Definitions and Functions (cont'd) Symbol Pins I/O Pad Class Power Functions Supply XTAL1 XTAL2 G26 G25 I O n.a. VDD Oscillator / PLL / Clock Generator Input / Output Pins2) N.C. A1 C22 G23 H3 AF1 AF26 AC21 AD23 AE22 AE23 - - - Not Connected These pins are reserved for future extension and should not be connected externally. W4 - - - ADC0/1 Analog Part Power Supply (3.3V) Y4 - - - ADC0/1 Analog Part Ground for VDDM AE9 - - - FADC Analog Part Power Supply (3.3V) AF9 - - - VFADC Analog Part Ground for VDDAF AC9 - - - FADC Analog Part Log. Pow. Sup. (1.5V) AD9 - - - FADC Analog Part Log Ground for VDDAF AE5 - - - ADC0 Reference Voltage AF5 - - - ADC0 Reference Ground AD6 - - - ADC1 Reference Voltage AC6 - - - ADC1 Reference Ground AF8 - - - FADC Reference Voltage AE8 - - - FADC Reference Ground F26 - - - Main Oscillator Power Supply (1.5V) E26 - - - Main Oscillator Power Supply (3.3V) F25 - - - Main Oscillator Ground A18 B18 - - - Power Supply for Flash (3.3V) - - - Power Supply for Stand-by SRAM (1.5V) Power Supplies VDDM VSSM VDDMF VSSMF VDDAF VSSAF VAREF0 VAGND0 VAREF1 VAGND1 VFAREF VFAGND VDDOSC3) VDDOSC3 VSSOSC3) VDDFL3 VDDSBRAM R1 Data Sheet 32 V1.0, 2008-04 TC1796 Preliminary Table 2 General Device Information Pin Definitions and Functions (cont'd) Symbol Pins I/O Pad Class Power Functions Supply VDDEBU H23 H24 H25 H26 M23 T23 Y23 AC18 AC22 - - - EBU Power Supply (2.3 - 3.3V) VDD B26 C25 D9 D16 D24 E23 H4 P23 R4 V23 AB23 AC11 AC20 - - - Core Power Supply (1.5V) VDDP A25 B24 C23 D7 D14 D22 K4 AC16 AD16 AE16 AF16 - - - Port Power Supply (3.3V) (also for OCDS) VSS See - Table 3 - - Ground 15 VSS lines are located at outer balls. 47 VSS lines are located at center balls. 1) In order to minimize noise coupling to the on-chip A/D converters, it is recommended to use these pins as less as possible in strong driver mode. Data Sheet 33 V1.0, 2008-04 TC1796 Preliminary General Device Information 2) In case of a power-fail condition (one or more power supply voltages drop below the specified voltage range), an undefined output driving level may occur at these pins. 3) Not bonded externally in the BC and BD steps of TC1796. An option for bonding them in future steps and products is kept open. Table 3 VSS Balls VSS Outer Balls VSS Center Balls A26, B25, C24, D8, D15, D23, J4, L23, R23, T4, W23, AC10, AC17, AC19, AC23 K[17:13], L[17:13], M[17:12], N[17:10], P[17:10], R[17:13], T[17:13], U[17:13] Data Sheet 34 V1.0, 2008-04 TC1796 Preliminary 2.5.1 General Device Information Pull-Up/Pull-Down Behavior of the Pins Table 4 List of Pull-Up/Pull-Down Reset Behavior of the Pins Pins PORST = 0 PORST = 1 TSTRES, Weak pull-up device active TDI, TMS, TESTMODE, BRKOUT, BRKIN, all GPIOs, RD, RD/WR, ADV, BC[3:0], MR/W, WAIT, BAA, HOLD, HLDA, BREQ, D[31:0], A[23,0], CS[3:0], CSCOMB NMI, PORST Weak pull-down device active BYPASS, SLSO0, SLSO1, MTSR0, MRST0, SCLK0, SLSI0, TDO, BFCLKI Weak pull-up device active High-impedance BFCLKO Weak pull-up device active Push-pull driver active HDRST Open-drain device drives 0 (strong pull-down) Weak pull-up device active Open-drain device active TRST, TCK High-impedance Weak pull-down device active Data Sheet 35 V1.0, 2008-04 TC1796 Preliminary 3 Functional Description Functional Description The following section gives an overview of the sub systems and the modules of the TC1796 and their connectivity. 3.1 System Architecture and On-Chip Bus Systems The TC1796 has four independent on-chip buses (see also TC1796 block diagram in Figure 1): * * * * Program Local Memory Bus (PLMB) Data Local Memory Bus (DLMB) System Peripheral Bus (SPB) Remote Peripheral Bus (RPB) The two LMB Buses (Program Local Memory Bus PLMB and Data Local Memory Bus DLMB) connect the TriCore CPU to its local resources for data and instruction fetches. The PLMB/DLMB Buses are synchronous and pipelined buses with variable block size transfer support. The protocol supports 8-, 16-, 32-, and 64-bit single transactions and variable length 64-bit block transfers. The System Peripheral Bus (SPB) is accessible by the CPU via the LFI Bridge. The LFI Bridge is a bi-directional bus bridge between the DLMB and the SPB. It supports all transactions types of both buses, DLMB Bus and FPI Bus. It handles address translation and transaction type translation between the two buses. The LFI Bridge further supports the pipelining of both connected buses. Therefore, no additional delay is created except for bus protocol conversions. The Remote Peripheral Bus (RPB) connects the peripherals with high data rates (SSC, ADC, FADC) with the Dual-port memory (DPRAM) in the DMI, relieving the SPB and the PLMB/DLMB Buses from these data transfers. The RPB is controlled by a bus switch which is located in the DMA controller. The two LMB Buses are running at CPU clock speed (clock rate of fCPU) while SPB and RPB are running at system clock speed (clock rate of fSYS). Note that fSYS can be equal to fCPU or half the fCPU frequency. Data Sheet 36 V1.0, 2008-04 TC1796 Preliminary 3.2 Functional Description On-Chip Memories As shown in the TC1796 block diagram on Page 10, some of the TC1796 units provide on-chip memories that are used as program or data memory. * * * * Program memory in PMU and PMI - 2 Mbyte on-chip Program Flash (PFLASH) - 16 Kbyte Boot ROM (BROM) - 48 Kbyte Scratch-Pad RAM (SPRAM) - 16 Kbyte Instruction Cache (ICACHE) Data memory in DMU, PMU and DMI - 56 Kbyte Local Data RAM (LDRAM) - 8 Kbyte Dual-port RAM (DPRAM) - 64 Kbyte Data Memory (SRAM) - 16 Kbyte data memory (SBRAM) for standby operation during power-down - 128 Kbyte on-chip Data Flash (DFLASH) Memory of the PCP2 - 32 Kbyte Code Memory (CMEM) - 16 Kbyte Parameter Memory (PRAM) On-chip SRAMs with parity error detection Features of the Program Flash * * * * * * * * * * * * 2 Mbyte on-chip program Flash memory Usable for instruction code execution or constant data storage 256-byte wide program interface - 256 bytes are programmed into PFLASH page in one step/command 256-bit read interface - Transfer from PFLASH to CPU/PMI by four 64-bit single-cycle burst transfers Dynamic correction of single-bit errors during read access Detection of double bit errors Fixed sector architecture - Eight 16 Kbyte, one 128 Kbyte, one 256 Kbyte, and three 512 Kbyte sectors - Each sector separately erasable - Each sector separately write-protectable Configurable read protection for complete PFLASH with sophisticated read access supervision, combined with write protection for complete PFLASH (protection against "Trojan horse" software) Configurable write protection for each sector - Each sector separately write-protectable - With capability to be re-programmed - With capability to be locked forever (OTP) Password mechanism for temporarily disable write or read protection On-chip programming voltage generation PFLASH is delivered in erased state (read all zeros) Data Sheet 37 V1.0, 2008-04 TC1796 Preliminary * * Functional Description JEDEC standard based command sequences for PFLASH control - Write state machine controls programming and erase operations - Status and error reporting by status flags and interrupt Margin check for detection of problematic PFLASH bits Features of the Data Flash * * * * * * * * * * * * * * * 128 Kbyte on-chip data Flash memory, organized in two 64 Kbyte banks Usable for data storage with EEPROM functionality 128 Byte program interface - 128 bytes are programmed into one DFLASH page by one step/command 64-bit read interface (no burst transfers) Dynamic correction of single-bit errors during read access Detection of double bit errors Fixed sector architecture - Two 64 Kbyte banks/sectors - Each sector separately erasable Configurable read protection (combined with write protection) for complete DFLASH together with PFLASH read protection Password mechanism to temporarily disable write and read protection Erasing/programming of one bank possible while reading data from the other bank Programming of one bank possible while erasing the other bank On-chip generation of programming voltage DFLASH is delivered in erased state (read all zeros) JEDEC-standard based command sequences for DFLASH control - Write state machine controls programming and erase operations - Status and error reporting by status flags and interrupt Margin check for detection of problematic DFLASH bits Data Sheet 38 V1.0, 2008-04 TC1796 Preliminary 3.3 Functional Description Architectural Address Map Table 5 shows the overall architectural address map as defined for the TriCore and implemented in TC1796. Table 5 TC1796 Architectural Address Map Seg- Contents ment Size Description 0-7 Global 8 x 256 Mbyte Reserved (MMU space), cached 8 Global Memory 256 Mbyte EBU (246 Mbyte), PMU with PFLASH, DFLASH, BROM, memory reserved for Emulation, cached 9 Global Memory 256 Mbyte FPI space; cached 10 Global Memory 256 Mbyte EBU (246 Mbyte), PMU with PFLASH, DFLASH, BROM, memory reserved for Emulation, noncached 11 Global Memory 256 Mbyte FPI space; non-cached 12 Local LMB Memory 256 Mbyte DMU, bottom 4 Mbyte visible from FPI Bus in segment 14, cached 13 DMI 64 Mbyte Local Data Memory RAM, non-cached PMI 64 Mbyte Local Code Memory RAM, non-cached EXTPER 96 Mbyte External Peripheral Space, non-cached EXTEMU 16 Mbyte External Emulator Range, non-cached BOOTROM 16 Mbyte Boot ROM space, BROM mirror; non-cached EXTPER 128 Mbyte External Peripheral Space non-speculative, no execution, non-cached 14 CPU[0 ..15] 16 x 8 image region Mbyte 15 LMBPER CSFRs INTPER Data Sheet 256 Mbyte Non-speculative, no execution, non-cached CSFRs of CPUs[0 ..15]; LMB & Internal Peripheral Space; non-speculative, no execution, non-cached 39 V1.0, 2008-04 TC1796 Preliminary 3.4 Functional Description Memory Protection System The TC1796 memory protection system specifies the addressable range and read/write permissions of memory segments available to the currently executing task. The memory protection system controls the position and range of addressable segments in memory. It also controls the kinds of read and write operations allowed within addressable memory segments. Any illegal memory access is detected by the memory protection hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the error. Thus, the memory protection system protects critical system functions against both software and hardware errors. The memory protection hardware can also generate signals to the Debug Unit to facilitate tracing illegal memory accesses. There are two Memory Protection Register Sets in the TC1796, numbered 0 and 1, which specify memory protection ranges and permissions for code and data. The PSW.PRS bit field determines which of these is the set currently in use by the CPU. Because the TC1796 uses a Harvard-style memory architecture, each Memory Protection Register Set is broken down into a Data Protection Register Set and a Code Protection Register Set. Each Data Protection Register Set can specify up to four address ranges to receive particular protection modes. Each Code Protection Register Set can specify up to two address ranges to receive particular protection modes. Each of the Data Protection Register Sets and Code Protection Register Sets determines the range and protection modes for a separate memory area. Each contains register pairs which determine the address range (the Data Segment Protection Registers and Code Segment Protection Registers) and one register (Data Protection Mode Register) which determines the memory access modes which apply to the specified range. Data Sheet 40 V1.0, 2008-04 TC1796 Preliminary 3.5 Functional Description External Bus Unit The External Bus Unit (EBU) of the TC1796 is the units that controls the transactions between external memories or peripheral units with the internal memories and peripheral units. The EBU is a part of the PMU and communicates with CPU and PMI via the Program Local Memory Bus. This configuration allows to get fast access times especially when using external burst FLASH memory devices. 32 Data Bus Data Path Control Control Lines 64 Burst Access State Machine Arbitration Signals Address Bus External Bus Arbitration 24 PLMB Data Region Selection 32 PLMB Address PLMB Interface Slave Master Asynchronous Access State Machine 64 Program Local Memory Bus Address Path Control External Bus Unit EBU MCB05713 Figure 4 EBU Block Diagram The following features are supported by the EBU: * * * 64-bit internal Program Local Memory Bus (PLMB) interface 32-bit external demultiplexed bus interface - Asynchronous read/write accesses support Intel-style and Motorola-style interface signals - Synchronous burst FLASH memory read - Five programmable regions associated each to one chip select output - Flexibly programmable access parameters for each chip select region - Little-endian and Big-endian support - Programmable wait state control Scalable external bus frequency - Derived from PLMB frequency (fCPU) divided by 1, 2, 3, or 4 - Max. 75 MHz Data Sheet 41 V1.0, 2008-04 TC1796 Preliminary * * * Functional Description Data buffering supported - Code prefetch buffer - Read/write buffer External bus arbitration control capability for the EBU bus Automatic self-configuration on boot from external memory 3.6 Peripheral Control Processor The Peripheral Control Processor (PCP2) in the TC1796 performs tasks that would normally be performed by the combination of a DMA controller and its supporting CPU interrupt service routines in a traditional computer system. It could easily be considered as the host processor's first line of defence as an interrupt-handling engine. The PCP2 can off-load the CPU from having to service time-critical interrupts. This provides many benefits, including: * * * * Avoiding large interrupt-driven task context-switching latencies in the host processor Reducing the cost of interrupts in terms of processor register and memory overhead Improving the responsiveness of interrupt service routines to data-capture and datatransfer operations Easing the implementation of multitasking operating systems. The PCP2 has an architecture that efficiently supports DMA-type transactions to and from arbitrary devices and memory addresses within the TC1796 and also has reasonable stand-alone computational capabilities. The PCP2 in the TC1796 contains an improved version of the TC1775's PCP with the following enhancements: * * * * * Optimized context switching Support for nested interrupts Enhanced instruction set Enhanced instruction execution speed Enhanced interrupt queueing The PCP2 is made up of several modular blocks as follows (see Figure 5): * * * * * * PCP2 Processor Core Code Memory (CMEM) Parameter Memory (PRAM) PCP2 Interrupt Control Unit (PICU) PCP2 Service Request Nodes (PSRN) System bus interface to the Flexible Peripheral Interface (FPI Bus) Data Sheet 42 V1.0, 2008-04 TC1796 Preliminary Functional Description Code Memory CMEM Parameter Memory PRAM PCP2 Processor Core PCP2 Service Req. Nodes PSRNs FPI-Interface FPI Bus PCP2 Interrupt Control Unit PICU PCP2 Interrupt Arbitration Bus CPU Interrupt Arbitration Bus Figure 5 PCP2 Block Diagram Table 6 PCP2 Instruction Set Overview MCB05666a Instruction Group Description DMA primitives Efficient DMA channel implementation Load/Store Transfer data between PRAM or FPI memory and the general purpose registers, as well as move or exchange values between registers Arithmetic Add, subtract, compare and complement Divide/Multiply Divide and multiply Logical And, Or, Exclusive Or, Negate Shift Shift right or left, rotate right or left, prioritize Bit Manipulation Set, clear, insert and test bits Flow Control Jump conditionally, jump long, exit Miscellaneous No operation, Debug Data Sheet 43 V1.0, 2008-04 TC1796 Preliminary 3.7 Functional Description DMA Controller and Memory Checker The Direct Memory Access (DMA) Controller of the TC1796 transfers data from data source locations to data destination locations without intervention of the CPU or other on-chip devices. One data move operation is controlled by one DMA channel. Sixteen DMA channels are provided in two independent DMA Sub-Blocks with eight DMA channels each. The Bus Switch provides the connection of two DMA Sub-Blocks to the two FPI Bus interfaces and an MLI bus interface. In the TC1796, the FPI Bus interfaces are connected to System Peripheral Bus and the Remote Peripheral Bus. The third specific bus interface provides a connection to Micro Link Interface modules (two MLI modules in the TC1796) and other DMA-related devices (Memory Checker module in the TC1796). Figure 6 shows the implementation details and interconnections of the DMA module. fDMA DMA Sub-Block 0 Request Selection/ Arbitration DMA Channels 00-07 Transaction Control Unitl DMA Requests of On-chip Periph. Units CH0n_OUT Bus Switch DMA Sub-Block 1 Address Decoder DMA Channels 10-17 Remote Peripheral Bus MLI0 Transaction Control Unit MLI1 Memory Checker CH1n_OUT Interrupt Request Nodes System Peripheral Bus MLI Interface Request Selection/ Arbitration FPI Bus Interface 0 DMA Controller FPI Bus Interface 1 Clock Control SR[15:0] DMA Interrupt Control Arbiter/ Switch Control MCB05680 Figure 6 Data Sheet DMA Controller Block Diagram 44 V1.0, 2008-04 TC1796 Preliminary Functional Description Features * * * * * * * * * * * 16 independent DMA channels - 8 DMA channels in each DMA Sub-Block - Up to 8 selectable request inputs per DMA channel - 2-level programmable priority of DMA channels within a DMA Sub-Block - Software and hardware DMA request - Hardware requests by selected on-chip peripherals and external inputs Programmable priority of the DMA Sub-Blocks on the bus interfaces Buffer capability for move actions on the buses (at least 1 move per bus is buffered). Individually programmable operation modes for each DMA channel - Single mode: stops and disables DMA channel after a predefined number of DMA transfers - Continuous mode: DMA channel remains enabled after a predefined number of DMA transfers; DMA transaction can be repeated. - Programmable address modification Full 32-bit addressing capability of each DMA channel - 4 GByte address range - Support of circular buffer addressing mode Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit Micro Link bus interface support Register set for each DMA channel - Source and destination address register - Channel control and status register - Transfer count register Flexible interrupt generation (the service request node logic for the MLI channels is also implemented in the DMA module) All buses connected to the DMA module must work at the same frequency. Read/write requests of the System Bus Side to the Remote Peripherals are bridged to the Remote Peripheral Bus (only the DMA is master on the RPB) Memory Checker The Memory Checker Module (MEMCHK) makes it possible to check the data consistency of memories. Any SPB bus master may access the memory checker. Preferable the DMA controller does it as described hereafter. It uses 8-bit, 16-bit, or 32bit DMA moves to read from the selected address area and to write the value read in a memory checker input register. With each write operation to the memory checker input register, a polynomial checksum calculation is triggered and the result of the calculation is stored in the memory checker result register. The memory checker uses the standard Ethernet polynomial, which is given by: G32 = x32+ x26+ x23+ x22+ x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x +1 Data Sheet 45 V1.0, 2008-04 TC1796 Preliminary Functional Description Note: Although the polynomial above is used for generation, the generation algorithm differs from the one that is used by the Ethernet protocol. 3.8 Interrupt System The TC1796 interrupt system provides a flexible and time-efficient means for processing interrupts. An interrupt request can be serviced either by the CPU or by the Peripheral Control Processor (PCP). These units are called "Service Providers". Interrupt requests are called "Service Requests" rather than "Interrupt Requests" in this document because they can be serviced by either of the Service Providers. Each peripheral in the TC1796 can generate service requests. Additionally, the Bus Control Units, the Debug Unit, the PCP, and even the CPU itself can generate service requests to either of the two Service Providers. As shown in Figure 7, each TC1796 unit that can generate service requests is connected to one or more Service Request Nodes (SRN). Each SRN contains a Service Request Control Register. Two arbitration buses connect the SRNs with two Interrupt Control Units, which handle interrupt arbitration among competing interrupt service requests, as follows: * * The Interrupt Control Unit (ICU) arbitrates service requests for the CPU and administers the CPU Interrupt Arbitration Bus. The Peripheral Interrupt Control Unit (PICU) arbitrates service requests for the PCP2 and administers the PCP2 Interrupt Arbitration Bus. The PCP2 can make service requests directly to itself (via the PICU), or it can make service requests to the CPU. The Debug Unit can generate service requests to the PCP2 or the CPU. The CPU can make service requests directly to itself (via the ICU), or it can make service requests to the PCP. The CPU Service Request Nodes are activated through software. Depending on the selected system clock frequency fSYS, the number of fSYS clock cycles per arbitration cycle must be selected as follows: * * fSYS < 60MHz: ICR.CONECYC = 1 and PCP_ICR.CONECYC = 1 fSYS > 60MHz: ICR.CONECYC = 0 and PCP_ICR.CONECYC = 0 Data Sheet 46 V1.0, 2008-04 TC1796 Preliminary Functional Description PCP Interrupt Arbitration Bus Service Requestors MSC0 MSC1 MLI0 MLI1 SSC0 SSC1 ASC0 ASC1 MultiCAN ADC0 ADC1 FADC GPTA0 GPTA1 LTCA2 STM FPU Flash Ext. Int. CPU Interrupt Arbitration Bus Service Req. Nodes 2 2 4 2 3 3 4 4 16 4 4 4 38 38 16 2 1 1 2 PCP Interrupt Control Unit 2 2 SRNs PICU Int. Req. 2 2 2 SRNs Interrupt Service Providers Int. Ack. PIPN 2 CCPN 4 4 SRNs 4 Service Req. Nodes 2 2 SRNs 2 5 3 3 SRNs 3 5 5 3 3 SRNs 3 2 4 4 SRNs 4 SRNs 4 5 4 5 2 SRNs 5 SRNs 5 2 5 CPU Interrupt Control Unit 16 4 4 4 SRNs 4 4 SRNs 4 Software & Breakpoint Interrupts CPU ICU Int. Req. PIPN 4 4 SRNs 5 SRNs 5 4 16 16 SRNs 5 SRNs PCP2 Int. Ack. CCPN 4 38 SRNs 38 SRNs 16 SRNs 2 SRNs 38 1 38 1 38 1 38 1 16 1 16 1 2 1 2 1 1 8 1 SRN 1 8 1 1 1 SRN 1 1 2 1 2 1 2 SRNs Service Req. Nodes 1 SRN 1 SRN 1 SRN 1 SRN 8 SRNs 1 SRN 1 SRN Service Requestors 1 1 1 1 8 1 1 DBCU PBCU SBCU RBCU DMA Cerberus Software MCB05742 Figure 7 Data Sheet Block Diagram of the TC1796 Interrupt System 47 V1.0, 2008-04 TC1796 Preliminary 3.9 Functional Description Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1) Figure 8 shows a global view of the functional blocks and interfaces of the two Asynchronous/Synchronous Serial Interfaces ASC0 and ASC1. Clock Control fASC P5.0 / A2 RXD0A RXD_I0 Address Decoder Interrupt Control To DMA A2 RXD_I1 ASC0 Module (Kernel) P5.1 / TXD0A RXD_O P6.8 / A2 RXD0B TXD_O EIR TBIR TIR RIR A2 P6.9 / TXD0B Port 5 & Port 6 Control ASC0_RDR ASC0_TDR P5.2 / A2 RXD1A RXD_I0 RXD_I1 ASC1 Module (Kernel) Interrupt Control To DMA Figure 8 A2 P5.3 / TXD1A RXD_O TXD_O EIR TBIR TIR RIR P6.10 / A2 RXD1B A2 P6.11 / TXD1B ASC1_RDR ASC1_TDR MCB05773 Block Diagram of the ASC Interfaces The Asynchronous/Synchronous Serial Interfaces provide serial communication between the TC1796 and other microcontrollers, microprocessors, or external peripherals. The ASC supports full-duplex asynchronous communication and half-duplex synchronous communication. In Synchronous Mode, data is transmitted or received synchronous to a shift clock which is generated by the ASC internally. In Asynchronous Data Sheet 48 V1.0, 2008-04 TC1796 Preliminary Functional Description Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be selected. Parity, framing, and overrun error detection are provided to increase the reliability of data transfers. Transmission and reception of data are double-buffered. For multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator provides the ASC with a separate serial clock signal which can be very accurately adjusted by a prescaler implemented as a fractional divider. Each ASC module, ASC0 and ASC1, communicates with the external world via two I/O lines. The RXD line is the receive data input signal (in Synchronous Mode also output). TXD is the transmit output signal. In the TC1796, the two I/O lines of each ASC can be alternatively switched to different pairs of GPIO lines. Clock control, address decoding, and interrupt service request control are managed outside the ASC module kernel. Features * * * * Full-duplex asynchronous operating modes - 8-bit or 9-bit data frames, LSB first - Parity bit generation/checking - One or two stop bits - Baud rate from 4.69 Mbit/s to 1.12 Bit/s (@ 75 MHz clock) - Multiprocessor mode for automatic address/data byte detection - Loop-back capability Half-duplex 8-bit synchronous operating mode - Baud rate from 9.38 Mbit/s to 763 Bit/s (@ 75 MHz clock) Double buffered transmitter/receiver Interrupt generation - On a transmit buffer empty condition - On a transmit last bit of a frame condition - On a receive buffer full condition - On an error condition (frame, parity, overrun error) Data Sheet 49 V1.0, 2008-04 TC1796 Preliminary 3.10 Functional Description High-Speed Synchronous Serial Interfaces (SSC0, SSC1) Figure 9 shows a global view of the functional blocks and interfaces of the two HighSpeed Synchronous Serial interfaces SSC0 and SSC1. fSSC0 Clock Control Master fCLC0 Slave SSC0 Module (Kernel) Address Decoder Interrupt Control EIR TIR RIR 8-Stage RXFIFO 8-Stage TXFIFO Slave Master A2 MTSR0 MTSRA MTSRB MRST A2 SCLK0 SCLKA SCLKB SCLK A2 SLSI0 SLSI[7:2] 1) M/S Selected SSC Enabled SSC0_TDR A2 MRST0 SLSI1 Slave SSC0_RDR To DMA MRSTA MRSTB MTSR Master SLSO0 A2 SLSO0 SLSO1 A2 SLSO1 SLSO[7:2] Clock Control Master fCLC1 Master Address Decoder Interrupt Control EIR TIR RIR SSC1_RDR To DMA SSC1_TDR SSC1 Module (Kernel) Slave Slave Master Slave SLSO[7:2] MRSTA MRSTB MTSR MTSRA MTSRB MRST SCLKA SCLKB SCLK SLSI1 A2 P2.7 / SLSO7 P6.4 / MTSR1 P6.5 / A2 MRST1 P6.6 / A2 SCLK1 P6.7 / A2 SLSI1 A2 Port 6 Control SLSI[7:2] 1) 1) These lines are not connected Figure 9 Port 2 Control P2.2 / SLSO2 ... fSSC1 A2 MCA05791 Block Diagram of the SSC Interfaces The SSC allows full-duplex and half-duplex serial synchronous communication up to 37.5 Mbit/s (@ 75 MHz module clock) with Receive and Transmit FIFO support. (FIFO only in SSC0). The serial clock signal can be generated by the SSC itself (Master Mode) Data Sheet 50 V1.0, 2008-04 TC1796 Preliminary Functional Description or can be received from an external master (Slave Mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPIcompatible devices. Transmission and reception of data is double-buffered. A shift clock generator provides the SSC with a separate serial clock signal. One slave select input is available for Slave Mode operation. Eight programmable slave select outputs (chip selects) are supported in Master Mode. The I/O lines of the SSC0 module are connected to dedicated device pins while the SSC1 module I/O lines are wired with general purpose I/O port lines. Features * * * * * * * * Master and Slave Mode operation - Full-duplex or half-duplex operation - Automatic pad control possible Flexible data format - Programmable number of data bits: 2 to 16 bits - Programmable shift direction: LSB or MSB shift first - Programmable clock polarity: Idle low or high state for the shift clock - Programmable clock/data phase: data shift with leading or trailing edge of the shift clock Baud rate generation from 37.5 Mbit/s to 572.2 Bit/s (@ 75 MHz module clock) Interrupt generation - On a transmitter empty condition - On a receiver full condition - On an error condition (receive, phase, baud rate, transmit error) Flexible SSC pin configuration One slave select input SLSI in slave mode Eight programmable slave select outputs SLSO in Master Mode - Automatic SLSO generation with programmable timing - Programmable active level and enable control SSC0 with 8-stage receive FIFO (RXFIFO) and 8-stage transmit FIFO (TXFIFO) - Independent control of RXFIFO and TXFIFO - 2- to 16-bit FIFO data width - Programmable receive/transmit interrupt trigger level - Receive and Transmit FIFO filling level indication - Overrun error generation - Underflow error generation Data Sheet 51 V1.0, 2008-04 TC1796 Preliminary 3.11 Functional Description Micro Second Bus Interfaces (MSC0, MSC1) The Micro Second Channel (MSC) interfaces provides a serial communication link typically used to connect power switches or other peripheral devices. The serial communication link is build up by a fast synchronous downstream channel and a slow asynchronous upstream channel. Figure 10 shows a global view the interface signals of the MSC interface. Clock Control fMSC0 FCLP fCLC0 FCLN SOP SR[1:0] Interrupt Control SR[3:2] Port 5 & Port 9 Control EN3 16 EMGSTOPMSC (from SCU) C FCLN0 C SOP0A C SON0 A2 P9.7 / SOP0B EN0 EN2 16 ALTINL[15:0] (from GPTA) ALTINH[15:0] FCLP0A A2 P9.8 / FCLP0B EN1 Upstr. Channel To DMA MSC0 Module (Kernel) Downstream Channel SON Address Decoder C A2 P5.4 / EN00 A2 P9.6 / EN01 A2 P9.5 / EN02 A2 P9.4 / EN03 SDI[0]1) A2 P5.5 / SDI0 C FCLP1A C FCLN1 C SOP1A C SON1 SR15 (from CAN) FCLP Clock Control fMSC1 FCLN fCLC1 SOP Address Decoder SR[1:0] Interrupt Control A2 P9.3 / FCLP1B A2 P9.2 / SOP1B EN0 Port 5 & Port 9 Control EN1 EN2 SR[3:2] ALTINL[15:0] (from GPTA) ALTINH[15:0] EN3 16 16 Upstr. Channel To DMA MSC1 Module (Kernel) Downstream Channel SON SDI[0] Data Sheet A2 P9.1 / EN11 A2 P9.0 / EN12 N.C. 1) 1) SDI[7:1] are connected to high level. Figure 10 A2 P5.6 / EN10 A2 P5.7 / SDI1 MCA05823 Block Diagram of the MSC Interfaces 52 V1.0, 2008-04 TC1796 Preliminary Functional Description The downstream and upstream channels of the MSC module communicate with the external world via nine I/O lines. Eight output lines are required for the serial communication of the downstream channel (clock, data, and enable signals). One out of eight input lines SDI[7:0] is used as serial data input signal for the upstream channel. The source of the serial data to be transmitted by the downstream channel can be MSC register contents or data that is provided at the ALTINL/ALTINH input lines. These input lines are typically connected to other on-chip peripheral units (for example with a timer unit like the GPTA). An emergency stop input signal allows to set bits of the serial data stream to dedicated values in emergency case. Clock control, address decoding, and interrupt service request control are managed outside the MSC module kernel. Service request outputs are able to trigger an interrupt or a DMA request. Features * * * Fast synchronous serial interface to connect power switches in particular, or other peripheral devices via serial buses High-speed synchronous serial transmission on downstream channel - Maximum serial output clock frequency: fFCL = fMSC/2 (= 37.5 Mbit/s @ 75 MHz module clock) - Fractional clock divider for precise frequency control of serial clock fMSC - Command, data, and passive frame types - Start of serial frame: Software-controlled, timer-controlled, or free-running - Programmable upstream data frame length (16 or 12 bits) - Transmission with or without SEL bit - Flexible chip select generation indicates status during serial frame transmission - Emergency stop without CPU intervention Low-speed asynchronous serial reception on upstream channel - Baud rate: fMSC divided by 8, 16, 32, 64, 128, 256, or 512 - Standard asynchronous serial frames - Parity error checker - 8-to-1 input multiplexer for SDI lines - Built-in spike filter on SDI lines Data Sheet 53 V1.0, 2008-04 TC1796 Preliminary 3.12 Functional Description MultiCAN Controller (CAN) Figure 11 shows a global view of the MultiCAN module with its functional blocks and interfaces. fCAN Clock Control Address Decoder Message Object Buffer DMA Interrupt Control LTCA2 MultiCAN Module Kernel fCLC INT_O [3:0] 128 Objects Linked List Control INT_O [15:4] INT_ O15 A2 CAN Node 3 TXDC3 RXDC3 CAN Node 2 TXDC2 RXDC2 CAN Node 1 TXDC1 RXDC1 CAN Node 0 TXDC0 RXDC0 A2 A2 Port 6 Control A2 A2 A2 A2 A2 CAN Control P6.15 / TXDCAN3 P6.14 / RXDCAN3 P6.13 / TXDCAN2 P6.12 / RXDCAN2 P6.11 / TXDCAN1 P6.10 / RXDCAN1 P6.9 / TXDCAN0 P6.8 / RXDCAN0 GPTA1 Timing Control and Synchronization GPTA0 ECTT1 ECTT3 Scheduler SCU Ext.Req. Unit ECTT4 ECTT5 ECTT2 ScheduleTiming DataMemory A1 A1 P1.3 / REQ3 P7.5 / REQ7 Time-Triggered Extension TTCAN MCA05864 Figure 11 Block Diagram of MultiCAN Module with Time-Triggered Extension The MultiCAN module contains four independently operating CAN nodes with Full-CAN functionality that are able to exchange Data and Remote Frames via a gateway function. Transmission and reception of CAN frames is handled in accordance with CAN specification V2.0 B (active). Each CAN node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. All four CAN nodes share a common set of message objects. Each message object can be individually allocated to one of the CAN nodes. Besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build gateways between the CAN nodes or to setup a FIFO buffer. The message objects are organized in double-chained linked lists, where each CAN node has it's own list of message objects. A CAN node stores frames only into message Data Sheet 54 V1.0, 2008-04 TC1796 Preliminary Functional Description objects that are allocated to the message object list of the CAN node, and it transmits only messages belonging to this message object list. A powerful, command-driven list controller performs all message object list operations. MultiCAN Features * * * * * * * * * * CAN functionality conforms to CAN specification V2.0 B active for each CAN node (compliant to ISO 11898) Four independent CAN nodes 128 independent message objects (shared by the CAN nodes) Dedicated control registers for each CAN node Data transfer rate up to 1Mbit/s, individually programmable for each node Flexible and powerful message transfer control and error handling capabilities Full-CAN functionality: message objects can be individually - Assigned to one of the four CAN nodes - Configured as transmit or receive object - Configured as message buffer with FIFO algorithm - Configured to handle frames with 11-bit or 29-bit identifiers - Provided with programmable acceptance mask register for filtering - Monitored via a frame counter - Configured for Remote Monitoring Mode Automatic Gateway Mode support 16 individually programmable interrupt nodes Analyzer mode for CAN bus monitoring Data Sheet 55 V1.0, 2008-04 TC1796 Preliminary Functional Description Time-Triggered Extension (TTCAN) In addition to the event-driven CAN functionality, a deterministic behavior can be achieved for CAN node 0 by an extension module that supports time-triggered CAN (TTCAN) functionality. The TTCAN protocol is compliant with the confirmed standardization proposal for ISO 11898-4 and fully conforms to the existing CAN protocol. The time-triggered functionality is added as higher-layer extension (session layer) to the CAN protocol in order to be able to operate in safety critical applications. The new features allow a deterministic behavior of a CAN network and the synchronization of networks. A global time information is available. The time-triggered extension is based on a scheduler mechanism with a timing control unit and a dedicated timing data part. TTCAN Features * * * * * * * * * * * Full support of basic cycle and system matrix functionality Support of reference messages level 1 and level 2 Usable as time master Arbitration windows supported in time-triggered mode Global time information available CAN node 0 can be configured either for event-driven or for time-triggered mode Built-in scheduler mechanism and a timing synchronization unit Write protection for scheduler timing data memory Module-external CAN time trigger inputs (ECTTx lines) can be used as transmit trigger for a reference message Timing-related interrupt functionality Parity protection for scheduler memory Data Sheet 56 V1.0, 2008-04 TC1796 Preliminary 3.13 Functional Description Micro Link Serial Bus Interface (MLI0, MLI1) The Micro Link Interface (MLI) is a fast synchronous serial interface that allows to exchange data between microcontrollers of the 32-bit AUDO microcontroller family without intervention of a CPU or other bus masters. Figure 12 shows how two microcontrollers are typically connected together via their MLI interfaces. The MLI operates in both microcontrollers as a bus master on the system bus. Controller 1 Controller 2 CPU CPU Peripheral A Peripheral B Peripheral C Peripheral D Memory MLI MLI Memory System Bus System Bus MCA05869 Figure 12 Typical Micro Link Interface Connection Features * * * * * * * * * Synchronous serial communication between MLI transmitters and MLI receivers located on the same or on different microcontroller devices Automatic data transfer/request transactions between local/remote controller Fully transparent read/write access supported (= remote programming) Complete address range of remote controller available Specific frame protocol to transfer commands, addresses and data Error control by parity bit 32-bit, 16-bit, and 8-bit data transfers Programmable baud rate: - MLI transmitter baud rate: max. fMLI/2 (= 37.5 Mbit/s @ 75 MHz module clock) - MLI receiver baud rate: max. fMLI Multiple remote (slave) controllers supported MLI transmitter and MLI receiver communicate with other off-chip MLI receivers and MLI transmitters via a 4-line serial I/O bus each. Several I/O lines of these I/O buses are available outside the MLI module kernel as four-line output or input buses. Figure 13 shows the functional blocks of the two MLI modules with its interfaces. Data Sheet 57 V1.0, 2008-04 TC1796 Preliminary Functional Description TCLK A1 P1.3 / TREADY0B Transmitter TREADYA fMLI0 Clock Control fDMA Address Decoder TREADYD A2 P1.6 / TVALID0A A2 P1.7 / TDATA0 Port 1 Control RCLKB Interrupt Control SR[3:0] A1 P1.5 / TREADY0A TVALIDA TVALIDB TVALIDD TDATA RCLKA MLI0 Module (Kernel) A2 P1.4 / TCLK0 TREADYB A2 P1.9 / RREADY0A RCLKD RREADYA A1 P1.10 / RVALID0A Receiver RREADYB SR[7:4] To DMA Cerberus BRKOUT A1 P1.8 / RCLK0A A1 P1.11 / RDATA0A RREADYD RVALIDA A1 P1.13 / RCLK0B RVALIDB A1 P1.14 / RVALID0B RVALIDD RDATAA A1 P1.15 / RDATA0B RDATAB RDATAD Port 5 Control A2 P5.4 / RREADY0B A2 P5.6 / TVALID0B MCA05906 TCLK fDMA TREADYA Transmitter fMLI1 Address Decoder Interrupt Control SR[1:0] Not Connected SR[3:2] A1 P8.1 / TREADY1A TVALIDA TVALIDD A2 P8.2 / TVALID1A A2 P8.3 / TDATA1 RCLKA MLI1 Module (Kernel) Port 8 Control RCLKD RREADYA SR[7:4] To DMA RREADYD BRKOUT A1 P8.4 / RCLK1A A2 P8.5 / RREADY1A RVALIDA A1 P8.6 / RVALID1A RVALIDD RDATAA Cerberus A2 P8.0 / TCLK1 TREADYD TDATA Receiver Clock Control A1 P8.7 / RDATA1A RDATAD MCA05907 Figure 13 Data Sheet Block Diagram of the MLI Modules 58 V1.0, 2008-04 TC1796 Preliminary 3.14 Functional Description General Purpose Timer Array The GPTA provides a set of timer, compare and capture functionalities that can be flexibly combined to form signal measurement and signal generation units. They are optimized for tasks typical of engine, gearbox, and electrical motor control applications, but can also be used to generate simple and complex signal waveforms needed in other industrial applications. The TC1796 contains two General Purpose Timer Arrays (GPTA0 and GPTA1) with identical functionality, plus an additional Local Timer Cell Array (LTCA2). Figure 14 shows a global view of the GPTA modules. GPTA0 GPTA1 Clock Generation Unit FPC0 FPC1 FPC0 DCM0 PDL0 FPC3 DCM2 PDL0 DCM1 FPC2 DIGITAL PLL FPC3 PDL1 DCM2 FPC4 DCM3 FPC5 DCM0 FPC1 DCM1 FPC2 FPC4 Clock Generation Unit PDL1 DCM3 FPC5 fGPTA fGPTA Clock Distribution Unit DIGITAL PLL Clock Distribution Unit GT1 Signal Generation Unit GT0 GT1 Clock Bus GT0 Clock Bus Clock Conn. Signal Generation Unit LTCA2 GTC00 GTC01 GTC02 GTC03 LTC00 LTC01 LTC02 LTC03 GTC00 GTC01 GTC02 GTC03 LTC00 LTC01 LTC02 LTC03 LTC00 LTC01 LTC02 LTC03 Global Timer Cell Array Local Timer Cell Array Global Timer Cell Array Local Timer Cell Array Local Timer Cell Array GTC30 GTC31 LTC62 LTC63 GTC30 GTC31 LTC62 LTC63 LTC62 LTC63 I/O Line Sharing Unit I/O Line Sharing Unit I/O Line Sharing Unit Interrupt Sharing Unit Interrupt Sharing Unit Interrupt Sharing Unit MCB05910 Figure 14 Data Sheet Block Diagram of the GPTA Modules 59 V1.0, 2008-04 TC1796 Preliminary 3.14.1 Functional Description Functionality of GPTA0/GPTA1 Each of the General Purpose Timer Arrays (GPTA0 and GPTA1) provides a set of hardware modules required for high speed digital signal processing: * * * * * * * Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation. Phase Discrimination Logic units (PDL) decode the direction information output by a rotation tracking system. Duty Cycle Measurement Cells (DCM) provide pulse-width measurement capabilities. A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA module clock ticks during an input signal's period. Global Timer units (GT) driven by various clock sources are implemented to operate as a time base for the associated Global Timer Cells. Global Timer Cells (GTC) can be programmed to capture the contents of a Global Timer on an external or internal event. A GTC may be also used to control an external port pin depending on the result of an internal compare operation. GTCs can be logically concatenated to provide a common external port pin with a complex signal waveform. Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may be also logically tied together to drive a common external port pin with a complex signal waveform. LTCs -- enabled in Timer Mode or Capture Mode -- can be clocked or triggered by various external or internal events. Input lines can be shared by an LTC and a GTC to trigger their programmed operation simultaneously. The following sections summarize the specific features of the GPTA units. The clock signal fGPTA is the input clock of the GPTA modules (max. 75 MHz in TC1796). Clock Generation Unit * * Filter and Prescaler Cell (FPC) - Six independent units - Three basic operating modes: Prescaler, Delayed Debounce Filter, Immediate Debounce Filter - Selectable input sources: Port lines, GPTA module clock, FPC output of preceding FPC cell - Selectable input clocks: GPTA module clock, prescaled GPTA module clock, DCM clock, compensated or uncompensated PLL clock. - fGPTA/2 maximum input signal frequency in Filter Modes Phase Discriminator Logic (PDL) - Two independent units - Two operating modes (2 and 3 sensor signals) Data Sheet 60 V1.0, 2008-04 TC1796 Preliminary * * * Functional Description - fGPTA/4 maximum input signal frequency in 2-sensor Mode, fGPTA/6 maximum input signal frequency in 3-sensor Mode. Duty Cycle Measurement (DCM) - Four independent units - 0 - 100% margin and time-out handling - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency Digital Phase Locked Loop (PLL) - One unit - Arbitrary multiplication factor between 1 and 65535 - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency Clock Distribution Unit (CDU) - One unit - Provides nine clock output signals: fGPTA, divided fGPTA clocks, FPC1/FPC4 outputs, DCM clock, LTC prescaler clock Signal Generation Unit * * * Global Timers (GT) - Two independent units - Two operating modes (Free Running Timer and Reload Timer) - 24-bit data width - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency Global Timer Cell (GTC) - 32 units related to the Global Timers - Two operating modes (Capture, Compare and Capture after Compare) - 24-bit data width - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency Local Timer Cell (LTC) - 64 independent units - Three basic operating modes (Timer, Capture and Compare) for 63 units - Special compare modes for one unit - 16-bit data width - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency Interrupt Sharing Unit * 286 interrupt sources, generating up to 92 service requests Data Sheet 61 V1.0, 2008-04 TC1796 Preliminary Functional Description I/O Sharing Unit * Interconnecting inputs and outputs from internal clocks, FPC, GTC, LTC, ports, and MSC interface. 3.14.2 Functionality of LTCA2 One Local Timer Cells Area provides a set of Local Timer Cells. * 64 Local Timer Cells (LTCs) - Three basic operating modes (Timer, Capture and Compare) for 63 units. - Special compare modes for one unit - 16-bit data width - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency Data Sheet 62 V1.0, 2008-04 TC1796 Preliminary 3.15 Functional Description Analog-to-Digital Converter (ADC0, ADC1) The two ADC modules of the TC1796 are analog to digital converters with 8-bit, 10-bit, or 12-bit resolution including sample & hold functionality. VDD VDDM VAGND0 VSS VSSM VAREF0 EMUX0 fCLC ASGT SW0TR, SW0GT External ETR, EGT Request Unit QTR, QGT (SCU) TTR, TGT Address Decoder Interrupt Control To DMA ADC0 Module Kernel Analog Multiplexer SR [3:0] Port 7 Control EMUX1 SR[7:4] Group 0 Analog Multiplexer Address Decoder Interrupt Control SR[3:0] AIN15 AIN16 Not Used VAGND1 VSS VSSM VAREF1 VDD VDDM Figure 15 Data Sheet D AN41 D AN42 ASGT SW0TR, SW0GT External ETR, EGT Request Unit QTR, QGT (SCU) TTR, TGT EMUX1 To DMA From GPTA D AN2 Die Temp. Sensor EMUX0 SR[7:4] 9 D AN1 AIN0 ADC1 Module Kernel From MSC0/1 AIN15 Synchronization Bridge AIN30 AIN31 2 D AN0 AIN31 Group 0 From Ports AIN0 AIN16 Group 1 8 Analog Input Sharing Crossbar Clock Control P7.1 / A1 AD0EMUX2 P7.2 / A1 AD0EMUX0 P7.3 / A1 AD0EMUX1 GRPS fADC Port 7 Control D AN43 8 From Ports 2 From MSC0/1 9 From GPTA P7.6 / AD1EMUX0 P7.7 / A1 AD1EMUX1 A1 MCA06033 Block Diagram of the ADC Module 63 V1.0, 2008-04 TC1796 Preliminary Functional Description The A/D converters operate by the method of the successive approximation. A multiplexer selects between up to 32 analog inputs that can be connected with the 16 conversion channels in each ADC module. An automatic self-calibration adjusts the ADC modules to changing temperatures or process variations. External Clock control, address decoding, and service request (interrupt) control is managed outside the ADC module kernel. A synchronization bridge is used for synchronization of two ADC modules. External trigger conditions are controlled by an External Request Unit. This unit generates the control signals for auto-scan control (ASGT), software trigger control (SW0TR, SW0GT), the event trigger control (ETR, EGT), queue control (QTR, QGT), and timer trigger control (TTR, TGT). Features * * * * * * * * * * * * * * * * * * * 8-bit, 10-bit, 12-bit A/D conversion Minimum conversion times (without sample time, @ 75 MHz module clock): - 1.05 s @ 8-bit resolution - 1.25 s @ 10-bit resolution - 1.45 s @ 12-bit resolution Extended channel status information on request source Successive approximation conversion method Total Unadjusted Error (TUE) of 2 LSB @ 10-bit resolution Integrated sample & hold functionality Direct control of up to 16(32) analog input channels per ADC Dedicated control and status registers for each analog channel Powerful conversion request sources Selectable reference voltages for each channel Programmable sample and conversion timing schemes Limit checking Flexible ADC module service request control unit Synchronization of the two on-chip A/D converters Automatic control of external analog multiplexers Equidistant samples initiated by timer External trigger and gating inputs for conversion requests Power reduction and clock control feature On-chip die temperature sensor output voltage measurement via ADC1 Data Sheet 64 V1.0, 2008-04 TC1796 Preliminary 3.16 Functional Description Fast Analog-to-Digital Converter Unit (FADC) The FADC module of the TC1796 basically is a 4-channel A/D converter with 10-bit resolution that operates by the method of the successive approximation. The main FADC functional blocks shown in Figure 16 are: * * * * * * The Input Stage contains the differential inputs and the programmable amplifier. The A/D Converter is responsible for the analog-to-digital conversion. The Data Reduction Unit contains programmable anti aliasing and data reduction filters. The Channel Trigger Control block defines the trigger and gating conditions for the four FADC channels. The gating source inputs GS[7:0] and trigger source inputs TS[7:0] are connected with GPTA0 module outputs, with GPIO port lines, and external request unit outputs. The Channel Timers can independently trigger the conversion of each FADC channel. The A/D control block is responsible for the overall FADC functionality. The FADC module is supplied by the following power supply and reference voltage lines: * * * VDDMF/VDDMF: FADC Analog Part Power Supply (3.3V) VDDAF/VDDAF: FADC Analog Part Logic Power Supply (1.5V) VFAREF/VFAGND: FADC Reference Voltage/FADC Reference Ground Data Sheet 65 V1.0, 2008-04 TC1796 Preliminary Functional Description VFAREF VDDAF VDDMF VFAGND VSSAF VSSMF fFADC Clock Control fCLC FAIN0P FAIN0N Address Decoder Interrupt Control FAIN1P FADC Module Kernel SR[3:0] FAIN1N FAIN2P FAIN2N To DMA GPTA0 FAIN3P OUT1 OUT9 OUT18 OUT26 OUT2 OUT10 OUT19 OUT27 FAIN3N D AN24 D AN25 D AN26 D AN27 D AN28 D AN29 D AN30 D AN31 A1 P1.0 / REQ0 A1 P1.1 / REQ1 GS[7:0] A1 P7.0 / REQ4 TS[7:0] A1 P7.1 / REQ5 PDOUT2 External Request Unit (SCU) PDOUT3 MCA06053 Figure 16 Block Diagram of the FADC Module Features * * * * * * * * * * * Extreme fast conversion: 21 cycles of fFADC (= 280ns @ fFADC = 75 MHz) 10-bit A/D conversion - Higher resolution by averaging of consecutive conversions is supported Successive approximation conversion method Four differential input channels Offset and gain calibration support for each channel Differential input amplifier with programmable gain of 1, 2, 4 and 8 for each channel Free-running (Channel Timers) or triggered conversion modes Trigger and gating control for external signals Built-in Channel Timers for internal triggering Channel timer request periods independently selectable for each channel Selectable, programmable anti aliasing and data reduction filter block Data Sheet 66 V1.0, 2008-04 TC1796 Preliminary 3.17 Functional Description System Timer The TC1796's STM is designed for global system timing applications requiring both high precision and long range. Features * * * * * * * * * Free-running 56-bit counter All 56 bits can be read synchronously Different 32-bit portions of the 56-bit counter can be read synchronously Flexible interrupt generation based on compare match with partial STM content Driven by max. 75 MHz (= fSYS, default after reset = fSYS/2) Counting starts automatically after a reset operation STM is reset by: - Watchdog reset - Software reset (RST_REQ.RRSTM must be set) - Power-on reset STM is not reset at a hardware reset STM can be halted in debug/suspend mode The STM is an upward counter, running either at the system clock frequency fSYS or at a fraction of it. In case of a power-on reset, a watchdog reset, or a software reset, the STM is reset. After one of these reset conditions, the STM is enabled and immediately starts counting up. It is not possible to affect the contents of the timer during normal operation of the TC1796. The timer registers can only be read but not written to. The STM can be optionally disabled or suspended for power-saving and debugging purposes via its clock control register. In suspend mode of the TC1796, the STM clock is stopped but all registers are still readable. The System Timer can be read in sections from seven registers, STM_TIM0 through STM_TIM6, which select increasingly higher-order 32-bit ranges of the System Timer. These can be viewed as individual 32-bit timers, each with a different resolution and timing range. For getting a synchronous and consistent reading of the complete STM contents, a capture register (STM_CAP), is implemented. It latches the contents of the high part of the STM each time when one of the registers STM_TIM0 to STM_TIM5 is read. Thus, it holds the upper value of the timer at exactly the same time when the lower part is read. The second read operation would then read the contents of the STM_CAP to get the complete timer value. The content of the 56-bit System Timer can be compared against the content of two compare values stored in the compare registers. Interrupts can be generated on a compare match of the STM with the STM_CMP0 or STM_CMP1 registers. The maximum clock period is 256 x fSTM. At fSTM = 75 MHz, for example, the STM counts 30.47 years before overflowing. Thus, it is capable of continuously timing the entire expected product life-time of a system without overflowing. Data Sheet 67 V1.0, 2008-04 TC1796 Preliminary Functional Description Figure 17 shows an overview on the System Timer with the options for reading parts of STM contents. STM Module 31 23 15 0 7 Compare Register 0 STM_CMP0 31 23 15 7 0 Compare Register1 STM_CMP1 STMIR1 Interrupt Control Clock Control 55 47 39 31 23 15 7 0 56-Bit System Timer STMIR0 Enable / Disable 00H STM_CAP fSTM 00H STM_TIM6 STM_TIM5 Address Decoder STM_TIM4 STM_TIM3 PORST STM_TIM2 STM_TIM1 STM_TIM0 MCB05746 Figure 17 Data Sheet General Block Diagram of the STM Module Registers 68 V1.0, 2008-04 TC1796 Preliminary 3.18 Functional Description Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failure. The WDT helps to abort an accidental malfunction of the TC1796 in a user-specified time period. When enabled, the WDT will cause the TC1796 system to be reset if the WDT is not serviced within a userprogrammable time period. The CPU must service the WDT within this time interval to prevent the WDT from causing a TC1796 system reset. Hence, routine service of the WDT confirms that the system is functioning properly. In addition to this standard "Watchdog" function, the WDT incorporates the EndInit feature and monitors its modifications. A system-wide line is connected to the End-ofInitialization (Endinit) feature and monitors its modifications. A system-wide line is connected to the WDT_CON0.ENDINIT bit, serving as an additional write-protection for critical registers (besides Supervisor Mode protection) A further enhancement in the TC1796's WDT is its reset pre-warning operation. Instead of immediately resetting the device on the detection of an error (the way that standard Watchdogs do), the WDT first issues an Non-Maskable Interrupt (NMI) to the CPU before finally resetting the device at a specified time period later. This gives the CPU a chance to save system state to memory for later examination of the cause of the malfunction, an important aid in debugging. Features * * * * * * * * * * 16-bit Watchdog counter Selectable input frequency: fSYS/256 or fSYS/16384 16-bit user-definable reload value for normal Watchdog operation, fixed reload value for Time-Out and Pre-warning Modes Incorporation of the ENDINIT bit and monitoring of its modifications Sophisticated password access mechanism with fixed and user-definable password fields Proper access always requires two write accesses. The time between the two accesses is monitored by the WDT and limited. Access Error Detection: Invalid password (during first access) or invalid guard bits (during second access) trigger the Watchdog reset generation. Overflow Error Detection: An overflow of the counter triggers the Watchdog reset generation. Watchdog function can be disabled; access protection and ENDINIT monitor function remain enabled. Double Reset Detection: If a Watchdog induced reset occurs twice, a severe system malfunction is assumed and the TC1796 is held in reset until a power-on reset. This prevents the device from being periodically reset if, for instance, connection to the external memory has been lost such that even system initialization could not be performed Data Sheet 69 V1.0, 2008-04 TC1796 Preliminary * Functional Description Important debugging support is provided through the reset pre-warning operation by first issuing an NMI to the CPU before finally resetting the device after a certain period of time. 3.19 System Control Unit The System Control Unit (SCU) of the TC1796 handles several system control tasks. These system control tasks of the SCU are: * * * * * * * * * * * * * * * * * Clock system selection and control Reset and boot operation control Power management control Configuration input sampling External Request Unit System clock output control Chip select generation for EBU EBU pull devices control On-chip SRAM Parity Control Pad driver temperature compensation control Emergency stop input control for GPTA outputs Die Temperature Sensor GPTA1 input IN0 control Pad Test Mode control for dedicated pins ODCS level 2 trace control NMI control Miscellaneous SCU control 3.20 Boot Options The TC1796 booting schemes provide a number of different boot options for the start of code execution. Table 7 shows the boot options available in the TC1796. Data Sheet 70 V1.0, 2008-04 TC1796 Preliminary Table 7 BRKIN Functional Description TC1796 Boot Selections HWCFG Type of Boot [3:0] Boot ROM Exit Jump Address Normal Boot Options 1 Data Sheet 0000B Enter bootstrap loader mode 1: Serial ASC0 boot via ASC0 pins 0001B Enter bootstrap loader mode 2: Serial CAN boot via CAN pins 0010B Start from internal PFLASH 0011B Alternate boot mode (ABM): start from internal As defined in PFLASH after CRC check is correctly executed; ABM header or enter a serial bootstrap loader mode1) if CRC D400 0000H check fails. 0100B Start from external memory with EBU as master, A100 0000H using CS0; automatic EBU configuration2); 0101B Alternate boot mode (ABM): start from external As defined in memory with CRC check and EBU as master, ABM header or using CS0; enter a serial bootstrap loader D400 0000H 2) mode if CRC checks fails; automatic EBU configuration2); 0110B Start from external memory with EBU as participant, using CS0; automatic EBU configuration2); 0111B Alternate boot mode (ABM): start from external As defined in memory with CRC check and EBU as ABM header or participant, using CS0; enter a serial bootstrap D400 0000H loader mode2) if CRC checks fails; automatic EBU configuration2); 1000B Start from emulation memory if emulation device TC1796ED is available; in case of TC1796: Execute stop loop; If TC1796ED: AFF0 0000H 1111B Enter bootstrap loader mode 3: Serial ASC0 boot via CAN pins D400 0000H Others Reserved; execute stop loop; - 71 D400 0000H A000 0000H A100 0000H V1.0, 2008-04 TC1796 Preliminary Table 7 Functional Description TC1796 Boot Selections (cont'd) BRKIN HWCFG Type of Boot [3:0] Boot ROM Exit Jump Address Debug Boot Options 0 0000B Tri-state chip - 1000B Go to external emulator space with EBU as master, using CSEMU/CSCOMB DE00 0000H Others Reserved; execute stop loop; - 1) The type of the alternate bootstrap loader mode is selected by the value of the SCU_SCLIR.SWOPT[2:0] bit field, which contains the levels of the P0.[2:0] latched in with the rising edge of the HDRST. For more details on ABM, see the User's Manual. 2) The EBU fetches the boot configuration from address offset 4 using CS0. Data Sheet 72 V1.0, 2008-04 TC1796 Preliminary 3.21 Functional Description Power Management System The TC1796 power management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. There are three power management modes: * * * Run Mode Idle Mode Sleep Mode The operation of each system component in each of these states can be configured by software. The power-management modes provide flexible reduction of power consumption through a combination of techniques, including stopping the CPU clock, stopping the clocks of other system components individually, and individually clockspeed reduction of some peripheral components. Besides these explicit software-controlled power-saving modes, in the TC1796 special attention has been paid for automatic power-saving in those operating units which are currently not required or idle. In that case they are shut off automatically until their operation is required again. Table 8 describes the features of the power management modes. Table 8 Power Management Mode Summary Mode Description Run The system is fully operational. All clocks and peripherals are enabled, as determined by software. Idle The CPU clock is disabled, waiting for a condition to return it to Run Mode. Idle Mode can be entered by software when the processor has no active tasks to perform. All peripherals remain powered and clocked. Processor memory is accessible to peripherals. A reset, Watchdog Timer event, a falling edge on the NMI pin, or any enabled interrupt event will return the system to Run Mode. Sleep The system clock signal is distributed only to those peripherals programmed to operate in Sleep Mode. The other peripheral module will be shut down by the suspend signal. Interrupts from operating peripherals, the Watchdog Timer, a falling edge on the NMI pin, or a reset event will return the system to Run Mode. Entering this state requires an orderly shut-down controlled by the Power Management State Machine. In typical operation, Idle Mode and Sleep Mode may be entered and exited frequently during the run time of an application. For example, system software will typically cause the CPU to enter Idle Mode each time it has to wait for an interrupt before continuing its tasks. In Sleep Mode and Idle Mode, wake-up is performed automatically when any enabled interrupt signal is detected, or if the Watchdog Timer signals the CPU with an NMI trap. Data Sheet 73 V1.0, 2008-04 TC1796 Preliminary 3.22 Functional Description On-Chip Debug Support Figure 18 shows a block diagram of the TC1796 OCDS system. TriCore CPU SBCU RBCU Watchdog Timer (WDT) PCP2 M U X TRCLK OCDS System Control Unit (OSCU) TDI TDO TMS JTAG Controller TCK JTAG Debug Interface (JDI) (Bus Bridge) System Peripheral Bus TRST Multi Core Break Switch (MCBS) BRKIN BRKOUT SPB Peripheral Unit 1 SPB Peripheral Unit m Remote Peripheral Bus Cerberus Break & Suspend Signals DMA Controller Enable, Control, R eset Signals TR[15:0] RPB Peripheral Unit 1 RPB Peripheral Unit n MCB05756_mod Figure 18 OCDS System Block Diagram The TC1796 basically supports three levels of debug operation: * * * OCDS Level 1 debug support OCDS Level 2 debug support OCDS Level 3 debug support Data Sheet 74 V1.0, 2008-04 TC1796 Preliminary Functional Description OCDS Level 1 Debug Support The OCDS Level 1 debug support is mainly assigned for real-time software debugging purposes which have a demand for low-cost standard debugger hardware. The OCDS Level 1 debug support is based on a JTAG interface which can be used by the external debug hardware to communicate with the system. The on-chip Cerberus module controls the interactions between the JTAG interface and the on-chip modules. The external debug hardware may become master of the internal buses and read or write the on-chip register/memory resources. The Cerberus also allows to define breakpoint and trigger conditions as well as to control user program execution (run/stop, break, single-step). OCDS Level 2 Debug Support The OCDS Level 2 debug support allows to implement program tracing capabilities for enhanced debuggers by extending the OCDS Level 1 debug functionality with an additional 16-bit wide trace port with trace clock. With the trace extension the following four trace capabilities are provided (only one of the four trace capabilities can be selected at a time): * * * * Trace capability of the CPU program flow Trace capability of the PCP2 program flow Trace capability of the DMA Controller transaction requests Trace capability of the DMA Controller move engine status information OCDS Level 3 Debug Support The OCDS Level 3 debug support is based on a special emulation device, the TC1796ED, which provides additional features required for high-end emulation purposes. The TC1796ED is a device which includes the TC1796 product chip and additional emulation extension hardware in a package with the same footprint as the TC1796. Data Sheet 75 V1.0, 2008-04 TC1796 Preliminary 3.23 Functional Description Clock Generation and PLL The TC1796 clock system performs the following functions: * * * * * * Acquires and buffers incoming clock signals to create a master clock frequency Distributes in-phase synchronized clock signals throughout the TC1796's entire clock tree Divides a system master clock frequency into lower frequencies required by the different modules for operation. Dynamically reduces power consumption during operation of functional units Statically reduces power consumption through programmable power-saving modes Reduces electromagnetic interference (EMI) by switching off unused modules The clock system must be operational before the TC1796 is able to run. Therefore, it also contains special logic to handle power-up and reset operations. Its services are fundamental to the operation of the entire system, so it contains special fail-safe logic. Features * * * * PLL operation for multiplying clock source by different factors Direct drive capability for direct clocking Comfortable state machine for secure switching between basic PLL, direct or prescaler operation Sleep and Power-Down Mode support The TC1796 Clock Generation Unit (CGU) as shown in Figure 19 allows a very flexible clock generation. It basically consists of an main oscillator circuit and a Phase- Locked Loop (PLL). The PLL can converts a low-frequency external clock signal from the oscillator circuit to a high-speed internal clock for maximum performance. The system clock fSYS is generated from an oscillator clock fOSC in either of four hardware/software selectable ways: * * * * Direct Drive Mode (PLL Bypass): In Direct Drive Mode, the PLL is bypassed and the CGU clock outputs are directly fed from the clock signal fOSC, i.e. fCPU = fOSC and fSYS = fOSC/2 or fOSC. This allows operation of the TC1796 with a reasonably small fundamental mode crystal. VCO Bypass Mode (Prescaler Mode): In VCO Bypass Mode, fCPU and fSYS are derived from fOSC by the two divider stages, P-Divider and K-Divider. The system clock fSYS can be equal to fCPU or fCPU/2. PLL Mode: In PLL Mode, the PLL is running. The VCO clock fVCO is derived from fOSC, divided by the P factor, multiplied by the PLL (N-Divider). The clock signals fCPU and fSYS are derived from fVCO by the K-Divider. The system clock fSYS can be equal to fCPU or fCPU/2. PLL Base Mode: In PLL Base Mode, the PLL is running at its VCO base frequency and fCPU and fSYS Data Sheet 76 V1.0, 2008-04 TC1796 Preliminary Functional Description are derived from fVCO only by the K-Divider. In this mode, the system clock fSYS can be equal to fCPU or fCPU/2. XTAL1 Main Osc. Circuit XTAL2 fCPU Clock Generation Unit (CGU) fOSC Clock Output Control PDivider 1 fP fVCO Phase Detect. fN VCO M U X fSYS KDivider NDivider SYSFS KDIV BYPPIN VCOBYP VCOSEL NDIV OSCDSIC PDIV ORDRES OSCR MOSC OGC PLL LOCK PLL Lock Detect. Osc. Run Detect. BYPASS Oscillator Control Register OSC_CON P5.3 / TXD1A Figure 19 PLL Clock Control and Status Register PLL_CLC System Control Unit (SCU) MCB05600 Clock Generation Unit Recommended Oscillator Circuits The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal oscillator or an external stable clock source. It basically consists of an inverting amplifier and a feedback element with XTAL1 as input, and XTAL2 as output. When using a crystal, a proper external oscillator circuitry must be connected to both pins, XTAL1 and XTAL2. The crystal frequency can be within the range of 4 MHz to 25 MHz. Additionally are necessary, two load capacitances CX1 and CX2, and depending on the crystal type a series resistor RX2 to limit the current. A test resistor RQ may be temporarily inserted to measure the oscillation allowance (negative resistance) of the oscillator circuitry. RQ values are typically specified by the crystal vendor. The CX1 and CX2 values shown in Figure 20 can be used as starting points for the negative resistance evaluation and for non-productive systems. The exact values and related operating range are dependent on the crystal frequency and have to be determined and Data Sheet 77 V1.0, 2008-04 TC1796 Preliminary Functional Description optimized together with the crystal vendor using the negative resistance method. Oscillation measurement with the final target system is strongly recommended to verify the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin negative resistance) for the oscillator-crystal system. When using an external clock signal, it must be connected to XTAL1. XTAL2 is left open (unconnected). The external clock frequency can be in the range of 0 - 40 MHz if the PLL is bypassed and 4 - 40 MHz if the PLL is used. The oscillator can also be used in combination with a ceramic resonator. The final circuitry must be also verified by the resonator vendor. Figure 20 shows the recommended external oscillator circuitries for both operating modes, external crystal mode and external input clock mode. VDDOSC VDDOSC3 fOSC XTAL1 4 - 25 MHz RQ VDDOSC External Clock Signal 41) - 40 MHz TC1796 Oscillator fOSC XTAL1 TC1796 Oscillator RX2 XTAL2 CX1 VDDOSC3 XTAL2 CX2 Fundamental Mode Crystal VSSOSC VSSOSC 1) in case of PLL bypass 0 MHz Crystal Frequency CX1, CX2 4 MHz 8 MHz 12 MHz 16 - 25 MHz 1) 33 pF 18 pF 12 pF 10 pF RX2 1) 0 0 0 0 1) Note that these are evaluation start values! Figure 20 MCS05601 Oscillator Circuitries A block capacitor between VDDOSC1)/VDDOSC3 and VSSOSC is recommended, too. Note: For crystal operation, it is strongly recommended to measure the negative resistance in the final target system (layout) to determine the optimum parameters 1) VDDOSC and VSSOSC are not bonded externally in the BC and BD steps of TC1796. An option for bonding them in future steps and products is kept open. Data Sheet 78 V1.0, 2008-04 TC1796 Preliminary Functional Description for the oscillator operation. Please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier. 3.24 Power Supply The TC1796 has several power supply lines for different voltage classes: * * * 1.5 V: Core logic and memory, oscillator, and A/D converter supply 3.3 V: I/O ports, Flash memories, oscillator, and A/D converter supply with reference voltages 2.3 V to 3.3 V: External bus interface supply Figure 21 shows the power supply concept of the TC1796 with the power supply pins and its connections to the functional units. VAREF0 VSS 62 (3.3 V) (3.3 V) (3.3 V) (1.5 V) VDDAF VFAREF VAGND0 VSSM VAGND1 VSSAF VFAGND VSSMF 2 VDDM VAREF1 2 2 2 (3.3 V) VDDMF (3.3 V) 2 2 TC1796 ADC0 Ports EBU 11 VDDP (3.3 V) 9 VDDEBU (2.3 - 3.3 V) ADC1 FADC Core PMI/PMU DMI/DMU Memories Stand-by SBRAM 13 VDD (1.5 V) 1 VDDSBRAM (1.5 V) PLL FLASH Memories 2 VDDFL3 (3.3 V) OSC 3 VDDOSC (1.5 V) VDDOSC3 (3.3 V) VSSOSC tc1 7 9 6 _ Pw rSu p p ly Figure 21 Data Sheet Power Supply Concept of TC1796 79 V1.0, 2008-04 TC1796 Preliminary 3.25 Functional Description Identification Register Values The Identification Registers uniquely identify a module or the whole device. Table 9 TC1796 Identification Registers Short Name Address Value Stepping SCU_ID F000 0008H 002C C002H - MANID F000 0070H 0000 1820H - CHIPID F000 0074H 0000 8A02H - RTID F000 0078H 0000 0000H BA-Step 0000 0001H BB-Step 0000 0100H BC-Step 0000 0101H BD-Step 0000 0300H BE-Step SBCU_ID F000 0108H 0000 6A0AH - STM_ID F000 0208H 0000 C006H - CBS_JPDID F000 0408H 0000 6307H - MSC0_ID F000 0808H 0028 C002H - MSC1_ID F000 0908H 0028 C002H - ASC0_ID F000 0A08H 0000 4402H - ASC1_ID F000 0B08H 0000 4402H - GPTA0_ID F000 1808H 0029 C003H BA-, BB-Step 0029 C004H BC-, BD-, BE-Step 0029 C003H BA-, BB-Step 0029 C004H BC-, BD-, BE-Step 002A C003H BA-, BB-Step 002A C004H BC-, BD-, BE-Step GPTA1_ID LTCA2_ID F000 2008H F000 2808H DMA_ID F000 3C08H 001A C002H - CAN_ID F000 4008H 002B C002H - PCP_ID F004 3F08H 0020 C003H - RBCU_ID F010 0008H 0000 6A0AH - SSC0_ID F010 0108H 0000 4530H - SSC1_ID F010 0208H 0000 4510H - FADC_ID F010 0308H 0027 C002H - Data Sheet 80 V1.0, 2008-04 TC1796 Preliminary Table 9 Functional Description TC1796 Identification Registers (cont'd) Short Name Address Value Stepping ADC0_ID F010 0408H 0030 C002H - MLI0_ID F010 C008H 0025 C005H - MLI1_ID F010 C108H 0025 C005H - MCHK_ID F010 C208H 001B C001H - CPS_ID F7E0 FF08H 0015 C006H - CPU_ID F7E1 FE18H 000A C005H - EBU_ID F800 0008H 0014 C005H - PMU_ID F800 0508H 002E C002H - FLASH_ID F800 2008H 0031 C002H - DMU_ID F801 0108H 002D C002H - DBCU_ID F87F FA08H 000F C005H - DMI_ID F87F FC08H 0008 C004H - PMI_ID F87F FD08H 000B C004H - LFI_ID F87F FF08H 000C C005H - PBCU_ID F87F FE08H 000F C005H - Data Sheet 81 V1.0, 2008-04 TC1796 Preliminary 4 Electrical Parameters 4.1 General Parameters 4.1.1 Parameter Interpretation Electrical Parameters The parameters listed in this section partly represent the characteristics of the TC1796 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column "Symbol": * * CC Such parameters indicate Controller Characteristics which are a distinctive feature of the TC1796 and must be regarded for a system design. SR Such parameters indicate System Requirements which must provided by the microcontroller system in which the TC1796 designed in. Data Sheet 82 V1.0, 2008-04 TC1796 Preliminary 4.1.2 Electrical Parameters Pad Driver and Pad Classes Summary This section gives an overview on the different pad driver classes and its basic characteristics. More details (mainly DC parameters) are defined in the Section 4.2.1. Table 10 Pad Driver and Pad Classes Overview Class Power Type Supply Sub Class A A1 (e.g. GPIO) 6 MHz 100 pF 500 nA A2 (e.g. serial I/Os) 40 MHz 50 pF 6 A Series termination recommended A3 75 MHz (e.g. Trace Outputs, serial I/Os) 50 pF 6 A Series termination recommended (for f > 25 MHz) A4 (e.g. Trace Clock) 150 MHz 25 pF 6 A Series termination recommended LVTTL B1 I/O (e.g. External Bus Interface) 40 MHz 50 pF 6 A No B2 (e.g. Bus Clock) 75 MHz 35 pF - 50 MHz B 3.3V 2.375 3.6V2) LVTTL I/O, LVTTL output Speed Load Grade C 3.3V LVDS D - Analog inputs, reference voltage inputs Leakage Termination 1) No Series termination recommended (for f > 25 MHz) - Parallel termination3), 100 10% 1) Values are for TJmax = 150 C. 2) AC characteristics for EBU pins are valid for 2.5 V 5% and 3.3 V 5%. 3) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected, or properly terminated with the differential parallel termination of 100 10%. Data Sheet 83 V1.0, 2008-04 TC1796 Preliminary 4.1.3 Electrical Parameters Absolute Maximum Ratings Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > related VDD or VIN < VSS) the voltage on the related VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Table 11 Absolute Maximum Rating Parameters Parameter Symbol TA SR Storage temperature TST SR Junction temperature TJ SR Voltage at 1.5 V power supply VDD pins with respect to VSS1) SR Voltage at 3.3 V power supply VDDEBU pins with respect to VSS2) VDDP SR Voltage on any Class A input VIN SR Ambient temperature Values Min. Typ. Max. Unit Note / Test Con dition -40 - 125 C Under bias -65 - 150 C - -40 - 150 C Under bias - - 2.25 V - - - 3.75 V - VDDP + 0.5 V Whatever is lower VDDEBU + 0.5 V Whatever is lower VDDM + 0.5 V Whatever is lower VDDMF + 0.5 V Whatever is lower -0.5 - pin and dedicated input pins with respect to VSS Voltage on any Class B input VIN pin with respect to VSS Voltage on any Class D analog input pin with respect to VAGND VAIN VAREFx Voltage on any Class D analog input pin with respect to VSSAF VAINF VFAREF CPU & LMB Bus Frequency fCPU fSYS FPI Bus Frequency or max. 3.7 SR -0.5 - or max. 3.7 -0.5 - or max. 3.7 SR -0.5 - or max. 3.7 SR SR - SR - - - 1503) 3) 75 MHz - MHz - 1) Applicable for VDD, VDDSBRAM, VDDOSC, VDDPLL, and VDDAF. 2) Applicable for VDDP, VDDEBU, VDDFL3, VDDM, and VDDMF. 3) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter parameters. Data Sheet 84 V1.0, 2008-04 TC1796 Preliminary 4.1.4 Electrical Parameters Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the TC1796. All parameters specified in the following table refer to these operating conditions, unless otherwise noticed. The following operating conditions must not be exceeded in order to ensure correct operation of the TC1796. All parameters specified in the following table refer to these operating conditions, unless otherwise noted. Table 12 Operating Condition Parameters Parameter Symbol Values Min. Digital supply voltage1) Typ. Max. Unit Note / Test Condition VDD SR 1.42 - 2) VDDOSC SR VDDP SR 3.13 - VDDOSC3 SR VDDEBU SR 2.375 - 1.583) V - 3.474) V For Class A pins (3.3V 5%) 3.474) V For Class B (EBU) pins VDDFL3 SR 3.13 VDDSBRAM5) 1.42 - 3.474) V - - 3) 1.58 V - Voltage on VDDSBRAM power supply pin to ensure data retention VDR SR 1.0 - - V 6) Digital ground voltage VSS TA SR 0 - - V - SR - -40 +125 C - - - - See separate specification Page 92, Page 99 SR Ambient temperature under bias Analog supply voltages - CPU clock Short circuit current Absolute sum of short circuit currents of a pin group (see Table 13) Inactive device pin current Data Sheet - fCPU ISC |ISC| SR -7) - 1508) MHz - SR -5 - +5 mA 9) SR - - 20 mA See note10) IID SR -1 - 1 mA Voltage on all power supply pins VDDx = 0 85 V1.0, 2008-04 TC1796 Preliminary Table 12 Electrical Parameters Operating Condition Parameters Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Absolute sum of short circuit currents of the device |ISC| SR - - 100 mA See note10) External load capacitance CL SR - - pF Depending on pin class. See DC characteristics - 1) Digital supply voltages applied to the TC1796 must be static regulated voltages which allow a typical voltage swing of 5%. 2) VDDOSC and VSSOSC are not bonded externally in the BC and BD steps of TC1796. An option for bonding them in future steps and products is kept open. 3) Voltage overshoot up to 1.7 V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 4) Voltage overshoot to 4 V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h 5) The VDDSB must be properly connected and supplied with power. If not, the TC1796 will not operate. In case of a stand-by operation, the core voltage must not float, but must be pulled low, in order to avoid internal crosscurrents. 6) This applies only during power down state. During normal SRAM operation regular VDD has to be applied. 7) The TC1796 uses a static design, so the minimum operation frequency is 0 MHz. Due to test time restriction no lower frequency boundary is tested, however. 8) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter parameters. 9) Applicable for digital outputs. 10) See additional document "TC1796 Pin Reliability in Overload" for overload current definitions. Table 13 Pin Groups for Overload/Short-Circuit Current Sum Parameter Group Pins 1 P4.[7:0] 2 P4.[14:8] 3 P4.15, SLSO[1:0], SCLK0, MTSR0, MRST0, SLSI0 4 WAIT, HOLD, BC[3:0], HLDA, MR/W, BAA, CSCOMB 5 CS[3:0], RD, RD/WR, BREQ, ADV, BFCLKO 6 BFCLKI, D[31:24] 7 D[23:16] 8 D[15:8] Data Sheet 86 V1.0, 2008-04 TC1796 Preliminary Table 13 Electrical Parameters Pin Groups for Overload/Short-Circuit Current Sum Parameter Group Pins 9 D[7:0] 10 A[23:16] 11 A[15:8] 12 A[7:0] 13 TSTRES, TDI, TMS, TCK, TRST, TDO, BRKOUT, BRKIN, TESTMODE 14 P10.[3:0], BYPASS, NMI, PORST, HDRST 15 P9.[8:0] 16 FCLP[1:0]A, FCLN[1:0], SOP[1:0]A, SON[1:0] 17 P5.[7:0] 18 P3.[7:0] 19 P3.[15:8] 20 P0.[7:0] 21 P0.[15:8] 22 P2.[15:7] 23 P2.[6:2], P6.9, P6.8, P6.6, P6.11 24 P6.[15:12], P6.10, P6.7, P6.[5:4] 25 P8.[7:0] 26 P1.[15:13], P1.[11:8], P1.5 27 P1.12, P1.[7:6], P1.[4:0] 28 TR[15:8] 29 TR[7:1], TRCLK 30 TR0, P7.[7:0] Data Sheet 87 V1.0, 2008-04 TC1796 Preliminary Electrical Parameters 4.2 DC Parameters 4.2.1 Input/Output Pins Table 14 Input/Output DC-Characteristics (Operating Conditions apply) Parameter Symbol Values Min. Typ. Max. 10 - Unit Note / Test Condition General Parameters Pull-up current1) |IPUH| 100 A CC VIN < VIHAmin; class A1/A2/Input pads. 20 - 200 A VIN <VIHAmin; class A3/A4 pads. 5 - 85 A VIN < VIHBmin; class B1/B2 pads. |IPDL| Pull-down current1) 10 - 150 A CC VIN >VILAmax; class A1/A2/Input pads. VIN > VILBmax; class B1/B2 pads 20 - 200 A VIN > VILAmax; class A3/A4 pads. Pin capacitance (Digital I/O) 1) CIO - - 10 pF f = 1 MHzTA = 25 C CC Input only Pads (VDDP = 3.13 to 3.47 V = 3.3 V 5%) - 0.34 x V - Input high voltage VIHA 0.64 x Class A1/A2 pins SR VDDP - VDDP VDDP+ V Whatever is lower Ratio VIL/VIH CC 0.53 - - - - Input hysteresis HYSA 0.1 x CC VDDP - - V 5)2) Input leakage current IOZI - 3000 6000 nA VDDP/2-1 < VIN < VDDP/2+1 Input low voltage Class A1/A2 pins Data Sheet VILA -0.3 SR - 0.3 or max. 3.6 CC 88 Otherwise3) V1.0, 2008-04 TC1796 Preliminary Table 14 Electrical Parameters Input/Output DC-Characteristics (cont'd)(Operating Conditions apply) Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. Class A Pads (VDDP = 3.13 to 3.47 V = 3.3V 5%) Output low voltage4) VOLA Output high voltage3) VOHA - - 0.4 V CC IOL = 2 mA for strong driver mode, IOL = 1.8 mA for medium driver mode, A2 pads IOL = 1.4 mA for medium driver mode, A1 pads IOL = 370 A for weak driver mode 2.4 - - V CC IOH = -2 mA for strong driver mode, IOH = -1.8 mA for medium driver mode, A1/A2 pads IOH = -370 A for weak driver mode VDDP - - - -0.3 - 0.34 x V - Input high voltage VIHA 0.64 x Class A1/2 pins SR VDDP - VDDP VDDP + V Whatever is lower Ratio VIL/VIH CC 0.53 - - - - Input hysteresis HYSA 0.1 x CC VDDP - - V 5)2) Input leakage current Class A2/3/4 pins IOZA24 - - 3000 6000 nA VDDP/2-1 < VIN < VDDP/2+1 Input leakage current Class A1 pins IOZA1 - 500 nA V 0.4 Input low voltage Class A1/2 pins Data Sheet VILA IOH = -1.4 mA for strong driver mode, IOH = -1 mA for medium driver mode, A1/A2 pads IOH = -280 A for weak driver mode SR 0.3 or 3.6 - CC 89 Otherwise3) 0 V < VIN < VDDP V1.0, 2008-04 TC1796 Preliminary Table 14 Electrical Parameters Input/Output DC-Characteristics (cont'd)(Operating Conditions apply) Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. Class B Pads (VDDEBU = 2.375 to 3.47 V) Output low voltage VOLB CC - 0.4 V VDDEBU - - V IOL = 2 mA IOL = 2 mA - -0.3 0.34 x V - - VDDEBU VDDEBU V Whatever is lower - - - - Input hysteresis HYSB 0.1 x - CC VDDEBU - V 5) Input leakage current Class B pins IOZB 3000 nA VDDEBU/2-0.6 < VIN < VDDEBU/2+0.66) Output high voltage VOHB Input low voltage VILB Input high voltage VIHB Ratio VIL/VIH - CC - 0.4 SR 0.64 x SR VDDEBU CC 0.53 - +0.3 or 3.6 - CC Otherwise3) 6000 Class C Pads (VDDP = 3.13 to 3.47 V = 3.3V 5%) Output low voltage VOL CC 815 Output high voltage VOH CC Output differential VOD CC 150 voltage Output offset voltage VOS CC 1075 Output impedance R0 CC 40 - mV Parallel termination 100 1% - 1545 mV Parallel termination 100 1% - 600 mV Parallel termination 100 1% - 1325 mV Parallel termination 100 1% - 140 - - - - - Class D Pads See ADC Characteristics - 1) Not subject to production test, verified by design / characterization. 2) The pads that have spike-filter function in the input path: PORST, HDRST, NMI, do not have hysteresis. 3) Only one of these parameters is tested, the other is verified by design characterization 4) Max. resistance between pin and next power supply pin 25 for strong driver mode (verified by design characterization). Data Sheet 90 V1.0, 2008-04 TC1796 Preliminary Electrical Parameters 5) Function verified by design, value verified by design characterization. Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise. 6) VDDEBU = 2.5 V 5%. For VDDEBU = 3.3 5% see class A2 pads. Data Sheet 91 V1.0, 2008-04 TC1796 Preliminary 4.2.2 Electrical Parameters Analog to Digital Converters (ADC0/ADC1) Table 15 ADC Characteristics (Operating Conditions apply) Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. 3.3 3.471) V - 2) Analog supply voltage VDDM VDD SR 1.42 1.5 1.58 V Power supply for ADC digital part, internal supply Analog ground voltage VSSM SR -0.1 - 0.1 V - Analog reference voltage17) VAREFx SR VAGNDx VDDM VDDM+ V - Analog reference ground17) VAGNDx SR VSSMx - 0 VAREF - V - Analog input voltage range VAIN VAREFx V - Analog reference voltage range5)17) VAREFxVDDM/2 - VAGNDx SR IDDM SR - 2.5 VDDM + 0.05 V - 4 mA rms For each module6) Power-up calibration time tPUC CC - 3840 fADC - Internal ADC clocks fBC fANA CC 2 - 40 MHz fBC = fANA x 4 CC 0.5 - 10 MHz fANA = fBC / 4 Total unadjusted error5) TUE7) CC - - 1 LSB 8-bit conversion. - - 2 LSB 10-bit conversion - - 4 LSB 12-bit conversion - 8 LSB 12-bit conversion VDDM supply current SR 3.13 +1V 0.05V SR VAGNDx 0.05 1)3)4) - - 1V CLK - 8)9) 10)9) DNL error11) 5) TUEDNL - CC 1.5 3.0 LSB 12-bit conversion INL error11)5) TUEINL 1.5 3.0 LSB 12-bit conversion Data Sheet - CC 92 12)9) 12)9) V1.0, 2008-04 TC1796 Preliminary Table 15 Electrical Parameters ADC Characteristics (cont'd) (Operating Conditions apply) Parameter Symbol Values Min. 11)5) Gain error Offset error11)5) Input leakage current at analog inputs AN0, AN1, AN4 to AN7, AN24 to AN31. see Figure 24 Unit Note / Test Condition 12-bit conversion Typ. Max. TUEGAIN - CC 0.5 3.5 LSB TUEOFF - CC 1.0 4.0 LSB IOZ1 - 300 nA (0% VDDM) < VIN < (2% VDDM) -200 - 400 nA (2% VDDM) < VIN < (95% VDDM) -200 - 1000 nA (95% VDDM) < VIN < (98% VDDM) -200 - 3000 nA (98% VDDM) < VIN < (100% VDDM) - 200 nA (0% VDDM) < VIN < (2% VDDM) -200 - 300 nA (2% VDDM) < VIN < (95% VDDM) -200 - 1000 nA (95% VDDM) < VIN < (98% VDDM) -200 - 3000 nA (98% VDDM) < VIN < (100% VDDM) CC -1000 12)9) 12)9) 13) 14) Input leakage current at the other analog inputs, that is AN2, AN3, AN8 to AN23, AN32 to AN43 see Figure 24 IOZ1 CC -1000 12-bit conversion 14) Input leakage current at VAREF IOZ2 CC - - 1 A 0 V < VAREF < VDDM, no conversion running Input current at IAREF CC - 35 75 A rms 0 V < VAREF < VAREF0/1 17) VDDM15) - 25 pF 9) Switched CAREFSW - capacitance at the CC positive reference voltage input17) 15 20 pF 9)18) Data Sheet 93 Total capacitance of the voltage reference inputs16)17) CAREFTOT - CC V1.0, 2008-04 TC1796 Preliminary Table 15 Electrical Parameters ADC Characteristics (cont'd) (Operating Conditions apply) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. - 1 1.5 k 500 Ohm increased for AN[1:0] used as reference input9) - - 25 pF 6)9) Switched CAINSW - capacitance at the CC analog voltage inputs - 7 pF 9)19) 1 1.5 k 9) 300 1000 Test feature available only for AIN79) 15 rms 30 peak mA Resistance of the reference voltage input path16) RAREF Total capacitance of the analog inputs16) CAINTOT ON resistance of the transmission gates in the analog voltage path RAIN CC CC CC - ON resistance for RAIN7T CC 200 the ADC test (pulldown for AIN7) Current through resistance for the ADC test (pulldown for AIN7) IAIN7T CC - Test feature available only for AIN79) 1) Voltage overshoot to 4 V are permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 2) Voltage overshoot to 1.7 V are permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 3) A running conversion may become inexact in case of violating the normal operating conditions (voltage overshoot). the reference voltage VAREF increases or the VDDM decreases, so that VAREF = (VDDM + 0.05V to VDDM + 0.07V), then the accuracy of the ADC decreases by 4LSB12. 5) If a reduced reference voltage in a range of VDDM/2 to VDDM is used, then the ADC converter errors increase. 4) If If the reference voltage is reduced with the factor k (k<1), then TUE, DNL, INL Gain and Offset errors increase with the factor 1/k. If a reduced reference voltage in a range of 1 V to VDDM/2 is used, then there are additional decrease in the ADC speed and accuracy. 6) Current peaks of up to 6 mA with a duration of max. 2 ns may occur 7) TUE is tested at VAREF = 3.3 V, VAGND = 0 V and VDDM = 3.3 V Data Sheet 94 V1.0, 2008-04 TC1796 Preliminary Electrical Parameters 8) ADC module capability. 9) Not subject to production test, verified by design / characterization. 10) Value under typical application conditions due to integration (switching noise, etc.). 11) The sum of DNL/INL/Gain/Offset errors does not exceed the related TUE total unadjusted error. 12) For 10-bit conversions the DNL/INL/Gain/Offset error values must be multiplied with factor 0.25. For 8-bit conversions the DNL/INL/Gain/Offset error values must be multiplied with 0.0625. 13) The leakage current definition is a continuous function, as shown in Figure 24. The numerical values defined determine the characteristic points of the given continuous linear approximation - they do not define step function. 14) Only one of these parameters is tested, the other is verified by design characterization. 15) IAREF_MAX is valid for the minimum specified conversion time. The current flowing during an ADC conversion with a duration of up to tC = 25s can be calculated with the formula IAREF_MAX = QCONV/tC. Every conversion needs a total charge of QCONV = 150pC from VAREF. All ADC conversions with a duration longer than tC = 25s consume an IAREF_MAX = 6A. 16) For the definition of the parameters see also Figure 23. 17) Applies to AIN0 and AIN1, when used as auxiliary reference inputs. 18) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead of this smaller capacitances are successively switched to the reference voltage. 19) The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before the sampling moment. Because of the parasitic elements the voltage measured at AINx is lower then VAREF/2, typically 0.85V. Data Sheet 95 V1.0, 2008-04 TC1796 Preliminary Electrical Parameters Table 16 Sample and Conversion Time (Operating Conditions apply) Parameter Symbol Values Min. tS Sample time Unit Note Typ. Max. 4 x (CHCONn.STC + 2) x tBC CC 8 x tBC - Conversion tC time - tS + 40 x tBC + 2 x tDIV tS + 48 x tBC + 2 x tDIV tS + 56 x tBC + 2 x tDIV CC s - s - s 8-bit conversion s 10-bit conversion s 12-bit conversion A/D Converter Module fCLC Fractional Divider fDIV Programmable fBC Clock Divider (1:1) to (1:256) CON.CTC Arbiter (1:20) fTIMER Control Unit (Timer) 1:4 Sample f ANA Programmable Time tS Counter CHCONn.STC Control/Status Logic Interrupt Logic External Trigger Logic External Multiplexer Logic Request Generation Logic MCA04657_mod Figure 22 Data Sheet ADC0/ADC1 Clock Circuit 96 V1.0, 2008-04 TC1796 Preliminary Electrical Parameters REXT VAIN = Analog Input Circuitry RAIN, On ANx CEXT CAINTOT - CAINSW VAGNDx CAINSW RAIN7T Reference Voltage Input Circuitry RAREF, On VAREFx VAREF CAREFTOT - CAREFSW CAREFSW VAGNDx Analog_InpRefDiag Figure 23 Data Sheet ADC0/ADC1 Input Circuits 97 V1.0, 2008-04 TC1796 Preliminary Electrical Parameters IO Z1 3uA AN0, AN1, AN4 - AN7, AN24 - AN31 1uA 400nA 300nA -200nA VIN[VDDM %] 95% 98% 100% 2% -1uA IOZ1 3uA Others 1uA 300nA 200nA -200nA V IN[VDDM%] 2% 95% 98% 100% -1uA ADC Leakage 7.vsd Figure 24 Data Sheet ADC0/ADC1Analog Inputs Leakage 98 V1.0, 2008-04 TC1796 Preliminary 4.2.3 Electrical Parameters Fast Analog to Digital Converter (FADC) Table 17 FADC Characteristics (Operating Conditions apply) Parameter Symbol Values Min. DNL error INL error Gradient error1)10) Unit Note / Test Condition Typ. Max. EDNL CC - EINL CC - EGRAD - - 1 LSB 10) - 4 LSB 10) - 3 % With calibration, gain 1, 22) EGRAD - - 5 % Without calibration gain 1, 2, 4 - - 6 % Without calibration gain 8 - - 204) mV With calibration2) CC - - 604) mV Without calibration - - 60 mV - CC EGRAD Offset error10) EOFF3) CC CC Reference error of internal VFAREF/2 EREF Analog supply voltages VDDMF SR 3.13 VDDAF SR 1.42 VSSAF -0.1 - 3.475) V - - 1.586) V - - 0.1 V - Analog reference voltage VFAREF - 3.475)7) V Nominal 3.3 V Analog reference ground VFAGND VSSAF - - VSSAF V - VFAGND - VDDMF V - - 9 mA - - 17 mA 8) - 150 A rms Independent of conversion - 500 nA 0 V < VIN < VDDMF - 8 A 0 V < VIN < VDDMF Analog ground voltage CC SR Analog input voltage VAINF range 3.13 SR SR 0.05V SR IDDMF SR - IDDAF SR - Input current at each IFAREF - VFAREF CC Input leakage current IFOZ2 - at VFAREF 9) CC Input leakage current IFOZ3 - at VFAGND CC Analog supply currents Data Sheet 99 +0.05V V1.0, 2008-04 TC1796 Preliminary Table 17 Electrical Parameters FADC Characteristics (Operating Conditions apply) (cont'd) Parameter Symbol Values Min. Conversion time tC CC - Unit Typ. Max. - 21 Note / Test Condition CLK of 10-bit conversion fADC fADC CC - RFAIN 100 - 75 MHz - - 200 k 10) Channel Amplifier Cutoff Frequency fCOFF 2 - - MHz - Settling Time of a Channel Amplifier after changing ENN or ENP tSET CC - - 5 sec - Converter Clock Input resistance of the analog voltage path (Rn, Rp) CC CC 1) Calibration of the gain is possible for the gain of 1 and 2, and not possible for the gain of 4 and 8. 2) Calibration should be performed at each power-up. In case of continuous operation, calibration should be performed minimum once per week. 3) The offset error voltage drifts over the whole temperature range maximum 3 LSB. 4) Applies when the gain of the channel equals one. For the other gain settings, the offset error increases; it must be multiplied with the applied gain. 5) Voltage overshoot to 4 V are permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 6) Voltage overshoot to 1.7 V are permissible, provided the pulse duration is less than 100 s and the cumulated sum of the pulses does not exceed 1 h. 7) A running conversion may become inexact in case of violating the normal operating conditions (voltage overshoots). 8) Current peaks of up to 40 mA with a duration of max. 2 ns may occur 9) This value applies in power-down mode. 10) Not subject to production test, verified by design / characterization. The calibration procedure should run after each power-up, when all power supply voltages and the reference voltage have stabilized. The offset calibration must run first, followed by the gain calibration. Data Sheet 100 V1.0, 2008-04 TC1796 Preliminary Electrical Parameters FADC Analog Input Stage FAINxN - = VFAGN D RN VFAR EF/2 + + FAINxP RP - FADC Reference Voltage Input Circuitry VFAR EF IFAR EF VFAR EF VFAGN D FAD C _ In p R e fD ia g Figure 25 Data Sheet FADC Input Circuits 101 V1.0, 2008-04 TC1796 Preliminary 4.2.4 Table 18 Electrical Parameters Oscillator Pins Oscillator Pins Characteristics (Operating Conditions apply) Parameter Symbol Values Min. Frequency Range Input low voltage at XTAL11) Input high voltage at XTAL11) Input current at XTAL1 fOSC CC 4 VILX SR -0.2 Typ. Max. Unit Note / Test Condition - 25 MHz - - 0.3 x VIHX SR 0.7 x - VDDOSC3 IIX1 CC - - V - VDDOSC3 VDDOSC3 V - 25 0 V < VIN < VDDOSC3 + 0.2 A 1) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.3 x VDDOSC3 is necessary. Note: It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal supplier. Data Sheet 102 V1.0, 2008-04 TC1796 Preliminary 4.2.5 Table 19 Electrical Parameters Temperature Sensor Temperature Sensor Characteristics (Operating Conditions apply) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Cond ition 150 C - Temperature Sensor Range TSR SR -40 Start-up time after resets inactive tTSST SR - - 10 s - TTSA A/D Converter clock fANA CC - - 10 C - SR - - 10 MHz conversion with ADC1 Sensor Inaccuracy for DTS signal Table 20 Temperature Sensor Characteristics (Operating Conditions apply) Parameter Symbol Typical Value Unit Note Temperature of the die at the sensor location TTS CC TTSx = (ADC_Code - 487) 0.396 - 40 C 10-bit ADC result TTSx = (ADC_Code - 1948) 0.099 - 40 C 12-Bit ADC result Data Sheet 103 V1.0, 2008-04 TC1796 Preliminary 4.2.6 Electrical Parameters Power Supply Current ??? Table 21 Power Supply Currents (Operating Conditions apply) Parameter Min. Typ. Max. Unit Note / Test Condition - - 300 mA The PLL running at the base frequency PORST low current at IDDP_PORST - VDDP, and PORST high CC current without any port activity - 25 mA The PLL running at the base frequency - 700 mA fCPU=150MHzfCPU/f PORST low current at VDD Symbol IDD_PORST Active mode core supply current1)2) IDD Active mode analog supply current IDDAx; IDDMx ISBSB Stand-by RAM supply current in stand-by Oscillator and PLL core IDDOSC3) power supply Oscillator and PLL pads IDDOSC3 power supply LVDS port supply (via VDDP)4) ILVDS Flash power supply current IDDFL3 Maximum Allowed Power Dissipation5) PD Values CC 10 CC SYS = 2:1 - - - mA See ADC0/1 FADC - - 9 mA VDDSB = 1V, Tj = 150oC - - 5 mA - - - 3.6 mA - - - 50 mA LVDS pads active - - 80 mA - - - PD x RTJA - worst case TA = 125oC CC CC CC CC CC CC SR < 25oC 1) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each custom application will most probably be lower than this value, but must be evaluated separately. 2) The IDD decreases for typically 120 mA if the fCPU is decreased for 50 MHz, at constant TJ = 150C, for the Infineon Max Power Loop. The dependency in this range is, at constant junction temperature, linear. 3) VDDOSC and VSSOSC are not bonded externally in the BC and BD steps of TC1796. An option for bonding them in future steps and products is kept open. 4) In case the LVDS pads are disabled, the power consumption pro pair is negligible (less than 1A). 5) For the calculation of junction to ambient thermal resistance RTJA, see Page 130. Data Sheet 104 V1.0, 2008-04 TC1796 Preliminary 4.3 Electrical Parameters AC Parameters All AC parameters are defined with the temperature compensation disabled. That means, keeping the pads constantly at maximum strength. 4.3.1 Testing Waveforms VDDP VDDEBU 90% 90% 10% 10% VSS tR tF rise_fall Figure 26 Rise/Fall Time Parameters VDDP VDDEBU VDDE / 2 Test Points VDDE / 2 VSS mct04881_a.vsd Figure 27 Testing Waveform, Output Delay VLoad+ 0.1 V VLoad- 0.1 V Timing Reference Points VOH - 0.1 V VOL - 0.1 V MCT04880_new Figure 28 Data Sheet Testing Waveform, Output High Impedance 105 V1.0, 2008-04 TC1796 Preliminary 4.3.2 Table 22 Electrical Parameters Output Rise/Fall Times Output Rise/Fall Times (Operating Conditions apply) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Class A1 Pads Rise/fall times 1) tRA1, tFA1 - - 50 ns 140 18000 150 550 65000 Regular (medium) driver, 50 pF Regular (medium) driver, 150 pF Regular (medium) driver, 20 nF Weak driver, 20 pF Weak driver, 150 pF Weak driver, 20 000 pF - 3.3 ns 6 5.5 16 50 140 18000 150 550 65000 Strong driver, sharp edge, 50 pF Strong driver, sharp edge, 100pF Strong driver, medium edge, 50 pF Strong driver, soft edge, 50 pF Medium driver, 50 pF Medium driver, 150 pF Medium driver, 20 000 pF Weak driver, 20 pF Weak driver, 150 pF Weak driver, 20 000 pF - 2.5 ns 50 pF tRA3, tFA3 - - 2.0 ns 25 pF tRB, tFB - - 3.0 4.0 7.0 ns 35 pF 50 pF 100 pF tRC, tFC - - 2 ns - Class A2 Pads Rise/fall times 1) tRA2, tFA2 - Class A3 Pads Rise/fall times 1) tRA3, tFA3 - Class A4 Pads Rise/fall times 1) Class B Pads Rise/fall times 1)2) Class C Pads Rise/fall times 1) Not all parameters are subject to production test, but verified by design/characterization and test correlation. Data Sheet 106 V1.0, 2008-04 TC1796 Preliminary Electrical Parameters 2) Parameter test correlation for VDDEBU = 2.5 V 5% 4.3.3 Power Sequencing There is a restriction for the power sequencing of the 3.3 V domain including VDDEBU as shown in Figure 29: it must always be higher than 1.5 V domain - 0.5 V. The grey area shows the valid range for V3.3V and VDDEBU relative to an exemplary 1.5 V ramp. VDDP, VDDOSC3, VDDFL3, VDDM, VDDMF belong to the 3.3 V power supply domain, that is referenced in Figure 29 as V3.3. The VDDM and VDDMF sub domains are connected with anti parallel ESD protection diodes in TC1796 design steps BC and BD. The VDDM, VDDMF, VDDP, VDDOSC3 sub domains are connected with anti parallel ESD protection diodes in TC1796 design step BE. VDD, VDDOSC and VDDAF belong to the 1.5 V power supply domain, referenced as V1.5. VDDEBU belongs to its own 2.5V to 3.3V domain. Val V DDEB id a and rea V 3.3 for V fo r 3.3 rea and V id a 1.5V V3.3, VDDEBU V1.5 Va l DD EB U 3.3V U V3.3, VDDEBU > V1.5 - 0.5V Time VDDP (3.3V) PORST Time PowerSeq 2 Figure 29 VDDP / VDDEBU / VDD Power Up Sequence All ground pins VSS must be externally connected to one single star point in the system. The difference voltage between the ground pins must not exceed 200 mV. The PORST signal must be activated at latest before any power supply voltage falls below the levels shown on the figure below. In this case, only the memory row of a Flash memory that was a target of a write at the moment of the power loss will contain unreliable content. Additionally, the PORST signal should be activated as soon as possible. The sooner the PORST signal is activated, the less time the system operates outside of the normal operating power supply range. Data Sheet 107 V1.0, 2008-04 TC1796 Preliminary Electrical Parameters VDDP, VDDEBU, VDDFL3 Power Supply Voltage 3.3V 3.13V VDDPmin VDDP -5% -12% 2.9V VPORST3.3 t PORST t 1.5V VDD 1.42V VDDmin VDD 1.32V VPORST1.5min -5% -12% t PORST t PowerDown3.3_1.5_reset_only.vsd Figure 30 Data Sheet Power Down / Power Loss Sequence 108 V1.0, 2008-04 TC1796 Preliminary 4.3.4 Table 23 Electrical Parameters Power, Pad and Reset Timing Power, Pad and Reset Timing Parameters Parameter Symbol Values Min. Typ. Max. Unit Note / Test Con dition Min. VDDP voltage to ensure defined pad states1) VDDPPA CC 0.6 - - V - Oscillator start-up time2) tOSCS tPOA CC - - 10 ms - SR 10 - - ms - HDRST pulse width tHD CC 1024 - clock cycles3)6) - fSYS - PORST rise time tPOR tPOS SR - - 50 ms - SR 0 - - ns - Hold time from PORST rising edge4) tPOH SR 100 - - ns - Setup time to HDRST rising edge5) tHDS SR 0 - - ns - Hold time from HDRST rising edge5) tHDH SR 100 + (2 x 1/ fSYS)6) - - ns - Ports inactive after PORST reset active7)8) tPIP CC - - 150 ns - Ports inactive after HDRST reset active tPI CC - - 150 + ns 5 x 1/ - Minimum PORST active time after power supplies are stable at operating levels Setup time to PORST rising edge4) fSYS Minimum VDDP PORST activation threshold9) VPORST3.3 - - 2.9 V - Minimum VDD PORST activation threshold9) VPORST1.5 - - 1.32 V - Power on Reset Boot Time9) tBP tB CC - - 2 ms - CC 150 - 350 s - Hardware/Software Reset Boot Time at fCPU=150MHz10) Data Sheet SR SR 109 V1.0, 2008-04 TC1796 Preliminary Electrical Parameters 1) This parameter is valid under assumption that PORST signal is constantly at low level during the powerup/power-down of the VDDP. 2) tOSCS is defined from the moment when VDDOSC3 = 3.13V until the oscillations reach an amplitude at XTAL1 of 0,3*VDDOSC3. This parameter is verified by device characterization. The external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended and specified by crystal suppliers. 3) Any HDRST activation is internally prolonged to 1024 FPI bus clock (fSYS) cycles. 4) Applicable for input pins TESTMODE, TRST, BRKIN, and TXD1A with noise suppression filter of PORST switched-on (BYPASS = 0). 5) The setup/hold values are applicable for Port 0 and Port 10 input pins with noise suppression filter of HDRST switched-on (BYPASS = 0), independently whether HDRST is used as input or output. 6) fSYS = fCPU/2 7) Not subject to production test, verified by design / characterization. 8) This parameter includes the delay of the analog spike filter in the PORST pad. 9) The duration of the boot-time is defined between the rising edge of the PORST and the moment when the first user instruction has entered the CPU and its processing starts. 10) The duration of the boot time is defined between the following events: 1. Hardware reset: the falling edge of a short HDRST pulse and the moment when the first user instruction has entered the CPU and its processing starts, if the HDRST pulse is shorter than 1024 x TSYS. If the HDRST pulse is longer than 1024 x TSYS, only the time beyond the 1024 x TSYS should be added to the boot time (HDRST falling edge to first user instruction). 2. Software reset: the moment of starting the software reset and the moment when the first user instruction has entered the CPU and its processing starts Data Sheet 110 V1.0, 2008-04 TC1796 Preliminary Electrical Parameters V DDPPA VDDPPA VDDP VDD V DDPR toscs OSC tPOA tPOA PORST thd thd HDRST 1) 2) Pads Padstate undefined 2) tpi 1) as programmed 1) 2) Padstate undefined 2) Tri-state, pull device active re se t_ b e h 1 Figure 31 Data Sheet Power, Pad and Reset Timing 111 V1.0, 2008-04 TC1796 Preliminary 4.3.5 Electrical Parameters Phase Locked Loop (PLL) Note: All PLL characteristics defined on this and the next page are verified by design characterization. Table 24 PLL Parameters (Operating Conditions apply) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Con dition Accumulated jitter DP See - Figure 3 2 - - VCO frequency range fVCO 400 - 500 MHz - 600 - 700 MHz - 500 - 600 MHz - 140 - 320 MHz - 150 - 400 MHz - 200 - 480 MHz - - - 200 s PLL base frequency1) PLL lock-in time fPLLBASE tL - - 1) The CPU base frequency which is selected after reset is calculated by dividing the limit values by 16 (this is the K factor after reset). Phase Locked Loop Operation When PLL operation is enabled and configured, the PLL clock fVCO (and with it the CPU clock fCPU) is constantly adjusted to the selected frequency. The relation between fVCO and fSYS is defined by: fVCO = K x fCPU. The PLL causes a jitter of fCPU and affects the clock outputs BFCLKO, TRCLK, and SYSCLK (P1.12) which are derived from the PLL clock fVCO. There will be defined two formulas that define the (absolute) approximate maximum value of jitter DP in ns dependent on the K-factor, the CPU clock frequency fCPU in MHz, and the number P of consecutive fCPU clock periods. Data Sheet 7000 x P P x K < 385 - + 0, 535 D p [ ns ] = -----------------------------------------2 f cpu [ MHz ] x K P x K 385 D p [ ns ] = -------------------------------------------- + 0, 535 2 f cpu [ MHz ] x K 2 2700000 112 (1) (2) V1.0, 2008-04 TC1796 Preliminary Electrical Parameters Note: The frequency of system clock fSYS can be selected to be either fCPU or fCPU/2. With rising number P of clock cycles the maximum jitter increases linearly up to a value of P that is defined by the K-factor of the PLL. Beyond this value of P the maximum accumulated jitter remains at a constant value. Further, a lower CPU clock frequency fCPU results in a higher absolute maximum jitter value. Figure 32 gives the jitter curves for several K/fCPU combinations. 20.0 DP ns fCPU = 50 MHz (K = 8) fCPU = 100 MHz (K = 4) 16.0 fCPU = 120 MHz (K = 4) 12.0 fCPU = 150 MHz (K = 4) 8.0 4.0 fCPU = 100 MHz (K = 7) 0.0 fCPU = 50 MHz (K = 14) 0 20 40 60 DP = Max. jitter P = Number of consecutive fCPU periods K = K-divider of PLL Figure 32 Data Sheet 80 100 120 oo P TC1976_PLL_JITT Approximated Maximum Accumulated PLL Jitter for Typical CPU Clock Frequencies fCPU (overview) 113 V1.0, 2008-04 TC1796 Preliminary DP Electrical Parameters 4.0 ns 3.5 fCPU = 50 MHz (K = 14) fCPU = 50 MHz (K = 8) 3.0 fCPU = 100 MHz (K = 4) 2.5 fCPU = 100 MHz (K = 7) 2.0 1.5 fCPU = 150 MHz (K = 4) 1.0 0.5 0.0 0 2 4 6 8 10 DP = Max. jitter P = Number of consecutive fCPU periods K = K-divider of PLL Figure 33 12 14 16 18 20 P TC1976_PLL_DETAIL Approximated Maximum Accumulated PLL Jitter for Typical CPU Clock Frequencies fCPU (detail) Note: The specified PLL jitter values are valid if the capacitive load at the External Bus Unit (EBU) is limited to CL=20pF. Note: The maximum peak-to-peak noise on the Core Supply Voltage (measured between VDD at pin E23 and VSS at pin D23, or adjacent supply pairs) is limited to a peak-to-peak voltage of VPP = 30mV. This condition can be achieved by appropriate blocking of the Core Supply Voltage as near as possible to the supply pins and using PCB supply and ground planes.=20pF. Data Sheet 114 V1.0, 2008-04 TC1796 Preliminary 4.3.6 Electrical Parameters BFCLKO Output Clock Timing VSS = 0 V;VDD = 1.5 V 5%; VDDEBU = 2.5 V 5% and 3.3 V 5%; TA = -40 C to +125 C; CL = 35 pF BFCLK0 Output Clock Timing Parameters1) Table 25 Parameter Symbol Values Max. Unit Note / Test Con dition 13.332) - - ns - 3 - - ns - 3 - - ns - - - 3 ns - - - 3 ns - 45 50 55 % divider of 2, 4, ...4) Min. BFCLKO clock period BFCLKO high time BFCLKO low time BFCLKO rise time BFCLKO fall time BFCLKO duty cycle t5/(t5 + t6)3) tBFCLKO CC t5 CC t6 CC t7 CC t8 CC DC24 CC Typ. BFCLKO duty cycle t5/(t5 + t6)3) DC3 CC 30 33.33 36 % divider of 3 4) BFCLKO high time reduction5) dt5 CC - - ns CL = 20pF 1.1 1) Not subject to production test, verified by design/characterization. 2) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter parameters. 3) The PLL jitter is not included in this parameter. If the BFCLKO frequency is equal to fCPU, the K-divider setting determines the duty cycle. 4) The division ratio between LMB and BFCLKO frequency is set by EBU_BFCON.EXTCLOCK. 5) Due to asymmetry of the delays and slopes of the rising and falling edge of the pad. The influence of the PLL jitter is included in this parameter. This parameter should be applied taking the typical value of the duty cycle in the account, not the minimum or maximum value. tBFCLKO BFCLKO 0.5 VDDP05 t5 t6 t8 t7 0.9 VDD 0.1 VDD MCT04883_mod Figure 34 Data Sheet BFCLKO Output Clock Timing 115 V1.0, 2008-04 TC1796 Preliminary Electrical Parameters BFCLK Timing and PLL Jitter The BFCLK timing is important for calculating the timing of an external flash memory. In principle BFCLK timing can be derived from the PLL jitter formulas. In case of only EBU synchronous read access to the flash device the worst case jitter is partially lower. For one BFCLK with a cycle time of 13,33 ns the maximum jitter is tJPP = |+/-620 ps| For two BFCLKs with an accumulated cycle time of 26,66 ns the maximum jitter is tJPACC = |+/- 660 ps| Data Sheet 116 V1.0, 2008-04 TC1796 Preliminary 4.3.7 Electrical Parameters Debug Trace Timing VSS = 0 V; VDDP = 3.13 to 3.47 V (Class A); TA = -40 C to +125 C; CL (TRCLK) = 25 pF; CL (TR[15:0]) = 50 pF; Table 26 Debug Trace Timing Parameter1) Parameter Symbol Values Min. TR[15:0] new state from TRCLK rising edge t9 CC -1 Typ. Max. Unit Note / Test Con dition - 4 ns - 1) Not subject to production test, verified by design/characterization. TRCLK t9 TR[15:0] Old State New State Trace_Tmg Figure 35 Data Sheet Debug Trace Timing 117 V1.0, 2008-04 TC1796 Preliminary 4.3.8 Electrical Parameters JTAG Interface Timing Operating Conditions apply, CL = 50 pF Table 27 TCK Clock Timing Parameter Parameter Symbol Values Typ. Max. Unit Note / Test Con dition SR 25 - - ns - SR 10 - - ns - SR 10 - - ns - SR - - 4 ns - SR - - 4 ns - Min. TCK clock period1) tTCK t1 t2 t3 t4 TCK high time TCK low time TCK clock rise time TCK clock fall time 1) fTCK should be lower or equal to fSYS. tTCK TCK 0.5 VDDP t1 t2 t4 t3 0.9 VDD 0.1 VDD JTAG_TCK Figure 36 Data Sheet TCK Clock Timing 118 V1.0, 2008-04 TC1796 Preliminary Table 28 Electrical Parameters JTAG Timing Parameters1) Parameter Symbol Values Min. TMS setup to TCK rising edge TMS hold to TCK rising edge TDI setup to TCK rising edge TDI hold to TCK rising edge TDO valid output from TCK falling edge2) TDO high impedance to valid output from TCK falling edge2) TDO valid output to high impedance from TCK falling edge2) Typ. Max. Unit Note / Test Con dition t1 t2 t1 t2 t3 t3 t4 SR 6.0 - - ns - SR 6.0 - - ns - SR 6.0 - - ns - SR 6.0 - - ns - CC - - 13 ns CL = 50 pF CC 3.0 - - ns CL = 20 pF CC - - 14 ns CL = 50 pF t5 CC - - 13.5 ns CL = 50 pF 1) fTCK should be lower or equal to fSYS. 2) The falling edge on TCK is used to capture the TDO timing. TCK t1 t2 t1 t2 TMS TDI t4 t3 t5 TDO Jtag Figure 37 JTAG Timing Note: The JTAG module is fully compliant with IEEE1149.1-2000 with JTAG clock at 20 MHz. The JTAG clock at 40MHz is possible with the modified timing diagram shown in Figure 37. Data Sheet 119 V1.0, 2008-04 TC1796 Preliminary 4.3.9 Electrical Parameters EBU Demultiplexed Timing VSS = 0 V;VDD = 1.5 V 5%; VDDEBU = 2.5 V 5% and 3.3 V 5%, Class B pins; TA = -40 C to +125 C; CL = 35 pF; Table 29 EBU Demultiplexed Timing Parameters1) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Con dition Output delay from BFCLKO rising edge2) t10 CC 0 - 5 ns - RD active/inactive after BFCLKO rising edge2) t12 CC 0 - 3 ns - Data setup to BFCLKO rising edge2) t13 SR 8.5 - - ns - Data hold from BFCLKO rising t14 edge2) SR 0 - - ns - WAIT setup (low or high) to BFCLKO rising edge2) t15 SR 3 - - ns - WAIT hold (low or high) from BFCLKO rising edge2) t16 SR 2 - - ns - Data hold after RD/WR rising edge t17 SR 0 - - ns - 1) Not subject to production test, verified by design/characterization. 2) Valid for BFCON.EXTCLOCK = 00B. Data Sheet 120 V1.0, 2008-04 TC1796 Preliminary 4.3.9.1 Electrical Parameters Demultiplexed Read Timing Address Phase Command Del. Phase (opt.) Command Phase Recovery New Addr. Phase (opt.) Phase BFCLKO t10 t10 A[23:0] Valid Address t10 t10 Inval. Address t10 Next Addr. t10 ADV t10 t10 t10 CS[3:0] CSCOMB t12 t12 RD RD/WR MR/W t13 D[31:0] t14 Valid Data t10 t10 t10 BC[3:0] t15 t16 WAIT DemuxRD_1.vsd Figure 38 Data Sheet EBU Demultiplexed Read Timing 121 V1.0, 2008-04 TC1796 Preliminary 4.3.9.2 Electrical Parameters Demultiplexed Write Timing Address Phase Command Del. Phase (opt.) Command Phase Data Hold Phase Recovery New Addr. Phase (opt.) Phase BFCLKO t10 t10 A[23:0] Valid Address t10 t10 Inval. Address t10 Next Addr. t10 ADV t10 t10 t10 CS[3:0] CSCOMB RD t10 t10 RD/WR t17 t10 t10 MR/W t10 t10 Data Out D[31:0] t10 t10 t10 t10 BC[3:0] t15 t16 WAIT DemuxWR_1.vsd Figure 39 Data Sheet EBU Demultiplexed Write Timing 122 V1.0, 2008-04 TC1796 Preliminary 4.3.10 Electrical Parameters EBU Burst Mode Read Timing VSS = 0 V;VDD = 1.5 V 5%; VDDEBU = 2.5 V 5% and 3.3 V 5%, Class B pins; TA = -40 C to +125 C; CL = 35 pF; Table 30 EBU Burst Mode Read Timing Parameters1) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Con dition Output delay from BFCLKO rising edge t10 CC 0 - 5 ns - RD active/inactive after BFCLKO rising edge t12 CC 0 - 5 ns - CSx output delay from BFCLKO rising edge t21 CC 0 - 4 ns - ADV/BAA active/inactive after t22 BFCLKO rising edge2) CC 0 - 4 ns - Data setup to BFCLKI rising edge t23 SR 3 - - ns - Data hold from BFCLKI rising edge t24 SR 0 - - ns - WAIT setup (low or high) to BFCLKI rising edge t25 SR 3 - - ns - WAIT hold (low or high) from BFCLKI rising edge t26 SR 2 - - ns - 1) Not subject to production test, verified by design/characterization. 2) This parameter is valid for BFCON.EBSE0 = 1 (or BFCON.EBSE1 = 1). Note that t22 is increased by: 1/2 of the LMB bus clock period TCPU = 1/fCPU when BFCON.EBSE0 = 0 (or BFCON.EBSE1 = 0). Data Sheet 123 V1.0, 2008-04 TC1796 Preliminary Electrical Parameters Address Phase(s) BFCLKI BFCLKO Command Phase(s) Burst Phase(s) Burst Phase(s) Recovery Phase(s) Next Addr. Phase(s) 1) t10 t10 A[23:0] Next Addr. Burst Start Address t22 t22 t22 ADV t10 t10 t10 CS[3:0] CSCOMB t12 t12 RD t22 t22 BAA t23 t24 t23 t24 D[31:0] (32-Bit) Data (Addr+0) Data (Addr+4) D[15:0] (16-Bit) Data (Addr+0) Data (Addr+2) t25 t26 WAIT 1) Figure 40 Data Sheet Output delays are always referenced to BCLKO. The reference clock for input characteristics depends on bit EBU_BFCON.FDBKEN. EBU_BFCON.FDBKEN = 0:BFCLKO is the input reference clock. EBU_BFCON.FDBKEN = 1:BFCLKI is the input reference clock (EBU clock feedback enabled). BurstRD_4.vsd EBU Burst Mode Read Timing 124 V1.0, 2008-04 TC1796 Preliminary 4.3.11 Electrical Parameters EBU Arbitration Signal Timing VSS = 0 V;VDD = 1.5 V 5%; VDDEBU = 2.5 V 5% and 3.3 V 5%, Class B pins; TA = -40C to +125 C; CL = 35 pF; Table 31 EBU Arbitration Signal Timing Parameters1) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Con dition Output delay from CLKOUT rising edge t27 CC - - 3 ns - Data setup to CLKOUT falling edge t28 SR 8 - - ns - Data hold from CLKOUT falling edge t29 SR 2 - - ns - 1) Not subject to production test, verified by design/characterization. BFCLKO t27 t27 HLDA Output t27 t27 BREQ Output BFCLKO t28 t28 t29 t29 HOLD Input HLDA Input Figure 41 Data Sheet EBUArb_1 EBU Arbitration Signal Timing 125 V1.0, 2008-04 TC1796 Preliminary 4.3.12 Electrical Parameters Peripheral Timings Note: Peripheral timing parameters are not subject to production test. They are verified by design/characterization. 4.3.12.1 Micro Link Interface (MLI) Timing Table 32 MLI Timing Parameters (Operating Conditions apply), CL = 50 pF Parameter Symbol Values Min. TCLK clock period1)2) Typ. Max. Unit Note / Test Con dition t30 t31 t35 CC 23) - - 1 / fSYS - SR 1 - - 1 / fSYS - CC 0 - 8 ns - MLI inputs setup to RCLK falling edge t36 SR 4 - - ns - MLI inputs hold to RCLK falling edge t37 SR 4 - - ns - RREADY output delay from t38 RCLK falling edge CC 0 - 8 ns - RCLK clock period MLI outputs delay from TCLK rising edge 1) TCLK signal rise/fall times are the same as the A2 Pads rise/fall times. 2) TCLK high and low times can be minimum 1 x TMLI. 3) When fSYS = 75 MHz, t30 = 26,67ns Data Sheet 126 V1.0, 2008-04 TC1796 Preliminary Electrical Parameters t30 0.9 VDDP 0.1 VDDP TCLKx t35 t35 TDATAx TVALIDx TREADYx t31 RCLKx t36 t37 RDATAx RVALIDx t38 t38 RREADYx MLI_Tmg_2.vsd Figure 42 MLI Interface Timing Note: The generation of RREADYx is in the input clock domain of the receiver. The reception of TREADYx is asynchronous to TCLKx. Data Sheet 127 V1.0, 2008-04 TC1796 Preliminary Electrical Parameters 4.3.12.2 Micro Second Channel (MSC) Interface Timing Table 33 MSC Interface Timing (Operating Conditions apply), CL = 50 pF Parameter Symbol Values Min. FCLP clock period1)2) SOP/ENx outputs delay from FCLP rising edge SDI bit time SDI rise time SDI fall time Typ. Unit Note / Test Con dition Max. t40 t45 CC 2 x TMSC3) - - ns - CC -10 10 ns - t46 t48 t49 CC 8 x TMSC - ns - SR 100 ns - SR 100 ns - 1) FCLP signal rise/fall times are the same as the A2 Pads rise/fall times. 2) FCLP signal high and low can be minimum 1 x TMSC. 3) TMSCmin = TSYS = 1/fSYS. When fSYS = 75 MHz, t40 = 26,67ns t40 0.9 VDDP 0.1 VDDP FCLP t45 t45 SOP EN t48 t49 0.9 VDDP 0.1 VDDP SDI t46 Figure 43 t46 MSC_Tmg_1.vsd MSC Interface Timing Note: The data at SOP should be sampled with the falling edge of FCLP in the target device. Data Sheet 128 V1.0, 2008-04 TC1796 Preliminary Electrical Parameters 4.3.12.3 Synchronous Serial Channel (SSC) Master Mode Timing Table 34 SSC Master Mode Timing (Operating Conditions apply), CL = 50 pF Parameter Symbol Values Min. SCLK clock period1)2) Typ. Unit Note / Test Con dition Max. t50 t51 CC 2 x TSSC3) - - ns - CC 0 - 8 ns - MRST setup to SCLK falling edge t52 SR 10 - - ns - MRST hold from SCLK falling edge t53 SR 5 - - ns - MTSR/SLSOx delay from SCLK rising edge 1) SCLK signal rise/fall times are the same as the A2 Pads rise/fall times. 2) SCLK signal high and low times can be minimum 1 x TSSC. 3) TSSCmin = TSYS = 1/fSYS. When fSYS = 75 MHz, t50 = 26,67ns t50 SCLK1)2) t51 t51 MTSR1) t52 t53 Data valid MRST1) t51 SLSOx2) 1) This timing is based on the following setup: CON.PH = CON.PO = 0. 2) The transition at SLSOx is based on the following setup: SSOTC.TRAIL = 0 and the first SCLK high pulse is in the first one of a transmission. SSC_Tmg_1.vsd Figure 44 Data Sheet SSC Master Mode Timing 129 V1.0, 2008-04 TC1796 Preliminary Package and Reliability 5 Package and Reliability 5.1 Package Parameters (P/PG-BGA-416-4) Table 35 Parameter Thermal Characteristics of the Package Symbol Values Max. Unit Note / Test Condi tion Thermal resistance junction RTJCT CC - case top1) 8 K/W - Thermal resistance junction RTJCB CC - case bottom1) 15 K/W - Min. Typ. 1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the case and the ambient (RTCAT, RTCAB) depend on the external system (PCB, case) characteristics, and are under user responsibility. The junction temperature can be calculated using the following equation: TJ = TA + RTJA x PD, where the RTJA is the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from the upper four partial thermal resistances. Data Sheet 130 V1.0, 2008-04 TC1796 Preliminary 5.2 Package and Reliability Package Outline 25 x 1 = 25 A26 1 25 x 1 = 25 A1 AF1 0.5 0.1 (0.56) (1.17) 2.5 MAX. 1 o0.63 +0.07 -0.13 416x o0.25 M A B C o0.1 M C 0.15 C 27 0.2 24 0.5 20 0.2 A Index Marking 20 0.2 24 0.5 27 0.2 Index Marking (sharp edge) B GPA09537 Figure 45 P/PG-BGA-416-4, Plastic Low Profile Pitch Ball Grid Array You can find our packages, sorts of packing and others in our Infineon Internet Web Site. Data Sheet 131 V1.0, 2008-04 TC1796 Preliminary 5.3 Package and Reliability Flash Memory Parameters The data retention time of the TC1796's Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Table 36 Flash Parameters Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. Program / Data Flash tRET CC 20 Retention Time, Physical Sector1)2) - - years Max. 1000 erase/program cycles Program / Data Flash tRETL CC 20 Retention Time Logical Sector1)2) - - years Max. 100 erase/program cycles Data Flash Endurance (128 KB) NE - - - Max. data retention time 5 years Data Flash Endurance, EEPROM Emulation (8 x 16 KB) NE8 CC 120 000 - - - Max. data retention time 5 years Programming Time per Page3) tPR CC - - 5 ms - Program Flash Erase Time per 256-KB Sector tERP CC - - 5 s fCPU = 150 MHz Data Flash Erase Time per 64-KB Sector tERD CC - - 2.5 s fCPU = 150 MHz Wake-up time tWU CC 4300 x 1/fCPU - - - - CC 15 000 + 40s 1) Storage and inactive time included. 2) At average weighted junction temperature Tj = 100oC, or the retention time at average weighted temperature of Tj = 110oC is minimum 10 years, or the retention time at average weighted temperature of Tj = 150oC is minimum 0.7 years. 3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The reprogramming takes additional 5 ms. Data Sheet 132 V1.0, 2008-04 TC1796 Preliminary 5.4 Table 37 Package and Reliability Quality Declarations Quality Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Operation Lifetime1)2) tOP - - 24000 hours at average weighted junction temperature Tj = 127oC - - 66000 hours at average weighted junction temperature Tj = 100oC - - 20 years at average weighted junction temperature Tj = 85oC ESD susceptibility VHBM according to Human Body Model (HBM) - - 2000 V Conforming to EIA/JESD22-A114-B ESD susceptibility VHBM1 of the LVDS pins - - 500 V - ESD susceptibility VCDM according to Charged Device Model (CDM) - - 500 V Conforming to JESD22-C101-C Moisture Sensitivity Level - - 3 - Conforming to Jedec J-STD-020C for 240C MSL 1) This lifetime refers only to the time when the device is powered on. 2) One example of a detailed temperature profile is: 2000 hours at Tj = 150oC 16000 hours at Tj = 125oC 6000 hours at Tj = 110oC This example is equivalent to the operation lifetime and average temperatures given in the table. Data Sheet 133 V1.0, 2008-04 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG