STK501
.............................................................................
User Guide
Table of Contents
i
Table of Contents
Section 1
Introduction ........................................................................................... 1-1
1.1 Features ....................................................................................................1-2
Section 2
Using the STK501 Top Module............................................................. 2-1
2.1 Connecting the STK501 to the STK500 Starter Kit...................................2-1
2.1.1 Placing an ATmega103(L) or ATmega128(L) on the STK500............2-1
2.2 PORT Connectors.....................................................................................2-2
2.2.1 PORT E/PORT F ................................................................................2-2
2.2.2 PORT G/AUX .....................................................................................2-3
2.2.2.1 PG0 - PG4 ...................................................................................2-3
2.2.2.2 A16...............................................................................................2-3
2.2.2.3 SRAMEN......................................................................................2-3
2.2.2.4 PEN..............................................................................................2-3
2.3 Programming the ATmega103(L)/ 128(L) .................................................2-3
2.3.1 In-System Programming.....................................................................2-3
2.3.2 High-voltage Programming.................................................................2-4
2.4 JTAG Connector .......................................................................................2-5
2.5 External SRAM .........................................................................................2-6
2.5.1 A16 .....................................................................................................2-7
2.5.2 SRAMEN ............................................................................................2-7
2.6 Ram High Address Jumpers .....................................................................2-8
2.7 A[7:0] Connector .......................................................................................2-8
2.8 Using the SRAM Interface with AT90S/LS8515 and ATmega161 ............2-8
2.9 TOSC Switch ............................................................................................2-9
2.10 RS-232C Port............................................................................................2-9
Section 3
Troubleshooting Guide ......................................................................... 3-1
Section 4
Technical Specifications ....................................................................... 4-1
Section 5
Technical Support................................................................................. 5-1
AVR® STK501 User Guide 1-1
Section 1
Introduction
The STK501 board is a top module designed to add ATmega103(L) and ATmega128(L)
support to the STK500 development board from Atmel Corporation. With this board the
STK500 is extended to support all current AVR devices in a single development
environment.
The STK501 includes connectors, jumpers and hardware allowing full utilization of the
new features of the ATmega128(L) while the Zero Insertion Force (ZIF) socket allows
easy use of TQFP packages for prototyping.
This user guide acts as a general getting started guide as well as a complete technical
reference for advanced users.
In addition to adding support for new devices, it also adds new support for peripherals
previously not supported by the STK500. An additional RS-232 port and external SRAM
interface are09/01 among the new features. Devices with dual UART or XRAM interface
can all take advantage of the new resources on the STK501 board.
Figure 1-1. STK501 Top Module for STK500
Rev. 2491A-09/01
Introduction
1-2 AVR® STK501 User Guide
1.1 Features
STK500 Compatible
AVR Studio® Compatible
Supports ATmega103(L) and ATmega128(L)
Zero Insertion Force Socket for TQFP Packages
TQFP Footprint for Emulator Adapters
Supports all Added Features in ATmega128(L)
JTAG Connector for On-chip Debugging Using JTAG ICE (ATmega128(L))
Additional RS-232C Port with Available RTS/CTS Handshake Lines
Adds External SRAM Support to the STK500 Board (Usable for all Devices with
XRAM Interface)
On-board 32 kHz Crystal for Easy RTC Implementations
AVR® STK501 User Guide 2-1
Section 2
Using the STK501 Top Module
2.1 Connecting the
STK501 to the
STK500 Starter
Kit
The STK501 should be connected to the STK500 expansion header 0 and 1. It is impor-
tant that the top module is connected in the correct orientation as shown in Figure 2-1.
The EXPAND0 written on the STK501 top module should match the EXPAND0 written
beside the expansion header on the STK500 board.
Figure 2-1. Connecting STK501 to the STK500 Board
Note: Connecting the STK501 with wrong orientation may damage the board.
2.1.1 Placing an
ATmega103(L) or
ATmega128(L) on
the STK500
The STK501 contains both a ZIF socket, and the pinout for a TQFP package; which
allows an easy way of soldering an emulator adapter directly into the STK501. Care
should be taken so that the device (or adapter) is mounted with the correct orientation.
Figure 2-2 shows the location of pin 1 for the ZIF socket and the TQFP footprint.
Caution: Do not mount an ATmega103(L) or ATmega128(L) on the STK501 at the
same time as an AVR is mounted on the STK500 board.
Rev. 2491A-09/01
Using the STK501 Top Module
2-2 AVR® STK501 User Guide
Figure 2-2. Pin1 on ZIF Socket and TQFP Footprint
2.2 PORT
Connectors
Since the ATmega103(L) and ATmega128(L) have additional ports not available on the
STK500, these ports are located on the STK501 board. They have the same pinout and
functionality as the ports on the STK500 board. Port A to Port D which are already
present on the STK500 board are not duplicated on the STK501.
2.2.1 PORT E/PORT F Figure 2-3 shows the pinout for the I/O port headers Port E and Port F.
Figure 2-3. General I/O Ports
Note: Port E is also present on the STK500, but only PE0 to PE2 (3 least significant
bits) are accessible there. To access all Port E bits the connector on the
STK501 must be used.
PE1
PE3
PE5
PE7
VTG
PE0
PE2
PE4
PE6
GND
1 2
PORT E
PF1
PF3
PF5
PF7
VTG
PF0
PF2
PF4
PF6
GND
1 2
PORT F
Using the STK501 Top Module
AVR® STK501 User Guide 2-3
2.2.2 PORT G/AUX In addition to the normal Port G pins, this connector has some extra signals. See Figure
2-4.
Figure 2-4. PORTG/AUX
2.2.2.1 PG0 - PG4 These are general I/O ports for the ATmega128(L) and connect to the ZIF socket and
the TQFP footprint. The PG3 and PG4 signals are routed through the TOSC switch
since these pins also are inputs for a 32 kHz oscillator. For a description on the TOSC
switch see Section 2.9.
Note: ATmega103(L) does not have Port G.
2.2.2.2 A16 This line goes to A16 (most significant address bit) on the SRAM. See Section 2.5 for
more information about this signal. can be connected to any AVR pin.
2.2.2.3 SRAMEN The SRAMEN signal controls if the SRAM is enabled or not. To enable the SRAM a
LOW level should be applied to this pin. See “External SRAM”, Section 2.5, for more
information on how to use this signal. This signal is pulled high by default.
2.2.2.4 PEN The PEN pin is connected to the PEN pin on the ATmega103(L)/128(L). This pin is
described in the programming section of the ATmega103(L) and ATmega128(L)
datasheets.
2.3 Programming the
ATmega103(L)/
128(L)
The ATmega103(L) and ATmega128(L) can be programmed using both SPI and High-
voltage Parallel Programming. This sub section will explain how to connect the program-
ming cables to successfully use one of these two modes. The AVR Studio STK500
software is used in the same way as for other AVR parts.
Note: The ATmega128(L) also supports Self Programming. See AVR109 application
note for more information on this topic.
2.3.1 In-System
Programming
To program the ATmega103(L) or ATmega128(L) using ISP programming mode, con-
nect the 6-wire cable between the ISP6PIN connector on the STK500 board and the ISP
connector on the STK501 board as shown in Figure 2-5.
The device can be programmed using the serial programming mode in the AVR Studio
STK500 software.
Note: See the STK500 User Guide for information on how to use the STK500 front-
end software for ISP programming.
PG1
PG3
A16
PEN
VTG
PG0
PG2
PG4
SRAMEN
GND
1 2
PORT G/AUX
Using the STK501 Top Module
2-4 AVR® STK501 User Guide
Figure 2-5. In-System Programming
2.3.2 High-voltage
Programming
To program the ATmega103(L) or ATmega128(L) using High-voltage (Parallel) Pro-
gramming, connect the PROGCTRL to PORTD and PROGDATA to PORTB on the
STK500 as shown in Figure 2-6.
As described in the STK500 User Guide, the BSFL2 jumper must be mounted when
High-voltage Programming ATmega devices. This also applies to the High-voltage Pro-
gramming of ATmega103(L) and ATmega128(L).
The device can now be programmed using the High-voltage Programming mode in AVR
Studio STK500 software.
Note: See the STK500 User Guide for information on how to use the STK500 front-
end software in High-voltage Programming mode.
Note: For the High-voltage Programming mode to function correctly, the target voltage
must be higher than 4.5V.
Caution: Make sure the SRAM (if mounted) can handle this voltage.
Using the STK501 Top Module
AVR® STK501 User Guide 2-5
Figure 2-6. High-voltage (Parallel) Programming
2.4 JTAG Connector The JTAG connector is intended for the ATmega128(L) that has a built-in JTAG inter-
face. The pinout of the JTAG connector is shown in Figure 2-7 and is compliant with the
pinout of the JTAG ICE available from Atmel. Connecting a JTAG ICE to this connector
allows On-chip Debugging of the ATmega128(L).
More information about the JTAG ICE and On-chip Debugging can be found in the AVR
JTAG ICE User Guide, which is available at the Atmel web site, www.atmel.com.
Figure 2-7. JTAG Connector
Figure 2-8 shows how to connect the JTAG ICE probe on the STK501 board.
GND
VTG
RST
NC
GND
TCK
TDO
TMS
VTG
TDI
1 2
JTAG
Using the STK501 Top Module
2-6 AVR® STK501 User Guide
Figure 2-8. Connecting JTAG ICE to the STK501
2.5 External SRAM The STK501 contains a footprint where an external SRAM device can be mounted.
Make sure the SRAM device has the same voltage range as the rest of the design.
Caution: Special care should be taken if a low voltage SRAM is used, since High-volt-
age Programming requires a programming voltage higher than 4.5V. Low-voltage
SRAM may be damaged if High-voltage Programming of the target AVR is done.
Table 2-1 shows a list of recommended SRAM devices, and typical range of operation.
It is important that the SRAM device is soldered with the correct orientation as shown in
Figure 2-9.
Note: The SRAM is disabled by default. To enable SRAM support, put a jumper
between the SRAMEN and GND pin on the PORTG/AUX connector.
Figure 2-9. Pin1 on SRAM Footprint and Pinout
A0
A1
A2
A3
CS
D0
D1
VCC
GND
D2
D3
WE
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A8
A9
A10
A11
A12
D4
D5
VCC
GND
D6
D7
OE
A13
A14
A15
A16
128Kx8
Using the STK501 Top Module
AVR® STK501 User Guide 2-7
2.5.1 A16 The A16 pin on the PORTG/AUX connector is connected to A16 (address pin 16) on the
SRAM. ATmega103(L) and ATmega128(L) support up to 60 KB of external SRAM. The
STK501 SRAM footprint is for a 128 KB SRAM. Implementing software control of the
A16 line will increase the memory range from 64 KB to 128 KB. This line is pulled low by
default, addressing the lower 64 KB of the SRAM.
Figure 2-10. SRAM Block Schematic
2.5.2 SRAMEN The SRAMEN pin on the PORTG/AUX connector is connected to the Chip-enable (CE)
pin of the SRAM. This signal controls if the SRAM should be enabled or not. To enable
the SRAM, a low level should be applied to this pin. This pin is pulled high by default,
through a 10 kΩ resistor. Figure 2-10 shows a simplified block schematic on how the
SRAM interface is implemented. Figure 2-11 shows how to enable the SRAM by short-
ing SRAMEN and GND on the PORTG/AUX connector using one of the supplied
jumpers.
This signal can also be controlled by software or by some external control logic.
Table 2-1. Recommended SRAM Devices
Manufacturer Part Number Supply Voltage (V) Package
ISSI IS63LV1024-T 3.3 TSOP-II
ISSI IS63LV1024-J 3.3 SOJ 300-mil
ISSI IS63LV1024-K 3.3 SOJ 400-mil
IDT IDT71124-Y 5.0 SOJ 400-mil
IDT IDT71V124SA-TY 3.3 SOJ 300-mil
IDT IDT71V124SA-Y 3.3 SOJ 400-mil
IDT IDT71V124SA-PH 3.3 TSOP-II
VTG
PA6
PA7
PA5
PA4
PA3
PA2
PA1
PA0
PA6
PA7
PA5
PA4
PA3
PA2
PA1
PA0
PC6
PC7
PC5
PC4
PC3
PC2
PC1
PC0
OE
WE
CE
SRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
D0
D1
D2
D3
D4
D5
D6
D7
10K x 12
LATCH
LE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D1
D2
D3
D4
D5
D6
D7
D0
AVR
PORTA
ALE (PG2)
WR (PG0)
RD (PG1)
PORTC
OE
A6 A7
A5A4
A3A2
A1A0
VTG
A[7:0]
A6
A4
A2
A0
A7
A5
A3
A1
A6
A4
A2
A0
A7
A5
A3
A1
From
PORTG/AUX
connector SRAMEN
A16
RAM HIGH
ADDRESS
Using the STK501 Top Module
2-8 AVR® STK501 User Guide
Figure 2-11. SRAMEN Connected to GND
2.6 Ram High
Address
Jumpers
When External Memory is enabled in an AVR, all Port C pins are by default used for the
high address byte. If the full 60 KB address space is not required to access the external
memory, some, or all, Port C pins can be released for normal port pin function as
described in the ATmega128(L) datasheet. AT90S/LS8515, ATmega103(L) and
ATmega161 do not have this feature, and all jumpers should be connected if using the
XRAM interface with these devices.
If some or all of the Port C pins are released for normal port pin functions, the corre-
sponding “RAM High Address” jumper should be removed to avoid any Port C activity to
reach the SRAM address pins thus corrupting the address.
If a jumper is removed, the corresponding address line will be pulled low giving a logic
zero on that address bit on the SRAM. See the block schematic on Figure 2-10.
2.7 A[7:0] Connector The connector marked A[7:0] contains the 8 least-significant bits of the external SRAM
address bus. The purpose of the connector is to provide easy access to the address
bus. The 8 most significant bits can be found on the “Ram High Addresses” jumpers or
the Port C connector.
The connector is placed after the latch as shown in Figure 2-10.
This connector is handy when using the SRAM interface to interface external devices.
2.8 Using the SRAM
Interface with
AT90S/LS8515
and ATmega161
When using the SRAM interface with devices placed in the STK500 board, some addi-
tional straps are required. The reason is that the RD, WR, and ALE signals are not on
the same port pins for the AT90S8515/ATmega161(L) and ATmega103(L)/
ATmega128(L), so these signals must be routed manually using two of the 2-wire
cables.
Table 2-2. Signal Routing Required for AT90S8515A and ATmega161(L)
Connections STK500 STK501 Description
Write Signal WR PD6 PG0 Connect PD6:STK500 to PG0:STK501
Read Signal RD PD7 PG1 Connect PD7:STK500 to PG1:STK501
Address Latch Enable ALE PE1 PG2 Connect PE1:STK500 to PG2:STK501
Using the STK501 Top Module
AVR® STK501 User Guide 2-9
Figure 2-12. Enabling SRAM Interface for Devices in STK500
2.9 TOSC Switch On the ATmega128(L) the TOSC1 and TOSC2 lines are shared with Port G (PG4 and
PG3). The TOSC switch select if the 32 kHz crystal, or the Port G connector pins should
be connected to the pins on the device.
Figure 2-13 shows a simplified block schematic on how this is implemented.
Note: Port G is not available on the ATmega103(L), the switch will thus only select if
the 32 kHz crystal should be connected or not.
Figure 2-13. TOSC Block Schematic
2.10 RS-232C Port The ATmega128(L) has an additional UART compared to the ATmega103(L). The RS-
232 port on the STK501 board has in addition to the RXD and TXD lines support for
RTS and CTS flow control. Figure 2-14 shows a simplified block schematic on how this
is implemented.
Note: The UART in ATmega128(L) does not support hardware RTS or CTS control. If
such functionality is needed, it must be implemented in software.
PG4/TOSC1
PG3/TOSC2
32 kHz
To
PORT G/AUX
Connector
PG3
PG4
TOSC
Switch
AVR
Using the STK501 Top Module
2-10 AVR® STK501 User Guide
Figure 2-14. UART Block Schematic
This UART can also be used from devices placed in the STK500 board. Simply connect
the appropriate port pins to RXD and TXD on the STK501 board.
Note: If no software RTS/CTS flow control is implemented, a jumper shorting RTS and
CTS will ensure correct communication with an external application that uses
such flow control.
RxD TxD
CTS RTS
RS-232/Logic Level
Converter
8
7
3
2
4
6
5
RS232 SPARE2
AVR® STK501 User Guide 3-1
Section 3
Troubleshooting Guide
Table 3-1. Troubleshooting Guide
Problem Reason Solution
SRAM does not work
properly.
The SRAM is not connected. Verify all solderings, and
make sure the Pin1 on the
SRAM matches the one on
the footprint. Make sure the
SRAM pinout is correct.
SRAMEN is not mounted. Make sure that the SRAMEN
is connected to GND on the
AUX connector.
XRAM interface is not
enabled in the AVR device.
Verify that the code actually
enables the XRAM interface.
Some of the ADDRESS
HIGH BYTE jumpers may be
set incorrectly.
Connect some or all of
ADDRESS HIGH BYTE
jumpers.
SRAM does not work when
used by devices on the
STK500 board.
WR, RD and ALE signals
must be strapped using two
2-wire cables.
Use two 2-wire cables, and
connect these signals to the
appropriate pins.
After doing a High-voltage
Programming of the AVR, the
SRAM does not work
properly.
The SRAM might be
damaged due to the High-
voltage needed to program
the AVR.
Make sure the SRAM
handles 5V, if High-voltage
Programming mode should
be used.
Troubleshooting Guide
3-2 AVR® STK501 User Guide
AVR® STK501 User Guide 4-1
Section 4
Technical Specifications
System Unit
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 x 119 x 27 mm
Weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 g
Operating Conditions
Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V - 5.5V
Connections
Serial Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-pin D-SUB female
Serial Communications Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 kbps
Technical Specifications
4-2 AVR® STK501 User Guide
AVR® STK501 User Guide 5-1
Section 5
Technical Support
For Technical support, please contact avr@atmel.com. When requesting technical sup-
port, please include the following information:
Which target AVR device is used (complete part number)
Target voltage and speed
Clock source and fuse setting of the AVR
Programming method (ISP or High-voltage)
Hardware revisions of the AVR tools, found on the PCB
Version number of AVR Studio. This can be found in the AVR Studio help menu.
PC operating system and version/build
PC processor type and speed
A detailed description of the problem
Technical Support
5-2 AVR® STK501 User Guide
AVR® STK501 User Guide 6-1
Section 6
Complete Schematics
On the following pages the complete schematics and assembly drawing of the STK501
revision B are shown.
Complete Schematics
6-2 AVR® STK501 User Guide
Figure 6-1. Schematics, 1 of 3
1 2 3 4 5 6 78
A
B
C
D
8
7654321
D
C
B
A
A9903.3.1010.B
13
19-Jun-2001
STK501
Page of
Rev. B
Copyright Atmel Corporation 2001
PAT[7..0]
PCT[7..0]
PAT[7..0]
PCT[7..0]
PFT[7..0]
PFT[7..0]
PGT[4..0]
PGT[4..0]
AREFT
XT1
XT2
PDT[7..0]
PBT[7..0]
PBT[7..0]
PDT[7..0]
PET0
PET1
PET2
PET3
PET4
PET5
PET6
PET7
RESET
PET[7..0]
PET[7..0]
PBT0
PBT1
PBT2
PBT3
PBT4
PBT5
PBT6
PBT7
VTGGND
PAT0
PAT1
PAT2
PAT3
PAT4
PAT5
PAT6
PAT7
PCT0
PCT1
PCT2
PCT3
PCT4
PCT5
PCT6
PCT7
VTG GND
PGT0
PGT1
PGT2
PDT0
PDT1
PDT2
PDT3
PDT4
PDT5
PDT6
PDT7
PFT0
PFT1
PFT2
PFT3
PFT4
PFT5
PFT6
PFT7
GND
AVTG
TOSC1
TOSC2
TOSC1
TOSC2
PAT[7..0]
PCT[7..0]
PAT[7..0]
PCT[7..0]
PFT[7..0]
PFT[7..0]
PGT[4..0]
PGT[4..0]
AREFT
XT1
XT2
PDT[7..0]
PBT[7..0]
PBT[7..0]
PDT[7..0]
PET0
PET1
PET2
PET3
PET4
PET5
PET6
PET7
RESET
PET[7..0]
PET[7..0]
PBT0
PBT1
PBT2
PBT3
PBT4
PBT5
PBT6
PBT7
VTGGND
PAT0
PAT1
PAT2
PAT3
PAT4
PAT5
PAT6
PAT7
PCT0
PCT1
PCT2
PCT3
PCT4
PCT5
PCT6
PCT7
VTG GND
PGT0
PGT1
PGT2
PDT0
PDT1
PDT2
PDT3
PDT4
PDT5
PDT6
PDT7
PFT0
PFT1
PFT2
PFT3
PFT4
PFT5
PFT6
PFT7
GND
AVTG
TOSC1
TOSC2
TOSC1
TOSC2
ZIF SocketTQFP Footprint
VTG AVTG
12
C101
100N_16V_X7R
12
C102
100N_16V_X7R
12
C106
100N_16V_X7R
12
C105
100N_16V_X7R
21
L101
BLM-21A102S
GND
RESET RESET
PD7/T2
32 PD6/T1
31 PD5
30 PD4/IC1
29 PD3/INT3
28 PD2/INT2
27 PD1/INT1
26 PD0/INT0
25
PEN
1
PE0/PDI/RXD
2
PE1/PDO/TXD
3
PE2/AC+
4
PE3/AC-
5
PE4/INT4
6
PE5/INT5
7
PE6/INT6
8
XTAL1
24 XTAL2
23 GND
22 VCC
21 RESET
20 PG4/TOSC1
19 PG3/TOSC2
18 PB7/OC2
17
PB6/OC1B
16 PB5/OC1A
15 PB4/OC0
14 PB3/MISO
13 PB2/MOSI
12 PB1/SCK
11 PB0/SS
10 PE7/INT7
9
WR/PG0 33
AD7/PA7 44
ALE/PG2 43
A15/PC7 42
A14/PC6 41
A13/PC5 40
A12/PC4 39
A11/PC3 38
A10/PC2 37
A9/PC1 36
A8/PC0 35
RD/PG1 34
AD6/PA6 45
AD5/PA5 46
AD4/PA4 47
AD3/PA3 48
AVCC 64
AGND 63
AREF 62
ADC0/PF0 61
ADC1/PF1 60
ADC2/PF2 59
ADC3/PF3 58
ADC4/PF4 57
ADC6/PF6 56
ADC6/PF6 55
ADC7/PF7 54
GND 53
VCC 52
AD0/PA0 51
AD1/PA1 50
AD2/PA2 49
U101
ATMEGA128
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
ST101
TQFP64 ZIF SOCKET
12
C103
100N_16V_X7R
12
C104
100N_16V_X7R
PEN PEN
PENPEN
12
C107
100N_16V_X7R
12
C108
100N_16V_X7R
AREFT AREFT
GNDGND
Complete Schematics
AVR® STK501 User Guide 6-3
Figure 6-2. Schematics, 2 of 3
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A
B
C
D
8
7654321
D
C
B
A
A9903.3.1010.B
23
19-Jun-2001
STK501
Page of
Rev. B
Copyright Atmel Corporation 2001
GNDGND
GND
PAT0PAT1
PAT2PAT3
PAT4PAT5
PAT6PAT7
PCT0PCT1
PCT2PCT3
PCT4PCT5
PCT6PCT7
GND
VTG
PET0PET1
PET2
RESET
AREFT
GNDGND
GND
GND VTGVTG
GND
PDT0PDT1
PDT2PDT3
PDT4PDT5
PDT6PDT7
PBT0PBT1
PBT2PBT3
PBT4PBT5
PBT6PBT7
XT2XT1
XT1
XT2
RESET AREFT
PAT[7..0]
PCT[7..0]
PAT[7..0]
PCT[7..0]
PET[7..0]
PET[7..0]
PDT[7..0]
PBT[7..0]
PBT[7..0]
PDT[7..0]
MISO 1
SCK 3
RESET 5
GND
6
VCC
2
MOSI
4
J206
ISP_CONNECTOR
GND
VTG
PET0
PET1
PBT1
VTGGND
PET0 PET1
PET2 PET3
PET4 PET5
PET6 PET7
PFT[7..0]
VTGGND
PFT0 PFT1
PFT2 PFT3
PFT4 PFT5
PFT6 PFT7
PFT[7..0]
PGT[4..0]
VTGGND
PGT[4..0]
PGT0 PGT1
PGT2 PGT3
PGT4
PFT4
PFT5
PFT6
PFT7
GND
VTG
GND
VTG
RESET
RESET
VTG
GND
VTGGND
A[7..0]
A16
PORTF PORTE
JTAG
PORTG/AUX LATCHED ADDRESS
A[7..0]
A0 A1
A2 A3
A4 A5
A6 A7
1 2
3 4
5 6
7 8
910
J204
1 2
3 4
5 6
7 8
910
J203
1 2
3 4
5 6
7 8
910
J205
1 2
3 4
5 6
7 8
910
J208
1 2
3 4
5 6
7 8
910
J207
A16
EXPAND0 EXPAND1
12
C201
100N_16V_X7R
12
C202
100N_16V_X7R
12
C203
100N_16V_X7R
12
C204
100N_16V_X7R
GND
GND
VTG VTG
SRAMEN
SRAMEN
JS201 JS202 Port G special features
PG0: nWR
PG1: nRD
PG2: ALE
PG3: TOSC2
PG4: TOSC1
PEN
PEN
1 2
R201
10K
VTG
1 2
R203
0R
GND
1 2
R202
0R
GND
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
J201
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
J202
NOT MOUNTED
Complete Schematics
6-4 AVR® STK501 User Guide
Figure 6-3. Schematics, 3 of 3
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A
B
C
D
8
7654321
D
C
B
A
A9903.3.1010.B
33
19-Jun-2001
STK501
Page of
Rev. B
Copyright Atmel Corporation 2001
OE
1
LE
11
D0
2
Q0 19
D1
3
Q1 18
D2
4
Q2 17
D3
5
Q3 16
D4
6
Q4 15
D5
7
Q5 14
D6
8
Q6 13
D7
9
Q7 12
VCC 20
GND
10
U301 74AHC573PW
A0
A1
A2
A3
A4
A5
A6
A7
PAT[7..0]
PCT[7..0]
PAT[7..0]
PCT[7..0]
PAT0
PAT1
PAT2
PAT3
PAT4
PAT5
PAT6
PAT7
A0
A1
A2
A3
A4
A5
A6
A7
PAT0
PAT1
PAT2
PAT3
PAT4
PAT5
PAT6
PAT7
PGT[4..0]
PGT[4..0]
PCT0
PCT1
PCT2
PCT3
PCT4
PCT5
PCT6
PCT7
A[7..0]
A[7..0]
GND
VTG
GND
PGT0
PGT1
VTG
PGT2
A16
PGT3
PGT4
TOSC1
TOSC2
TOSC1
TOSC2
PGT[4..0]
PGT[4..0]
1
6
2
7
3
8
4
9
5
10
11
J301
KF22-E-9-S-N
GND
GND
12
C305
100N_16V_X7R
12
C303
100N_16V_X7R
GNDGND
VTG
12
C304
100N_16V_X7R
1 2
C306
100N_16V_X7R
VTG
TXDRXD
RTSCTS
JS307JS305JS303JS301 JS302 JS304 JS306 JS308
A16
12
C301
100N_16V_X7R
GND
VTG
1 2
C307
100N_16V_X7R
GNDVTG
1 2
C302
100N_16V_X7R
GND
VTG
32kHz
1 2
R301
10K
1 2
R302
10K
1 2
R303
10K
1 2
R304
10K
1 2
R305
10K
1 2
R306
10K
1 2
R307
10K
1 2
R308
10K
1 2
R309
10K
12
R310
10K
1
23
4
XC301
RS232 SPARE2
1 2
3 4
J302
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
JP301
VTG
GND
GND
A15
31 A14
30 A13
29 A12
21 A11
20 A10
19 A9
18 A8
17 A7
16 A6
15 A5
14 A4
13 A3
4A2
3A1
2A0
1
A16
32
I/O0 6
I/O1 7
I/O2 10
I/O3 11
I/O4 22
I/O5 23
I/O6 26
I/O7 27
CE
5
WE
12 OE
28
VCC 8
VCC 24
GND 9
GND 25
U302
128Kx8 SRAM
SRAMEN
SRAMEN
GND
21
3
56
4
7
SW301
JS309
T1
R1
T2
R2
V+
2
14
13
7
8
V-
6
C1- 3
11
12
10
9
C2+ 4
C2- 5
C1+ 1
VCC 16
GND
15
U303
MAX3232ECAE
12
C308
10P_50V_NP0
1 2
R311
33R
GND
VTG
VTG
12
R312
10K
12
R313
10K
A8
A9
A10
A11
A12
A13
A14
A15
RAM HIGH
ADDRESS
A16
TOSC
Complete Schematics
AVR® STK501 User Guide 6-5
Figure 6-4. Assembly Drawing, 1 of 1
Complete Schematics
6-6 AVR® STK501 User Guide
© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
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