S5N8952X
ADSL Transceiver for NIC
Preliminary Information
(Revision 2.0)
September. 2000
SAMSUNG ELECTRONICS CONFIDENTIAL PROPRIETARY
Copyright ©1999-2000 Samsung Electronics, Inc. All Rights Reserved
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S5N8952X
ADSL Transceiver for NIC
Preliminary Information (Rev.2.0)
Contents
1. Features.......................................................................................................... 5
2. General Description........................................................................................... 5
3. Logical Symbol Diagram .................................................................................... 6
4. Pin Configuration.............................................................................................. 7
5. Pin Description................................................................................................. 8
6. Functional Description..................................................................................... 13
7. I/O Timing Description..................................................................................... 14
8. Electrical Characteristics.................................................................................. 16
9. Package Description........................................................................................ 17
3
S5N8952X
ADSL Transceiver for NIC
Preliminary Information (Rev.2.0)
List of Figures
Figure 1: General Block Diagram.........................................................................5
Figure 2: Logical Symbol Diagram of the S5N8952X.............................................6
Figure 3: Pin Configuration of the S5N8952X ......................................................7
Figure 4: Functional Block Diagram of the S5N8952X......................................... 13
Figure 5: AFE Data I/F Timing Diagram..............................................................14
Figure 6: AFE Control I/F Timing Diagram.......................................................... 14
Figure 7: PCI I/F Timing Diagram...................................................................... 15
Figure 8: 208-LQFP Package Diagram...............................................................17
4
S5N8952X
ADSL Transceiver for NIC
Preliminary Information (Rev.2.0)
List of Tables
Table 1: Pin Description of the S5N8952X ..........................................................8
Table 2: Absolute Maximum Ratings................................................................. 16
Table 3: Recommended Operating Conditions .................................................... 16
Table 4: Power Dissipation.............................................................................. 16
Table 5: DC Characteristics............................................................................. 16
5
S5N8952X
ADSL Transceiver for NIC
Preliminary Information (Rev.2.0)
1. Features
• Full Compliance with T1.413 Issue-2, ITU-T G.992.1 (G.dmt) and G.992.2 (G.lite).
• FDM and EC-based DMT Line Coding
• Data Rate: over 8Mbps for Downstream and 640 Kbps for Upstream.
• Reach: 6.7 Km (22Kft) with 24 AWG and 5.5 Km (18 Kft) with 26 AWG
• Supports Rate Adaptive Mode (steps of 32kbps)
• Reed-Solomon Forward Error Correction with(or without) Interleaver
• Adaptive Frequency and Time Domain Equalizer.
• Trellis Coding and Echo Cancellation.
• Supports Normal or Reduced Overhead Framing Modes
• Supports Analog and Digital PLL.
• Compatible to PCI V2.2
• Handle ATM Cells (On-Chip SAR and Connection Memory)
• Supports Fast Retraining Function in G.lite Mode
• Supports Network Management Function
• Supports Power Management Function
• 0.18µm, 1.8V CMOS Technology
• Operating Temperature: -40 °C to 85 °C
• Package Type: 208-LQFP
2. General Description
The S5N8952X is a complete ATM-based ADSL modem solution with associated F/W and
an Analog Front-End (S5N8951). The S5N8952X provides all the digital functions such as
PCI I/F, SAR, ATM framing, channel codec, DMT modulation, and DSP control.
There are two interfaces for external communications; PCI bus interface for NIC
applications and AD/DA interface. The S5N8952X is optimized for providing NIC solution
for CPE, and uses 17.664MHz Xtal oscillator as a master clock.
Figure 1: General Block Diagram
Phone
Line
DMT
Processor
ATM
Framer
Analog
Front-
End
Hybrid
Line
Driver
DSP
PCI
&
SAR
ROM
ROM
PCI_BUS
S5N8952
6
S5N8952X
ADSL Transceiver for NIC
Preliminary Information (Rev.2.0)
3. Logical Symbol Diagram
S5N8952X
RESET_N LD_TX_PWDN
XTAL_IN LD_RX_PWDN
XTAL_OUT
EXT_CLK AFE_RESET_N
PLL_FILT AFE_SDI
TEST_MODE[3:0] AFE_SDO
TEST_SCN_EN AFE_SCK
TEST_IN AFE_SEN_N
TEST_OUT AFE_BUSY
TX_SHOW AFE_PME
RX_SHOW AFE_NOISE
GP_OUT[1:0]
BT_MODE[1:0] AFE_DA_REF
NTR AFE_DA_CLK
AFE_DA_DAT[6:0]
PCI_AD[31:0] AFE_AD_REF
PCI_CBE_N[3:0] AFE_AD_CLK
PCI_FRAME_N AFE_AD_DAT[6:0]
PCI_IRDY_N
PCI_TRDY_N TL_TMS
PCI_DEVSEL_N TL_TCK
PCI_STOP_N TL_TDI
PCI_PERR_N TL_TDO
PCI_PAR TL_TINTP
PCI_GNT_N
PCI_PME_N
PCI_REQ_N
PCI_SERR_N
PCI_INTA_N
PCI_RST_N
PCI_CLK
PCI_IDSEL
EPROM_CS_N
EPROM_SI
EPROM_SO
EPROM_CK
PWR_ON
AUX_PWR_ON
Figure 2: Logical Symbol Diagram of the S5N8952X
7
S5N8952X
ADSL Transceiver for NIC
Preliminary Information (Rev.2.0)
4. Pin Configuration
Figure 3: Pin Configuration of the S5N8952X
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
S5N8952X
ADSL Transceiver for NIC
(208-LQFP)
TL_TMS
TL_TCK
VDD25
GND25
TL_TDI
TL_TDO
TL_TINTP
VDD24
GND24
LD_TX_PWDN
LD_RX_PWDN
TEST_IN
TEST_OUT
GND23
VDD23
GND22
PWR_ON
AUX_PWR_ON
GND21
VDD22
GND20
EPROM_CS_N
EPROM_SI
VDD21
GND19
EPROM_SO
EPROM_CK
VDD20
GND18
PCI_AD_0
PCI_AD_1
VDD19
GND17
PCI_AD_2
PCI_AD_3
GND16
VDD18
GND15
PCI_AD_4
PCI_AD_5
GND14
VDD17
GND13
PCI_AD_6
PCI_CBE_N_0
VDD16
PCI_AD_7
VDD15
GND12
PCI_AD_8
PCI_AD_9
PCI_AD_10
GP_OUT_0
GP_OUT_1
VDD34
GND38
NTR
VDD35
GND39
BT_MODE_0
BT_MODE_1
VDD36
GND40
XTAL_IN
XTAL_OUT
VDDA37
GNDA41
PLL_FILT
GNDA42
VDDA38
GNDA43
VDDA39
GNDA44
RESET_N
GND45
VDD40
GND46
TX_SHOW
RX_SHOW
VDD41
GND47
PCI_INTA_N
PCI_RST_N
VDD42
GND48
PCI_CLK
PCI_GNT_N
GND49
VDD43
GND50
PCI_REQ_N
PCI_PME_N
GND51
VDD44
GND52
PCI_AD_31
PCI_AD_30
VDD45
PCI_AD_29
PCI_AD_28
VDD46
GND53
PCI_AD_27
PCI_AD_26
PCI_AD_25
PCI_AD_24
VDD1
GND1
PCI_CBE_N_3
PCI_IDSEL
VDD2
GND2
PCI_AD_23
PCI_AD_22
VDD3
PCI_AD_21
PCI_AD_20
VDD4
GND3
PCI_AD_19
PCI_AD_18
VDD5
GND4
PCI_AD_17
PCI_AD_16
VDD6
PCI_CBE_N_2
GND5
VDD7
GND6
PCI_FRAME_N
VDD8
GND7
PCI_IRDY_N
VDD9
PCI_TRDY_N
PCI_DEVSEL_N
VDD10
GND8
PCI_STOP_N
PCI_PERR_N
VDD11
GND9
PCI_SERR_N
PCI_PAR
VDD12
PCI_CBE_N_1
PCI_AD_15
VDD13
GND10
PCI_AD_14
PCI_AD_13
VDD14
GND11
PCI_AD_12
PCI_AD_11
EXT_CLK
AFE_DA_CLK
VDD33
GND37
TEST_MODE_3
AFE_DA_REF
TEST_MODE_2
GND36
VDD32
GND35
TEST_MODE_1
AFE_DA_DAT_6
TEST_MODE_0
GND34
VDD31
GND33
AFE_DA_DAT_5
TEST_SCN_EN
VDD30
GND32
AFE_DA_DAT_4
AFE_AD_CLK
AFE_DA_DAT_3
VDD29
GND31
AFE_AD_REF
AFE_DA_DAT_2
AFE_AD_DAT_6
AFE_DA_DAT_1
VDD28
GND30
AFE_AD_DAT_5
AFE_AD_DAT_3
AFE_AD_DAT_4
GND29
VDD27
GND28
AFE_AD_DAT_1
AFE_DA_DAT_0
AFE_SDI
AFE_SDO
AFE_AD_DAT_2
AFE_RESET_N
AFE_AD_DAT_0
AFE_SCK
GND27
VDD26
GND26
AFE_BUSY
AFE_SEN_N
AFE_PME
AFE_NOISE
8
S5N8952X
ADSL Transceiver for NIC
Preliminary Information (Rev.2.0)
5. Pin Description
Table 1: Pin Description of the S5N8952X
No Name I/O Description
178 RESET_N ISystem master reset (Active low)
168 XTAL_IN I
169 XTAL_OUT OSystem master clock (17.664MHz)
156 EXT_CLK IExternal clock for test
(Float in normal mode)
172 PLL_FILT OPLL pump out
(A 320pF capacitor between the pin and GNDA)
152 TEST_MODE_3
150 TEST_MODE_2
146 TEST_MODE_1
144 TEST_MODE_0
IChip test mode
[0] Normal mode, [1-15] Test mode
139 TEST_SCN_EN IScan enable (Set to ‘0’ in normal mode)
93 TEST_IN ITest input (Float in normal mode)
92 TEST_OUT OTest output (Float in normal mode)
182 TX_SHOW OTx showtime indicator
(Active high. Connect to LED)
183 RX_SHOW ORx showtime indicator
(Active high. Connect to LED)
158 GP_OUT_1
157 GP_OUT_0 OGeneral purpose outputs
(Float if not needed)
165 BT_MODE_1
164 BT_MODE_0 IBoot mode
[0] Reset, [1] Boot from host
[2] Boot from JTAG, [3] Self-booting
161 NTR BATM network timing reference (8KHz. Float if not
needed)
200 PCI_AD_31
201 PCI_AD_30
203 PCI_AD_29
204 PCI_AD_28
207 PCI_AD_27
208 PCI_AD_26
1PCI_AD_25
2PCI_AD_24
9PCI_AD_23
10 PCI_AD_22
12 PCI_AD_21
13 PCI_AD_20
16 PCI_AD_19
17 PCI_AD_18
20 PCI_AD_17
21 PCI_AD_16
44 PCI_AD_15
47 PCI_AD_14
48 PCI_AD_13
BPCI address data [31:0]
9
S5N8952X
ADSL Transceiver for NIC
Preliminary Information (Rev.2.0)
51 PCI_AD_12
52 PCI_AD_11
53 PCI_AD_10
54 PCI_AD_9
55 PCI_AD_8
58 PCI_AD_7
61 PCI_AD_6
65 PCI_AD_5
66 PCI_AD_4
70 PCI_AD_3
71 PCI_AD_2
74 PCI_AD_1
75 PCI_AD_0
BPCI address data [31:0]
5PCI_CBE_N_3 B
23 PCI_CBE_N_2 B
43 PCI_CBE_N_1 B
60 PCI_CBE_N_0 B
PCI command byte enable [3:0]
27 PCI_FRAME_N BPCI frame
30 PCI_IRDY_N BPCI initiator ready
32 PCI_TRDY_N BPCI target ready
33 PCI_DEVSEL_N BPCI device select
36 PCI_STOP_N BPCI stop
37 PCI_PERR_N BPCI parity error
41 PCI_PAR BPCI parity bit
191 PCI_GNT_N IPCI grant
40 PCI_SERR_N OZ PCI system error
186 PCI_INTA_N OZ PCI interrupt A
196 PCI_PME_N OZ PCI power management event
195 PCI_REQ_N OZ PCI request
187 PCI_RST_N IPCI reset
190 PCI_CLK IPCI clock
6PCI_IDSEL IPCI initialization device select
79 EPROM_SO IEPROM scan out
82 EPROM_SI EPROM scan in
83 EPROM_CS_N EPROM chip select
78 EPROM_CK OEPROM clock
87 AUX_PWR_ON IAux power detected (Active high)
88 PWR_ON IMain power detected (Active high)
95 LD_TX_PWDN OTx line driver power-down (Active high)
94 LD_RX_PWDN ORx line driver power-down (Active high)
114 AFE_RESET_N OAFE reset (Active low)
117 AFE_SDI IAFE serial interface data in
116 AFE_SDO OAFE serial interface data out
112 AFE_SCK OAFE serial interface clock
107 AFE_SEN_N OAFE serial interface data enable (Active low)
108 AFE_BUSY IAFE serial interface busy (Active high. Float if not
10
S5N8952X
ADSL Transceiver for NIC
Preliminary Information (Rev.2.0)
needed)
106 AFE_PME IAFE power management event (Active high. Float if
not needed)
105 AFE_NOISE IAudible noise detection for power cutback (Active
high. Float if not needed)
155 AFE_DA_CLK ODAC sample reference 1 (8.832MHz)
151 AFE_DA_REF ODAC sample reference 0 (4.416MHz)
145 AFE_DA_DAT_6
140 AFE_DA_DAT_5
136 AFE_DA_DAT_4
134 AFE_DA_DAT_3
130 AFE_DA_DAT_2
128 AFE_DA_DAT_1
118 AFE_DA_DAT_0
ODAC data [6:0]
135 AFE_AD_CLK IADC sample reference 1 (Float in normal mode)
131 AFE_AD_REF IADC sample reference 0 (Float in normal mode)
129 AFE_AD_DAT_6
125 AFE_AD_DAT_5
123 AFE_AD_DAT_4
124 AFE_AD_DAT_3
115 AFE_AD_DAT_2
119 AFE_AD_DAT_1
113 AFE_AD_DAT_0
IADC Data [6:0]
104 TL_TMS IJTAG test mode select (Float in normal mode)
103 TL_TCK IJTAG test clock (Float in normal mode)
100 TL_TDI IJTAG test input data (Float in normal mode)
99 TL_TDO OZ JTAG test output data (Float in normal mode)
98 TL_TINTP OTJAM interrupt to host (Float in normal mode)
11 VDD3
22 VDD6
31 VDD9
42 VDD12
59 VDD16
77 VDD20
85 VDD22
97 VDD24
110 VDD26
127 VDD28
138 VDD30
148 VDD32
159 VDD34
162 VDD35
180 VDD40
202 VDD45
P1 1.8V supply voltage
3VDD1
14 VDD4
18 VDD5 P1 3.3V supply voltage
11
S5N8952X
ADSL Transceiver for NIC
Preliminary Information (Rev.2.0)
25 VDD7
34 VDD10
38 VDD11
49 VDD14
57 VDD15
63 VDD17
73 VDD19
81 VDD21
90 VDD23
102 VDD25
121 VDD27
133 VDD29
142 VDD31
154 VDD33
166 VDD36
184 VDD41
188 VDD42
198 VDD44
205 VDD46
P1 3.3V supply voltage
7VDD2
28 VDD8
45 VDD13
68 VDD18
193 VDD43
P1 3.3V or 5V supply voltage for PCI only
4GND1
8GND2
15 GND3
19 GND4
24 GND5
26 GND6
29 GND7
35 GND8
39 GND9
46 GND10
50 GND11
56 GND12
62 GND13
64 GND14
67 GND15
69 GND16
72 GND17
76 GND18
80 GND19
84 GND20
86 GND21
89 GND22
91 GND23
96 GND24
101 GND25
P0 Ground
12
S5N8952X
ADSL Transceiver for NIC
Preliminary Information (Rev.2.0)
109 GND26
111 GND27
120 GND28
122 GND29
126 GND30
132 GND31
137 GND32
141 GND33
143 GND34
147 GND35
149 GND36
153 GND37
160 GND38
163 GND39
167 GND40
179 GND45
181 GND46
185 GND47
189 GND48
192 GND49
194 GND50
197 GND51
199 GND52
206 GND53
P0 Ground
170 VDDA37
174 VDDA38
176 VDDA39 P1 1.8V analog supply voltage
171 GNDA41
173 GNDA42
175 GNDA43
177 GNDA44
P0 Analog ground
I = Input
O= Output
OZ = Tri-state output
B= Bi-direction
P1= Power
P0 = Ground
13
S5N8952X
ADSL Transceiver for NIC
Preliminary Information (Rev.2.0)
6. Functional Description
The ADSL modem for customer premises consists of two main chips; ADSL transceiver
chip (S5N8952) and analog front-end chip (S5N8951). The analog front-end provides an
analog interface with line drivers and hybrid components for connecting to the PSTN. The
ADSL Transceiver provides all the digital functions as depicted in Figure 4.
DMT inherently transmits an optimized time-variable spectrum. This spectrum is adjusted
according to the desired data rate and the transmission characteristics (transfer function
and noise spectrum) on each and every subchannel. For this, CO and CPE transmit 256
4kHz-wide tone downstream and upstream respectively to each other during initialization.
They measure the quality of each of these received tones and then decide whether a tone
has sufficient quality to be used for further transmission and, if so, how much data this
tone should carry relative to the other tones that are used. They inform the bit loading
informations to each other.
In FDM-based DMT (Discrete MultiTone) modulation, the frequency band, 0 to 1.104MHz,
is divided into 256 equi-spaced subchannels with 4.3125KHz tone spacing. The frequency
band, 26KHz (#6) to 134KHz (#31) is used for the upstream, and 142KHz (#33) to
1.1MHz (#255) for the downstream.
The S5N8952 provides PCI bus interface for NIC application and 14-bit AD/DA interface.
SAR (Segmentation and Reassembly) and ATM TC (Transmission Convergence) are
implemented for ATM cell handling and especially on-chip hardware SAR provides more
processing power by reducing the PCI bus traffic than the software SAR. Reed-Solomon
error correction with/without interleaver and Trellis coded modulation increase channel
noise immunity. Time/frequency-domain equalizers, echo canceller, and digital filters, of
which coefficients are adaptively updated according to the channel conditions, enhance
the performance of data recovery.
Figure 4: Functional Block Diagram of the S5N8952X
PCI
TEAKLITE
DSP
SAR ATM
TC
FRAMER/
RS CODEC
TCM/
VITERBI/
QAM CODEC
FFT/IFFT/
ROTER
TEQ/FEQ/
FILTER/
ECHO
PCI_BUS
RAM ROM
ANALOG
FRONT_END
HOST
I/F
14
S5N8952X
ADSL Transceiver for NIC
Preliminary Information (Rev.2.0)
7. I/O Timing Description
AFE_DA_CLK
(8.832MHz)
AFE_DA_REF
(4.416MHz)
AFE_DA_DAT
[6:0] [6:0] [13:7]
AFE_AD_DAT
[6:0] [6:0] [13:7]
Parameter Description Min Max Unit
t1AFE_DA_DAT setup to AFE_DA_CLK ↑15 ns
t2AFE_DA_DAT hold after AFE_DA_CLK ↑15 ns
t3AFE_AD_DAT setup to AFE_DA_CLK ↓30 ns
t4AFE_AD_DAT hold after AFE_DA_CLK ↓1ns
Figure 5: AFE Data I/F Timing Diagram
AFE_SEN_N
AFE_SCK
(1.104MHz)
AFE_SDO
AFE_SDI
Parameter Description Min Max Unit
t1AFE_SDI setup to AFE_SCK↑30 ns
t2AFE_SEN_N ↓ before AFE_SCK ↑30 ns
t3AFE_SEN_N ↑ from AFE_SCK ↑15 ns
Figure 6: AFE Control I/F Timing Diagram
CS1
CS0
A4
A0
RW
D15
D14
D0
D15
D14
D0
t
1
t
3
t
2
t
1
t
2
t
3
t
4
15
S5N8952X
ADSL Transceiver for NIC
Preliminary Information (Rev.2.0)
PCI_CLK
(33MHz)
Inputs
Outputs
Tri-state
Outputs
Parameter Description Min Max Unit
t1Input setup to PCI_CLK ↑3ns
t2Input hold after PCI_CLK ↑0ns
t3PCI_CLK period 30 ns
t4PCI_CLK low time 6ns
t5PCI_CLK high time 6ns
t6PCI_CLK ↑ to signal valid delay 1 6 ns
t7Float to active delay 1ns
t8Active to float delay 14 ns
Figure 7: PCI I/F Timing Diagram
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
16
S5N8952X
ADSL Transceiver for NIC
Preliminary Information (Rev.2.0)
8. Electrical Characteristics
Table 2: Absolute Maximum Ratings
Symbol Parameter Rating Unit
ILATCH Latch-up Current ±200 mA
TSTG Storage Temperature -65 to 150 °C
Table 3: Recommended Operating Conditions
Symbol Parameter Rating Unit
1.8V I/O 1.65 to 1.95
3.3V I/O 3.0 to 3.6
DC Supply Voltage 5V-tolerant I/O
(3.3V Interface) 3.0 to 3.6
VDD
Analog Core DC Supply
Voltage 1.8V Core 1.8±5%
V
TAOperating Temperature
(Ambient) Commercial 0 to 70 °C
Table 4: Power Dissipation
Symbol Parameter Min Typ Max Unit
PDPower Dissipation -0.3-W
Table 5: DC Characteristics
Symbol Parameters Min Typ Max Unit
VIH Input High Voltage 2.0 - -
VIL Input Low Voltage - - 0.8
VOH Output High Voltage 2.4 - -
VOL Output Low Voltage - - 0.4
VT Switching Threshold -1.4 -
VT+Schmitt Trigger, Positive-going
Threshold - - 2.0
VT- Schmitt Trigger, Negative-
going Threshold 0.8 - -
V
-10 -10
IIH Input High Current (VIN=VDD)10* 33* 60*
-10 -10
IIL Input Low Current (VIN=VSS)-60* -33* -10*
IOZ Tri-state Output Leakage
Current -10 -10
IDD Quiescent Supply Current - - 100
µA
CIN Input Capacitance - - 4
COUT Output Capacitance - - 4pF
NOTES:
* - input buffer with pull-up(VIN=VSS) or pull-down(VIN=VDD).
17
S5N8952X
ADSL Transceiver for NIC
Preliminary Information (Rev.2.0)
9. Package Description
Figure 8: 208-LQFP Package Diagram
0.08MAX
0.50
A: 30.00±0.30
B: 28.00±0.20
#1
#208
B
A
AB
(1.25)
0.20
1.40±0.10
1.60MAX
0.10MAX
0.50±0.20
0~8°
+0.10
−0.05
0.10±0.05
18
S5N8952X
ADSL Transceiver for NIC
Preliminary Information (Rev.2.0)
Revision History
Revision
No. Date Description
1.0 2000-09-15 First released.
1.1 2000-09-20 Pin configuration changed.
2.0 2000-11-15 T1.413 issue-2 added.
PCI version upgraded from 2.1 to 2.2
IMPORTANT NOTICE
The information furnished by Samsung Electronics in this document is belived to be
accurate and reliable. However, no resposibility is assumed by Samsung Electronics for its
use, nor for any infringements of patents or other rights of third parties resulting from its
use. No license is granted under any patents or patent rights of Samsung Electronics.
Samsung Electronics reserves the right to make changes to its products or to discontinue
any semiconductor product or service without notice, and advises its customers to obtain
the latest version of relevant information to verify, before placing orders, that the
information being relied on is current and complete.
For More Information
Tel: (82)-(31)-209-8301, Fax: (82)-(31)-209-8309
E-mail: kimil@sec.samsung.com
http://www.intl.samsungsemi.com