AT24C11-W2.7-11 - Atmel Corporation

Features

•Low Voltage and Standard Voltage Operation

– 2.7 (VCC = 2.7V to 5.5V)

– 1.8 (VCC = 1.8V to 5.5V)

•Internally Organized 128 x 8

•Two-wire Serial Interface

•Bidirectional Data Transfer Protocol

•400 kHz (1.8V) and 1 MHz (2.5V, 2.7V, 5V) Compatibility

•4-Byte Page Write Mode

•Self-Timed Write Cycle (5 ms max)

•High Reliability

– Endurance: 1 Million Write Cycles

– Data Retention: 100 Years

•Automotive Grade, Extended Temperature and Lead-Free/Halogen-Free

Devices Available

•8-lead PDIP, 8-lead JEDEC SOIC, 5-lead SOT23 and 8-lead TSSOP Packages

•Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers

•Access to One Additional Page Upon Request

Description

The AT24C11 provides 1024 bits of serial electrically erasable and programmable

read only memory (EEPROM) organized as 128 words of 8 bits each. The device is

optimized for use in many industrial and commercial applications where low power

and low voltage operation are essential. The AT24C11 is available in space saving

8-lead PDIP, 8-lead JEDEC SOIC, 5-lead SOT23 and 8-lead TSSOP packages and is

accessed via a two-wire serial interface. In addition, the entire family is available in

2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.

Table 0-1. Pin Configuration

Pin Name Function

NC No Connect

SDA Serial Data

SCL Serial Clock Input

TEST Test Input (GND or VCC)

Two-wire Serial

EEPROM

1K (128 x 8)

AT24C11

Note: Not recommended for new

design; please refer to

AT24C01B datasheet.

Rev. 3409G–SEEPR–8/07

8-lead PDIP

GND

VCC

TEST

SCL

SDA

8-lead SOIC

GND

VCC

TEST

SCL

SDA

8-lead TSSOP

GND

VCC

TEST

SCL

SDA

5-lead SOT23

SCL

GND

SDA

VCC

TEST

3409G–SEEPR–8/07

AT24C11

Figure 0-1. Block Diagram

1. Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM

device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain

driven and may be wire-ORed with any number of other open-drain or open collector devices.

Absolute Maximum Ratings*

Operating Temperature..................................–55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Storage Temperature .....................................–65°C to +150°C

Voltage on Any Pin

with Respect to Ground ....................................–1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

STA RT

STOP

LOGIC

VCC

GND

SCL

SDA

SERIAL

CONTROL

LOGIC

EN H.V. PUMP/TIMING

EEPROM

DATA RECOVERY

SERIAL MUX

X DEC

DOUT/ACK

LOGIC

COMP

LOAD INC

DATA WO RD

ADDR/COUNTER

Y DEC

R/W

DOUT

DIN

LOAD

DEVICE

ADDRESS

COMPARATOR

3409G–SEEPR–8/07

AT24C11

2. Memory Organization

AT24C11, 1K SERIAL EEPROM: Internally organized with 32 pages of 4 bytes each. The 1K

requires a 7-bit data word address for random word addressing. Access to one additional page

(33rd page) available upon request.

Note: 1. VIL min and VIH max are reference only and are not tested.

Table 2-1. Pin Capacitance

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.

Symbol Test Condition Max Units Condition

CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V

CIN Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V

Table 2-2. DC Characteristics

Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, VCC = +2.7V to +5.5V

(unless otherwise noted)

Symbol Parameter Test Condition Min Typ Max Units

VCC1 Supply Voltage 1.8 5.5 V

VCC2 Supply Voltage 2.5 5.5 V

VCC3 Supply Voltage 2.7 5.5 V

VCC4 Supply Voltage 4.5 5.5 V

ICC Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA

ICC Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA

ISB1 Standby Current VCC = 1.8V VIN = VCC or VSS 0.6 3.0 µA

ISB2 Standby Current VCC = 2.5V VIN = VCC or VSS 1.4 4.0 µA

ISB3 Standby Current VCC = 2.7V VIN = VCC or VSS 1.6 4.0 µA

ISB4 Standby Current VCC = 5.0V VIN = VCC or VSS 8.0 18.0 µA

ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA

ILO Output Leakage Current VOUT = VCC or VSS 0.05 3.0 µA

VIL Input Low Level(1) –0.6 VCC × 0.3 V

VIH Input High Level(1) VCC × 0.7 VCC + 0.5 V

VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V

VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V

3409G–SEEPR–8/07

AT24C11

Note: 1. This parameter is characterized and is not 100% tested.

Table 2-3. AC Characteristics

Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, VCC = +2.7V to +5.5V,

CL = 1 TTL Gate and 100 pF (unless otherwise noted)

Symbol Parameter

1.8V 2.7V, 2.5V, 5.0V

UnitsMin Max Min Max

fSCL Clock Frequency, SCL 400 1000 kHz

tLOW Clock Pulse Width Low 1.2 0.4 µs

tHIGH Clock Pulse Width High 0.6 0.4 µs

tAA Clock Low to Data Out Valid 0.1 0.9 0.05 0.55 µs

tBUF

Time the bus must be free before a new

transmission can start(1) 1.2 0.5 µs

tHD.STA Start Hold Time 0.6 0.25 µs

tSU.STA Start Set-up Time 0.6 0.6 µs

tHD.DAT Data In Hold Time 0 0 µs

tSU.DAT Data In Set-up Time 100 100 ns

tRInputs Rise Time(1) 0.3 0.3 µs

tFInputs Fall Time(1) 300 100 ns

tSU.STO Stop Set-up Time 0.6 0.25 µs

tDH Data Out Hold Time 50 50 ns

tWR Write Cycle Time 5 5 ms

Endurance(1) 5.0V, 25°C, Page Mode 1M 1M Write

Cycles

3409G–SEEPR–8/07

AT24C11

3. Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external

device. Data on the SDA pin may change only during SCL low time periods (see Figure 3-3 on

page 7). Data changes during SCL high periods will indicate a start or stop condition as defined

below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which

must precede any other command (see Figure 3-4 on page 7).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition which ter-

minates all communications. After a read sequence, the stop command will place the EEPROM

in a standby power mode (see Figure 3-4 on page 7).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the

EEPROM in 8-bit words. Any device on the system bus receiving data (when communicating

with the EEPROM) must pull the SDA bus low to acknowledge that it has successfully received

each word. This must happen during the ninth clock cycle after each word received and after all

other system devices have freed the SDA bus. The EEPROM will likewise acknowledge by pull-

ing SDA low after receiving each address or data word (see Figure 3-5 on page 7).

STANDBY MODE: The AT24C11 features a low power standby mode which is enabled: (a)

upon power-up and (b) after the receipt of the STOP bit and the completion of any internal

operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part

can be reset by following these steps:

(a) clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create

a start condition as SDA is high.

3409G–SEEPR–8/07

AT24C11

Figure 3-1. Bus Timing

SCL: Serial Clock, SDA: Serial Data I/O

Figure 3-2. Write Cycle Timing

SCL: Serial Clock, SDA: Serial Data I/O

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

SCL

SDA IN

SDA OUT

tHIGH

tLOW tLOW

tAA tDH tBUF

tSU.STO

tSU.DAT

tHD.DAT

tHD.STA

tSU.STA

twr(1)

STOP

CONDITION START

CONDITION

WORDn

ACK

8th BIT

3409G–SEEPR–8/07

AT24C11

Figure 3-3. Data Validity

Figure 3-4. Start and Stop Definition

Figure 3-5. Output Acknowledge

SDA

SCL

DATA STABLE DATA STABLE

DATA

CHANGE

SDA

SCL

STA RT STOP

SCL

DATA IN

DATA OUT

START ACKNOWLEDGE

3409G–SEEPR–8/07

AT24C11

4. Write Operations

BYTE WRITE: Following a start condition, a write operation requires a 7-bit data word address

and a low write bit. Upon receipt of this address, the EEPROM will again respond with a zero

and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM

will output a zero and the addressing device, such as a microcontroller, must terminate the write

sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle

to the nonvolatile memory. All inputs are disabled during this write cycle, tWR, and the EEPROM

will not respond until the write is complete (see Figure 5-1 on page 9).

PAGE WRITE: The AT24C11 is capable of a 4-byte page write.

A page write is initiated the same as a byte write but the microcontroller does not send a stop

condition after the first data word is clocked in. Instead, after the EEPROM acknowledges

receipt of the first data word, the microcontroller can transmit up to three more data words. The

EEPROM will respond with a zero after each data word received. The microcontroller must ter-

minate the page write sequence with a stop condition (see Figure 5-2 on page 9).

The data word address lower 2 bits are internally incremented following the receipt of each data

word. The higher five data word address bits are not incremented, retaining the memory page

row location. When the word address, internally generated, reaches the page boundary, the fol-

lowing byte is placed at the beginning of the same page. If more than four data words are

transmitted to the EEPROM, the data word address will “roll over” and previous data will be

overwritten. Access to 1 additional page is available upon request.

ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the

EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a

start condition followed by the device address word. The read/write bit is representative of the

operation desired. Only if the internal write cycle has completed will the EEPROM respond with

a zero allowing the read or write sequence to continue.

5. Read Operations

Read operations are initiated the same way as write operations with the exception that the

read/write select bit in the device address word is set to one. There are two read operations:

byte read and sequential read.

BYTE READ: A byte read is initiated with a start condition followed by a 7-bit data word address

and a high read bit. The AT24C11 will respond with an acknowledge and then serially output 8

data bits. The microcontroller does not respond with a zero but does generate a following stop

condition (see Figure 5-3 on page 9).

SEQUENTIAL READ: Sequential reads are initiated the same as a byte read. After the micro-

controller receives an 8-bit data word, it responds with an acknowledge. As long as the

EEPROM receives an acknowledge, it will continue to increment the data word address and

serially clock out sequential data words. When the memory address limit is reached, the data

word address will “roll over” and the sequential read will continue. The sequential read operation

is terminated when the microcontroller does not respond with an input zero but does generate a

following stop condition (see Figure 5-4 on page 9).

3409G–SEEPR–8/07

AT24C11

Figure 5-1. Byte Write

Figure 5-2. Page Write

Figure 5-3. Byte Read

Figure 5-4. Sequential Read

3409G–SEEPR–8/07

AT24C11

Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics

tables.

2. “U” designates Green package + RoHS compliant.

3. Die sales available in waffle pack and wafer form, order as SL719 for wafer form. Bumped die sales available upon request.

Please contact Serial EEPROM Marketing.

AT24C11 Ordering Information(1)

Ordering Code Package Operation Range

AT24C11-10PI-2.7

AT24C11N-10SI-2.7

AT24C11-10TI-2.7

8P3

8S1

8A2

Industrial Temperature

(–40°C to 85°C)

AT24C11-10PI-1.8

AT24C11N-10SI-1.8

AT24C11-10TI-1.8

8P3

8S1

8A2

Industrial Temperature

(–40°C to 85°C)

AT24C11-10PU-2.7(2)

AT24C11-10PU-1.8(2)

AT24C11N-10SU-2.7(2)

AT24C11N-10SU-1.8(2)

AT24C11-10TU-2.7(2)

AT24C11-10TU-1.8(2)

AT24C11-10TSU-1.8(2)

8P3

8S1

8A2

5TS1

Lead-free/Halogen-free/

Industrial Temperature

(–40°C to 85°C)

AT24C11-W2.7-11(3)

AT24C11-W1.8-11(3)

Die Sale

Industrial Temperature

(–40°C to 85°C)

Package Type

8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2 8-lead, 4.4 mm Body, Plastic, Thin Shrink Small Outline Package (TSSOP)

5TS1 5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)

Options

–2.7 Low-Voltage (2.7V to 5.5V)

–1.8 Low-Voltage (1.8V to 5.5V)

3409G–SEEPR–8/07

AT24C11

6. Packaging Information

8P3 – PDIP

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

8P3, 8-lead, 0.300" Wide Body, Plastic Dual

In-line Package (PDIP)

01/09/02

8P3B

A2 A

4 PLCS

Top View

Side View

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.

4. E and eA measured with the leads constrained to be perpendicular to datum.

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

A 0.210 2

A2 0.115 0.130 0.195

b 0.014 0.018 0.022 5

b2 0.045 0.060 0.070 6

b3 0.030 0.039 0.045 6

c 0.008 0.010 0.014

D 0.355 0.365 0.400 3

D1 0.005 3

E 0.300 0.310 0.325 4

E1 0.240 0.250 0.280 3

e 0.100 BSC

eA 0.300 BSC 4

L 0.115 0.130

3409G–SEEPR–8/07

AT24C11

8S1 – JEDEC SOIC

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TITLE DRAWING NO.

REV.

Note:

10/7/03

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing

Small Outline (JEDEC SOIC) 8S1 B

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A1 0.10 – 0.25

These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

A 1.35 – 1.75

b 0.31 – 0.51

C 0.17 – 0.25

D 4.80 – 5.00

E1 3.81 – 3.99

E 5.79 – 6.20

e 1.27 BSC

L 0.40 – 1.27

∅ 0˚ – 8˚

∅

Top View

End View

Side View

3409G–SEEPR–8/07

AT24C11

8A2 – TSSOP

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

5/30/02

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

D 2.90 3.00 3.10 2, 5

E 6.40 BSC

E1 4.30 4.40 4.50 3, 5

A – – 1.20

A2 0.80 1.00 1.05

b0.19 – 0.30 4

e 0.65 BSC

L 0.45 0.60 0.75

L1 1.00 REF

8A2, 8-lead, 4.4 mm Body, Plastic

Thin Shrink Small Outline Package (TSSOP)

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,

datums, etc.

2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed

0.15 mm (0.006 in) per side.

3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm

(0.010 in) per side.

4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the

b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between

protrusion and adjacent lead is 0.07 mm.

5. Dimension D and E1 to be determined at Datum Plane H.

8A2 B

Side View

End View

Top View

123

Pin 1 indicator

this corner

3409G–SEEPR–8/07

AT24C11

5TS1 – SOT23

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TITLE DRAWING NO.

REV.

PO5TS1

6/20/03

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

5TS1, 5-lead, 1.60 mm Body, Plastic Thin Shrink

Small Outline Package (SHRINK SOT)

A - - 1.10

0.00 - 0.10

0.70 0.90 1.00

c 0.08 - 0.20 3

D 2.90 BSC 1,2

E 2.80 BSC 1,2

1.60 BSC 1,2

0.60 REF

e 0.95 BSC

1.90 BSC

b 0.30 - 0.50 3,4

1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash,

protrusions or gate burrs shall not exceed 0.15 mm per end. Dimension E1 does

not include interlead flash or protrusion. Interlead flash or protrusion shall not

exceed 0.15 mm per side.

2. The package top may be smaller than the package bottom. Dimensions D and E1

are determined at the outermost extremes of the plastic body exclusive of mold

flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch

between the top and bottom of the plastic body.

3. These dimensions apply to the flat section of the lead between 0.08 mm and 0.15

mm from the lead tip.

4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion

shall be 0.08 mm total in excess of the "b" dimension at maximum material

condition. The dambar cannot be located on the lower radius of the foot. Minimum

space between protrusion and an adjacent lead shall not be less than 0.07 mm.

This drawing is for general information only. Refer to

JEDEC Drawing MO-193, Variation AB for additional

information.

END VIEW

PLANE

SEATING

SIDE VIEW

TOP VIEW

3409G–SEEPR–8/07

Headquarters International

Atmel Corporation

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San Jose, CA 95131

USA

Tel: 1(408) 441-0311

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Japan

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Fax: (81) 3-3523-7581

Product Contact

Web Site

www.atmel.com

Technical Support

s_eeprom@atmel.com

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www.atmel.com/contacts

Literature Requests

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