M29W200BB70N1 - STMicroelectronics

1/22July 2000

M29W200BT

M29W200BB

2 Mbit (256Kb x8 or 128Kb x16, Boot Block)

Low Voltage Single Supply Flash Me mory

■SI NGLE 2 .7 t o 3.6V SUPPL Y VOLT AG E f o r

PROGRAM, ERASE and R EAD O PER AT IONS

■ACCESS TIME: 5 5ns

■PRO GRAMMIN G TIME

– 10µs per Byte/Word typical

■7 MEMORY BLOCK S

– 1 Boot Block (Top or Bottom Locat ion)

– 2 Parameter and 4 Main Blocks

■PROGRAM/ERASE CON TROLLER

– Embedded Byt e/Word Program algorithm

– Embedded Multi-Block/Chip Erase algorithm

– Status Register Pol ling and Toggle Bits

– Ready/Busy Output Pin

■ERASE SUSPEND and RESUM E MOD ES

– Read and Program another Block during

Erase Su spend

■UNLOCK BYPASS PROGRAM COMM AND

– Fas ter Production/Batc h Prog ramm ing

■TEMPORARY BLOCK UNPROTECTION

MODE

■LOW POWER CONSUM PTION

– Standby and Autom atic Standby

■100,000 PROGRAM/ERASE CYCLES per

BLOCK

■20 YEAR S DATA RETENTION

– Defect ivity below 1 ppm/ year

■ELECTRONIC SIG NATURE

– Manufacturer Code: 0020h

– Top Device Code M29 W200B T : 0051h

– Bottom Device Code: M29W 200BB 0057h

TSOP48 (N)

12 x 20mm SO44 (M)

Figure 1. Logic Diagram

AI02948

A0-A16

DQ0-DQ14

VCC

M29W200BT

M29W200BB

VSS

DQ15A–1

BYTE

M29W200BT, M29W200BB

2/22

Figu re 2. TSOP C onnecti on s

DQ3

DQ9

DQ2

A6 DQ0

DQ6

A9 DQ13

A10 DQ14

DQ12

DQ10

DQ15A–1

VCC

DQ4

DQ5

DQ7

AI02944

M29W200BT

M29W200BB

24 25

DQ8

DQ1

DQ11

A12

A13

A16

A11

BYTE

A15

A14 VSS

VSS

Figu re 3. SO C onnecti on s

DQ0

DQ8

VSS

A13

VSS

A14

A15

DQ7

A12

A16

BYTE

DQ15A–1

DQ5DQ2

DQ3 VCC

DQ11 DQ4

DQ14

WRB

NC RP

AI02945

M29W200BT

M29W200BB

2322

17DQ1

DQ9

DQ6

DQ13

A11

A10

DQ10 21 DQ12

NC A8

Table 1. Sign al Names

A0-A16 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

DQ8-DQ14 Data Inputs/Outputs

DQ15A–1 Data Input/Output or Address Input

EChip Enable

GOutput Enable

WWrite Enable

RP Reset/Block Temporary Unprotect

RB Ready/Busy Output

BYTE Byte/Word Organization Select

VCC Supply Voltage

VSS Ground

NC Not Connected Internally

SUMMARY DESCRIPTION

The M29W200B is a 2 Mbit (256Kb x8 or 128Kb

x16) non- volatile memory that can be read, erased

and reprogrammed. These operations can be per-

formed using a single low voltage (2.7 to 3.6V)

supply. On power-up the memory defaults to its

Read mode where it can be read in the same way

as a ROM or EPROM. The M29W200B is fully

backward compatible with the M29W200.

The memory is divided into blocks that can be

erased independently so it is pos sible to preserv e

valid data while old dat a is erased. Each block can

be protected independently to prevent accidental

Program or Erase commands from modifying the

memory. P rogram and Eras e com m ands are wri t-

ten to the Com mand Interface of t he memory. An

on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by

taking care of al l of the special operations that are

required to update the mem ory con tents. The end

of a program or erase operation can be detected

and any error conditions identified. The c om m and

set required to control the memory is consistent

with JEDEC standards.

3/22

M29W200BT, M29W200BB

The blocks in the mem ory are asymmetrically ar-

ranged, see Tables 3 and 4, Block Addresses. The

first or last 64 Kbytes have been divide d into four

additional blocks. The 16 Kbyte Boot Bl ock can be

used for small initi alization code to start the micro-

processor, the two 8 Kbyte Parame ter Blocks can

be used for param eter storage and the rem aining

32K is a small Main Block where the application

may be stored.

Chip Enable, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic .

The memory is offered in TSOP48 (12 x 20mm)

and SO 44 packages and it is s uppl ied with all t he

bits erased (set to ’1’).

Table 2. Absolute M axim um Ratings (1)

Note: 1. Exc ept for th e ratin g "Oper ating T emperat ure Range", stres ses above th ose lis te d i n the T able "A bsolu te Maxim um Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above thos e indicated in t he Op erating sect i ons of this specification is not i m plied. Ex posure to A bsol ut e M aximum R ating condi -

tions for extended pe riods may aff ect device reliabilit y. Refer also to the STMic ro electronics SURE Program and other r elevant qual-

i ty do cu m ent s .

2. Mini m um Voltage may undershoo t t o –2V during transiti on and for less tha n 20ns duri ng trans i tions.

Symbol Parameter Value Unit

TAAmbient Operating Temperature (Temperature Range Option 1) 0 to 70 °C

Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C

TBIAS Temperature Under Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO (2) Input or Output Volta ge –0.6 to 4 V

VCC Supply Vo ltage –0.6 to 4 V

VID Identification Voltage –0.6 to 13.5 V

Table 3. Top Boot Block Addresses

M29W200BT

#Size

(Kbytes) Address Rang e

(x8) Address Range

(x16)

6 16 3C000h-3FFFFh 1E000h-1FFFFh

5 8 3A000h-3BFFFh 1D000h-1DFFFh

4 8 38000h-39FFFh 1C000h-1CFFFh

3 32 30000h-37FFFh 18000h-1BFFFh

2 64 20000h-2FFFFh 10000h-17FFFh

1 64 10000h-1FFFFh 08000h-0FFFFh

0 64 00000h-0FFFFh 00000h-07FFFh

Table 4. Bottom Boot Block Addresses

M29W200BB

#Size

(Kbytes) Address Rang e

(x8) Address Range

(x16)

6 64 30000h-3FFFFh 18000h-1FFFFh

5 64 20000h-2FFFFh 10000h-17FFFh

4 64 10000h-1FFFFh 08000h-0FFFFh

3 32 08000h-0FFFFh 04000h-07FFFh

2 8 06000h-07FFFh 03000h-03FFFh

1 8 04000h-05FFFh 02000h-02FFFh

0 16 00000h-03FFFh 00000h-01FFFh

M29W200BT, M29W200BB

4/22

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diag ram, and T able 1, Sign al

Names, for a brief overview of the s ignals connect -

ed to this device.

Address Inputs (A0-A16). The Address Inputs

select the cell s in the memory arra y to access dur-

ing Bus Read operations. During Bus Writ e opera-

tions they control the commands sent to the

Comman d Interface of the internal stat e ma chine.

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation. During Bus

Write operations they represent the commands

sent to the Command Interface of the internal state

machine.

Data Inputs/Output s (DQ8-DQ14). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operati on when BYTE

is High, VIH. When BYTE is Low, VIL, these pins

are not used and are high impedance. During Bus

Write operations the Command Register does not

use these bit s. When reading t he Status Register

these bits should be ignored.

Data Input/Output or Address Input (D Q15A-1).

When BYTE is High, VIH, this pin behaves as a

Data Input/Output pin (as DQ8-DQ14). When

BYTE is Low, VIL, this pin behav es as an address

pin; DQ15A–1 Low wil l select t he LSB of the Word

on the other addresses, DQ15A–1 High will select

the MSB. Throughout the t ext consider references

to the Data Input/Output to include this pin when

BYTE is High and references to the Address In-

puts to inc lude this pin when BYTE is Low except

when stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates

the memor y, allowing Bus Read and Bus Wr ite op-

erations to be performed. When Chip Enable is

High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

ma nd Inte r face.

Reset /Bl ock T emporar y Unpr otect (RP). The Re-

set/Block Temporary Unprotect pin can be used to

apply a Hardware Reset to the memory or to tem-

porarily unprotect all Blocks that have been pro-

tected.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, VIL, for at least

tPLPX. After Reset/Block Temporary Unprotect

goes High, V IH, the memory will be read y for Bus

Read and Bus Write operations after tPHEL or

tRHEL, whichever occurs last. See the Ready/ Busy

Output section, Table 17 and Figure 11, Reset/

Temporary Unprot ect AC Characte ristics for more

details.

Holding RP at VID will temporarily unprotect the

protected Blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from VIH to VID must be slower than

tPHPHH.

Ready/Busy Output (RB). The Ready/Busy pin

is an open-drain output that can be used to identify

when the memory array can be read . Ready/Busy

is high-impedance during Read mode, Auto Select

mode and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be-

comes h igh-impeda nc e. See Tabl e 17 and Figure

11, Reset/Temporary Unprotect AC Characteris-

tics.

During Program or Erase operations Ready/Busy

is Low, VOL. Ready/Busy will remain Low during

Read/Reset c ommands or Hardw are Rese ts until

the memory is ready to enter Read mode.

The use of an open-drain output allows the Ready /

Busy pins from several memor ies to be connected

to a single pull-up resistor. A Low will then indicate

that one, or more, of the memories is busy.

Byte /Wor d Orga niz ation Sele ct (BYTE). The Byte/

Word Organization S elect pin is used to switch be-

tween the 8-bit and 16-bit Bus modes of the mem-

ory. When B yte/Word Organiz ation Select is Low,

VIL, the m emory is in 8-bi t mode, w hen it is High,

VIH, the memory is in 16-bit mode.

VCC Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Pro-

gram, Erase etc.).

The Command Interface is dis abled when the VCC

Supply Voltage is less than the Lockout Voltage,

VLKO. This prevent s Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being alt ered will be invalid.

A 0.1µF capacitor should be connected between

the V CC Supply Voltage pin and the VSS Ground

pin to decoupl e the current surges from the power

supply. The PCB track widths must be sufficient to

carry the currents required during program and

erase operat ions, ICC3.

VSS Ground. The VSS Ground is the reference for

all voltage measureme nts.

5/22

M29W200BT, M29W200BB

Table 5. Bus Operations, BYTE = VIL

No te: X = VIL or VIH.

Table 6. Bus Operations, BYTE = VIH

No te: X = VIL or VIH.

Operation E G W Address Inputs

DQ15A–1, A0-A16 Data Inputs/Outputs

DQ14-DQ8 DQ7-DQ0

Bus Read VIL VIL VIH Cell Address Hi-Z Data Output

Bus Write VIL VIH VIL Command Address Hi-Z Data Input

Output Disable X VIH VIH X Hi-Z Hi-Z

Standby VIH X X X Hi-Z Hi-Z

Read Manufacturer

Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or VIH Hi-Z 20h

Read Device Code VIL VIL VIH A0 = V IH, A1 = VIL, A9 = V ID,

Others VIL or VIH Hi-Z 51h (M29W200BT)

57h (M29W200BB)

Operation E G W Address Inputs

A0-A16 Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Bus Read VIL VIL VIH Cell Address Data Output

Bus Write VIL VIH VIL Command Address Data Input

Output Disable X VIH VIH X Hi-Z

Standby VIH X X X Hi-Z

Read Manufacturer

Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or VIH 0020h

Read Device Code VIL VIL VIH A0 = V IH, A1 = VIL, A9 = V ID,

Others VIL or VIH 0051h (M29W200BT)

0057h (M29W200BB)

BUS OPERATIONS

There are five standard bus operations that control

the device. These are Bus Read, Bus Wri te, Out-

put Disable, Standby and Automatic Standby. See

Tables 5 and 6, Bus Operations, for a summary.

Typically glitches of less than 5ns on Chi p Enable

or Wri te Enable are ignored by t he memory and do

not affec t bus operations.

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desi red address on the Address

Inputs, appl ying a Low s ig nal, VIL, to Chip Enab le

and Output Enable and keeping Write Enable

High, VIH. The Data Input s/Ou tputs will outp ut the

value, see Figure 8, Read Mode AC Waveforms,

and Table 14, Read AC Characteristics, for details

of when the output becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desire d address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Dat a Input s/Outpu ts a re latched by the Com -

mand Interface on the rising edge of Chip Ena ble

or Write Enable, whichever occurs first. Output En-

able must remai n High, VIH, during the whole Bus

Write operation. See Figures 9 and 10, Write AC

Waveforms, and Tables 15 and 16, Write AC

Characteristics, for details of the timing require-

ments.

Outp ut Disable . The Data Inputs/Outputs are in

the high impeda nce state when Output Enable is

High, VIH.

Standby. When Chip Enable is High, VIH, the

memory enters Standby mode and the Data In-

puts/Outputs pins are placed in the high-imped-

ance state. To reduce the Supply Current to the

Standby Supply Current, ICC2, Chip Enable should

be held within VCC ± 0.2V. For t he Standby current

level see Table 13, DC Characteristics.

During program or erase operations the memory

will continue to use the Program/Erase Supply

Current, ICC3, for Program or Erase operations un-

til t he operat ion com pletes.

M29W200BT, M29W200BB

6/22

Automatic Standby. If CMOS levels (VCC ± 0.2V)

are used to drive the bus and the bus is inactive for

150ns or more the memory enters Automatic

Standby where the internal Supply Current is re-

duced to the Standby Supply Current, ICC2. The

Data Inputs/Outputs will still output data if a Bus

Read operation is in progress.

Special Bus Operati ons

Additional bus operations can be performed to

read the Electronic Signature and also to apply

and remove Block Protection. These bus opera-

tions are intended for use by programming equip-

ment and are not usually used in applications.

They require VID to be applied to some pins.

Electronic Sign ature . The memory has two

codes, the manufacturer code and the device

code, that can be read to identify the memory.

These co des can be re ad by app lying the si gnals

listed in Tables 5 and 6, Bus Operations.

Block Protection and Blocks Unprotection. Each

block can be separately protected against acci-

dental Program or Erase. Protected blocks can be

unprotected to allow data to be changed.

There are two methods available for protecting

and unprotecting the blocks, one for use on pro-

gramming equipment and the other for in-system

use. For further information refer to Application

Note AN1122, Applying P rotection and Unp rotec-

tion to M29 Series Flash.

COMMAND INTERFACE

All Bus Write operations t o the memory are in ter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. Failure to observe a vali d sequence of Bus

Write operations will result in the memory return-

ing to Read mode. The long command sequences

are imposed to maximize data security.

The address used for the commands changes de-

pending on whether the mem ory is in 16-bit or 8-

bit mode. See e ither Table 7, or 8, depending on

the configuration that is being used, for a summary

of the c om m ands.

Read/Reset Comm and. The Read/Reset com-

mand returns the memory to its Read mode where

it behaves like a ROM or EPROM. It also resets

the errors in the Status Register. Either one or

three Bus Write operations can be used to issue

the Read/ Reset c ommand.

If the Read/Reset command is issued during a

Block Erase operation or following a Programming

or Erase error then the memory will take up to 10µs

to abort. During th e abort period no valid data can

be read from the memory. Issuing a Read/Reset

command during a Block Erase operation will

leave invalid data in the memory.

Auto Select Command. The Auto Select com-

mand i s us ed to read the Man ufacturer Code, the

Device Code and the Block Protection Status.

Three consecutive Bus Write operations are re-

quired to issue the Auto Select command. Once

the Auto Select command is issued the memory

remains in Auto Select mode until another com-

mand is issued.

From the Auto Select mode the Manufacturer

Code can be read using a Bus Read operation

with A 0 = VIL and A1 = VIL. The other address bits

may be set to either VIL or VIH. T he Ma nufa cturer

Code for STMicroelectronics is 0020h.

The Device Code can b e read using a Bus Read

operation with A0 = VIH and A1 = VIL. The other

address bits may be set to either V IL or VIH. The

Device Code for the M29W200BT is 0051h and for

the M29W200B B is 0057h.

Th e Bloc k Protecti on Status of each block can b e

read using a Bus Read operation with A0 = VIL,

A1 = VIH, and A 12-A1 6 s p ecifyi ng th e addr ess of

th e block. The oth er address bits may be set to ei-

ther VIL or VIH. If th e addr ess ed bloc k is p rot ecte d

then 01h is output on Data Inputs/Outputs DQ0-

DQ7, otherwise 00h is output.

Progra m Command . The Program command

can be used to program a value to one address in

the memory array at a time. The command re-

quires four Bus Write operations, the final write op-

eration latches the address and data in the internal

state machine and starts the Program/Erase Con-

troller.

If the address falls in a protected block then the

Program command is ignored, the data remains

unchanged. The Status Register is never read and

no error condition is given.

During the program operation the me mory will ig-

nore all co mmands. I t is not poss ible t o issue any

command to abort or pause the operation. Typical

program times are given in Table 9. Bus Read op-

erations during the program operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the program operation has completed the

memory will return to the Read mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be i ssued to re-

set the error condition and return to Read mode.

Note that t he Program command cannot change a

bit set at ’0’ back to ’1’. One of the Erase Com-

mands must be used to set all the bits in a block or

in the whole memory from ’0’ to ’1’.

7/22

M29W200BT, M29W200BB

Table 7. Commands, 16- bit mode, BYTE = VIH

Table 8. Commands, 8-bi t mode, BYTE = VIL

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.

All values in the table are in hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A16, DQ8-DQ14 and DQ15 are Don’t Care.

DQ15A–1 is A–1 when BYT E is V IL or DQ1 5 when BY T E is VIH.

Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.

Auto Select. After an Aut o Select com m and, read Man ufactu rer ID, Device ID o r B l ock Protec tion St atus.

Pro gr am, Unl ock Bypass Progr am, Chi p E r ase, Bl o ck E r ase. Aft er thes e commands read th e Status Register until t he Pro gram/Erase

Co nt rol l er com p l et es a nd the memory returns to Read Mode. Add addi tional B l ocks dur in g Block E rase Com mand wi t h additional Bus Write

Ope ration s until Timeout Bit is set.

Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.

Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.

Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands

on non-era sing bloc ks as nor m al .

Erase Resume. A fte r th e Er as e Res ume com man d th e sus pe nded Eras e o perat ion re sumes , re ad the Stat us R egi ster unt il t he Prog ram/

Eras e Controller completes and the mem ory returns to Read Mode.

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1X F0

3 555 AA 2AA 55 X F0

Auto Select 3 555 AA 2AA 55 555 90

Program 4 555 AA 2AA 55 555 A0 PA PD

Unlock Bypass 3 555 AA 2AA 55 555 20

Unlock Bypass

Program 2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1X F0

3 AAA AA 555 55 X F0

Auto Select 3 AAA AA 555 55 AAA 90

Program 4 AAA AA 555 55 AAA A0 PA PD

Unlock Bypass 3 AAA AA 555 55 AAA 20

Unlock Bypass

Program 2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

M29W200BT, M29W200BB

8/22

Unlock Bypass Comman d. The Unlock Bypass

command is used in conjunction with the Unlock

Bypass Program c ommand to program the memo-

ry. When the access time to the device is long (as

with some EPROM programmers) considerable

time saving can be made by using these com-

mands. Three Bus Write operations are required

to issue the Unlock Bypass comm and.

Once the Unlock Bypass command has been is-

sued the memory will only accept the Unlock By-

pass Program command and the Unlock Bypass

Reset command. The memory can be read as i f in

Read mode.

Unlock Bypass Prog ram Comm an d. The Un-

lock Bypass Program command can be used to

program one address in memory at a time. The

command requires two Bus Write ope ra tions, the

final write operation latches the address and data

in the internal state machine and starts the Pro-

gram/Erase Controller.

The Program operation using the Unlock Bypass

Program c ommand behaves identically to the Pro-

gram operation using the Program command. A

protected block cannot be program m ed; the oper-

ation cannot be aborted and the Status Register is

read. Errors must be reset using the Read/Reset

command, w hich l eaves the de vice in Unlo ck By-

pass Mode. See the Program command for details

on the behavior.

Unlock Bypass Reset Comman d. The Unlock

Bypass Re se t comm and can be used t o return to

Read/Reset mode from Unlock Bypass Mode.

Two Bus Write operations are required to issue the

Unlo ck Bypa ss Reset command.

Chip Erase Command. The Chip Erase com-

mand can be used to erase the entire chip. Six Bus

Write operations are required to issue the Chip

Erase Command and start the Program/Erase

Controller.

If any blocks are protected then these are ignored

and all the other blocks are erased. If all of the

blocks a re p rote cted the Chi p Era se o perat i on ap-

pears to start but will terminate within about 100µs,

leaving the data unchange d. No error condit ion is

given when protected blocks are ignored.

During the erase operation the memory wi ll ignore

all commands. It is not possible to issue any com-

mand to abort the operation. Typical chip erase

times are given in Table 9. All Bus Read opera-

tions during the Chip Erase operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the Chip Erase operation has com pleted t he

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be i ssued to re-

set the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in un-

protected blocks of the memory to ’1’. All previous

data is lost.

Block Erase Command. The Block Erase com-

mand can be used to erase a list of one or more

blocks. Six Bus Write operations are required to

select the first block in the list. Each additional

block in the list can be selected by repeating the

sixth Bus Wr ite operation using the addres s of the

additional block. The Bl ock Erase operation st arts

the Program/Erase Controller about 50µs after the

last Bus Write operation. Once the Program/Erase

Controller starts it is not possible to select any

more blocks. Each additional block must therefore

be selected within 50µs of the last block. The 50µs

timer r estarts when an additional block is select ed.

The Status Register can be read after the sixth

Bus Write operation. See the Status Register for

details on how to identify if the Program/Erase

Controller has started the Block Erase operation.

If any selected blocks are protected then these are

ignored and all the other selected blocks are

erased. If all of the selected blocks are pro tected

the Block Erase operation appears to s tart but will

terminate within about 100µs, l eaving the data un-

changed. No error condition is given when protect-

ed blocks are ignored.

During the Blo ck Erase ope ra tion the me mory will

ignore all commands except the Erase Suspend

and Read/Reset commands. Typical block erase

times are given in Table 9. All Bus Read opera-

tions du ring the Blo ck Er ase operation will ou tput

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the Block Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be i ssued to re-

set the error condition and return to Read mode.

The Block Erase Command sets all of the bits in

the unprotected selec ted blocks to ’1’. All previous

data in the selected blocks is lost.

9/22

M29W200BT, M29W200BB

Erase Suspend Comm and. The Erase Suspend

Comman d m ay be used to temporarily suspend a

Block Erase operation and return the memory to

Read mode. The command requires one Bus

Write operation.

The Prog ram/Eras e Controlle r will sus pend within

15µs of the Erase Suspend Command being is-

sued. Once the Program/Erase Controller has

stopped the memory will be set t o Read mode and

the Erase will be suspended. If the Erase Suspend

command is issued during the period when the

memory is waiting for an additional block (before

the Program/Erase Controller starts) then the

Erase is susp ended i mmedi ately and wi ll start im-

mediately when the Erase Resume Command is

issued. It will not be possible to select any further

blocks fo r er asur e aft er the Erase Resume.

During Erase Suspend it is p ossi ble to Read and

Program cells in blocks that are not being erased;

both Read and Program operations behave as

normal on these bl ocks. Read ing from b locks that

are being erased will output the Status Register. It

is also possible to enter the Auto Select mode: the

memory will behave as in the Auto Select mode on

all blocks until a Read/Reset command returns the

memory to Erase Suspen d mode.

Erase Resum e Command. The Erase Resume

command must be used to restart the Program/

Erase Controller from Erase Suspend. An erase

can be suspended and resumed more than once.

Table 9. Pro gra m , Erase Times and Progra m , Erase Enduran ce Cycle s

(TA = 0 to 70°C or –40 to 85°C)

Note: 1. TA = 25°C, VCC = 3.3V.

Parameter Min Typ (1) Typical after

100k W/E Cycles (1) Max Unit

Chip Erase (All bits in the memory set to ‘0’) 1.3 1.3 sec

Chip Erase 3 3 18 sec

Block Erase (64 Kbytes) 0.8 0.8 6 sec

Program (Byte or Word) 10 10 200 µs

Chip Program (Byte by Byte) 2.8 2.8 15 sec

Chip Program (Word by Word) 1.4 1.4 8 sec

Program/Erase Cycles (per Block) 100,000 cycles

M29W200BT, M29W200BB

10/22

STATUS REGIST ER

Bus Read operations from any address always

read the Status Register during Program and

Erase operations. It is also read during Erase Sus-

pend when an address within a block being erased

is acce ssed .

The bits in the Status Register are s um marized in

Table 10, Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can

be used to identify whether the Program/Erase

Controller has successfully completed its opera-

tion or if it has responded to an Erase Suspend.

The Data Polling Bit is output on DQ7 when the

Status Register is read.

During Program operations the Data Polling Bit

outputs the complement of the bit being pro-

grammed to DQ7. After successful completion of

the Program operation the memory returns to

Read mode and Bus Read oper ations from t he ad-

dress just programmed output DQ7, not its com-

plement.

During Erase ope rations the Data Po lling Bit out-

puts ’0’, the complement of the erased state of

DQ7. Aft er s uc cessful completion of the Erase op-

eration the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will

output a ’1’ during a Bus Read operation within a

block being erased. The Data Polling Bit will

change f rom a ’0’ to a ’1’ when the Program/Erase

Controller has suspe nded the Erase operat ion.

Figure 4, Data Polling Flowchart, gives an exam-

ple of how to use the Data Polling Bit. A V alid Ad-

dress is the address being programmed or an

address within the block being erased.

Toggle Bit (DQ6). The Toggle Bit c an be used to

identify whether the Program/Erase Controller has

successfully completed its operation or if it has re-

sponded to an Erase Suspend. The Toggle Bit is

output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle

Bit changes f rom ’0 ’ to ’ 1’ to ’ 0’, et c., with succes-

sive Bus Read operations at any address. After

successful completion of the operation the memo-

ry returns to Read mode.

During Erase Suspend mode the Toggle Bit will

output when addressing a cell within a block being

erased. The Toggle Bit will stop toggling when the

Program/Erase Controller has suspended the

Erase operation.

Figure 5 , Data Toggle Flowchart, g ives an exam-

ple of how to use the Data Toggle Bit .

Error Bit (DQ5). The Error Bit can be used to

identify errors detected by the Program/Erase

Controller. The Erro r Bit is set to ’1’ wh en a Pro-

gram, Block Erase or Chip Erase operation fails to

write the correct data to the memory. If the Error

Bit is set a Rea d/Re se t comm and must be iss ued

before other command s a re issued. The Error bit

is output on DQ5 when the Status Register is read.

Note that t he Program command cannot change a

bit set at ’0’ back to ’1’ and attempting to do so may

or may not set DQ5 at ’1’. In both cases, a s uc ces-

sive Bus Read operation will show the bit is st ill ’0’.

One of the Erase comm ands must be used to set

all the bits in a blo ck or in the whole memory from

’0’ to ’1’.

Table 10. Status Register Bits

No te : Unspeci f i ed data bi ts should be ignored.

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB

Program Any Address DQ7 Toggle 0 ––0

Program During Erase

Suspend Any Address DQ7 Toggle 0 – – 0

Program Error Any Address DQ7 Toggle 1 – – 0

Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before

timeout Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Block Erase Erasing Block 0 Toggle 0 1 Toggle 0

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erase Suspend Erasing Block 1 No Toggle 0 – Toggle 1

Non-Erasing Block Data read as normal 1

Erase Error Good Block Address 0 Toggle 1 1 No Toggle 0

Faulty Block Address 0 Toggle 1 1 Toggle 0

11/22

M29W200BT, M29W200BB

Figu re 4. Da ta Po lli ng Fl owch a rt

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

at VALID ADDRESS

FAIL PASS

AI03598

DQ7

DATA YES

YES

DQ5

= 1

DQ7

DATA YES

Figu re 5. Da ta To ggl e Fl owchar t

READ DQ6

START

READ DQ6

TWICE

FAIL PASS

AI01370B

DQ6

TOGGLE NO

YES

DQ5

= 1

YES

DQ6

TOGGLE

READ

DQ5 & DQ6

Erase Timer Bit (DQ3). The Erase Timer Bit can

be used to identify the start of Program/Erase

Controller operation during a Block Erase com-

mand. Once the Program/Erase Controller starts

erasing the Erase Ti mer Bit is set to ’1’. Before the

Program/Erase Controller starts the Erase Timer

Bit is set to ’0’ and additional block s to b e erased

may be written to the Command Interface. The

Erase Timer Bit is output on DQ3 when the Status

Alternative Toggle Bit (DQ2). The Alternative

Toggle Bit can be used to monitor the Program/

Erase controller during Erase operations. The Al-

ternative Toggle Bit is output on DQ2 when the

Status Register is read.

During Chip Erase and Block Erase operations the

Toggle Bit changes fro m ’0’ to ’1’ to ’0’, etc., with

successive Bus Re ad operations from addresses

withi n the blocks being erased. Once the operation

completes the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive

Bus Read operations from addresses within the

blocks being erased. Bus Read operations to ad-

dresses within blocks not being erased will ou tput

the memory cell data as i f in Read mode.

After an Erase operation that c auses t he Error Bit

to be set the Alternative Toggle Bit can be used to

identify which block or bl ocks have caused t he er-

ror. The Altern ative Toggle Bit changes from ’0’ t o

’1’ to ’0’, etc. with successive Bus Read Opera-

tions from addresses within blocks that have not

erased correctly. The Alternative Toggle Bit does

not change if the addressed block has erased cor-

rectly.

M29W200BT, M29W200BB

12/22

Figure 6. AC Testing Input Output Waveform

AI01417

1.5V

Fi gure 7. AC Testing Load Circuit

AI02762

0.8V

OUT

CL = 30pF or 100pF

CL includes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

Table 12. Capacitance

(TA = 25 °C, f = 1 MHz)

No te : Sam pled only, not 100% tested .

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN = 0V 6pF

OUT Output Capacitance VOUT = 0V 12 pF

Table 11. AC Measurement Conditions

Parameter M29W200B

55 70 90 / 120

VCC Supply Voltage 3.0 to 3.6V 2.7 to 3.6V 2.7 to 3.6V

Load Capacitance (CL)30pF 30pF 100pF

Input Rise and Fall Times ≤ 10ns ≤ 10ns ≤ 10ns

Input Pulse Voltages 0 to 3V 0 to 3V 0 to 3V

Input and Output Timing Ref. Voltages 1.5V 1.5V 1.5V

13/22

M29W200BT, M29W200BB

Table 13. DC Characteristics

(TA = 0 to 70°C or –40 to 85°C)

Not e: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Current (Read) E = VIL, G = VIH, f = 6MHz 10 mA

ICC2 Supply Current (Standby) E = VCC ± 0.2V 100 µA

ICC3 (1) Supply Current (Program/Erase) Program/Erase

Controller active 20 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7VCC VCC + 0.3 V

VOL Output Low Voltage IOL = 1.8mA 0.45 V

VOH Output High Voltage IOH = –100µAVCC – 0.4 V

VID Identification Voltage 11.5 12.5 V

IID Identification Current A9 = VID 100 µA

VLKO (1) Program/Erase Lockout Supply

Voltage 1.8 2.3 V

M29W200BT, M29W200BB

14/22

Figure 8. Read Mode AC Waveforms

AI02915

tAVAV

tAVQV tAXQX

tELQX tEHQZ

tGLQV

tGLQX tGHQX

VALID

A0-A16/

A–1

DQ0-DQ7/

DQ8-DQ15

tELQV tEHQX

tGHQZ

VALID

tBHQV

tELBL/tELBH tBLQZ

BYTE

Table 14. Read AC Characteristi cs

(TA = 0 to 70°C or –40 to 85°C)

Not e: 1. Sampled only, not 100% tested.

Symbol Alt Parameter Test Condition M29W200B Unit

55 70 90 / 120

tAVAV tRC Address Valid to Next Address V alid E = VIL,

G = VIL Min 55 70 90 ns

tAVQV tACC Address Valid to Output Valid E = VIL,

G = VIL Max 55 70 90 ns

tELQX (1) tLZ Chip Enable Low to Output

Transition G = VIL Min 0 0 0 ns

tELQV tCE Chip Enable Low to Output Valid G = VIL Max 55 70 90 ns

tGLQX (1) tOLZ Output Enable Low to Output

Transition E = VIL Min 0 0 0 ns

tGLQV tOE Output Enable Low to Output Valid E = VIL Max 30 30 35 ns

tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 20 25 30 ns

tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 20 25 30 ns

tEHQX

tGHQX

tAXQX tOH Chip Enable, Output Enable or

Address Transition to Output

Transition Min 0 0 0 ns

tELBL

tELBH tELFL

tELFH Chip Enable to BYTE Low or High Max 5 5 5 ns

tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 25 25 30 ns

tBHQV tFHQV BYTE High to Output Valid Max 30 30 40 ns

15/22

M29W200BT, M29W200BB

Figure 9. Write AC Wavefor m s, Write Enable Con trolled

AI01991

A0-A16/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWHtGHWL

tWHRL

Table 15. Write AC Characteristics, Write Enable Controlle d

(TA = 0 to 70°C or –40 to 85°C)

Not e: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29W200B Unit

55 70 90 / 120

tAVAV tWC Address Valid to Next Address Valid Min 55 70 90 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 0 ns

tWLWH tWP Write Enable Low to Write Enable High Min 40 45 45 ns

tDVWH tDS Input Valid to Write Enable High Min 25 30 45 ns

tWHDX tDH Write Enable High to Input Transition Min 0 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 30 30 30 ns

tAVWL tAS Address Valid to Write Enable Low Min 0 0 0 ns

tWLAX tAH Write Enable Low to Address Transition Min 40 45 45 ns

tGHWL Output Enable High to Write Enable Low Min 0 0 0 ns

tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 0 ns

tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 35 ns

tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 50 µs

M29W200BT, M29W200BB

16/22

Table 16. Write AC Characteristics, Chip Enable Controlled

(TA = 0 to 70°C or –40 to 85°C)

Not e: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29W200B Unit

55 70 90 / 120

tAVAV tWC Address Valid to Next Address Valid Min 55 70 90 ns

tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 40 45 45 ns

tDVEH tDS Input Valid to Chip Enable High Min 25 30 45 ns

tEHDX tDH Chip Enable High to Input Transition Min 0 0 0 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 30 30 30 ns

tAVEL tAS Address Valid to Chip Enable Low Min 0 0 0 ns

tELAX tAH Chip Enable Low to Address Transition Min 40 45 45 ns

tGHEL Output Enable High Chip Enable Low Min 0 0 0 ns

tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 0 ns

tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 35 ns

tVCHWL tVCS VCC High to Write Enable Low Min 50 50 50 µs

Figure 10. Write AC Wavefo rms, Chip Enable Controlled

AI01992

A0-A16/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEHtGHEL

tEHRL

17/22

M29W200BT, M29W200BB

Table 17. Reset/Block Temporary Unprotect AC Characteri stics

(TA = 0 to 70°C or –40 to 85°C)

Not e: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29W200B Unit

55 70 90 / 120

tPHWL (1)

tPHEL

tPHGL (1) tRH RP High to Write Enable Low, Chip Enable

Low, Output Enable Low Min 50 50 50 ns

tRHWL (1)

tRHEL (1)

tRHGL (1) tRB RB High to Write Enable Low, Chip Enable

Low, Output Enable Low Min 0 0 0 ns

tPLPX tRP RP Pulse Width Min 500 500 500 ns

tPLYH (1) tREADY RP Low to Read Mode Max 10 10 10 µs

tPHPHH (1) tVIDR RP Rise Time to VID Min 500 500 500 ns

Figure 11. Reset/Block Tem porary Unp rotec t AC Waveforms

AI02931

RP tPLPX

tPHWL, tPHEL, tPHGL

tPLYH

tPHPHH

E, G

tRHWL, tRHEL, tRHGL

M29W200BT, M29W200BB

18/22

Table 18. Ordering Information Scheme

Note: The last two charac ters o f the ordering code m ay be replaced by a letter code for preprogramm ed

parts, otherwise devi ces are shipped from the factory with the memory content bits erased to ’1’.

For a list of availabl e options (S peed, P ack age, et c...) or for further information on any aspect of this de-

vice, pleas e contact the ST Sales Office nearest to you.

Example: M29W200BB 55 N 1 T

Device Type

M29

Operating Voltage

W = VCC = 2.7 to 3.6V

Device Function

200B = 2 Mbit (256Kb x8 or 128Kb x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

55 = 55 ns

70 = 70 ns

90 = 90 ns

120 = 120 ns

Package

N = TSOP48: 12 x 20 mm

M = SO44

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

T = Tape & Reel Packing

19/22

M29W200BT, M29W200BB

Table 19. Revision History

Date Revision Details

July 1999 First Issue

03/30/00

Status Register bit DQ5 clarification

Data Polling Flowchart diagram change (Figure 4)

Data Toggle Flowchart diagram change (Figure 5)

Program/Erase Times Maximum specification added (Table 9)

07/28/00 Documnet Type: from Preliminary Data to Data Sheet

M29W200BT, M29W200BB

20/22

Table 20. TSOP48 - 48 lead Plastic Thin Small Ou tline, 12 x 20mm, Packag e Mech anical Data

Symbol mm inches

Typ Min Max Typ Min Max

A 1.20 0.0472

A1 0.05 0.15 0.0020 0.0059

A2 0.95 1.05 0.0374 0.0413

B 0.17 0.27 0.0067 0.0106

C 0.10 0.21 0.0039 0.0083

D 19.80 20.20 0.7795 0.7953

D1 18.30 18.50 0.7205 0.7283

E 11.90 12.10 0.4685 0.4764

e 0.50 – – 0.0197 – –

L 0.50 0.70 0.0197 0.0279

α0° 5° 0° 5°

N48 48

CP 0.10 0.0039

Figure 12. TSOP48 - 48 lead Plastic Thin Small Outli ne, 12 x 20mm, Package Outl ine

Drawing is not to scale.

TSOP-a

1 N

N/2

DIE

LA1 α

21/22

M29W200BT, M29W200BB

Figure 13. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline

Drawing is not to scale.

SO-b

LA1 α

Table 21. SO44 - 44 lead Plastic Small Outline, 525 mils body width , Packag e Mech an ical Data

Symbol mm inches

Typ Min Max Typ Min Max

A 2.42 2.62 0.0953 0.1031

A1 0.22 0.23 0.0087 0.0091

A2 2.25 2.35 0.0886 0.0925

B 0.50 0.0197

C 0.10 0.25 0.0039 0.0098

D 28.10 28.30 1.1063 1.1142

E 13.20 13.40 0.5197 0.5276

e 1.27 – – 0.0500 – –

H 15.90 16.10 0.6260 0.6339

L 0.80 – – 0.0315 – –

α3° – – 3° – –

N44 44

CP 0.10 0.0039

M29W200BT, M29W200BB

22/22

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