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M29W200BT, M29W200BB
4/22
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diag ram, and T able 1, Sign al
Names, for a brief overview of the s ignals connect -
ed to this device.
Address Inputs (A0-A16). The Address Inputs
select the cell s in the memory arra y to access dur-
ing Bus Read operations. During Bus Writ e opera-
tions they control the commands sent to the
Comman d Interface of the internal stat e ma chine.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Data Inputs/Output s (DQ8-DQ14). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operati on when BYTE
is High, VIH. When BYTE is Low, VIL, these pins
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bit s. When reading t he Status Register
these bits should be ignored.
Data Input/Output or Address Input (D Q15A-1).
When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behav es as an address
pin; DQ15A–1 Low wil l select t he LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the t ext consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to inc lude this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memor y, allowing Bus Read and Bus Wr ite op-
erations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
ma nd Inte r face.
Reset /Bl ock T emporar y Unpr otect (RP). The Re-
set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem-
porarily unprotect all Blocks that have been pro-
tected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, V IH, the memory will be read y for Bus
Read and Bus Write operations after tPHEL or
tRHEL, whichever occurs last. See the Ready/ Busy
Output section, Table 17 and Figure 11, Reset/
Temporary Unprot ect AC Characte ristics for more
details.
Holding RP at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read . Ready/Busy
is high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes h igh-impeda nc e. See Tabl e 17 and Figure
11, Reset/Temporary Unprotect AC Characteris-
tics.
During Program or Erase operations Ready/Busy
is Low, VOL. Ready/Busy will remain Low during
Read/Reset c ommands or Hardw are Rese ts until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready /
Busy pins from several memor ies to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte /Wor d Orga niz ation Sele ct (BYTE). The Byte/
Word Organization S elect pin is used to switch be-
tween the 8-bit and 16-bit Bus modes of the mem-
ory. When B yte/Word Organiz ation Select is Low,
VIL, the m emory is in 8-bi t mode, w hen it is High,
VIH, the memory is in 16-bit mode.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is dis abled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevent s Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being alt ered will be invalid.
A 0.1µF capacitor should be connected between
the V CC Supply Voltage pin and the VSS Ground
pin to decoupl e the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operat ions, ICC3.
VSS Ground. The VSS Ground is the reference for
all voltage measureme nts.