ISL29023IROZ-T7 - Intersil - Datasheet.Directory

Integrated Digital Light Sensor with Interrupt

ISL29023

The ISL29023 is an integrated ambient and infrared light to

digital converter with I2C (SMBus Compatible) Interface. Its

advanced self-calibrated photodiode array emulates human eye

response with excellent IR rejection. The on-chip ADC is capable

of rejecting 50Hz and 60Hz flicker caused by artificial light

sources. The lux range select feature allows users to program the

lux range for optimized counts/lux.

For ambient light sensing, an internal 16-bit ADC has been

designed based upon the charge-balancing technique. The

ADC conversion time is nominally 90ms and is user adjustable

from 11µs to 90ms, depending on oscillator frequency and

ADC resolution. In normal operation, typical current

consumption is 70µA. In order to further minimize power

consumption, two power-down modes have been provided. If

polling is chosen over continuous measurement of light, the

auto-power-down function shuts down the whole chip after

each ADC conversion for the measurement. The other

power-down mode is controlled by software via the I2C

interface. The power consumption can be reduced to less than

0.3µA when powered down.

The ISL29023 supports a software and hardware interrupt that

remains asserted until the host clears it through I2C interface.

Function of ADC conversion continues without stopping after

interrupt is asserted.

Designed to operate on supplies from 2.25V to 3.63V with an I2C

supply from 1.7V to 3.63V, the ISL29023 is specified for

operation over the -40°C to +85°C ambient temperature range.

Features

• Resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-bits ADC

• Integrated Noise Reduction . . . . . . . . . . . . . . . . . . . . 50/60Hz

• Light Sensor Close to Human Eye Response

• Excellent Light Sensor IR and UV Rejection

• Range Selection via I2C

- Range1 = 0.015 to 1,000 Lux

- Range2 = 0.06 to 4,000 Lux

- Range3 = 0.24 to 16,000 Lux

- Range4 = 0.96 to 64,000 Lux

• Shutdown Modes . . . . . . . . . . . . . . . . . .Software & Automatic

• Supply Current (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85µA

• Shutdown Current (Max) . . . . . . . . . . . . . . . . . . . . . . . . . .0.3µA

• Control Interface . . . . . . . . . . . . . . . I2C and SMB Compatible

•I

2C Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 3.63V

• Sensor Power Supply. . . . . . . . . . . . . . . . . . . . . 2.25V to 3.63V

• Operating Temperature Range. . . . . . . . . . . . -40°C to +85°C

• Small Form Factor Package . . . . . . . .6 Ld 2.0x2.1x0.7 ODFN

Applications

• Mobile Devices: Smart Phone, PDA, GPS

• Computing Devices: Notebook PC, Webpad

• Consumer devices: LCD-TV, Digital Picture Frame, Digital

Camera

• Industrial and Medical Light Sensing

FIGURE 1. ISL29023 TYPICAL APPLICATION DIAGRAM FIGURE 2. NORMALIZED SPECTRAL RESPONSE FOR AMBIENT

LIGHT SENSING AND IR SENSING

REXT

MCU

10µF 0.1µF

SCL

SDA

VDD

VSS

SCL

SDA

GPIO

RRR

INT

VBUS VDD

500k

-0.2

0.2

0.4

0.6

0.8

1.0

1.2

300 400 500 600 700 800 900 1000 1100

WAVELENGTH (nm)

NORMALIZED RESPONSE

HUMAN EYE

IR SENSING

AMBIENT LIGHT SENSING

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

July 17, 2012

FN6691.1

ISL29023

2FN6691.1

July 17, 2012

Block Diagram

Pin Configuration

ISL29023

(6 LD ODFN)

TOP VIEW

SCL

SDA

INTEGRATING

ADC CMD Register

DATA

INTERRUPT

COMMAND

LIGHT DATA

PROCESS

INT

GND

VDD

I2C/SMB

PHOTODIODE

ARRAY

IREF

fOSC

REXT

*EXPOSED PAD CAN BE CONNECTED TO GND OR

ELECTRICALLY ISOLATED

2SCL

SDA

VDD

GND

3INT

REXT

PAD

Pin Descriptions

PIN NUMBER PIN NAME DESCRIPTION

1 VDD Positive supply; connect this pin to a 2.25V to

3.63V supply

2GNDGround pin

EXT External resistor pin for ADC reference;

connect this pin to ground through a (nominal)

499kΩ resistor.

4INT

Interrupt pin; low for interrupt alarming. INT

pin is open drain. INT remains asserted until

the interrupt flag status bit is reset.

5SCLI

2C serial clock. This line can be pulled from

1.7V to above VDD, 3.63V max.

6SDAI

2C serial data. This line can be pulled from

1.7V to above VDD, 3.63V max.

PAD Exposed pad connected to ground or

electrically isolated

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

TEMP RANGE

(°C)

PACKAGE

TAPE & REEL (Pb-free)

PKG.

DWG. #

ISL29023IROZ-T7S2378 -40 to +85 6 Ld ODFN L6.2x2.1

ISL29023IROZ-EVALZ Evaluation Board (Pb-free)

NOTES:

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate

- e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL29023. For more information on MSL please see tech brief TB477.

ISL29023

3FN6691.1

July 17, 2012

Absolute Maximum Ratings Thermal Information

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0V

I2C Bus (SCL, SDA) and INT Pin Voltage. . . . . . . . . . . . . . . . . . -0.2V to 4.0V

I2C Bus (SCL, SDA) and INT Pin Current. . . . . . . . . . . . . . . . . . . . . . . <10mA

REXT Pin Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to VDD+0.5V

Thermal Resistance (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . θJA (°C/W)

6 Ld ODFN Package (Notes 4, 4) . . . . . . . . . . . . . . . . . . . . . . . . . 90

Maximum Junction Temperature (TJMAX). . . . . . . . . . . . . . . . . . . . . . . +90°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Pb-Free Reflow Profile) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

Brief TB379.

Electrical Specifications VDD = 3V, TA = +25°C, REXT = 499kΩ 1% tolerance, 16-bit ADC operation, unless otherwise specified.

PARAMETER DESCRIPTION CONDITION

MIN

(Note 7) TYP

MAX

(Note 7) UNIT

VDD Power Supply Range 2.25 3.63 V

IDD Supply Current 70 85 µA

IDD1 Supply Current when Powered Down Software disabled or auto power-down 0.01 0.3 µA

VI2CSupply Voltage Range for I2C Interface 1.7 3.63 V

fOSC Internal Oscillator Frequency 675 750 825 kHz

tint ADC Integration/Conversion Time 16-bit ADC data 90 ms

FI2CI2C Clock Rate Range 1 to 400 kHz

DATA_0 Count Output When Dark E = 0 lux, Range 1 (1k lux) 1 5 Counts

DATA_F Full Scale ADC Code 65535 Counts

DDATA

DATA

Count Output Variation Over Three Light

Sources: Fluorescent, Incandescent and

Sunlight

Ambient light sensing ±10 %

DATA_1 Light Count Output With LSB of

0.015 lux/count

E = 300 lux, Fluorescent light (Note 5), ALS Range

1 (1k lux)

15000 20000 25000 Counts

DATA_2 Light Count Output With LSB of

0.06 lux/count

E = 300 lux, Fluorescent light (Note 5), ALS Range

2 (4k lux)

5000 Counts

DATA_3 Light Count Output With LSB of

0.24 lux/count

E = 300 lux, Fluorescent light (Note 5), ALS Range

3 (16k lux)

1250 Counts

DATA_4 Light Count Output With LSB of

0.96 lux/count

E = 300 lux, Fluorescent light (Note 5), ALS Range

4 (64k lux)

312 Counts

DATA_IR1 Infrared Count Output E = 210 lux, Sunlight (Note 6), IR sensing, Range 1 15000 20000 25000

DATA_IR2 Infrared Count Output E = 210 lux, Sunlight (Note 6), IR sensing, Range 2 5000

DATA_IR3 Infrared Count Output E = 210 lux, Sunlight (Note 6), IR sensing, Range 3 1250

DATA_IR4 Infrared Count Output E = 210 lux, Sunlight (Note 6), IR sensing, Range 4 312

VREF Voltage of REXT Pin 0.52 V

VIL SCL and SDA Input Low Voltage 0.55 V

VIH SCL and SDA Input High Voltage 1.25 V

ISDA SDA Current Sinking Capability 4 5 mA

IINT INT Current Sinking Capability 4 5 mA

NOTES:

5. 550nm green LED is used in production test. The 550nm LED irradiance is calibrated to produce the same DATA count against an illuminance level of

300 lux fluorescent light.

6. 850nm IR LED is used in production test. The 850nm LED irradiance is calibrated to produce the same DATA_IR count against an illuminance level of

210 lux sunlight at sea level.

7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

ISL29023

4FN6691.1

July 17, 2012

Typical Performance Curves

FIGURE 3. NORMALIZED SPECTRAL RESPONSE OF LIGHT SOURCES FIGURE 4. NORMALIZED SPECTRAL RESPONSE FOR AMBIENT

LIGHT SENSING AND IR SENSING

FIGURE 5. RADIATION PATTERN FIGURE 6. SENSITIVITY TO THREE LIGHT SOURCES

FIGURE 7. OUTPUT CODE FOR 0 LUX vs TEMPERATURE FIGURE 8. OUTPUT CODE vs TEMPERATURE

FIGURE 9. SUPPLY CURRENT vs TEMPERATURE IN ALS SENSING

300 400 500 600 700 800 900 1000 1100

WAVELENGTH (nm)

NORMALIZED LIGHT INTENSITY

SUN

HALOGEN

INCANDESCENT

FLUORESCENT

-0.2

0.2

0.4

0.6

0.8

1.0

1.2

300 400 500 600 700 800 900 1000 1100

WAVELENGTH (nm)

NORMALIZED RESPONSE

HUMAN EYE

IR SENSING

AMBIENT LIGHT SENSING

RADIATION PATTERN

LUMINOSITY

ANGLE

RELATIVE SENSITIVITY

90°

80°

70°

60°

50°

40°

30° 20° 10° 0° 10° 20° 30° 40°

50°

60°

70°

80°

90°

0.2 0.4 0.6 0.8 1.0 0

100

200

300

400

500

600

700

800

900

1000

0 100 200 300 400 500 600 700 800 900 1000

LUX METER READING (LUX)

CALCULATED ALS READING (LUX)

INCANDESCENT

HALOGEN

FLUORESCENT

ALS SENSING

RANGE 1 (1k Lux)

16-BIT ADC

ADC OUTPUT (COUNT)

32768

65535

1000 LUX

Ecal = 216 x DATA

NO COVER GLASS

OUTPUT CODE (COUNTS)

TEMPERATURE (°C)

-60 -20 20 60 100

NORMALIZED OUTPUT CODE

TEMPERATURE (°C)

0.90

0.95

1.00

1.05

1.10

-60 -20 20 60 100

300 Lux FLUORESCENT LIGHT

ALS SENS IN G

RANGE 1 (1k Lux)

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

ALS SENSING

10,000 Lux

ISL29023

5FN6691.1

July 17, 2012

Principles of Operation

Photodiodes and ADC

The ISL29023 contains two photodiode arrays, which convert light

into current. The spectral response for ambient light sensing and IR

sensing is shown in Figure 4 in the performance curves section.

After light is converted to current during the light signal process, the

current output is converted to digital by a built-in 16-bit Analog-to-

Digital Converter (ADC). An I2C command reads the ambient light or

IR intensity in counts.

The converter is a charge-balancing integrating type 16-bit ADC. The

chosen method for conversion is best for converting small current

signals in the presence of an AC periodic noise. A 100ms integration

time, for instance, highly rejects 50Hz and 60Hz power line noise

simultaneously.

The built-in ADC offers user flexibility in integration time or

conversion time. There are two timing modes: Internal Timing Mode

and External Timing Mode. In Internal Timing Mode, integration time

is determined by an internal oscillator (fOSC), and the n-bit (n = 4, 8,

12, 16) counter inside the ADC. In External Timing Mode, integration

time is determined by the time between two consecutive I2C

External Timing Mode commands. A good balancing act of

integration time and resolution (depending on the application) is

required for optimal results.

The ADC has I2C programmable range select to dynamically

accommodate various lighting conditions. For very dim

conditions, the ADC can be configured at its lowest range

(Range 1) in the ambient light sensing.

Low-Power Operation

The ISL29023 initial operation is at the power-down mode after a

supply voltage is provided. The data registers contain the default

value of 0. When the ISL29023 receives an I2C command to do a

one-time measurement from an I2C master, it will start ADC

conversion with light sensing. It will go to the power-down mode

automatically after one conversion is finished and keep the

conversion data available for the master to fetch anytime

afterwards. The ISL29023 will continuously do ADC conversion

with light sensing if it receives an I2C command of continuous

measurement. It will continuously update the data registers with

the latest conversion data. It will go to the power-down mode

after it receives the I2C command of power-down.

Ambient Light and IR Sensing

There are four operational modes in ISL29023: Programmable ALS

once with auto power-down, programmable IR sensing once with

auto power-down, programmable continuous ALS sensing and

programmable continuous IR sensing. These four modes can be

programmed in series to fulfill the application needs. The detailed

program configuration is listed in “Command-I Register (Address:

0x00)” on page 8.

When the part is programmed for ambient light sensing, the

ambient light with wavelength within the “Ambient Light

Sensing” spectral response curve in Figure 4 is converted into

current. With ADC, the current is converted to an unsigned n-bit

(up to 16 bits) digital output.

When the part is programmed for infrared (IR) sensing, the IR

light with wavelength within the “IR Sensing” spectral response

curve in Figure 4 is converted into current. With ADC, the current

is converted to an unsigned n-bit (up to 16-bits) digital output.

Interrupt Function

The active low interrupt pin is an open drain pull-down

configuration. The interrupt pin serves as an alarm or monitoring

function to determine whether the ambient light level exceeds

the upper threshold or goes below the lower threshold. It should

be noted that the function of ADC conversion continues without

stopping after interrupt is asserted. If the user needs to read the

ADC count that triggers the interrupt, the reading should be done

before the data registers are refreshed by the following

conversions. The user can also configure the persistency of the

interrupt pin. This reduces the possibility of false triggers, such as

noise or sudden spikes in ambient light conditions. An

unexpected camera flash, for example, can be ignored by setting

the persistency to 8 integration cycles.

Serial Interface

The ISL29023 supports the Inter-Integrated Circuit (I2C) bus data

transmission protocol. The I2C bus is a two wire serial

bidirectional interface consisting of SCL (clock) and SDA (data).

Both the wires are connected to the device supply via pull-up

resistors. The I2C protocol defines any device that sends data

onto the bus as a transmitter and the receiving device as the

receiver. The device controlling the transfer is a master and the

device being controlled is the slave. The transmitting device pulls

down the SDA line to transmit a “0” and releases it to transmit a

“1”. The master always initiates the data transfer, only when the

bus is not busy, and provides the clock for both transmit and

receive operations. The ISL29023 operates as a slave device in

all applications. The serial communication over the I2C interface

is conducted by sending the most significant bit (MSB) of each

byte of data first.

Start Condition

During data transfer, the SDA line must remain stable while the

SCL line is HIGH. All I2C interface operations must begin with a

START condition, which is a HIGH to LOW transition of SDA while

SCL is HIGH (refer to Figure 12). The ISL29023 continuously

monitors the SDA and SCL lines for the START condition and does

not respond to any command until this condition is met (refer to

Figure 12). A START condition is ignored during the power-up

sequence.

Stop Condition

All I2C interface operations must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA while SCL is

HIGH (refer to Figure 12). A STOP condition at the end of a

read/write operation places the device in its standby mode. If a

stop is issued in the middle of a Data byte, or before 1 full Data

byte + ACK is sent, then the serial communication of ISL29023

resets itself without performing the read/write. The contents of

the array are not affected.

ISL29023

6FN6691.1

July 17, 2012

Acknowledge

An acknowledge (ACK) is a software convention used to indicate

a successful data transfer. The transmitting device releases the

SDA bus after transmitting 8-bits. During the ninth clock cycle,

the receiver pulls the SDA line LOW to acknowledge the reception

of the eight bits of data (refer to Figure 12). The ISL29023

responds with an ACK after recognition of a START condition

followed by a valid Identification Byte, and once again, after

successful receipt of an Address Byte. The ISL29023 also

responds with an ACK after receiving a Data byte of a write

operation. The master must respond with an ACK after receiving

a Data byte of a read operation

Device Addressing

Following a START condition, the master must output a Device

Address byte. The 7 MSBs of the Device Address byte are known as

the device identifier. The device identifier bits of ISL29023 are

internally hard-wired as “1000100”. The LSB of the Device Address

byte is defined as read or write (R/W) bit. When this R/W bit is a

“1”, a read operation is selected and when “0”, a write operation is

selected (refer to Figure 10). The master generates a START

condition followed by Device Address byte 1000100x (x as R/W)

and the ISL29023 compares it with the internal device identifier.

Upon a correct comparison, the device outputs an acknowledge

(LOW) on the SDA line (refer to Figure 12).

Write Operation

BYTE WRITE

In a byte write operation, ISL29023 requires the Device Address

byte, Register Address byte, and the Data byte. The master starts

the communication with a START condition. Upon receipt of the

Device Address byte, Register Address byte, and the Data byte,

the ISL29023 responds with an acknowledge (ACK). Following

the ISL29023 data acknowledge response, the master

terminates the transfer by generating a STOP condition.

ISL29023 then begins an internal write cycle of the data to the

volatile memory. During the internal write cycle, the device inputs

are disabled and the SDA line is in a high impedance state, so the

device will not respond to any requests from the master (refer to

Figure 11).

BURST WRITE

The ISL29023 has a burst write operation, which allows the

master to write multiple consecutive bytes from a specific

address location. It is initiated in the same manner as the byte

write operation, but instead of terminating the write cycle after

the first Data byte is transferred, the master can write to the

whole register array. After the receipt of each byte, the ISL29023

responds with an acknowledge, and the address is internally

incremented by one. The address pointer remains at the last

address byte written. When the counter reaches the end of the

FIGURE 10. DEVICE ADDDRESS, REGISTER ADDRESS, & DATA BYTE

DEVICE

ADDRESS BYTE

DATA BYTE

1 0 0 0 1 0 0 R/W

A7 A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

FIGURE 11. BYTE WRITE SEQUENCE

10001000

DEVICE ADDRESS

BYTE ADDRESS BYTE DATA BYTE

SIGNAL FROM

MAST ER DEVI CE

SIGNAL AT SDA

SIGNALS FROM

SLAVE DEVICE

FIGURE 12. START, DATA STABLE, ACKNOWLEDGE, AND STOP CONDITION

SDA FROM

RECEIVER

SDA FROM

TRANSMITTER

SCL FROM

MASTER

START DATA

CHANGE DATA

STABLE

DATA

STABLE ACK STOP

8th

CLk 9th CLk

HIGH IMPEDANCE

ISL29023

7FN6691.1

July 17, 2012

Read Operation

ISL29023 has two basic read operations: Byte Read and Burst

Read.

BYTE READ

Byte read operations allow the master to access any register

location in the ISL29023. The Byte read operation is a two step

process. The master issues the START condition and the Device

Address byte with the R/W bit set to “0”, receives an

acknowledge, then issues the Register Address byte. After

acknowledging receipt of the register address byte, the master

immediately issues another START condition and the Device

Address byte with the R/W bit set to “1”. This is followed by an

acknowledge from the device and then by the 8-bit data word.

The master terminates the read operation by not responding with

an acknowledge and then issuing a stop condition. Refer to

Figure 13.

BURST READ

Burst read operation is identical to the Byte Read operation.

After the first Data byte is transmitted, the master now responds

with an acknowledge, indicating it requires additional data. The

device continues to output data for each acknowledge received.

The master terminates the read operation by not responding with

an acknowledge but issuing a STOP condition (refer to Figure 14).

For more information about the I2C standard, please consult the

Phillips™ I2C specification documents.

Power On Reset

The Power-On Reset (POR) circuitry protects the internal logic

against powering up in the incorrect state. The ISL29023 will

power up into Standby mode after VDD exceeds the POR trigger

level and will power down into Reset mode when VDD drops

below the POR trigger level. This bi-directional POR feature

protects the device against ‘brown-out’ failure following a

temporary loss of power.

The POR is an important feature because it prevents the

ISL29023 from starting to operate with insufficient voltage, prior

to stabilization of the internal bandgap. The ISL29023 prevents

communication to its registers and greatly reduces the likelihood

of data corruption on power-up.

FIGURE 13. BYTE ADDRESS READ SEQUENCE

10001000

DEVI CE AD DRESS

WRITE ADDRESS BYTE

SIGNAL FROM

MASTER DEVICE

SIGNAL AT SDA

SIGNALS FROM

SLAVE DEVICE

DEVI CE ADD RESS

READ DATA BYTE

T10001001

FIGURE 14. BURST READ SEQUENCE

10001000

DEVICE ADDRESS

WRITE ADDRESS BYTE

SIGNAL FROM

MASTER DEVICE

SIGNAL AT SDA

SIGNALS FROM

SLAVE DEVICE

DEVICE ADDRESS

READ DATA BYTE 1

T10001001

DATA BYTE 2

DATA BYTE n

(“n” is any integer

greater than 1)

ISL29023

8FN6691.1

July 17, 2012

Following are detailed descriptions of the control registers

related to the operation of the ISL29023 ambient light sensor

device. These register are accessed by the I2C serial interface.

For details on the I2C interface, refer to “Serial Interface” on

page 5.

All the functionalities of the device are controlled by the

registers. The ADC data can also be read. The following sections

explain the details of each register bit. All RESERVED bits must

be set to zero, unless otherwise specified.

Decimal to Hexadecimal Conversion

To convert decimal value to hexadecimal value, divide the

decimal number by 16, and write the remainder on the side as

the least significant digit. This process is continued by dividing

the quotient by 16 and writing the remainder until the quotient is

0. When performing the division, the remainders, which will

represent the hexadecimal equivalent of the decimal number,

are written beginning at the least significant digit (right) and

each new digit is written to the next more significant digit (the

left) of the previous digit. Consider the number 175 decimal.

Command-I Register (Address: 0x00)

The Command-I register consists of control and status bits. In

this register, there are two interrupt persist bits, one interrupt

status bit, and three operation mode bits. The operation mode

bits and the interrupt persist bits are independent of each other.

The default register value is 0x00 at power on.

INTERRUPT PERSIST BITS (B0 - B1)

The interrupt persist bits provides control over when interrupts

occur. There are four different selections for this feature. A value

of N (where N is 1, 4, 8, and 16) results in an interrupt only if the

value remains outside the threshold window for N consecutive

integration cycles. For example, if N is equal to 16 and the ADC

resolution is set to 16-bits then the integration time is 100ms. An

interrupt is generated whenever the last conversion results in a

value outside of the programmed threshold window. The

interrupt is active-low and remains asserted until cleared by

writing the COMMAND register with the CLEAR bit set. Table 4

lists the possible interrupt presist bits.

INTERRUPT FLAG BIT (B2)

The interrupt flag bit is a status bit for light intensity detection.

The bit is set to logic HIGH when the light intensity crosses the

interrupt thresholds window (register address 0x04 - 0x07), and

set to logic LOW when its within the interrupt thresholds window.

Once the interrupt is triggered, the INT pin goes low and the

interrupt status bit goes HIGH until the status bit is polled

through the I2C read command. Both the INT pin and the

interrupt status bit are automatically cleared at the end of the

8-bit Device Register byte (0x00) transfer. Table 5 shows interrupt

flag states.

TABLE 1. REGISTER MAP

NAME

DEC HEX B7 B6 B5 B4 B3 B2 B1 B0 HEX

COMMAND-I 0 0x00 OP2 OP1 OP0 RESERVED FLAG PRST1 PRST0 0x00

COMMAND-II 1 0x01 RESERVED RES1 RES0 RANGE1 RANGE0 0x00

DATALSB 20x02D7D6D5D4D3D2D1D00x00

DATAMSB 3 0x03 D15 D14 D13 D12 D11 D10 D9 D8 0x00

INT_LT_LSB 4 0x04 TL7 TL6 TL5 TL4 TL3 TL2 TL1 TL0 0x00

INT_LT_MSB 5 0x05 TL15 TL14 TL13 TL12 TL11 TL10 TL9 TL8 0x00

INT_HT_LSB 6 0x06 TH7 TH6 TH5 TH4 TH3 TH2 TH1 TH0 0xFF

INT_HT_MSB 7 0x07 TH15 TH14 TH13 TH12 TH11 TH10 TH9 TH8 0xFF

TABLE 2. DECIMAL TO HEXADECIMAL

DIVISION QUOTIENT REMINDER HEX NUMBER

175/16 10 = A 15 = F 0xAF

TABLE 3. COMMAND-I REGISTER ADDRESS

NAME

Reg. Addr

(Hex)

(Hex)B7 B6 B5 B4 B3 B2 B1 B0

COMMANDI 0x00 OP2 OP1 OP0 0 0 FLAG PRST1 PRST0 0x00

TABLE 4. INTERRUPT PERSIST BITS

B1 B0 NUMBER OF INTEGRATION CYCLES (n)

00 1

01 4

10 8

11 16

TABLE 5. INTERRUPT FLAG BIT

BIT 2 OPERATION

0 Interrupt is cleared or not triggered yet

1 Interrupt is triggered

ISL29023

9FN6691.1

July 17, 2012

OPERATION MODE BITS (B5 - B7)

ISL29023 has different operating modes. These modes are

selected by setting B5 -B7 bits on register address 0x00. The

device powers up on a disable mode. Table 6 lists the possible

operating modes.

Command-II Register (Address: 0x01)

The Command-II register consists of ADC control bits. In this

The default register value is 0x00 at power on.

FULL SCALE RANGE (B0 - B1)

The Full Scale Range (FSR) has four different selectable ranges.

The range determines the ADC resolution (4-bits, 8-bits, 12-bits,

and 16-bits). Each range has a maximum allowable lux value.

Higher range values offer better resolution and wider ALS lux

value. Table 8 lists the possible values of FSR for the 499kΩ REXT

resistor.

ADC RESOLUTION (B3 - B2)

B2 and B3 determine the ADC’s resolution and the number of

clock cycles per conversion. Changing the number of clock cycles

does more than just change the resolution of the device; it also

changes the integration time, which is the period the device’s

analog-to-digital (A/D) converter samples the photodiode current

signal for a measurement. Table 9 lists the possible ADC

resolution.

Data Registers (Addresses: 0x02 & 0x03)

The ISL29023 has two 8-bit read-only registers to hold the upper

and lower byte of the ADC value. The upper byte is accessed at

address 0x03 and the lower byte is accessed at address 0x02.

For 16-bit resolution, the data is from D0 to D15; for 12-bit

resolution, the data is from D0 to D11; for 8-bit resolution, the

data is from D0 to D7 and 4-bit resolution, the data is from D0 to

D3. The registers are refreshed after every conversion cycle. The

default register value is 0x00 at power on.

Lower Interrupt Threshold Registers

(Address: 0x04 & 0x05)

The lower interrupt threshold registers are used to set the lower

trigger point for interrupt generation. If the ALS value crosses

below or is equal to the lower threshold, an interrupt is asserted

on the interrupt pin and the interrupt flag. Registers INT_LT_LSB

(0x04) and INT_LT_MSB (0x05) provide the low and high bytes,

respectively, of the lower interrupt threshold. The high and low

bytes from each set of registers are combined to form a 16-bit

threshold value. The interrupt threshold registers default to 0x00

upon power up.

TABLE 6. OPERATING MODES BITS

B7 B6 B5 OPERATION

0 0 0 Power-down the device (Default)

0 0 1 The IC measures ALS only once every

integration cycle. This is the lowest

operating mode.

010IR once

011Reserved (DO NOT USE)

100Reserved (DO NOT USE)

1 0 1 The IC measures ALS continuously

1 1 0 The IC measures IR continuous

111Reserved (DO NOT USE)

TABLE 7. COMMAND-II REGISTER BITS

NAME

Reg.

Addr

(Hex)

DFLT

(Hex)B7 B6 B5 B4 B3 B2 B1 B0

COMMANDII 0x01 0 0 0 0 RES1 RES0 RANGE1 RANGE0 0x00

TABLE 8. RANGE REGISTER BITS

B0 B1 k RANGE(k)

FSR (LUX) @ ALS

SENSING

FSR @ IR

SENSING

00 1 Range1 1,000

0 1 2 Range2 4,000

1 0 3 Range3 16,000

1 1 4 Range4 64,000

TABLE 9. ADC RESOLUTION DATA WIDTH

B3 B2 NUMBER OF CLOCK CYCLES n-BIT ADC

002

16 = 65,536 16

012

12 = 4,096 12

102

8 = 256 8

112

4 = 16 4

TABLE 10. ADC REGISTER BITS

NAME

Reg.

Addr

(Hex)

DFLT

(Hex)B7 B6 B5 B4 B3 B2 B1 B0

DATALSB 0x02 D7 D6 D5 D4 D3 D2 D1 D0 0x00

DATAMSB 0x03 D15 D14 D13 D12 D11 D10 D9 D8 0x00

TABLE 11. ADC DATA REGISTERS

ADDRESS

(hex) CONTENTS

0x02 D0 is LSB for 4, 8, 12 or 16-bit resolution; D3 is MSB for

4-bit resolution; D7 is MSB for 8-bit resolution

0x03 D15 is MSB for 16-bit resolution; D11 is MSB for 12-bit

resolution

TABLE 12. INTERRUPT REGISTER BITS

NAME

Reg.

Addr

(Hex)

DFLT

(Hex)B7 B6 B5 B4 B3 B2 B1 B0

INT_LT_LSB 0x04 TL7 TL6 TL5 TL4 TL3 TL2 TL1 TL0 0x00

INT_LT_MSB 0x05 TL15 TL14 TL13 TL12 TL11 TL10 TL9 TL8 0x00

ISL29023

10 FN6691.1

July 17, 2012

Upper Interrupt Threshold Registers

(Address: 0x06 & 0x07)

The upper interrupt threshold registers are used to set the upper

trigger point for interrupt generation. If the ALS value crosses

above or is equal to the upper threshold, an interrupt is asserted

on the interrupt pin and the interrupt flag. Registers INT_HT_LSB

(0x06) and INT_HT_MSB (0x07) provide the low and high bytes,

respectively, of the upper interrupt threshold. The high and low

bytes from each set of registers are combined to form a 16-bit

threshold value. The interrupt threshold registers default to 0xFF

on power up.

Applications Information

Calculating Lux

The ISL29023’s ADC output codes, DATA, are directly

proportional to lux in the ambient light sensing.

Here, Ecal is the calculated lux reading. The constant α is

determined by the Full Scale Range and the ADC’s maximum

output counts. The constant is independent of the light sources

(fluorescent, incandescent and sunlight) because the light

sources’ IR component is removed during the light signal

process. The constant can also be viewed as the sensitivity (the

smallest lux measurement the device can measure).

Here, Range(k) is defined in Table 8. Countmax is the maximum

output counts from the ADC.

The transfer function used for n-bits ADC becomes:

Here, n = 4, 8, 12 or 16. This is the number of ADC bits

programmed in the command register. 2n represents the

maximum number of counts possible from the ADC output. Data

is the ADC output stored in the data registers (02 hex and 03

hex).

Integration and Conversion Time

The ADC resolution and fOSC determine the integration time, tint.

where n is the number of bits of resolution and n = 4, 8, 12 or 16.

Therefore, 2n is the number of clock cycles. n can be programmed

at the command register 01(hex) bits 3 and 2.

External Scaling Resistor REXT for fOSC and

Range

The ISL29023 uses an external resistor REXT to fix its internal

oscillator frequency fOSC and the light sensing range, Range. fOSC

and Range are inversely proportional to REXT. For user simplicity,

the proportionality constant is referenced to 499kΩ:

ADC Output in IR Sensing

The ISL29023’s ADC output codes, DATA, are directly

proportional to the IR intensity received in the IR sensing.

Here, EIR is the received IR intensity. The constant β changes with

the spectrum of background IR noise, such as sunlight and

incandescent light. The β also changes with the ADC’s range and

resolution selections.

Noise Rejection

Electrical AC power worldwide is distributed at either 50Hz or

60Hz. Artificial light sources vary in intensity at the AC power

frequencies. The undesired interference frequencies are infused

on the electrical signals. This variation is one of the main sources

of noise for the light sensors. Integrating type ADC’s have

excellent noise-rejection characteristics for periodic noise

sources whose frequency is an integer multiple of the conversion

rate. By setting the sensor’s integration time to an integer

multiple of periodic noise signal, the performance of an ambient

light sensor can be improved greatly in the presence of noise. In

order to reject the AC noise, the integration time of the sensor

must to adjusted to match the AC noise cycle. For instance, a

60Hz AC unwanted signal’s sum from 0ms to k*16.66ms

(k = 1,2...ki) is zero. Similarly, setting the device’s integration

time to be an integer multiple of the periodic noise signal greatly

improves the light sensor output signal in the presence of noise.

Suggested PCB Footprint

It is important that users check the “Surface Mount Assembly

Guidelines for Optical Dual Flat Pack No Lead (ODFN) Package”

before starting ODFN product board mounting.

http://www.intersil.com/data/tb/TB477.pdf

TABLE 13. INTERRUPT REGISTER BITS

NAME

Reg.

Addr

(Hex)

DFLT

(Hex)B7 B6 B5 B4 B3 B2 B1 B0

INT_HT_LSB 0x06 TH7 TH6 TH5 TH4 TH3 TH2 TH1 TH0 0xFF

INT_HT_MSB 0x07 TH15 TH14 TH13 TH12 TH11 TH10 TH9 TH8 0xFF

Ecal αDATA×=(EQ. 1)

αRange k()

Countmax

----------------------------

=(EQ. 2)

(EQ. 3)

Ecal Range k()

--------------------------- DATA×=

tint 2n1

fOSC

--------------

×2nREXT

725kHz 499kΩ×

----------------------------------------------

×== (EQ. 4)

TABLE 14. INTEGRATION TIME OF n-BIT ADC

REXT (kΩ)n = 16-BIT n = 12-BIT n = 8-BIT n = 4-BIT

499** 90ms 5.6ms 352µs 22µs

**Recommended REXT resistor value

(EQ. 5)

Range 499kΩ

REXT

------------------ Range k()×=

(EQ. 6)

fOSC 499kΩ

REXT

------------------ 725×kHz=

DATAIR βEIR

×=(EQ. 7)

ISL29023

11 FN6691.1

July 17, 2012

Board Mounting Considerations

For applications requiring the light measurement, the board

mounting location should be reviewed. The device uses an

Optical Dual Flat Pack No Lead (ODFN) package, which subjects

the die to mild stresses when the printed circuit (PC) board is

heated and cooled, which slightly changes the shape. Because of

these die stresses, placing the device in areas subject to slight

twisting can cause degradation of reference voltage accuracy. It

is normally best to place the device near the edge of a board, or

on the shortest side, because the axis of bending is most limited

in that location.

Layout Considerations

The ISL29023 is relatively insensitive to layout. Like other I2C

devices, it is intended to provide excellent performance even in

significantly noisy environments. There are only a few

considerations that will ensure best performance.

Route the supply and I2C traces as far as possible from all

sources of noise. Use two power-supply decoupling capacitors,

1µF and 0.1µF, placed close to the device. REXT must be placed

as closely to the pin as possible to eliminate the stray

capacitance, which will greatly affect the performance of the

sensor.

Soldering Considerations

Convection heating is recommended for reflow soldering; direct-

infrared heating is not recommended. The plastic ODFN package

does not require a custom reflow soldering profile, and is

qualified to +260°C. A standard reflow soldering profile with a

+260°C maximum is recommended.

Temperature Coefficient

The limits stated for temperature coefficient (Tempco) are

governed by the method of measurement. The overwhelming

standard for specifying the temperature drift of a reference is to

measure the reference voltage at two temperatures, take the

total variation, (VHIGH - VLOW), and divide by the temperature

extremes of measurement (THIGH - TLOW). The result is divided

by the nominal reference voltage (at T = +25°C) and multiplied

by 106 to yield ppm/°C. This is the "Box" method for specifying

temperature coefficient.

Digital Inputs and Termination

The ISL29023 digital inputs are guaranteed to CMOS levels. The

internal register is updated on the rising edge of the clock. To

minimize reflections, proper termination should be

implemented. If the lines driving the clock and the digital inputs

are 50Ω lines, then 50Ω termination resistors should be placed

as close to the sensor inputs as possible, connected to the digital

ground plane (if separate grounds are used).

Typical Circuit

A typical application for the ISL29023 is shown in Figure 1. The

ISL29023’s I2C address is internally hard-wired as 1000100. The

device can be tied onto a system’s I2C bus together with other I2C

compliant devices.

FIGURE 15. ISL29023 TYPICAL SYSTEM DIAGRAM

VDD

GND

REXT

3INT 4

SCL 5

SDA 6

ISL29023

R1 R2

REXT

499k

0.1µF

10µF

2.25V TO 3.63V

MICROCONTROLLER

SDA

SCL

I2C SLAVE_ 0 I2C SLAVE_ 1 I2C SLAVE_n

I2C MASTER

SCL

SDA

SCL

SDA

1.7V TO 3.63V

INT

ISL29023

12 FN6691.1

July 17, 2012

FIGURE 16. 6-LD ODFN SENSOR LOCATION OUTLINE

SENSOR OFFSET

0.54

0.37

0.40

ISL29023

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6691.1

July 17, 2012

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Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest revision.

DATE REVISION CHANGE

May 14, 2012 FN6691.1 I2C section & Register description explained in more detail.

March 3, 2009 FN6691.0 Initial Release

ISL29023

14 FN6691.1

July 17, 2012

Package Outline Drawing

L6.2x2.1

6 LEAD OPTICAL DUAL FLAT NO-LEAD PLASTIC PACKAGE (ODFN)

Rev 3, 5/11

located within the zone indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.15mm and 0.30mm from the terminal tip.

Dimension applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to ASME Y14.5m-1994.

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES:

BOTTOM VIEW

DETAIL "X"

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

(4X) 0.10

INDEX AREA

PIN 1

ABPIN #1

B0.10 MAC

SEATING PLANE

BASE PLANE

0.08

0.10

SEE DETAIL "X"

0 . 00 MIN.

0 . 05 MAX.

0 . 2 REF

2.10

2.00

2.10

2.50

(1.35)

(6x0.30)

0.65

(6x0.55)

(6x0.20)

(4x0.65)

1.30 REF1.35

0.65

6x0.35 ± 0.05

PACKAGE

6X 0.30±0.05

INDEX AREA

OUTLINE

MAX 0.75