Fiber Channel/Ethernet Clock Generator IC, 7 Clock Outputs AD9572 FEATURES FUNCTIONAL BLOCK DIAGRAM REFSEL XTAL OSC CMOS 1 x 25MHz REFCLK LVPECL OR LVDS DIVIDERS LPF THIRD ORDER PFD/CP LDO VCO 2 x 106.25MHz LVPECL OR LVDS 1 x 156.25MHz LVPECL OR LVDS DIVIDERS LPF 3RD ORDER LDO PFD/CP Fully integrated dual VCO/PLL cores 0.22 ps rms jitter from 0.637 MHz to 10 MHz at 106.25 MHz 0.19 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz 0.42 ps rms jitter from 12 kHz to 20 MHz at 125 MHz Input crystal or clock frequency of 25 MHz Preset divide ratios for 106.25 MHz, 156.25 MHz, 33.33 MHz, 100 MHz, and 125 MHz Choice of LVPECL or LVDS output format Integrated loop filters Copy of reference clock output Rates configured via strapping pins 0.71 W power dissipation (LVDS operation) 1.07 W power dissipation (LVPECL operation) 3.3 V operation Space saving, 6 mm x 6 mm, 40-lead LFCSP VCO 2 x 100MHz OR 125MHz CMOS APPLICATIONS 1 x 33.33MHz AD9572 FREQSEL Figure 1. GENERAL DESCRIPTION The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. A second PLL also operates as an integer-N synthesizer and drives two LVPECL or LVDS output buffers for 106.25 MHz operation. No external loop filter components are required, thus conserving valuable design time and board space. CPU ISLAND 16-PORT FIBRE CHANNEL ASIC QUAD SFP PHY 1 x 156.25MHz 2 x 106.25MHz 1 x 100MHz/125MHz 1 x 25MHz 1 x 33.33MHz AD9572 07498-002 10G SFP+ QUAD SFP PHY feedback divider and output divider. By connecting an external crystal or reference clock to the REFCLK pin, frequencies up to 156.25 MHz can be locked to the input reference. Each output divider and feedback divider ratio is preprogrammed for the required output rates. The AD9572 is available in a 40-lead, 6 mm x 6 mm lead frame chip scale package (LFCSP) and can be operated from a single 3.3 V supply. The temperature range is -40C to +85C. The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump (CP), a low phase noise voltage controlled oscillator (VCO), and a preprogrammed QUAD SFP PHY 07498-001 FORCE_LOW Fiber channel line cards, switches, and routers Gigabit Ethernet/PCIe support included Low jitter, low phase noise clock generation QUAD SFP PHY Figure 2. Typical Application Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009-2011 Analog Devices, Inc. All rights reserved. AD9572 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................9 Applications....................................................................................... 1 Pin Configuration and Function Descriptions........................... 10 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ........................................... 13 General Description ......................................................................... 1 Terminology .................................................................................... 15 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 16 Specifications..................................................................................... 3 Outputs ........................................................................................ 16 PLL Characteristics ...................................................................... 3 Phase Frequency Detector (PFD) and Charge Pump............ 17 LVDS Clock Output Jitter............................................................ 4 Power Supply............................................................................... 17 LVPECL Clock Output Jitter....................................................... 5 CMOS Clock Distribution ........................................................ 17 CMOS Clock Output Jitter.......................................................... 5 LVPECL Clock Distribution ..................................................... 18 Reference Input............................................................................. 5 LVDS Clock Distribution .......................................................... 18 Clock Outputs ............................................................................... 6 Reference Input........................................................................... 18 Timing Characteristics ................................................................ 6 Control Pins .................................................................................. 7 Power and Grounding Considerations and Power Supply Rejection...................................................................................... 19 Power.............................................................................................. 7 Outline Dimensions ....................................................................... 20 Crystal Oscillator.......................................................................... 7 Ordering Guide .......................................................................... 20 Timing Diagrams.............................................................................. 8 Absolute Maximum Ratings............................................................ 9 Thermal Resistance ...................................................................... 9 REVISION HISTORY /11--Rev. A to Rev. B Changes to Output Rise Time, tRC2 Parameter and Output Fall Time, tFC2 Parameter in Table 7....................................................... 6 11/10--Rev. 0 to Rev. A Changes to Features.......................................................................... 1 Changes to Table 2............................................................................ 4 Changes to Table 3 and Table 4....................................................... 5 Changes to Table 7............................................................................ 6 Added Figure 7 and Figure 8......................................................... 11 Added Figure 14, Figure 15, and Figure 16 ................................. 13 Deleted Original Figure 16 and Figure 19................................... 16 Renumbered Figures Sequentially............................... Throughout Changes to CMOS Clock Distribution Section.......................... 17 Changes to LVPECL Clock Distribution Section, Added Figure 23 and Figure 24 ................................................................. 18 Changes to LVDS Clock Distribution Section, Added Figure 26 .......................................................................................... 18 Changes to Reference Input Section ............................................ 18 Changes to Power and Grounding Considerations and Power Supply Rejection Section ............................................................... 19 7/09--Revision 0: Initial Version Rev. B | Page 2 of 20 AD9572 SPECIFICATIONS PLL CHARACTERISTICS Typical (typ) is given for VS = 3.3 V, TA = 25C, unless otherwise noted. Table 1. Parameter PHASE NOISE CHARACTERISTICS PLL Noise (106.25 MHz LVDS Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (156.25 MHz LVDS Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (125 MHz LVDS Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (100 MHz LVDS Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (106.25 MHz LVPECL Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (156.25 MHz LVPECL Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz Min Typ Max Unit Test Conditions/Comments -123 -127 -129 -150 -152 -153 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled -118 -125 -126 -145 -151 -151 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled -119 -127 -128 -147 -151 -152 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled -121 -128 -130 -147 -150 -150 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled -121 -128 -129 -151 -154 -155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled -119 -125 -126 -147 -152 -153 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled Rev. B | Page 3 of 20 AD9572 Parameter PLL Noise (125 MHz LVPECL Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (100 MHz LVPECL Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (33.33 MHz CMOS Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 5 MHz Phase Noise (25 MHz CMOS Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 5 MHz Spurious Content 1 PLL Figure of Merit 1 Min Typ Max Unit Test Conditions/Comments -122 -127 -128 -148 -152 -153 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled -122 -128 -130 -148 -150 -151 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled 33.33 MHz output disabled -130 -138 -139 -152 -152 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -133 -142 -148 -148 -148 -70 -217.5 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc dBc/Hz Dominant amplitude, all outputs active When the 33.33 MHz, 100 MHz, and 125 MHz clocks are enabled simultaneously, a worst-case -50 dBc spurious content might be presented on Pin 21 and Pin 22 only. LVDS CLOCK OUTPUT JITTER Typical (typ) is given for VS = 3.3 V, TA = 25C, unless otherwise noted. Table 2. Jitter Integration Bandwidth (Typ) 12 kHz to 20 MHz 100 MHz 0.51 106.25 MHz 0.44 125 MHz 33M = Off/On 1 0.42/0.88 1.875 MHz to 20 MHz 637 kHz to 10 MHz 200 kHz to 10 MHz 12 kHz to 35 MHz 1 156.25 MHz 0.42 Unit ps rms 0.19 ps rms 0.22 0.32 ps rms 0.25/0.78 ps rms 0.50 (off only) ps rms The typical 125 MHz rms jitter data is collected from the differential pair, Pin 21 and Pin 22, unless otherwise noted. Rev. B | Page 4 of 20 Test Conditions/Comments LVDS output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVDS output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVDS output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVDS output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVDS output frequency combinations are 1 x 156.25 MHz, 2 x 125 MHz, 2 x 106.25 MHz AD9572 LVPECL CLOCK OUTPUT JITTER Typical (typ) is given for VS = 3.3 V, TA = 25C, unless otherwise noted. Table 3. Jitter Integration Bandwidth (Typ) 12 kHz to 20 MHz (Typ) 100 MHz 0.61 106.25 MHz 0.45 12 kHz to 20 MHz (Max) 0.87 0.81 125 MHz 33M = Off/On 0.44/2.2 0.56 (off only) 1.875 MHz to 20 MHz (Typ) 637 kHz to 10 MHz (Typ) 200 kHz to 10 MHz (Typ) 156.25 MHz 0.46 Unit ps rms 0.56 ps rms 0.28 ps rms 0.23 0.38 12 kHz to 35 MHz (Typ) 12 kHz to 35 MHz (Max) ps rms 0.24/2.2 ps rms 0.52 (off only) 0.66 (off only) ps rms ps rms Test Conditions/Comments LVPECL output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVPECL output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVPECL output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVPECL output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVPECL output frequency combinations are 1 x 156.25 MHz, 1 x 100 MHz, 1 x 125 MHz, 2 x 106.25 MHz LVPECL output frequency combinations are 156.25 MHz unterminated, 2 x 125 MHz, 2 x 106.25 MHz LVPECL output frequency combinations are 156.25 MHz unterminated, 2 x 125 MHz, 2 x 106.25 MHz CMOS CLOCK OUTPUT JITTER Typical (typ) is given for VS = 3.3 V, TA = 25C, unless otherwise noted. Table 4. Jitter Integration Bandwidth 12 kHz to 5 MHz (Typ) 12 kHz to 5 MHz (Max) 200 kHz to 5 MHz (Typ) 200 kHz to 5 MHz (Max) 25 MHz 0.78 1.1 0.76 1.0 33.3 MHz 0.41 N/A 0.52 N/A Unit ps rms ps rms ps rms ps rms Test Conditions/Comments REFERENCE INPUT Typical (typ) is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (-40C to +85C) variation. Table 5. Parameter CLOCK INPUT (REFCLK) Input Frequency Input High Voltage Input Low Voltage Input Current Input Capacitance Min Typ Max 25 2.0 0.8 +1.0 -1.0 2 Rev. B | Page 5 of 20 Unit MHz V V A pF Test Conditions/Comments AD9572 CLOCK OUTPUTS Typical (typ) is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (-40C to +85C) variation. Table 6. Parameter LVPECL CLOCK OUTPUTS Output Frequency Output High Voltage (VOH) Output Low Voltage (VOL) Output Differential Voltage (VOD) Duty Cycle LVDS CLOCK OUTPUTS Output Frequency Differential Output Voltage (VOD) Delta VOD Output Offset Voltage (VOS) Delta VOS Short-Circuit Current (ISA, ISB) Duty Cycle CMOS CLOCK OUTPUTS Output Frequency Output High Voltage (VOH) Output Low Voltage (VOL) Duty Cycle Min Typ Max Unit VS - 1.24 VS - 2.07 700 45 VS - 1.05 VS - 1.87 825 156.25 VS - 0.83 VS - 1.62 950 55 MHz V V mV % 250 350 1.125 1.25 156.25 475 25 1.375 25 24 55 MHz mV mV V mV mA % 33.33 MHz V V % 14 45 VS - 0.1 0.1 58 42 Test Conditions/Comments Output shorted to GND Sourcing 1.0 mA current Sinking 1.0 mA current TIMING CHARACTERISTICS Typical (typ) is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (-40C to +85C) variation. Table 7. Parameter LVPECL Min Typ Max Unit Output Rise Time, tRP Output Fall Time, tFP LVDS 480 480 625 625 810 810 ps ps Output Rise Time, tRL Output Fall Time, tFL CMOS Output Rise Time, tRC 160 160 350 350 540 540 ps ps 0.25 0.50 2.5 ns Output Fall Time, tFC 0.25 0.70 2.5 ns Output Rise Time, tRC2 1.3 2.1 2.6 ns Output Fall Time, tFC2 1.4 2.3 3.0 ns Rev. B | Page 6 of 20 Test Conditions/Comments Termination = 200 to 0 V; CLOAD = 0 pF; CAC = 100 nF; oscilloscope set to 50 termination 20% to 80%, measured differentially 80% to 20%, measured differentially Termination = 100 differential; CLOAD = 0 pF; CAC = 100 nF; oscilloscope set to 50 termination 20% to 80%, measured differentially 80% to 20%, measured differentially 20% to 80%; termination = 50 to 0 V; CLOAD = 5 pF; CAC = 100 nF 80% to 20%; termination = 50 to 0 V; CLOAD = 5 pF; CAC = 100 nF 20% to 80%; active probe measurement, Cprobe = 1 pF, Rprobe=20 k, CLOAD = 3.9 pF 80% to 20%; active probe measurement, Cprobe = 1 pF, Rprobe=20 k, CLOAD = 3.9 pF AD9572 CONTROL PINS Typical (typ) is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (-40C to +85C) variation. Table 8. Parameter INPUT CHARACTERISTICS REFSEL Pin Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current FREQSEL Pin Logic 1 Voltage Min Typ Unit 0.8 1.0 155 V V A A Test Conditions/Comments REFSEL has a 30 k pull-up resistor. 2.0 FREQSEL has a 150 k pull-up resistor and a 100 k pull-down resistor. V 2/3(VS) + 0.2 Logic 0 Voltage Logic 1 Current Logic 0 Current FORCE_LOW Pin Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Max 1/3(VS) - 0.2 45 30 V A A FORCE_LOW has a 16 k pull-down resistor. 2.0 0.8 240 2.0 V V A A POWER Typical (typ) is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (-40C to +85C) variation. Table 9. Parameter Power Supply LVDS Power Dissipation LVPECL Power Dissipation Min 3.0 Typ 3.3 715 1075 Max 3.6 870 1305 Unit V mW mW Test Conditions/Comments CRYSTAL OSCILLATOR Typical (typ) is given for VS = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (-40C to +85C) variation. Table 10. Parameter CRYSTAL SPECIFICATION Frequency ESR Load Capacitance Phase Noise Stability Min Typ Max 25 50 14 -135 -30 +30 Unit MHz pF dBc/Hz ppm Rev. B | Page 7 of 20 Test Conditions/Comments Fundamental mode At 1 kHz offset AD9572 TIMING DIAGRAMS DIFFERENTIAL SINGLE-ENDED 80% 80% VOD CMOS 5pF LOAD 0% 20% 20% tFP tRC Figure 3. LVPECL Timing, Differential DIFFERENTIAL 80% VOD 0% 20% tFL 07498-023 LVDS tRL tFC Figure 5. CMOS Timing, Single-Ended, 5 pF Load Figure 4. LVDS Timing, Differential Rev. B | Page 8 of 20 07498-006 tRP 07498-022 LVPECL AD9572 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 11. Parameter VS to GND REFCLK to GND BYPASSx to GND XO to GND FREQSEL, FORCE_LOW, and REFSEL to GND 25M, 33M, 100M/125M, 106M, and 156M to GND Junction Temperature1 Storage Temperature Range 1 JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Thermal impedance measurements were taken on a 4-layer board in still air in accordance with EIA/JESD51-7. Rating -0.3 V to +3.6 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V Table 12. Thermal Resistance Package Type 40-Lead LFCSP -0.3 V to VS + 0.3 V ESD CAUTION 150C -65C to +150C See Table 12 for JA. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 9 of 20 JA 27.5 Unit C/W AD9572 40 39 38 37 36 35 34 33 32 31 VS VS * FORCE_LOW BYPASS1 VS GND VS 106M 106M PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR AD9572 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 106M 106M VS FREQSEL VS VS VS 33M 100M/125M 100M/125M NOTES 1. * = SHORT TO PIN 36. 2. ** = SHORT TO PIN 14. 3. NC = NO CONNECT. 4. NOTE THAT THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL CONNECTION AS WELL AS A THERMAL ENHANCEMENT. FOR THE DEVICE TO FUNCTION PROPERLY, THE PADDLE MUST BE ATTACHED TO GROUND (GND). 07498-007 VS ** ** BYPASS2 VS VS 156M 156M 100M/125M 100M/125M 11 12 13 14 15 16 17 18 19 20 GND 1 VS 2 NC 3 25M 4 VS 5 XO 6 XO 7 REFCLK 8 REFSEL 9 GND 10 Figure 6. Pin Configuration Table 13. Pin Function Descriptions 1 Pin No. 1, 10, 34 2 3 4 5 6, 7 8 9 11 12, 13 14, 36 15 16 17 18 19, 21 20, 22 23 24 25 26 27 28 29, 31 30, 32 Mnemonic GND VS NC 25M VS XO REFCLK REFSEL VS N/A BYPASS2, BYPASS1 VS VS 156M 156M 100M/125M 100M/125M 33M VS VS VS FREQSEL VS 106M 106M Description Ground. Includes external paddle (EPAD). Power Supply Connection for the 25M CMOS Buffer. No Connect. This pin should be left floating. CMOS 25 MHz Output. Power Supply Connection for the Crystal Oscillator. External 25 MHz Crystal. 25 MHz Reference Clock Input. Tie low when not in use. Logic Input. Used to select the reference source. Power Supply Connection for the GbE PLL. Short to Pin 14. These pins are for bypassing each LDO to ground with a 220 nF capacitor. Power Supply Connection for the GbE VCO. Power Supply Connection for the 156M LVDS Output Buffer and Output Dividers. LVPECL/LVDS Output at 156.25 MHz. Complementary LVPECL/LVDS Output at 156.25 MHz. LVPECL/LVDS Output at 100 MHz or 125 MHz. Selected by FREQSEL pin strapping. Complementary LVPECL/LVDS Output at 100 MHz or 125 MHz. CMOS 33.33 MHz Output. Power Supply Connection for the 33M CMOS Output Buffer and Output Dividers. Power Supply Connection for the 100M/125M LVDS Output Buffer and Output Dividers. Power Supply Connection for the GbE PLL Feedback Divider. Logic Input. Used to configure output drivers. Power Supply Connection for the FC PLL Feedback Divider. LVPECL/LVDS Output at 106.25 MHz. Complementary LVPECL/LVDS Output at 106.25 MHz. Rev. B | Page 10 of 20 AD9572 Pin No. 33 35 37 38 39 40 Description Power Supply Connection for the 106.25 MHz LVDS Output Buffer and Output Dividers. Power Supply Connection for the FC VCO. Forces the 33.33 MHz output into a low state. Short to Pin 36. Power Supply Connection for the FC PLL. Power Supply Connection for Miscellaneous Logic. The exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to ground (GND). 50 50 106M GND VS BYPASS1 FORCE_LOW CD RT = 100 106M 50 VS 106M 50 NC VS GND VS CD VS 0.22F CD VS 106M VS TEST VS CD VS VS VS CD = 100nF||10nF RT = 100 CD CD TO CMOS INPUT 50 VS CX = 22pF VS FREQSEL 25M VS VS CD CD AD9572 XO VS 25MHz XO VS CX = 22pF CD CD VS VS VS 50 REFCLK 33M REFSEL 100M/125M 50 GND 100M/125M 50 TO CMOS INPUT 100M/125M 100M/125M 50 50 VS RT = 100 RT = 100 Figure 7. Typical Application Schematic, LVDS Format Outputs, 1 x 25 MHz, 1 x 156.25 MHz, 2 x 125 MHz, and 2 x 106.25 MHz Rev. B | Page 11 of 20 07498-024 VS 156M 0.22F VS 50 CD 156M VS VS CD 50 CD BYPASS2 TEST TEST RT = 100 VS 1 Mnemonic VS VS FORCE_LOW N/A VS VS AD9572 VS VS CD = 100nF||10nF CD VS VS VS 0.22F CD CD VS 127 127 83 83 50 CD 50 VS 106M 50 NC VS CD CD 50 VS CX = 22pF VS VS 127 127 83 83 FREQSEL 25M VS VS CD CD AD9572 XO VS 25MHz XO VS CX = 22pF CD CD 100M/125M 100M/125M VS CD 50 VS 50 VS VS VS TO CMOS INPUT 127 83 VS VS 127 83 VS 127 127 83 83 50 0.22F VS 156M 50 156M 100M/125M VS GND BYPASS2 50 TEST 100M/125M TEST REFSEL VS 33M CD VS 50 REFCLK CD VS 50 VS 83 127 83 127 VS Figure 8. Typical Application Schematic, LPECL Format Outputs, 1 x 25 MHz, 1 x 156.25 MHz, 2 x 125 MHz, and 2 x 106.25 MHz Rev. B | Page 12 of 20 07498-025 TO CMOS INPUT VS 106M 106M VS GND VS BYPASS1 106M GND VS FORCE_LOW TEST VS VS 50 AD9572 TYPICAL PERFORMANCE CHARACTERISTICS -100 -100 -110 -110 PHASE NOISE (dBc/Hz) -120 -130 -140 -140 -150 10k 100k 1M 10M 100M FREQUENCY (Hz) -160 1k 07498-008 -160 1k -130 1M 10M 100M Figure 12. 156.25 MHz Phase Noise -100 -100 -110 -110 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) 100k FREQUENCY (Hz) Figure 9. 106.25 MHz Phase Noise -120 -130 -140 -150 -120 -130 -140 -150 10k 100k 1M 10M 100M FREQUENCY (Hz) -160 1k 07498-009 -160 1k 10k 07498-011 -150 -120 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 10. 125 MHz Phase Noise 07498-012 PHASE NOISE (dBc/Hz) Phase noise plots taken with 100 MHz and 125 MHz outputs enabled; 33.3 MHz output disabled. Figure 13. 100 MHz Phase Noise -100 500mV/DIV -120 -130 -140 -160 1k 10k 100k 1M FREQUENCY (Hz) Figure 11. 25 MHz Phase Noise 10M 100M 10ns/DIV 07498-026 -150 07498-010 PHASE NOISE (dBc/Hz) -110 Figure 14. 25 MHz CMOS Output, 3.9 pF Load Capacitance on Evaluation Board, Active-Probe Measurement, Rprobe=20 k, Cprobe=1 pF Rev. B | Page 13 of 20 2ns/DIV Figure 15. 156.25 MHz LVPECL Output, Differential Plot, 200 Termination to GND on Evaluation Board, AC-Coupled via 0.1 F Capacitors to Oscilloscope Set to 50 Input Termination 07498-028 100mV/DIV 2ns/DIV 07498-027 200mV/DIV AD9572 Figure 16. 125 MHz LVDS Output, Differential Plot, AC-Coupled via 0.1 F Capacitors to Oscilloscope Set to 50 Input Termination Rev. B | Page 14 of 20 AD9572 TERMINOLOGY Phase Jitter An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle. Actual signals, however, display a certain amount of variation from the ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as Gaussian (normal) in distribution. This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. Phase Noise When the total power contained within some interval of offset frequencies (for example, 12 kHz to 20 MHz) is integrated, it is called the integrated phase noise over that frequency offset interval, and it can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on error rate performance by increasing eye closure at the transmitter output and reducing the jitter tolerance/sensitivity of the receiver. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings is seen to vary. In a square wave, the time jitter is seen as a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the Gaussian distribution. Additive Phase Noise Additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. Additive Time Jitter Additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillator or clock source has been subtracted. This makes it possible to predict the degree to which the device will impact the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev. B | Page 15 of 20 AD9572 THEORY OF OPERATION REFSEL BYPASS1 VS GND VS XTAL OSC REFCLK CMOS 1 25M 0 PHASE FREQUENCY DETECTOR LDO DIVIDE BY 17 106.25MHz 106M 106M CHARGE PUMP DIVIDE BY 5 DIVIDE BY 4 LVPECL/ LVDS 106M VCO 106M VLDO LDO BYPASS2 DIVIDE BY 25 156.25MHz CHARGE PUMP DIVIDE BY 4 DIVIDE BY 4 LVPECL/ LVDS VCO VLDO DIVIDE BY 5 DIVIDE BY 4 0 1 125MHz/100MHz LVPECL/ LVDS LEVEL DECODE DIVIDE BY 5 0 1 156M 100M/125M 100M/125M FREQSEL 125MHz/100MHz LVPECL/ LVDS 100M/125M 100M/125M 33.33MHz DIVIDE BY 3 AD9572 156M 33M CMOS 07498-013 PHASE FREQUENCY DETECTOR FORCE_LOW Figure 17. Detailed Block Diagram Figure 17 shows a block diagram of the AD9572. The chip combines dual PLL cores, which are configured to generate the specific clock frequencies required for networking applications without any user programming. This PLL is based on proven Analog Devices synthesizer technology, noted for its exceptional phase noise performance. The AD9572 is highly integrated and includes loop filters, regulators for supply noise immunity, all the necessary dividers with multiple output buffers in a choice of formats, and a crystal oscillator. A user need only supply a 25 MHz reference clock or an external crystal to implement an entire line card clocking solution that does not require any processor intervention. A copy of the 25 MHz reference source is also available. OUTPUTS Table 14 provides a summary of the outputs available. Table 14. Output Formats Frequency 25 MHz 106.25 MHz 156.25 MHz 100 MHz or 125 MHz 33.33 MHz Format CMOS LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS CMOS Copies 1 2 1 2 1 Note that the pins labeled 100M/125M can provide 100 MHz or 125 MHz by strapping the FREQSEL pin as shown in Table 15. Rev. B | Page 16 of 20 AD9572 Table 15. FREQSEL (Pin 27) Definition Frequency Available from Pin 21 and Pin 22 (MHZ) 125 100 100 3.3V HIGH REFCLK D1 Q1 UP CHARGE PUMP CLR1 CP The simplified equivalent circuits of the LVDS and LVPECL outputs are shown in Figure 18 and Figure 19. 3.5mA HIGH CLR2 DOWN D2 Q2 FEEDBACK DIVIDER OUT GND OUTB 07498-016 FREQSEL 0 1 NC Frequency Available from Pin 19 and Pin 20 (MHZ) 125 100 125 frequency difference between them. Figure 20 shows a simplified schematic. Figure 20. PFD Simplified Schematic 07498-014 POWER SUPPLY 3.5mA The AD9572 requires a 3.3 V 10% power supply for VS. The tables in the Specifications section give the performance expected from the AD9572 with the power supply voltage within this range. The absolute maximum range of -0.3 V to +3.6 V, with respect to GND, must never be exceeded on the VS pin. Figure 18. LVDS Output Simplified Equivalent Circuit 3.3V Good engineering practice should be followed in the layout of power supply traces and the ground plane of the PCB. The power supply should be bypassed on the PCB with adequate capacitance (>10 F). The AD9572 should be bypassed with adequate capacitors (0.1 F) at all power pins as close as possible to the part. The layout of the AD9572 evaluation board is a good example. OUT GND 07498-015 OUTB Figure 19. LVPECL Output Simplified Equivalent Circuit The differential outputs are factory programmed to either LVPECL or LVDS format, and either option can be sampled on request. CMOS drivers tend to generate more noise than differential outputs and, as a result, the proximity of the 33.33 MHz output to Pin 21 and Pin 22 does affect the jitter performance when FREQSEL = 0 (that is, when the differential output is generating 125 MHz). For this reason, the 33 MHz pin can be forced to a low state by asserting the FORCE_LOW signal on Pin 37 (see Table 16). An internal pull-down enables the 33.33 MHz output if the pin is not connected. Table 16. FORCE_LOW (Pin 37) Definition FORCE_LOW 0 or NC 1 33.33 MHz Output (Pin 23) 33.33 MHz 0 PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The PFD takes inputs from the reference clock and feedback divider to produce an output proportional to the phase and The exposed metal paddle on the AD9572 package is an electrical connection, as well as a thermal enhancement. For the device to function properly, the paddle must be properly attached to ground (GND). The PCB acts as a heat sink for the AD9572; therefore, this GND connection should provide a good thermal path to a larger dissipation area, such as a ground plane on the PCB. CMOS CLOCK DISTRIBUTION The AD9572 provides two CMOS clock outputs (one 25 MHz and one 33.33 MHz) that are dedicated CMOS levels. Whenever single-ended CMOS clocking is used, some of the following general guidelines should be followed. Point-to-point nets should be designed such that a driver has one receiver only on the net, if possible. This allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the net. CMOS outputs are limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 6 inches are recommended to preserve signal rise/fall times and signal integrity. Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9572 do not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown in Figure 21. The far-end Rev. B | Page 17 of 20 AD9572 VTERM termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets. 50 50 LVPECL 50 200 07498-031 200 100 50 5pF Figure 24. LVPECL AC- Coupled Termination 07498-018 100 LVDS CLOCK DISTRIBUTION Figure 21. CMOS Output with Far-End Termination LVPECL CLOCK DISTRIBUTION The LVPECL outputs, which are open emitter, require a dc termination to bias the output transistors. The simplified equivalent circuit in Figure 19 shows the LVPECL output stage. In most applications, a standard LVPECL far-end termination is recommended, as shown in Figure 22. The resistor network is designed to match the transmission line impedance (50 ) and establish a dc bias of (VCC - 2 V). An alternative dc-coupled LVPECL termination network with a reduced number of components is also possible as shown in Figure 23. The AD9572 is also available with low voltage differential signaling (LVDS) outputs. LVDS uses a current mode output stage with a factory programmed current level. The normal value (default) for this current is 3.5 mA, which yields a 350 mV output swing across a 100 resistor. The LVDS outputs meet or exceed all ANSI/TIA/EIA-644 specifications. A recommended termination circuit for the LVDS outputs is shown in Figure 25. 50 100 LVDS LVDS 50 3.3V 07498-032 10 LVPECL 0.1F VPULLUP = 3.3V CMOS 50 0.1F Figure 25. LVDS Output Termination 3.3V 127 127 3.3V See the AN-586 Application Note on the Analog Devices website at www.analog.com for more information about LVDS. 50 SINGLE-ENDED (NOT COUPLED) LVPECL LVPECL REFERENCE INPUT 50 83 83 07498-029 VT = VCC - 2.0V VCC = 3.3V Figure 22. LVPECL Far-End Termination 50 LVPECL LVPECL 50 50 50 REFSEL 07498-030 50 By default, the crystal oscillator is enabled and used as the reference source, which requires the connection of an external 25 MHz crystal cut to resonate in fundamental mode. The total load capacitance presented to the oscillator should sum to 14 pF. In the example shown in Figure 26, parasitic trace capacitance of 1.5 pF, and an AD9572 input pin capacitance of 1.5 pF are assumed, with the series combination of the two 22 pF capacitances providing a further 11 pF. The REFSEL pin is pulled high internally by about 30 k to support default operation. 22pF XTAL OSC Figure 23. LVPECL Y Termination An ac- coupled LVPECL termination scheme is shown in Figure 24. TO PLLs 07498-033 22pF REFCLK Figure 26. Reference Input section When REFSEL is tied low, the crystal oscillator is powered down, and the REFCLK pin must provide a good quality 25 MHz reference clock instead. This single-ended input can be driven by either a dc-coupled LVCMOS level signal or an ac-coupled Rev. B | Page 18 of 20 AD9572 sine wave or square wave, provided that an external divider is used to bias the input at VS/2. Table 17. REFSEL (Pin 9) Definition REFSEL 0 1 Reference Source REFCLK input Internal crystal oscillator POWER AND GROUNDING CONSIDERATIONS AND POWER SUPPLY REJECTION Many applications seek high speed and performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the PCB is as important as the circuit design. Proper RF techniques must be used for device selection, placement, and routing, as well as for power supply bypassing and grounding to ensure optimum performance. Each power supply pin should have independent decoupling and connections to the power supply plane. It is recommended that the device exposed paddle be directly connected to the ground plane by a grid of at least nine vias. Care should be taken to ensure that the output traces cannot couple onto the reference or crystal input circuitry. Traces should not be routed under the crystal. Output signal traces should be kept on the top PCB layer; these traces have very high edge rates, and the use of PCB vias will result in signal integrity problems. Rev. B | Page 19 of 20 AD9572 OUTLINE DIMENSIONS 0.30 0.25 0.18 31 40 30 0.50 BSC 1 TOP VIEW 0.80 0.75 0.70 4.60 SQ 4.50 10 11 20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE *4.70 EXPOSED PAD 21 0.45 0.40 0.35 PIN 1 INDICATOR BOTTOM VIEW 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5 WITH EXCEPTION TO EXPOSED PAD DIMENSION. 02-02-2010-A PIN 1 INDICATOR 6.10 6.00 SQ 5.90 Figure 27. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 6 mm x 6 mm Body, Very Very Thin Quad (CP-40-7) Dimensions shown in millimeters ORDERING GUIDE Model1, 2, 3 AD9572ACPZLVD AD9572ACPZLVD-RL Temperature Range -40C to +85C -40C to +85C AD9572ACPZLVD-R7 -40C to +85C AD9572ACPZPEC AD9572ACPZPEC-RL -40C to +85C -40C to +85C AD9572ACPZPEC-R7 -40C to +85C AD9572-EVALZ-LVD AD9572-EVALZ-PEC Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 13" Tape and Reel, 2,500 Pieces 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 7" Tape and Reel, 750 Pieces 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 13" Tape and Reel, 2,500 Pieces 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 7" Tape and Reel, 750 Pieces Evaluation Board Evaluation Board 1 Z = RoHS Compliant Part. LVD indicates LVDS-compliant, differential clock outputs. 3 PEC indicates LVPECL-compliant, differential clock outputs. 2 (c)2009-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07498-0-4/11(B) Rev. B | Page 20 of 20 Package Option CP-40-7 CP-40-7 CP-40-7 CP-40-7 CP-40-7 CP-40-7