ADS1148IPWR - Texas Instruments - Datasheet.Directory

Input

Mux

3rdOrder

Modulator

REFP REFN

PGA

Burnout

Detect

Burnout

Detect

DVDD

DGND

ADS1146

AVSS

AIN0

AIN1

SCLK

DIN

DRDY

DOUT/DRDY

START

RESET

AVDD

InternalOscillator

Adjustable

Digital

Filter

Serial

Interface

and

Control

CLK

Input

Mux

3rdOrder

Modulator

REFP1 REFN1 VREFOUT VREFCOM

REFP0/

GPIO0

REFN0/

GPIO1

Burnout

Detect

Burnout

Detect

DVDD

DGND

IEXC1AVSS

AIN0/IEXC

AIN1/IEXC

AIN2/IEXC/GPIO2

AIN3/IEXC/GPIO3

AIN4/IEXC/GPIO4

AIN5/IEXC/GPIO5

AIN6/IEXC/GPIO6

AIN7/IEXC/GPIO7

ADS1148 Only

SCLK

DIN

DRDY

DOUT/DRDY

START

RESET

AVDD

IEXC2

InternalOscillator

Voltage

Reference

Serial

Interface

and

Control

VBIAS

GPIO

CLK

ADS1148 Only

ADS1147

ADS1148

PGA

System

Monitor

Adjustable

Digital

Filter

Dual

Current

DACs

VREFMux

ADS1148 Only

VBIAS

ADS1146

ADS1147

ADS1148

www.ti.com

SBAS453F –JULY 2009–REVISED APRIL 2012

16-Bit Analog-to-Digital Converters for Temperature Sensors

Check for Samples: ADS1146,ADS1147,ADS1148

1FEATURES DESCRIPTION

The ADS1146, ADS1147, and ADS1148 are highly-

23• 16 Bits, No Missing Codes integrated, precision, 16-bit analog-to-digital

• Data Output Rates Up to 2kSPS converters (ADCs). The ADS1146/7/8 feature an

• Single-Cycle Settling for All Data Rates onboard, low-noise, programmable gain amplifier

(PGA), a precision delta-sigma ADC with a single-

• Simultaneous 50/60Hz Rejection at 20SPS cycle settling digital filter, and an internal oscillator.

• 4 Differential/7 Single-Ended Inputs (ADS1148) The ADS1147 and ADS1148 also provide a built-in

• 2 Differential/3 Single-Ended Inputs (ADS1147) voltage reference with 10mA output capacity, and two

matched programmable current digital-to-analog

• Matched Current Source DACs converters (DACs). The ADS1146/7/8 provide a

• Internal Voltage Reference complete front-end solution for temperature sensor

• Sensor Burnout Detection applications including thermal couples, thermistors,

and resistance temperature detectors (RTDs).

• 4/8 General-Purpose I/Os (ADS1147/8)

• Internal Temperature Sensor An input multiplexer supports four differential inputs

for the ADS1148, two for the ADS1147, and one for

• Power Supply and VREF Monitoring the ADS1146. In addition, the multiplexer has a

(ADS1147/8) sensor burnout detect, voltage bias for

• Self and System Calibration thermocouples, system monitoring, and general-

• SPI™-Compatible Serial Interface purpose digital I/Os (ADS1147 and ADS1148). The

onboard, low-noise PGA provides selectable gains of

• Analog Supply Operation: 1 to 128. The delta-sigma modulator and adjustable

+2.7V to +5.25V Unipolar, ±2.5V Bipolar digital filter settle in only one cycle, for fast channel

• Digital Supply: +2.7V to +5.25V cycling when using the input multiplexer, and support

• Operating Temperature –40°C to +125°C data rates up to 2kSPS. For data rates of 20SPS or

less, both 50Hz and 60Hz interference are rejected

by the filter.

APPLICATIONS

• Temperature Measurement The ADS1146 is offered in a small TSSOP-16

package, the ADS1147 is available in a TSSOP-20

– RTDs, Thermocouples, and Thermistors package, and the ADS1148 is available in TSSOP-28

• Pressure Measurement and QFN-32 packages. All three devices operate over

• Industrial Process Control the extended specified temperature range of –40°C to

+105°C.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI is a trademark of Motorola, Inc.

3All other trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADS1146

ADS1147

ADS1148

SBAS453F –JULY 2009–REVISED APRIL 2012

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION(1)

DUAL SENSOR

EXCITATION

NUMBER OF VOLTAGE CURRENT PACKAGE-

PRODUCT RESOLUTION INPUTS REFERENCE SOURCES LEAD

1 Differential

ADS1246 24 bits or External NO TSSOP-16

1 Single-Ended

2 Differential

ADS1247 24 bits or Internal or External YES TSSOP-20

3 Single-Ended

4 Differential

ADS1248 24 bits or Internal or External YES TSSOP-28

7 Single-Ended

1 Differential

ADS1146 16 bits or External NO TSSOP-16

1 Single-Ended

2 Differential

ADS1147 16 bits or Internal or External YES TSSOP-20

3 Single-Ended

4 Differential

16 bits or Internal or External YES TSSOP-28

7 Single-Ended

ADS1148 4 Differential

16 bits or Internal or External YES QFN-32

7 Single-Ended

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder on www.ti.com.

ABSOLUTE MAXIMUM RATINGS(1)

Over operating free-air temperature range, unless otherwise noted. ADS1146, ADS1147, ADS1148 UNIT

AVDD to AVSS –0.3 to +5.5 V

AVSS to DGND –2.8 to +0.3 V

DVDD to DGND –0.3 to +5.5 V

100, momentary mA

Input current 10, continuous mA

Analog input voltage to AVSS AVSS – 0.3 to AVDD + 0.3 V

Digital input voltage to DGND –0.3 to DVDD + 0.3 V

Maximum junction temperature +150 °C

Operating temperature range –40 to +125 °C

Storage temperature range –60 to +150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-

maximum-rated conditions for extended periods may affect device reliability.

(V )(Gain)

AVSS 0.1V+ +

AVDD 0.1V- - (V )(Gain)

ADS1146

ADS1147

ADS1148

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SBAS453F –JULY 2009–REVISED APRIL 2012

ELECTRICAL CHARACTERISTICS

Minimum/maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications at

AVDD = +5V, DVDD = +3.3V, AVSS = DGND = 0V, VREF = +2.048V, and oscillator frequency = 4.096MHz, unless otherwise

noted. ADS1146, ADS1147, ADS1148

PARAMETER CONDITIONS MIN TYP MAX UNIT

ANALOG INPUTS

Full-scale input voltage ±VREF/PGA(1) V

(VIN = ADCINP – ADCINN)

Common-mode input range V

Differential input current 100 pA

1, 2, 4, 8, 16, 32,

PGA gain settings 64, 128

Burnout current source 0.5, 2, or 10 μA

Bias voltage (AVDD + AVSS)/2 V

Bias voltage output impedance 400 Ω

SYSTEM PERFORMANCE

Resolution No missing codes 16 Bits

5, 10, 20, 40, 80,

Data rate 160, 320, 640, SPS

1000, 2000

Integral nonlinearity (INL) Differential input, end point fit, PGA = 1 ±0.5 ±1 LSB

Offset error After calibration 1 LSB

PGA = 1 100 nV/°C

Offset drift PGA = 128 15 nV/°C

Gain error Excluding VREF errors ±0.5 %

PGA = 1, excludes VREF drift 1 ppm/°C

Gain drift PGA = 128, excludes VREF drift –3.5 ppm/°C

ADC conversion time Single-cycle settling See Table 12

Noise See Table 1 and Table 2

Normal-mode rejection See Table 5

At dc, PGA = 1 90 dB

Common-mode rejection At dc, PGA = 32 100 dB

Power-supply rejection AVDD, DVDD at dc 100 dB

VOLTAGE REFERENCE INPUT

Voltage reference input (AVDD –

0.5 V

(VREF = VREFP – VREFN) AVSS) – 1

Negative reference input (REFN) AVSS – 0.1 REFP – 0.5 V

Positive reference input (REFP) REFN + 0.5 AVDD + 0.1 V

Reference input current 30 nA

ON-CHIP VOLTAGE REFERENCE

Output voltage 2.038 2.048 2.058 V

Output current(2) ±10 mA

Load regulation 50 μV/mA

Drift(3) TA= –40°C to +105°C 20 50 ppm/°C

Startup time See Table 6 μs

(1) For VREF > 2.7V, the analog input differential voltage should not exceed 2.7V/PGA

(2) Do not exceed this loading on the internal voltage reference.

(3) Specified by the combination of design and final production test.

ADS1146

ADS1147

ADS1148

SBAS453F –JULY 2009–REVISED APRIL 2012

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

Minimum/maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications at

AVDD = +5V, DVDD = +3.3V, AVSS = DGND = 0V, VREF = +2.048V, and oscillator frequency = 4.096MHz, unless otherwise

noted. ADS1146, ADS1147, ADS1148

PARAMETER CONDITIONS MIN TYP MAX UNIT

CURRENT SOURCES (IDACS)

50, 100, 250,

Output current 500, 750, 1000, μA

1500

Voltage compliance All currents AVDD – 0.7 V

Initial error All currents, each IDAC –6 ±1.0 6 % of FS

Initial mismatch All currents, between IDACs ±0.03 % of FS

Temperature drift Each IDAC 200 ppm/°C

Temperature drift matching Between IDACs 10 ppm/°C

SYSTEM MONITORS

Voltage TA= +25°C 118 mV

Temperature

sensor reading Drift 405 μV/°C

GENERAL-PURPOSE INPUT/OUTPUT (GPIO)

VIH 0.7AVDD AVDD V

VIL AVSS 0.3AVDD V

Logic levels VOH IOH = 1mA 0.8AVDD V

VOL IOL = 1mA AVSS 0.2 AVDD V

DIGITAL INPUT/OUTPUT (other than GPIO)

VIH 0.7DVDD DVDD V

VIL DGND 0.3DVDD V

Logic levels VOH IOH = 1mA 0.8DVDD V

VOL IOL = 1mA DGND 0.2 DVDD V

Input leakage DGND < VDIGITAL IN < DVDD ±10 μA

Frequency 1 4.5 MHz

Clock input

(CLK) Duty cycle 25 75 %

Internal oscillator frequency 3.89 4.096 4.3 MHz

POWER SUPPLY

DVDD 2.7 5.25 V

AVSS –2.5 0 V

AVDD AVSS + 2.7 AVSS + 5.25 V

Normal mode, DVDD = 5V, 230 μA

data rate = 20SPS, internal oscillator

DVDD current Normal mode, DVDD = 3.3V, 210 μA

data rate = 20SPS, internal oscillator

Sleep mode 0.2 µA

Converting, AVDD = 5V, 225 µA

data rate = 20SPS, external reference

Converting, AVDD = 3.3V, 212 µA

data rate = 20SPS, external reference

AVDD current Sleep mode 0.1 µA

Additional current with internal reference 180 μA

enabled

AVDD = DVDD = 5V, data rate = 20SPS, 2.3 mW

external reference, internal oscillator

Power dissipation AVDD = DVDD = 3.3V, data rate = 20SPS, 1.4 mW

external reference, internal oscillator

TEMPERATURE RANGE

Specified –40 +105 °C

Operating –40 +125 °C

Storage –60 +150 °C

ADS1146

ADS1147

ADS1148

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SBAS453F –JULY 2009–REVISED APRIL 2012

THERMAL INFORMATION ADS1146,

ADS1147,

ADS1148

THERMAL METRIC(1) UNITS

θJA Junction-to-ambient thermal resistance(2) 79.5

θJC(top) Junction-to-case(top) thermal resistance (3) 31.8

θJB Junction-to-board thermal resistance (4) 40.9 °C/W

ψJT Junction-to-top characterization parameter (5) 3.0

ψJB Junction-to-board characterization parameter (6) 41.1

θJC(bottom) Junction-to-case(bottom) thermal resistance (7) n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Product Folder Link(s): ADS1146 ADS1147 ADS1148

DIN

SCLK

DVDD

DGND

AIN3/IEXC/GPIO3

AIN2/IEXC/GPIO2

AIN7/IEXC/GPIO7

AIN6/IEXC/GPIO6

AIN5/IEXC/GPIO5

AIN4/IEXC/GPIO4

AIN1/IEXC

AIN0/IEXC

DOUT/DRDY

CLK

DRDY

RESET

REFP0/GPIO0

START

REFN0/GPIO1

AVDD

REFP1

AVSS

REFN1

IEXC1

VREFOUT

IEXC2

VREFCOM

ADS1146

ADS1147

ADS1148

SBAS453F –JULY 2009–REVISED APRIL 2012

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PIN CONFIGURATIONS

RHB PACKAGE

QFN-32

(TOP VIEW)

Product Folder Link(s): ADS1146 ADS1147 ADS1148

ADS1146

ADS1147

ADS1148

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SBAS453F –JULY 2009–REVISED APRIL 2012

ADS1148 (QFN-32) PIN DESCRIPTIONS

NAME PIN NO. FUNCTION DESCRIPTION

DIN 1 Digital input Serial data input

SCLK 2 Digital input Serial clock input

NC 3 Not connected Pin can be grounded or left disconnected

NC 4 Not connected Pin can be grounded or left disconnected

NC 5 Not connected Pin can be grounded or left disconnected

NC 6 Not connected Pin can be grounded or left disconnected

DVDD 7 Digital Digital power supply

DGND 8 Digital Digital ground

CLK 9 Digital input External clock input. Tie this pin to DGND to activate the internal oscillator.

RESET 10 Digital input Chip reset (active low). Returns all register values to reset values.

Analog input;

REFP0/GPIO0 11 Positive external reference input 0, or general-purpose digital input/output pin 1

Digital in/out

Analog input;

REFN0/GPIO1 12 Negative external reference input 0, or general-purpose digital input/output pin 1

Digital in/out

REFP1 13 Analog input Positive external reference 1 input

REFN1 14 Analog input Negative external reference 1 input

VREFOUT 15 Analog output Positive internal reference voltage output

Negative internal reference voltage output. Connect this pin to AVSS when using a unipolar

VREFCOM 16 Analog output supply, or to the midvoltage of the power supply when using a bipolar supply.

AIN0/IEXC 17 Analog input Analog input 0, optional excitation current output

AIN1/IEXC 18 Analog input Analog input 1, optional excitation current output

Analog input;

AIN4/IEXC/GPIO4 19 Analog input 4, optional excitation current output, or general-purpose digital input/output pin 4

Digital in/out

Analog input;

AIN5/IEXC/GPIO5 20 Analog input 5, optional excitation current output, or general-purpose digital input/output pin 5

Digital in/out

Analog input;

AIN6/IEXC/GPIO6 21 Analog input 6, optional excitation current output, or general-purpose digital input/output pin 6

Digital in/out

Analog input;

AIN7/IEXC/GPIO7 22 Analog input 7, optional excitation current output, or general-purpose digital input/output pin 7

Digital in/out

Analog input;

AIN2/IEXC/GPIO2 23 Analog input 2, optional excitation current output, or general-purpose digital input/output pin 2

Digital in/out

Analog input;

AIN3/IEXC/GPIO3 24 Analog input 3, optional excitation current output, or general-purpose digital input/output pin 3

Digital in/out

IEXC2 25 Analog output Excitation current output 2

IEXC1 26 Analog output Excitation current output 1

AVSS 27 Analog Negative analog power supply

AVDD 28 Analog Positive analog power supply

START 29 Digital input Conversion start. See text for complete description.

Digital input Chip

CS 30 Chip select (active low)

select (active low)

DRDY 31 Digital output Data ready (active low)

Serial data output, or data out combined with data ready (active low when DRDY function

DOUT/DRDY 32 Digital output enabled)

Product Folder Link(s): ADS1146 ADS1147 ADS1148

DVDD

DGND

CLK

RESET

REFP

REFN

AINP

AINN

SCLK

DIN

DOUT/DRDY

DRDY

START

AVDD

AVSS

ADS1146

ADS1147

ADS1148

SBAS453F –JULY 2009–REVISED APRIL 2012

www.ti.com

PW PACKAGE

TSSOP-16

(TOP VIEW)

ADS1146 (TSSOP-16) PIN DESCRIPTIONS

NAME PIN NO. FUNCTION DESCRIPTION

DVDD 1 Digital Digital power supply

DGND 2 Digital Digital ground

CLK 3 Digital input External clock input. Tie this pin to DGND to activate the internal oscillator.

RESET 4 Digital input Chip reset (active low). Returns all register values to reset values.

REFP 5 Analog input Positive external reference input

REFN 6 Analog input Negative external reference input

AINP 7 Analog input Positive analog input

AINN 8 Analog input Negative analog input

AVSS 9 Analog Negative analog power supply

AVDD 10 Analog Positive analog power supply

START 11 Digital input Conversion start. See text for description of use.

CS 12 Digital input Chip select (active low)

DRDY 13 Digital output Data ready (active low)

Serial data out output, or

DOUT/DRDY 14 Digital output data out combined with data ready (active low when DRDY function enabled)

DIN 15 Digital input Serial data input

SCLK 16 Digital input Serial clock input

Product Folder Link(s): ADS1146 ADS1147 ADS1148

DVDD

DGND

CLK

RESET

REFP0/GPIO0

REFN0/GPIO1

VREFOUT

VREFCOM

AIN0/IEXC

AIN1/IEXC

SCLK

DIN

DOUT/DRDY

DRDY

START

AVDD

AVSS

AIN3/IEXC/GPIO3

AIN2/IEXC/GPIO2

ADS1147

ADS1146

ADS1147

ADS1148

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SBAS453F –JULY 2009–REVISED APRIL 2012

PW PACKAGE

TSSOP-20

(TOP VIEW)

ADS1147 (TSSOP-20) PIN DESCRIPTIONS

NAME PIN NO. FUNCTION DESCRIPTION

DVDD 1 Digital Digital power supply

DGND 2 Digital Digital ground

CLK 3 Digital input External clock input. Tie this pin to DGND to activate the internal oscillator.

RESET 4 Digital input Chip reset (active low). Returns all register values to reset values.

Analog input Positive external reference input, or

REFP0/GPIO0 5 Digital in/out general-purpose digital input/output pin 0

Analog input Negative external reference input, or

REFN0/GPIO1 6 Digital in/out general-purpose digital input/output pin 1

VREFOUT 7 Analog output Positive internal reference voltage output

Negative internal reference voltage output. Connect this pin to AVSS when using a unipolar

VREFCOM 8 Analog output supply, or to the midvoltage of the power supply when using a bipolar supply.

AIN0/IEXC 9 Analog input Analog input 0, optional excitation current output

AIN1/IEXC 10 Analog input Analog input 1, optional excitation current output

Analog input Analog input 2, optional excitation current output, or

AIN2/IEXC/GPIO2 11 Digital in/out general-purpose digital input/output pin 2

Analog input Analog input 3, with or without excitation current output, or

AIN3/IEXC/GPIO3 12 Digital in/out general-purpose digital input/output pin 3

AVSS 13 Analog Negative analog power supply

AVDD 14 Analog Positive analog power supply

START 15 Digital input Conversion start. See text for description of use.

CS 16 Digital input Chip select (active low)

DRDY 17 Digital output Data ready (active low)

Serial data out output, or

DOUT/DRDY 18 Digital output data out combined with data ready (active low when DRDY function enabled)

DIN 19 Digital input Serial data input

SCLK 20 Digital input Serial clock input

Product Folder Link(s): ADS1146 ADS1147 ADS1148

DVDD

DGND

CLK

RESET

REFP0/GPIO0

REFN0/GPIO1

REFP1

REFN1

VREFOUT

VREFCOM

AIN0/IEXC

AIN1/IEXC

AIN4/IEXC/GPIO4

AIN5/IEXC/GPIO5

SCLK

DIN

DOUT/DRDY

DRDY

START

AVDD

AVSS

IEXC1

IEXC2

AIN3/IEXC/GPIO3

AIN2/IEXC/GPIO2

AIN7/IEXC/GPIO7

AIN6/IEXC/GPIO6

ADS1148

ADS1146

ADS1147

ADS1148

SBAS453F –JULY 2009–REVISED APRIL 2012

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PW PACKAGE

TSSOP-28

(TOP VIEW)

Product Folder Link(s): ADS1146 ADS1147 ADS1148

ADS1146

ADS1147

ADS1148

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SBAS453F –JULY 2009–REVISED APRIL 2012

ADS1148 (TSSOP-28) PIN DESCRIPTIONS

NAME PIN NO. FUNCTION DESCRIPTION

DVDD 1 Digital Digital power supply

DGND 2 Digital Digital ground

CLK 3 Digital input External clock input. Tie this pin to DGND to activate the internal oscillator.

RESET 4 Digital input Chip reset (active low). Returns all register values to reset values.

REFP0/GPIO0 5 Analog input Positive external reference input 0, or general-purpose digital input/output pin 0

REFN0/GPIO1 6 Analog input Negative external reference 0 input, or general-purpose digital input/output pin 1

REFP1 7 Analog input Positive external reference 1 input

REFN1 8 Analog input Negative external reference 1 input

VREFOUT 9 Analog output Positive internal reference voltage output

Negative internal reference voltage output. Connect this pin to AVSS when using a unipolar

VREFCOM 10 Analog output supply, or to the midvoltage of the power supply when using a bipolar supply.

AIN0/IEXC 11 Analog input Analog input 0, optional excitation current output

AIN1/IEXC 12 Analog input Analog input 1, optional excitation current output

Analog input

AIN4/IEXC/GPIO4 13 Analog input 4, optional excitation current output, or general-purpose digital input/output pin 4

Digital in/out

Analog input

AIN5/IEXC/GPIO5 14 Analog input 5, optional excitation current output, or general-purpose digital input/output pin 5

Digital in/out

Analog input

AIN6/IEXC/GPIO6 15 Analog input 6, optional excitation current output, or general-purpose digital input/output pin 6

Digital in/out

Analog input

AIN7/IEXC/GPIO7 16 Analog input 7, optional excitation current output, or general-purpose digital input/output pin 7

Digital in/out

Analog input

AIN2/IEXC/GPIO2 17 Analog input 2, optional excitation current output, or general-purpose digital input/output pin 2

Digital in/out

Analog input

AIN3/IEXC/GPIO3 18 Analog input 3, optional excitation current output, or general-purpose digital input/output pin 3

Digital in/out

IEXC2 19 Analog output Excitation current output 2

IEXC1 20 Analog output Excitation current output 1

AVSS 21 Analog Negative analog power supply

AVDD 22 Analog Positive analog power supply

START 23 Digital input Conversion start. See text for complete description.

CS 24 Digital input Chip select (active low)

DRDY 25 Digital output Data ready (active low)

Serial data out output, or data out combined with data ready (active low when DRDY function

DOUT/DRDY 26 Digital output enabled)

DIN 27 Digital input Serial data input

SCLK 28 Digital input Serial clock input

Product Folder Link(s): ADS1146 ADS1147 ADS1148

SCLK

DOUT[7] DOUT[6] DOUT[5] DOUT[4] DOUT[1] DOUT[0]

DIN[0] DIN[7] DIN[6] DIN[5] DIN[4] DIN[1] DIN[0]

DOUT/ (1)

DRDY

DIN

tCSSC

tDIST tDIHD

tSCLK tSCCS

tCSDO

tDOPD

tSPWL

tSPWH

tDOHD

tCSPW

SCLK(3)

1 2 3 87654

DRDY

tSTD

tDTS

tPWH

ADS1146

ADS1147

ADS1148

SBAS453F –JULY 2009–REVISED APRIL 2012

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TIMING DIAGRAMS

Figure 1. Serial Interface Timing

Timing Characteristics for Figure 1(1)

SYMBOL DESCRIPTION MIN MAX UNIT

tCSSC CS low to first SCLK high (set up time) 10 ns

tSCCS SCLK low to CS high (hold time) 7 tOSC (2)

tDIST DIN set up time 5 ns

tDIHD DIN hold time 5 ns

tDOPD SCLK rising edge to new data valid 50(3) ns

tDOHD DOUT hold time 0 ns

500 ns

tSCLK SCLK period 64 conversions

tSPWH SCLK pulse width high 0.25 0.75 tSCLK

tSPWL SCLK pulse width low 0.25 0.75 tSCLK

tCSDO CS high to DOUT high impedance 10 ns

tCSPW Chip Select high pulse width 5 tOSC

(1) DRDY MODE bit = 0.

(2) tOSC = 1/fCLK. The default clock frequency fCLK = 4.096MHz.

(3) For DVDD > 3.6V, tDOPD = 180ns.

Figure 2. SPI Interface Timing to Allow Conversion Result Loading(4)(5)

Timing Characteristics for Figure 2

SYMBOL DESCRIPTION MIN MAX UNIT

tPWH DRDY pulse width high 3 tOSC

tS TD SCLK low prior to DRDY low 5 tOSC

tDTS DRDY falling edge to SCLK rising edge 1/fCLK ns

(4) This timing diagram is applicable only when the CS pin is low. SCLK need not be low during tSTD when CS is high.

(5) SCLK should only be sent in multiples of eight during partial retrieval of output data.

Product Folder Link(s): ADS1146 ADS1147 ADS1148

tSTART

START

SCLK

RESET

tRESET

tRHSC

ADS1146

ADS1147

ADS1148

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SBAS453F –JULY 2009–REVISED APRIL 2012

Figure 3. Minimum START Pulse Width

Timing Characteristics for Figure 3

SYMBOL DESCRIPTION MIN MAX UNIT

tSTART START pulse width high 3 tOSC

Figure 4. Reset Pulse Width and SPI Communication After Reset

Timing Characteristics for Figure 4

SYMBOL DESCRIPTION MIN MAX UNIT

tRESET RESET pulse width low 4 tOSC

tRHSC RESET high to SPI communication start 0.6(1) ms

(1) For fOSC = 4.096MHz, scales proportionately with fOSC frequency.

Product Folder Link(s): ADS1146 ADS1147 ADS1148

ADS1146

ADS1147

ADS1148

SBAS453F –JULY 2009–REVISED APRIL 2012

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NOISE PERFORMANCE

The ADS1146/7/8 noise performance can be optimized by adjusting the data rate and PGA setting. As the

averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value

reduces the input-referred noise, particularly useful when measuring low-level signals. Table 1 and Table 2

summarize noise performance of the ADS1146/7/8. The data are representative of typical noise performance at

T = +25°C. The data shown are the result of averaging the readings from multiple devices and were measured

with the inputs shorted together.

Table 1 lists the input-referred noise in units μVPP. In many of the settings, especially at lower data rates, the

inherent device noise is less than 1LSB. For these cases, the noise is rounded up to 1LSB. Table 2 lists the

corresponding data in units of ENOB (effective number of bits) where:

ENOB = ln(Full-Scale Range/Noise)/ln(2) (1)

Table 1. Noise in μVPP

At VREF = 2.048V, AVDD = 5V, and AVSS = 0V

PGA SETTING

DATA RATE

(SPS) 1 2 4 8 16 32 64 128

5 62.50(1) 31.25(1) 15.63(1) 7.81(1) 3.91(1) 1.95(1) 0.98(1) 0.49(1)

10 62.50(1) 31.25(1) 15.63(1) 7.81(1) 3.91(1) 1.95(1) 0.98(1) 0.49(1)

20 62.50(1) 31.25(1) 15.63(1) 7.81(1) 3.91(1) 1.95(1) 0.98(1) 0.55

40 62.50(1) 31.25(1) 15.63(1) 7.81(1) 3.91(1) 1.95(1) 0.98(1) 0.75

80 62.50(1) 31.25(1) 15.63(1) 7.81(1) 3.91(1) 1.95(1) 1.09 0.98

160 62.50(1) 31.25(1) 15.63(1) 7.81(1) 3.91(1) 1.95(1) 1.88 1.57

320 62.50(1) 35.30 17.52 8.86 4.35 3.03 2.44 2.34

640 93.06 45.20 18.73 12.97 6.51 4.20 3.69 3.50

1000 284.59 129.77 61.30 33.04 16.82 9.08 5.42 4.65

2000 273.39 130.68 67.13 36.16 19.22 9.87 6.93 6.48

(1) Peak-to-peak noise rounded up to 1LSB.

Table 2. Effective Number of Bits From Peak-to-Peak Noise

At VREF = 2.048V, AVDD = 5V, and AVSS = 0V

PGA SETTING

DATA RATE

(SPS) 1 2 4 8 16 32 64 128

5 16 16 16 16 16 16 16 16

10 16 16 16 16 16 16 16 16

20 16 16 16 16 16 16 16 15.8

40 16 16 16 16 16 16 16 15.4

80 16 16 16 16 16 16 15.8 15.0

160 16 16 16 16 16 16 15.1 14.3

320 16 15.8 15.8 15.8 15.8 15.4 14.7 13.7

640 15.4 15.5 15.7 15.3 15.3 14.9 14.1 13.2

1000 13.8 13.9 14.0 13.9 13.9 13.8 13.5 12.7

2000 13.9 13.9 13.9 13.8 13.7 13.7 13.2 12.3

Product Folder Link(s): ADS1146 ADS1147 ADS1148

330

310

290

270

250

230

210

190

Temperature( C)°

DigitalCurrent( A)m

-40 -20 0 20 40 60 80 100 120

5/10/20SPS

40/80/160SPS

320/640/1kSPS

2kSPS

DVDD=5V

800

700

600

500

400

300

200

100

Temperature( C)°

AnalogCurrent( A)m

-40 -20 0 20 40 60 80 100 120

5/10/20SPS

40/80/160SPS

320/640/1kSPS

2kSPS

AVDD=5V

700

600

500

400

300

200

100

Temperature( C)°

AnalogCurrent( A)m

-40 -20 0 20 40 60 80 100 120

5/10/20SPS

40/80/160SPS

320/640/1kSPS

2kSPS

AVDD=3.3V

310

290

270

250

230

210

190

Temperature( C)°

DigitalCurrent( A)m

-40 -20 0 20 40 60 80 100 120

5/10/20SPS

40/80/160SPS

320/640/1kSPS

2kSPS

DVDD=3.3V

600

550

500

450

400

350

300

250

200

150

100

DataRate(SPS)

AnalogCurrent( A)m

5 10 20 40 80 160 320 640 1000 2000

AVDD=5V

AVDD=3.3V

290

270

250

230

210

190

170

DataRate(SPS)

DigitalCurrent( A)m

5 10 20 40 80 160 320 640 1000 2000

DVDD=3.3V

DVDD=5V

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ADS1147

ADS1148

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SBAS453F –JULY 2009–REVISED APRIL 2012

TYPICAL CHARACTERISTICS

At TA= +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.

ANALOG CURRENT DIGITAL CURRENT

vs TEMPERATURE vs TEMPERATURE

Figure 5. Figure 6.

ANALOG CURRENT vs TEMPERATURE DIGITAL CURRENT vs TEMPERATURE

Figure 7. Figure 8.

ANALOG CURRENT vs DATA RATE DIGITAL CURRENT vs DATA RATE

Figure 9. Figure 10.

Product Folder Link(s): ADS1146 ADS1147 ADS1148

1.002

1.001

1.000

0.999

0.998

0.997

0.996

0.995

0.994

0.993

0.992

0.991

AVDD(V)

NormalizedOutputCurrent

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

750 Am

250 Am

1.5mA

500 Am

100 Am

1mA

50 Am

IDACCurrentSettings

3.0

2.5

2.0

1.5

1.0

0.5

1.0

1.5

2.0

2.5

3.0

Temperature( C)°

DataRateError(%)

-40 -20 0 20 40 60 80 100 120

DVDD=5V

DVDD=3.3V

−120

−100

−80

−60

−40

−20

0 200 400 600 800 1000

Time (hours)

Reference Drift (ppm)

32 Units

G000

0.004

0.003

0.002

0.001

-0.001

-0.002

-0.003

-0.004

Temperature( C)°

IEXC1 IEXC2(- mA)

-40 -20 0 20 40 60 80 100 120

1.5mASetting,10Units

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

0 1 2 3 4 5

Voltage (V)

Normalized IDAC Current

50µA

100µA

250µA

500µA

750µA

1mA

1.5mA

0.98

0.985

0.99

0.995

1.005

1.01

0 1 2 3 4 5

Voltage (V)

Normalized IDAC Current

ADS1146

ADS1147

ADS1148

SBAS453F –JULY 2009–REVISED APRIL 2012

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TYPICAL CHARACTERISTICS (continued)

At TA= +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.

DATA RATE ERROR vs TEMPERATURE IDAC LINE REGULATION

Figure 11. Figure 12.

IDAC DRIFT INTERNAL REFERENCE LONG TERM DRIFT

Figure 13. Figure 14.

IDAC VOLTAGE COMPLIANCE IDAC VOLTAGE COMPLIANCE

Figure 15. Figure 16.

Product Folder Link(s): ADS1146 ADS1147 ADS1148

Input

Mux

3rdOrder

Modulator

REFP REFN

PGA

Burnout

Detect

Burnout

Detect

DVDD

DGND

ADS1146

AVSS

AIN0

AIN1

SCLK

DIN

DRDY

DOUT/DRDY

START

RESET

AVDD

InternalOscillator

Adjustable

Digital

Filter

Serial

Interface

and

Control

CLK

VBIAS

Input

Mux

3rdOrder

Modulator

REFP1 REFN1 VREFOUT VREFCOM

REFP0/

GPIO0

REFN0/

GPIO1

Burnout

Detect

Burnout

Detect

DVDD

DGND

IEXC1AVSS

AIN0/IEXC

AIN1/IEXC

AIN2/IEXC/GPIO2

AIN3/IEXC/GPIO3

AIN4/IEXC/GPIO4

AIN5/IEXC/GPIO5

AIN6/IEXC/GPIO6

AIN7/IEXC/GPIO7

ADS1148 Only

SCLK

DIN

DRDY

DOUT/DRDY

START

RESET

AVDD

IEXC2

InternalOscillator

Voltage

Reference

Serial

Interface

and

Control

VBIAS

GPIO

CLK

ADS1148 Only

ADS1147

ADS1148

PGA

System

Monitor

Adjustable

Digital

Filter

Dual

Current

DACs

VREFMux

ADS1148 Only

ADS1146

ADS1147

ADS1148

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SBAS453F –JULY 2009–REVISED APRIL 2012

GENERAL DESCRIPTION

OVERVIEW The ADS1147 and ADS1148 also include a flexible

The ADS1146, ADS1147 and ADS1148 are highly input multiplexer with system monitoring capability

integrated 24-bit data converters. Each device and general-purpose I/O settings, a very low-drift

includes a low-noise, high-impedance programmable voltage reference, and two matched current sources

gain amplifier (PGA), a delta-sigma (ΔΣ) ADC with an for sensor excitation. Figure 17 and Figure 18 show

adjustable single-cycle settling digital filter, internal the various functions incorporated into each device.

oscillator, and a simple but flexible SPI-compatible

serial interface.

Figure 17. ADS1146 Diagram

Figure 18. ADS1147, ADS1148 Diagram

Product Folder Link(s): ADS1146 ADS1147 ADS1148

System Monitors

Temperature

Diode

VREFP

VREFN

VREFP1/4

VREFN1/4

VREFP0/4

VREFN0/4

AVDD/4

AVSS/4

DVDD/4

DGND/4

ADS1148 Only

ADS1147/8 Only

VBIAS

AIN0

AIN1

VBIAS

AIN2

VBIAS

AIN3

VBIAS

AIN4

VBIAS

AIN5

VBIAS

AIN6

VBIAS

AIN7

AVDD

IDAC1

IDAC2

AVDD

VBIAS

PGA

AINP

AVSS

AVDD

Burnout Current Source

(0.5 A, 2 A, 10m m mA)

Burnout Current Source

(0.5 A, 2 A, 10m m mA)

AINN

ADC

AVSS

AVDD

AVDD AVDD

ADS1146

ADS1147

ADS1148

SBAS453F –JULY 2009–REVISED APRIL 2012

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ADC INPUT AND MULTIPLEXER Any analog input pin can be selected as the positive

input or negative input through the MUX0 register.

The ADS1146/7/8 ADC measures the input signal The ADS1146/7/8 have a true fully differential mode,

through the onboard PGA. All analog inputs are meaning that the input signal range can be from

connected to the internal AINPor AINNanalog inputs –2.5V to +2.5V (when AVDD = 2.5V and

through the analog multiplexer. A block diagram of AVSS = –2.5V).

the analog input multiplexer is shown in Figure 19.Through the input multiplexer, the ambient

The input multiplexer connects to eight (ADS1148), temperature (internal temperature sensor), AVDD,

four (ADS1147), or two (ADS1146) analog inputs that DVDD, and external reference can all be selected for

can be configured as single-ended inputs, differential measurement. Refer to the System Monitor section

inputs, or in a combination of single-ended and for details.

differential inputs. The multiplexer also allows the on-

chip excitation current and/or bias voltage to be On the ADS1147 and ADS1148, the analog inputs

selected to a specific channel. can also be configured as general-purpose

inputs/outputs (GPIOs). See the General-Purpose

Digital I/O section for more details.

Figure 19. Analog Input Multiplexer Circuit

Product Folder Link(s): ADS1146 ADS1147 ADS1148

REFN1REFP1

ADC

ADS1148 Only

REFN0REFP0

VREFN

VREFP

VREFCOMVREFOUT

ReferenceMultiplexer

Internal

Voltage

Reference

ADS1146

ADS1147

ADS1148

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SBAS453F –JULY 2009–REVISED APRIL 2012

ESD diodes protect the ADC inputs. To prevent these VREF = VREFP – VREFN

diodes from turning on, make sure the voltages on In the case of the ADS1146, these pins are dedicated

the input pins do not go below AVSS by more than inputs. For the ADS1147 and ADS1148, there is a

100mV, and do not exceed AVDD by more than multiplexer that selects the reference inputs, as

100mV, as shown in Equation 2. Note that the same shown in Figure 20. The reference input uses a buffer

caution is true if the inputs are configured to be to increase the input impedance.

GPIOs. As with the analog inputs, REFP0 and REFN0 can be

AVSS – 100mV < (AINX) < AVDD + 100mV (2) configured as digital I/Os on the ADS1147 and

ADS1148.

Settling Time for Channel Multiplexing

The ADS1146/7/8 is a true single-cycle settling ΔΣ

converter. The first data available after the start of a

conversion are fully settled and valid for use. The

time required to settle is roughly equal to the inverse

of the data rate. The exact time depends on the

specific data rate and the operation that resulted in

the start of a conversion; see Table 12 for specific

values.

ANALOG INPUT IMPEDANCE

The ADS1146/7/8 inputs are buffered through a high-

impedance PGA before they reach the ΔΣ modulator.

For the majority of applications, the input current

leakage is minimal and can be neglected. However,

because the PGA is chopper-stabilized for noise and Figure 20. Reference Input Multiplexer

offset performance, the input impedance is best

described as a small absolute input current. The The reference input circuit has ESD diodes to protect

absolute current leakage for selected channels is the inputs. To prevent the diodes from turning on,

approximately proportional to the selected modulator make sure the voltage on the reference input pin is

clock. Table 3 shows the typical values for these not less than AVSS – 100mV, and does not exceed

currents with a differential voltage coefficient and the AVDD + 100mV, as shown in Equation 3:

corresponding input impedances over data rate. AVSS – 100mV < (VREFP or VREFN) < AVDD + 100mV (3)

VOLTAGE REFERENCE INPUT

The voltage reference for the ADS1146/7/8 is the

differential voltage between REFP and REFN:

Table 3. Typical Values for Analog Input Current Over Data Rate

EFFECTIVE INPUT

CONDITION ABSOLUTE INPUT CURRENT IMPEDANCE

DR = 5SPS, 10SPS, 20SPS ± (0.5nA + 0.1nA/V) 5000MΩ

DR = 40SPS, 80SPS, 160SPS ± (2nA + 0.5nA/V) 1200MΩ

DR = 320SPS, 640SPS, 1kSPS ± (4nA + 1nA/V) 600MΩ

DR = 2kSPS ± (8nA + 2nA/V) 300MΩ

Product Folder Link(s): ADS1146 ADS1147 ADS1148

()

(V )(Gain)

AVSS+0.1V + £VCMI £

()

(V )(Gain)

AVDD 0.1V- -

ADC

454W

7.5pF

AINP

AINN

ADS1146

ADS1147

ADS1148

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LOW-NOISE PGA

The ADS1146/7/8 feature a low-drift, low-noise, high (4)

input impedance programmable gain amplifier (PGA).

The PGA can be set to gain of 1, 2, 4, 8, 16, 32, 64, MODULATOR

or 128 by register SYS0. A simplified diagram of the

PGA is shown in Figure 21.A third-order modulator is used in the ADS1146/7/8.

The modulator converts the analog input voltage into

a pulse code modulated (PCM) data stream. To save

power, the modulator clock runs from 32kHz up to

512kHz for different data rates, as shown in Table 4.

DIGITAL FILTER

The ADS1146/7/8 use linear-phase finite impulse

response (FIR) digital filters that can be adjusted for

different output data rates. The digital filter always

settles in a single cycle.

Table 5 shows the exact data rates when an external

oscillator equal to 4.096MHz is used. Also shown is

the signal –3dB bandwidth, and the 50Hz and 60Hz

attenuation. For good 50Hz or 60Hz rejection, use a

data rate of 20SPS or slower.

The frequency responses of the digital filter are

Figure 21. Simplified Diagram of the PGA shown in Figure 22 to Figure 32.Figure 25 shows a

detailed view of the filter frequency response from

48Hz to 62Hz for a 20SPS data rate. All filter plots

The PGA consists of two chopper-stabilized are generated with 4.096MHz external clock.

amplifiers (A1 and A2) and a resistor feedback

network that sets the gain of the PGA. The PGA input Table 4. Modulator Clock Frequency for Different

is equipped with an electromagnetic interference Data Rates

(EMI) filter, as shown in Figure 21. Note that as with

any PGA, it is necessary to ensure that the input DATA RATE fMOD

voltage stays within the specified common-mode (SPS) (kHz)

input range specified in the Electrical Characteristics.5, 10, 20 32

The common-mode input (VCMI) must be within the 40, 80, 160 128

range shown in Equation 4:320, 640, 1000 256

2000 512

Table 5. Digital Filter Specifications(1)

ATTENUATION

DATA RATE –3dB BANDWIDTH fIN = 50Hz ±0.3Hz fIN = 60Hz ±0.3Hz fIN = 50Hz ±1Hz fIN = 60Hz ±1Hz

5SPS 2.26Hz –106dB –74dB –81dB –69dB

10SPS 4.76Hz –106dB –74dB –80dB –69dB

20SPS 14.8Hz –71dB –74dB –66dB –68dB

40SPS 9.03Hz

80SPS 19.8Hz

160SPS 118Hz

320SPS 154Hz

640SPS 495Hz

1000SPS 732Hz

2000SPS 1465Hz

(1) Values shown for fOSC = 4.096MHz.

Product Folder Link(s): ADS1146 ADS1147 ADS1148

-20

-40

-60

-80

-100

-120

0 40 60

Frequency(Hz)

Magnitude(dB)

80 100 120 140 160 180 200

50 52 54 56 58 60

-60

-70

-80

-90

-100

-110

-120

Frequency(Hz)

Magnitude(dB)

-20

-40

-60

-80

-100

-120

0 40 60

Frequency(Hz)

Magnitude(dB)

80 100 120 140 160 180 200

200

-20

-40

-60

-80

-100

-120

0 400 600

Frequency(Hz)

Magnitude(dB)

800 1000 1200 1400 1600 1800 2000

-20

-40

-60

-80

-100

-120

0 40 60

Frequency(Hz)

Magnitude(dB)

80 100 120 140 160 180 200

200

-20

-40

-60

-80

-100

-120

0 400 600

Frequency(Hz)

Gain(dB)

800 1000 1200 1400 1600 1800 2000

ADS1146

ADS1147

ADS1148

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SBAS453F –JULY 2009–REVISED APRIL 2012

Figure 22. Filter Profile with Data Rate = 5SPS Figure 25. Detailed View of Filter Profile with Data

Rate = 20SPS between 48Hz and 62Hz

Figure 23. Filter Profile with Data Rate = 10SPS Figure 26. Filter Profile with Data Rate = 40SPS

Figure 24. Filter Profile with Data Rate = 20SPS Figure 27. Filter Profile with Data Rate = 80SPS

Product Folder Link(s): ADS1146 ADS1147 ADS1148

200

-20

-40

-60

-80

-100

-120

0 400 600

Frequency(Hz)

Magnitude(dB)

800 1000 1200 1400 1600 1800 2000

-20

-40

-60

-80

-100

-120

0 2 3

Frequency(kHz)

Magnitude(dB)

45678910

500

-20

-40

-60

-80

-100

-120

0 1000 1500

Frequency(Hz)

Magnitude(dB)

2000 2500 3000 3500 4000 4500 5000

-20

-40

-60

-80

-100

-120

0 4 6

Frequency(kHz)

Magnitude(dB)

8 10 12 14 16 18 20

500

-20

-40

-60

-80

-100

-120

0 1000 1500

Frequency(Hz)

Magnitude(dB)

2000 2500 3000 3500 4000 4500 5000

ADS1146

ADS1147

ADS1148

SBAS453F –JULY 2009–REVISED APRIL 2012

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Figure 28. Filter Profile with Data Rate = 160SPS Figure 31. Filter Profile with Data Rate = 1kSPS

Figure 29. Filter Profile with Data Rate = 320SPS Figure 32. Filter Profile with Data Rate = 2kSPS

CLOCK SOURCE

The ADS1146/7/8 can use either the internal

oscillator or an external clock. Connect the CLK pin to

DGND before power-on or reset to activate the

internal oscillator. Connecting an external clock to the

CLK pin at any time deactivates the internal oscillator,

with the device then operating on the external clock.

After the device switches to the external clock, it

cannot be switched back to the internal oscillator

without cycling the power supplies or resetting the

device.

Figure 30. Filter Profile with Data Rate = 640SPS

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SBAS453F –JULY 2009–REVISED APRIL 2012

INTERNAL VOLTAGE REFERENCE The two matched current sources can be connected

to dedicated current output pins IOUT1 and IOUT2

The ADS1147 and ADS1148 include an onboard (ADS1148 only), or to any AIN pin (ADS1147 and

voltage reference with a low temperature coefficient. ADS1148); refer to the ADS1147/48 Detailed

The output of the voltage reference is 2.048V with the Register Definitions section for more information. It is

capability of both sourcing and sinking up to 10mA of possible to connect both current sources to the same

current. pin. Note that the internal reference must be turned

on and properly compensated when using the

The voltage reference must have a capacitor excitation current source DACs.

connected between VREFOUT and VREFCOM. The

value of the capacitance should be in the range of

1μF to 47μF. Large values provide more filtering of SENSOR DETECTION

the reference; however, the turn-on time increases The ADS1146/7/8 provide a selectable current

with capacitance, as shown in Table 6. For stability (0.5μA, 2μA, or 10μA) to help detect a possible

reasons, VREFCOM must have a path with an sensor malfunction.

impedance less than 10Ωto ac ground nodes, such

as GND (for a 0V to 5V analog power supply), or When enabled, two burnout current sources flow

AVSS for a ±2.5V analog power supply). In case this through the selected pair of analog inputs to the

impedance is higher than 10Ω, a capacitor of at least sensor. One sources the current to the positive input

0.1μF should be connected between VREFCOM and channel, and the other sinks the same current from

an ac ground node (for example, GND). Note that the negative input channel.

because it takes time for the voltage reference to When the burnout current sources are enabled, a full-

settle to the final voltage, care must be taken when scale reading may indicate an open circuit in the

the device is turned off between conversions. Allow front-end sensor, or that the sensor is overloaded. It

adequate time for the internal reference to fully settle. may also indicate that the reference voltage is

absent. A near-zero reading may indicate a short-

Table 6. Internal Reference Settling Time circuit in the sensor.

VREFOUT SETTLING TIME TO REACH THE

CAPACITOR ERROR SETTLING ERROR BIAS VOLTAGE GENERATION

±0.5% 70μs

1μFA selectable bias voltage is provided for use with

±0.1% 110μsungrounded thermocouples. The bias voltage is

±0.5% 290μs(AVDD + AVSS)/2 and can applied to any analog

4.7μF±0.1% 375μsinput channel through internal input multiplexer. The

±0.5% 2.2ms bias voltage turn-on times for different sensor

47μFcapacitances are listed in Table 7.

±0.1% 2.4ms The internal bias generator when selected on multiple

The onboard reference is controlled by the registers; channels causes them to be internally shorted.

by default, it is off after startup (see the ADS1147/48 Because of this, it is important that care be taken to

Detailed Register Definitions section for more details). limit the amount of current that may flow through the

Therefore, the internal reference must first be turned device. It is recommended that under no

on and then connected via the internal reference circumstances more than 5mA be allowed to flow

multiplexer. Because the onboard reference is used through this path. This applies when the device is in

to generate the current reference for the excitation operation and when it is in shutdown mode.

current sources, it must be turned on before the

excitation currents become available. Table 7. Bias Voltage Settling Time

SENSOR CAPACITANCE SETTLING TIME

EXCITATION CURRENT SOURCE DACS 0.1μF 220μs

The ADS1147 and ADS1148 provide two matched 1μF 2.2ms

excitation current sources for RTD applications. For 10μF 22ms

three- or four-wire RTD applications, the matched

current sources can be used to cancel the errors 200μF 450ms

caused by sensor lead resistance. The output current

of the current source DACs can be programmed to

50μA, 100μA, 250μA, 500μA, 750μA, 1000μA, or

1500μA.

Product Folder Link(s): ADS1146 ADS1147 ADS1148

IOCFG

AINx/GPIOx

ToAnalogMux

DIOWRITE

IODIR

DIOREAD

REFx0/GPIOx

ADS1146

ADS1147

ADS1148

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Power-Supply Monitor

GENERAL-PURPOSE DIGITAL I/O The system monitor can measure the analog or

The ADS1148 has eight pins and the ADS1147 has digital power supply. When measuring the power

four pins that serve a dual purpose as either analog supply, the resulting conversion is approximately 1/4

inputs or general-purpose digital inputs/outputs of the actual power supply voltage.

(GPIOs). Conversion Result = (VSP/4)/VREF (5)

Figure 33 shows a diagram of how these functions

are combined onto a single pin. Note that when the Where VSP is the selected supply to be measured.

pin is configured as a GPIO, the corresponding logic

is powered from AVDD and AVSS. When the External Voltage Reference Monitor

ADS1147 and ADS1148 are operated with bipolar The ADS1146/7/8 can be selected to measure the

analog supplies, the GPIO outputs bipolar voltages. external voltage reference. In this configuration, the

Care must be taken loading the GPIO pins when monitored external voltage reference is connected to

used as outputs because large currents can cause the analog input. The result (conversion code) is

droop or noise on the analog supplies. approximately 1/4 of the actual reference voltage.

Conversion Result = (VREX/4)/VREF (6)

Where VREX is the external reference to be

monitored.

NOTE: The internal reference voltage must be

enabled when measuring an external voltage

reference using the system monitor.

Ambient Temperature Monitor

On-chip diodes provide temperature-sensing

capability. When selecting the temperature monitor

function, the anodes of two diodes are connected to

Figure 33. Analog/Data Interface Pin the ADC. Typically, the difference in diode voltage is

118mV at +25°C with a temperature coefficient of

405μV/°C.

SYSTEM MONITOR Note that when the onboard temperature monitor is

The ADS1147 and ADS1148 provide a system selected, the PGA is automatically set to '1'.

monitor function. This function can measure the However, the PGA register bits in are not affected

analog power supply, digital power supply, external and the PGA returns to its set value when the

voltage reference, or ambient temperature. Note that temperature monitor is turned off.

the system monitor function provides a coarse result.

When the system monitor is enabled, the analog

inputs are disconnected.

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ADC S

OFC

Final

Output

OutputData

Clippedto16Bits

FSCRegister

400000h

FinalOutputData= (Input OFC[2:1])- ´ FSC[2:0]

400000h

-1.251V > |Offset Scaling|

Gain Scaling

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CALIBRATION LSB correction and are used by the ADS1146/7/8

calibration commands. If an ADS1146/7/8 calibration

The conversion data are scaled by offset and gain command is issued and the offset register is then

registers before yielding the final output code. As read for storage and re-use later, it is recommended

shown in Figure 34, the output of the digital filter is that all 24 bits of the OFC be used. When the

first subtracted by the offset register (OFC) and then calibration commands are not used and the offset is

multiplied by the full-scale register (FSC). A digital corrected by writing a user-calculated value to the

clipping circuit ensures that the output code does not OFC register, it is recommended that only that only

exceed 16 bits. Equation 7 shows the scaling. OFC[2:1] be used and that OFC[0] be left as all

zeros.

Note that while the offset calibration register value

can correct offsets ranging from –FS to +FS (as

shown in Table 8), make sure to avoid overloading

the analog inputs.

Table 8. Final Output Code versus Offset

Calibration Register Setting

Figure 34. Calibration Block Diagram FINAL OUTPUT CODE WITH

OFFSET REGISTER VIN = 0

7FFFFFh 8000000h

(7) 000001h FFFFFFh

000000h 000000h

The values of the offset and full-scale registers are

set by writing to them directly, or they are set FFFFFFh 000000h

automatically by calibration commands. 8000000h 7FFFFFh

The gain and offset calibration features are intended 1. Excludes effects of noise and inherent offset

for correction of minor system level offset and gain errors.

errors. When entering manual values into the

calibration registers, care must be taken to avoid Full-Scale Calibration Register: FSC[2:0]

scaling down the gain register to values far below a The full-scale or gain calibration is a 24-bit word

scaling facter of 1.0. Under extreme situations it composed of three 8-bit registers. The full-scale

becomes possible to over-range the ADC. To avoid calibration value is 24-bit, straight binary, normalized

this, make sure to avoid encountering situations to 1.0 at code 400000h. Table 9 summarizes the

where the analog inputs are connected to voltages scaling of the full-scale register. Note that while the

greater than the reference/PGA. full-scale calibration register can correct gain errors

Care must also be taken when increasing the digital > 1 (with gain scaling < 1), make sure to avoid

gain. When implementing custom digital gains less overloading the analog inputs.

than 20% higher than nominal and offsets less than

40% of full scale, no special care is required. When Table 9. Gain Correction Factor versus Full-Scale

operating at digital gains greater than 20% higher Calibration Register Setting

than nominal and offsets greater than 40% of full FULL-SCALE REGISTER GAIN SCALING

scale, make sure that the offset and gain registers 800000h 2.0

follow the conditions of equation 8. 400000h 1.0

200000h 0.5

(8) 000000h 0

Offset Calibration Register: OFC[2:0]

The offset calibration is a 24-bit word, composed of

three 8-bit registers. The upper 16 bits, OFC[2:1], are

the most important for calibration and can correct

offsets ranging from –FS to +FS, as shown in

Table 8. The lower eight bits, OFC[0], provide sub-

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fOSC

fMOD

fDATA

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Calibration Commands calibrations the offset calibration register (OFC) is

updated afterwards. When either offset calibration

The ADS1146/7/8 provide commands for three types command is issued, the ADS1146/7/8 stop the

of calibration: system gain calibration, system offset current conversion and start the calibration procedure

calibration and self offset calibration. Where absolute immediately.

accuracy is needed, it is recommended that

calibration be performed after power on, a change in Calibration Timing

temperature, a change of PGA and in some cases a

change in channel. At the completion of calibration, When calibration is initiated, the device performs 16

the DRDY signal goes low indicating the calibration is consecutive data conversions and averages the

finished. The first data after calibration are always results to calculate the calibration value. This

valid. If the START pin is taken low or a SLEEP provides a more accurate calibration value. The time

command is issued after any calibration command, required for calibration is shown in Table 10 and can

the devices goes to sleep after completing calibration. be calculated using Equation 9:

It is important to allow a pending system calibration to

complete before issuing any other commands. (9)

Issuing commands during a calibration can result in

corrupted data. If this occurs either resend the Table 10. Calibration Time versus Data Rate

calibration command that was aborted or issue a DATA RATE (SPS) CALIBRATION TIME (ms)

device reset. 5 3201.01

System Gain Calibration 10 1601.01

20 801.012

System gain calibration corrects for gain error in the 40 400.26

signal path. The system gain calibration is initiated by

sending the SYSGCAL command while applying a 80 200.26

full-scale input to the selected analog inputs. 160 100.14

Afterwards the full-scale calibration register (FSC) is 320 50.14

updated. When a system gain calibration command is 640 25.14

issued, the ADS1146/7/8 stop the current conversion 1000 16.14

and start the calibration procedure immediately. 2000 8.07

System Offset and Self Offset Calibration 1. For fOSC = 4.096MHz.

System offset calibration corrects both internal and

external offset errors. The system offset calibration is ADC SLEEP MODE

initiated by sending the SYSOCAL command while Power consumption can be dramatically reduced by

applying a zero differential input (VIN = 0) to the placing the ADS1146/7/8 into sleep mode. There are

selected analog inputs. The self offset calibration is two ways to put the device into sleep mode: the sleep

initiated by sending the SELFOCAL command. command (SLEEP) and through the START pin.

During self offset calibration, the selected inputs are

disconnected from the internal circuitry and a zero During sleep mode, the internal reference status

differential signal is applied internally. With both offset depends on the setting of the VREFCON bits in the

MUX1 register; see the Register Descriptions section

for details.

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Converting

START

DOUT/DRDY

SCLK

DRDY

ADS1146/7/8

Status Shutdown

1 2 3 16

tCONV

tSTART

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ADC CONTROL down to save power. During shutdown, the

conversion result can be retrieved; however, START

ADC Conversion Control must be taken high before communicating with the

configuration registers. The device stays shut down

The START pin provides easy and precise control of until the START pin is once again taken high to begin

conversions. Pulse the START pin high to begin a a new conversion. When the START pin is taken

conversion, as shown in Figure 35 and Table 11. The back high again, the decimation filter is held in a

conversion completion is indicated by the reset state for 32 modulator clock cycles internally to

DOUT/DRDY pin going low. When the conversion allow the analog circuits to settle.

completes, the ADS1146/7/8 automatically shuts

Figure 35. Timing for Single Conversion Using START Pin

Table 11. START Pin Conversion Times for Figure 35

SYMBOL DESCRIPTION DATA RATE (SPS) VALUE UNIT

5 200.295 ms

10 100.644 ms

20 50.825 ms

40 25.169 ms

80 12.716 ms

Time from START pulse to DRDY and

tCONV DOUT/DRDY going low 160 6.489 ms

320 3.247 ms

640 1.692 ms

1000 1.138 ms

2000 0.575 ms

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Converting Converting Converting Converting

START

DOUT/DRDY

ADS1146/7/8

Status

DataReady DataReady DataReady

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The ADS1146/7/8 can be configured to convert transferred to the ADS1146/7/8, new settings become

continuously by holding the START pin high, as active at the end of each byte sent. Therefore, a brief

shown in Figure 36. With the START pin held high, overload condition can occur during the transmission

the ADC converts the selected input channels of configuration data after the completion of the

continuously. This configuration continues until the MUX0 byte and before the completion of the SYS0

START pin is taken low. byte. This temporary overload can result in

intermittent incorrect readings. To ensure that an

The START pin can also be used to perform the overload does not occur, it may be necessary to split

synchronized measurement for the multi-channel the communication into two separate communications

applications by pulsing the START pin. allowing the change of the SYS0 register bfore the

change of the MUX0 register.

RESET In the event of an overloaded state, care must also

When the RESET pin goes low, the device is be taken to ensure single cycle settling into the next

immediately reset. All the registers are restored to cycle. Because the ADS1146/7/8 implement a

default values. The device stays in reset mode as chopper-stabilized PGA, changing data rates during

long as the RESET pin stays low. When it goes high, an overload state can cause the chopper to become

the ADC comes out of reset mode and is able to unstable. This instability results in slow settling time.

convert data. After the RESET pin goes high, and To prvent this slow settling, always change the PGA

when the system clock frequency is 4.096MHz, the setting or MUX setting to a non-overloaded state

digital filter and the registers are held in a reset state bfore changing the data rate.

for 0.6ms when fOSC = 4.096MHz. Therefore, valid

SPI communication can only be resumed 0.6ms after Single-Cycle Settling

the RESET pin goes high; see Figure 4. When the

RESET pin goes low, the clock selection is reset to The ADS1146/7/8 are capable of single-cycle settling

the internal oscillator. across all gains and data rates. However, to achieve

single-cycle settling at 2kSPS, special care must be

Channel Cycling and Overload Recovery taken with respect to the interface. When operating at

2kSPS, the SPI data SCLK period must not exceed

When cycling through channels, care must be taken 520ns, and the time between the beginning of a byte

when configuring the ADS1146/7/8 to ensure that and the beginning of a subsequent byte must not

settling occurs within one cycle. For setups that exceed 4.2µs. Additionally, when performing multiple

simply cycle through MUX channels, but do not individual write commands to the first four registers,

change PGA and data rate settings, simply changing wait at least 64 oscillator clocks before initiating

the MUX0 register is sufficient. However, when another write command.

changing PGA and data rate settings it is important to

ensure that an overloaded condition cannot occur

during the transmission. When configuration data are

NOTE: SCLK held low in this example.

Figure 36. Timing for Conversion with START Pin High

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Digital Filter Reset Operation takes place in the VBIAS, MUX1, or SYS0 registers,

the filter is reset as well, regardless of whether the

Apart from the RESET command and the RESET pin, value changed or not. The reset pulse lasts for 32

the digital filter is reset automatically when either a modulator clocks after the write operation. If there are

write operation to the MUX0, VBIAS, MUX1, or SYS0 multiple write operations, the resulting reset pulse

registers is performed, when a SYNC command is may be viewed as the ANDed result of the different

issued, or the START pin is taken high. active low pulses created individually by each action.

The filter is reset two system clocks after the last bit Table 12 shows the conversion time after a filter

of the SYNC command is sent. The reset pulse reset. Note that this time depends on the operation

created internally lasts for two multiplier clock cycles. initiating the reset. Also, the first conversion after a

If any write operation takes place in the MUX0 filter reset has a slightly different time than the

value changed or not. Internally, the filter pulse lasts

for two system clock periods. If any write activity

Table 12. Data Conversion Time

FIRST DATA CONVERSION TIME AFTER FILTER RESET

HARDWARE RESET, RESET

COMMAND, START PIN HIGH,

WAKEUP COMMAND, VBIAS, SECOND AND SUBSEQUENT

SYNC COMMAND, MUX0 MUX1, or SYS0 REGISTER CONVERSION TIME AFTER

NO. OF NO. OF NO. OF

NOMINAL EXACT DATA SYSTEM SYSTEM SYSTEM

DATA RATE RATE CLOCK CLOCK CLOCK

(SPS) (SPS) (ms)(1) CYCLES (ms)(1) CYCLES (ms) CYCLES

5 5.019 199.258 816160 200.26 820265 199.250 816128

10 10.038 99.633 408096 100.635 412201 99.625 408064

20 20.075 49.820 204064 50.822 208169 49.812 204032

40 40.151 24.920 102072 25.172 103106 24.906 102016

80 80.301 12.467 51064 12.719 52098 12.453 51008

160 160.602 6.241 25560 6.492 26594 6.226 25504

320 321.608 3.124 12796 3.250 13314 3.109 12736

640 643.216 1.569 6428 1.695 6946 1.554 6368

1000 1000.000 1.014 4156 1.141 4674 1.000 4096

2000 2000.000 0.514 2108 0.578 2370 0.500 2048

(1) For fOSC = 4.096MHz.

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Data Format The ADS1146/7/8 implement a timout function for all

listed commands in the event that data is corrupted

The ADS1146/7/8 output 16 bits of data in binary and chip select is permanently tied low. However, it is

twos complement format. The least significant bit important in systems where chip select is tied low

(LSB) has a weight of (VREF/PGA)/(215 – 1). The permanently that register writes always be fully

positive full-scale input produces an output code of completed in 8 bit increments. The SCLK line should

7FFFh and the negative full-scale input produces an also be kept clean and situations should be avoided

output code of 8000h. The output clips at these codes where noise on the SCLK line could cause the device

for signals exceeding full-scale. Table 13 summarizes to interpret the transient as a false SCLK pulse. In

the ideal output codes for different input signals. systems where such events are likely to occur, it is

recommended that chip select be used to frame

Table 13. Ideal Output Code vs Input Signal communications to the device.

INPUT SIGNAL, VIN SCLK

(AINP– AINN) IDEAL OUTPUT CODE This signal is the serial clock signal. SCLK provides

≥+VREF/PGA 7FFFh the clock for serial communication. It is a Schmitt-

(+VREF/PGA)/(215 – 1) 0001h trigger input, but it is highly recommended that SCLK

0 0000h be kept as clean as possible to prevent glitches from

(–VREF/PGA)/(215 – 1) FFFFh inadvertently shifting the data. Data are shifted into

DIN on the falling edge of SCLK and shifted out of

≤–(VREF/PGA) × (215/215 – 1) 8000h DOUT on the rising edge of SCLK.

1. Excludes effects of noise, linearity, offset, and DIN

gain errors. This pin is the data input pin. DIN is used along with

SCLK to send data to the device. Data on DIN are

Digital Interface shifted into the device on the falling edge of SCLK.

The ADS1146/7/8 provide a standard SPI serial The communication of this device is full-duplex in

communication interface plus a data ready signal nature. The device monitors commands shifted in

(DRDY). Communication is full-duplex with the even when data are being shifted out. Data that are

exception of a few limitations in regards to the RREG present in the output shift register are shifted out

command and the RDATA command. These when sending in a command. Therefore, it is

limitations are explained in detail in the SPI important to make sure that whatever is being sent on

Commands section of this data sheet. For the basic the DIN pin is valid when shifting out data. When no

serial interface timing characteristics, see Figure 1 command is to be sent to the device when reading

and Figure 2 of this document. out data, the NOP command should be sent on DIN.

CS DRDY

This pin is the chip select pin (active low). The CS pin This pin is the data ready pin. The DRDY pin goes

activates SPI communication. CS must be low before low to indicate a new conversion is complete, and the

data transactions and must stay low for the entire SPI conversion result is stored in the conversion result

communication period. When CS is high, the buffer. The SPI clock must be low in a short time

DOUT/DRDY pin enters a high-impedance state. frame around the DRDY low transition (see Figure 2)

Therefore, reading and writing to the serial interface so that the conversion result is loaded into both the

are ignored and the serial interface is reset. DRDY result buffer and the output shift register. Therefore,

pin operation is independent of CS. no commands should be issued during this time

Taking CS high deactivates only the SPI frame if the conversion result is to be read out later.

communication with the device. Data conversion This constraint applies only when CS is asserted.

continues and the DRDY signal can be monitored to When CS is not asserted, SPI communication with

check if a new conversion result is ready. A master other devices on the SPI bus does not affect loading

device monitoring the DRDY signal can select the of the conversion result. After the DRDY pin goes

appropriate slave device by pulling the CS pin low. low, it is forced high on the first falling edge of SCLK

(so that the DRDY pin can be polled for '0' instead of

waiting for a falling edge). If the DRDY pin is not

taken high after it falls low, a short high pulse is

created on it to indicate the next data are ready.

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SCLK

D[15]

1 2 14 1 2 815 163

D[14] D[13] D[2] D[1] D[0]

DOUT/ (1)

DRDY

SCLK

DIN

D[15] D[14]D[15]D[14] D[13]

NOP NOP

D[2] D[1] D[0] D[0]

3 14 15 16 16

DOUT/ (1)

DRDY

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DOUT/DRDY by providing 16 SCLKs. In order to force

This pin has two modes: data out (DOUT) only, or DOUT/DRDY high (so that DOUT/DRDY can be

data out (DOUT) combined with data ready (DRDY). polled for a '0' instead of waiting for a falling edge), a

The DRDY MODE bit determines the function of this no operation command (NOP) or any other command

pin. In either mode, the DOUT/DRDY pin goes to a that does not load the data output register can be

high-impedance state when CS is taken high. sent after reading out the data. Because SCLKs can

only be sent in multiples of eight, a NOP can be sent

When the DRDY MODE bit is set to '0', this pin to force DOUT/DRDY high if no other command is

functions as DOUT only. Data are clocked out at pending. The DOUT/DRDY pin goes high after the

rising edge of SCLK, MSB first, as shown in first rising edge of SCLK after reading the conversion

Figure 37.result completely (see Figure 39). The same condition

also applies after an RREG command. After all the

When the DRDY MODE bit is set to '1', this pin register bits have been read out, the rising edge of

functions as both DOUT and DRDY. Data are shifted SCLK forces DOUT/DRDY high. Figure 40 illustrates

out from this pin, MSB first, at the rising edge of an example where sending four NOP commands after

SCLK. This combined pin allows for the same control an RREG command forces the DOUT/DRDY pin

but with fewer pins. high.

When the DRDY MODE bit is enabled and a new The DRDY MODE bit modifies only the DOUT/DRDY

conversion is complete, DOUT/DRDY goes low if it is pin functionality. The DRDY pin functionality remains

high. If it is already low, then DOUT/DRDY goes high unaffected.

and then goes low, as shown in Figure 38. Similar to

the DRDY pin, a falling edge on the DOUT/DRDY pin

signals that a new conversion result is ready. After

DOUT/DRDY goes low, the data can be clocked out

(1) CS tied low.

Figure 37. Data Retrieval with the DRDY MODE Bit = 0 (Disabled)

(1) CS tied low.

Figure 38. Data Retrieval with the DRDY MODE Bit = 1 (Enabled)

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SCLK

DIN

D[15] D[14]D[15]D[14] D[13]

NOP NOP NOP

D[2] D[1] D[0] D[0]

3 14 15 16 1 2 8 16

DOUT/ (1)

DRDY

SCLK

DOUT/ (1)

DRDY

DIN NOP

reg[7] reg[1] reg[0]

2 1 2 7 87 8

NOP

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(1) DRDY MODE bit enabled, CS tied low.

Figure 39. DOUT/DRDY Forced High After Retrieving the Conversion Result

(1) DRDY MODE bit enabled, CS tied low.

Figure 40. DOUT/DRDY Forced High After Reading Register Data

SPI Reset SPI Communication During Sleep Mode

SPI communication can be reset in several ways. In When the START pin is low or the device is in sleep

order to reset the SPI interface (without resetting the mode, only the RDATA, RDATAC, SDATAC,

registers or the digital filter), the CS pin can be pulled WAKEUP, and NOP commands can be issued. The

high. Taking the RESET pin low causes the SPI RDATA command can be used to repeatedly read the

interface to be reset along with all the other digital last conversion result during sleep mode. Other

functions. In this case, the registers and the commands do not function because the internal clock

conversion are reset. is shut down to save power during sleep mode.

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ADS1146 REGISTER MAP

Table 14. ADS1146 Register Map

ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

00h BCS BCS1 BCS0 0 0 0 0 0 1

01h VBIAS 0 0 0 0 0 0 VBIAS1 VBIAS0

02h MUX1 CLKSTAT 0 0 0 0 MUXCAL2 MUXCAL1 MUXCAL0

03h SYS0 0 PGA2 PGA1 PGA0 DR3 DR2 DR1 DR0

04h OFC0 OFC7 OFC6 OFC5 OFC4 OFC3 OFC2 OFC1 OFC0

05h OFC1 OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC9 OFC8

06h OFC2 OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16

07h FSC0 FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0

08h FSC1 FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8

09h FSC2 FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16

DRDY

0Ah ID ID3 ID2 ID1 ID0 0 0 0

MODE

ADS1146 DETAILED REGISTER DEFINITIONS

BCS—Burnout Current Source Register. These bits control the settling of the sensor burnout detect current

source.

BCS - ADDRESS 00h RESET VALUE = 01h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

BCS1 BCS0 0 0 0 0 0 1

Bits[7:6] BCS[1:0]

These bits select the magnitude of the sensor burnout detect current source.

00 = Burnout current source off (default)

01 = Burnout current source on, 0.5μA

10 = Burnout current source on, 2μA

11 = Burnout current source on, 10μA

Bits[5:0] These bits must always be set to '000001'.

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ADS1146 DETAILED REGISTER DEFINITIONS (continued)

VBIAS—Bias Voltage Register. This register enables a bias voltage on the analog inputs.

VBIAS - ADDRESS 01h RESET VALUE = 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 0 0 0 0 0 VBIAS1 VBIAS0

Bits[7:2] These bits must always be set to '000000'.

Bits[1:0] VBIAS[1:0]

These bits apply a bias voltage of midsupply (AVDD + AVSS)/2 to the selected analog input. Bit 0

is for AIN0, and bit 1 is for AIN1.

0 = Bias voltage not enabled (default)

1 = Bias voltage is applied to the analog input

MUX—Multiplexer Control Register.

MUX - ADDRESS 02h RESET VALUE = x0h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

CLKSTAT 0 0 0 0 MUXCAL2 MUXCAL1 MUXCAL0

Bit 7 CLKSTAT

This bit is read-only and indicates whether the internal or external oscillator is being used.

0 = Internal oscillator in use

1 = External oscillator in use

Bits[6:3] These bits must always be set to '0000'.

Bits[2:0] MUXCAL[2:0]

These bits are used to select a system monitor. The MUXCAL selection supercedes selections

from the VBIAS register.

000 = Normal operation (default)

001 = Offset calibration. The analog inputs are disconnected and AINP and AINN are internally

connected to midsupply (AVDD + AVSS)/2.

010 = Gain calibration. The analog inputs are connected to the voltage reference.

011 = Temperature measurement. The inputs are connected to a diode circuit that produces a

voltage proportional to the ambient temperature of the device.

Table 15 lists the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting reverts to

the original SYS0 register setting when MUXCAL is taken back to normal operation or offset measurement.

Table 15. MUXCAL Settings

MUXCAL[2:0] PGA GAIN SETTING ADC INPUT

000 Set by SYS0 register Normal operation

001 Set by SYS0 register Offset calibration: inputs shorted to midsupply (AVDD + AVSS)/2

010 Forced to 1 Gain calibration: VREFP – VREFN (full-scale)

011 Forced to 1 Temperature measurement diode

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ADS1146 DETAILED REGISTER DEFINITIONS (continued)

SYS0—System Control Register 0.

SYS0 - ADDRESS 03h RESET VALUE = 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 PGA2 PGA1 PGA0 DOR3 DOR2 DOR1 DOR0

Bit 7 These bits must always be set to '0'.

Bits[6:4] PGA[2:0]

These bits determine the gain of the PGA.

000 = 1 (default)

001 = 2

010 = 4

011 = 8

100 = 16

101 = 32

110 = 64

111 = 128

Bits[3:0] DOR[3:0]

These bits select the output data rate of the ADC. Bits with a value higher than 1001 select the

highest data rate of 2000SPS.

0000 = 5SPS (default)

0001 = 10SPS

0010 = 20SPS

0011 = 40SPS

0100 = 80SPS

0101 = 160SPS

0110 = 320SPS

0111 = 640SPS

1000 = 1000SPS

1001 to 1111 = 2000SPS

OFC[23:0]

These bits make up the offset calibration coefficient register of the ADS1148.

OFC0—Offset Calibration Coefficient Register 0

OFC0 - ADDRESS 04h RESET VALUE = 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OFC7 OFC6 OFC5 OFC4 OFC3 OFC2 OFC1 OFC0

OFC1—Offset Calibration Coefficient Register 1

OFC1 - ADDRESS 05h RESET VALUE = 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC9 OFC8

OFC2—Offset Calibration Coefficient Register 2

OFC2 - ADDRESS 06h RESET VALUE = 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16

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ADS1146 DETAILED REGISTER DEFINITIONS (continued)

FSC[23:0]

These bits make up the full-scale calibration coefficient register.

FSC0—Full-Scale Calibration Coefficient Register 0

FSC0 - ADDRESS 07h RESET VALUE IS PGA DEPENDENT(1)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0

(1) The reset value for FSC is factory-trimmed for each PGA setting. Note that the factory-trimmed FSC reset value is automatically loaded

whenever the PGA setting is changed.

FSC1—Full-Scale Calibration Coefficient Register 1

FSC1 - ADDRESS 08h RESET VALUE IS PGA DEPENDENT(1)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8

(1) The reset value for FSC is factory-trimmed for each PGA setting. Note that the factory-trimmed FSC reset value is automatically loaded

whenever the PGA setting is changed.

FSC2—Full-Scale Calibration Coefficient Register 2

FSC2 - ADDRESS 09h RESET VALUE IS PGA DEPENDENT(1)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16

(1) The reset value for FSC is factory-trimmed for each PGA setting. Note that the factory-trimmed FSC reset value is automatically loaded

whenever the PGA setting is changed.

ID—ID Register

IDAC0 - ADDRESS 0Ah RESET VALUE = x0h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ID3 ID2 ID1 ID0 DRDY MODE 0 0 0

Bits 7:4 ID3:0

Read-only, factory-programmed bits; used for revision identification.

Bit 3 DRDY MODE

This bit sets the DOUT/DRDY pin functionality. In either setting of the DRDY MODE bit, the DRDY

pin continues to indicate data ready, active low.

0 = DOUT/DRDY pin functions only as Data Out (default)

1 = DOUT/DRDY pin functions both as Data Out and Data Ready, active low

Bits 2:0 These bits must always be set to '000'.

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SBAS453F –JULY 2009–REVISED APRIL 2012

ADS1147 AND ADS1148 REGISTER MAP

Table 16. ADS1147 and ADS1148 Register Map

ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

00h MUX0 BCS1 BCS0 MUX_SP2 MUX_SP1 MUX_SP0 MUX_SN2 MUX_SN1 MUX_SN0

01h VBIAS VBIAS7 VBIAS6 VBIAS5 VBIAS4 VBIAS3 VBIAS2 VBIAS1 VBIAS0

02h MUX1 CLKSTAT VREFCON1 VREFCON0 REFSELT1 REFSELT0 MUXCAL2 MUXCAL1 MUXCAL0

03h SYS0 0 PGA2 PGA1 PGA0 DR3 DR2 DR1 DR0

04h OFC0 OFC7 OFC6 OFC5 OFC4 OFC3 OFC2 OFC1 OFC0

05h OFC1 OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC9 OFC8

06h OFC2 OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16

07h FSC0 FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0

08h FSC1 FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8

09h FSC2 FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16

DRDY

0Ah IDAC0 ID3 ID2 ID1 ID0 IMAG2 IMAG1 IMAG0

MODE

0Bh IDAC1 I1DIR3 I1DIR2 I1DIR1 I1DIR0 I2DIR3 I2DIR2 I2DIR1 I2DIR0

0Ch GPIOCFG IOCFG7 IOCFG6 IOCFG5 IOCFG4 IOCFG3 IOCFG2 IOCFG1 IOCFG0

0Dh GPIODIR IODIR7 IODIR6 IODIR5 IODIR4 IODIR3 IODIR2 IODIR1 IODIR0

0Eh GPIODAT IODAT7 IODAT6 IODAT5 IODAT4 IODAT3 IODAT2 IODAT1 IODAT0

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ADS1147 AND ADS1148 DETAILED REGISTER DEFINITIONS

MUX0—Multiplexer Control Register 0. This register allows any combination of differential inputs to be selected

on any of the input channels. Note that this setting can be superceded by the MUXCAL and VBIAS bits.

MUX0 - ADDRESS 00h RESET VALUE = 01h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

BCS1 BCS0 MUX_SP2 MUX_SP1 MUX_SP0 MUX_SN2 MUX_SN1 MUX_SN0

Bits[7:6] BCS[1:0]

These bits select the magnitude of the sensor detect current source.

00 = Burnout current source off (default)

01 = Burnout current source on, 0.5μA

10 = Burnout current source on, 2μA

11 = Burnout current source on, 10μA

Bits[5:3] MUX_SP[2:0]

Positive input channel selection bits.

000 = AIN0 (default)

001 = AIN1

010 = AIN2

011 = AIN3

100 = AIN4 (ADS1148 only)

101 = AIN5 (ADS1148 only)

110 = AIN6 (ADS1148 only)

111 = AIN7 (ADS1148 only)

Bits[2:0] MUX_SN[2:0]

Negative input channel selection bits.

000 = AIN0

001 = AIN1 (default)

010 = AIN2

011 = AIN3

100 = AIN4 (ADS1148 only)

101 = AIN5 (ADS1148 only)

110 = AIN6 (ADS1148 only)

111 = AIN7 (ADS1148 only)

VBIAS—Bias Voltage Register

VBIAS - ADDRESS 01h RESET VALUE = 00h

DEVICE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ADS1148 VBIAS7 VBIAS6 VBIAS5 VBIAS4 VBIAS3 VBIAS2 VBIAS1 VBIAS0

ADS1147 0 0 0 0 VBIAS3 VBIAS2 VBIAS1 VBIAS0

Bits[7:0] VBIAS[7:0]

These bits apply a bias voltage of midsupply (AVDD + AVSS)/2 to the selected analog input.

0 = Bias voltage not enabled (default)

1 = Bias voltage is applied on the corresponding analog input (bit 0 corresponds to AIN0, etc.).

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ADS1147 AND ADS1148 DETAILED REGISTER DEFINITIONS (continued)

MUX1—Multiplexer Control Register 1

MUX1 - ADDRESS 02h RESET VALUE = 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

CLKSTAT VREFCON1 VREFCON0 REFSELT1 REFSELT0 MUXCAL2 MUXCAL1 MUXCAL0

Bit 7 CLKSTAT

This bit is read-only and indicates whether the internal or external oscillator is being used.

0 = Internal oscillator in use

1 = External oscillator in use

Bits[6:5] VREFCON[1:0]

These bits control the internal voltage reference. These bits allow the reference to be turned on or

off completely, or allow the reference state to follow the state of the device. Note that the internal

reference is required for operation of the IDAC functions.

00 = Internal reference is always off (default)

01 = Internal reference is always on

10 or 11 = Internal reference is on when a conversion is in progress and shuts down when the

device receives a shutdown opcode or the START pin is taken low

Bits[4:3] REFSELT[1:0]

These bits select the reference input for the ADC.

00 = REF0 input pair selected (default)

01 = REF1 input pair selected (ADS1148 only)

10 = Onboard reference selected

11 = Onboard reference selected and internally connected to REF0 input pair

Bits[2:0] MUXCAL[2:0]

These bits are used to select a system monitor. The MUXCAL selection supercedes selections

from registers MUX0 and MUX1 (MUX_SP, MUX_SN, and VBIAS).

000 = Normal operation (default)

001 = Offset measurement

010 = Gain measurement

011 = Temperature diode

100 = External REF1 measurement (ADS1148 only)

101 = External REF0 measurement

110 = AVDD measurement

111 = DVDD measurement

Table 17 provides the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting

reverts to the original SYS0 register setting when MUXCAL is taken back to normal operation or offset

measurement.

Table 17. MUXCAL Settings

MUXCAL[2:0] PGA GAIN SETTING ADC INPUT

000 Set by SYS0 register Normal operation

001 Set by SYS0 register Inputs shorted to midsupply (AVDD + AVSS)/2

010 Forced to 1 VREFP – VREFN (full-scale)

011 Forced to 1 Temperature measurement diode

100 Forced to 1 (VREFP1 – VREFN1)/4

101 Forced to 1 (VREFP0 – VREFN0)/4

110 Forced to 1 (AVDD – AVSS)/4

111 Forced to 1 (DVDD – DVSS)/4

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ADS1147 AND ADS1148 DETAILED REGISTER DEFINITIONS (continued)

SYS0—System Control Register 0

SYS0 - ADDRESS 03h RESET VALUE = 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 PGA2 PGA1 PGA0 DOR3 DOR2 DOR1 DOR0

Bit 7 This bit must always be set to '0'

Bits[6:4] PGA[2:0]

These bits determine the gain of the PGA.

000 = 1 (default)

001 = 2

010 = 4

011 = 8

100 = 16

101 = 32

110 = 64

111 = 128

Bits[3:0] DOR[3:0]

These bits select the output data rate of the ADC. Bits with a value higher than 1001 select the

highest data rate of 2000SPS.

0000 = 5SPS (default)

0001 = 10SPS

0010 = 20SPS

0011 = 40SPS

0100 = 80SPS

0101 = 160SPS

0110 = 320SPS

0111 = 640SPS

1000 = 1000SPS

1001 to 1111 = 2000SPS

OFC[23:0]

These bits make up the offset calibration coefficient register of the ADS1148.

OFC0—Offset Calibration Coefficient Register 0

OFC0 - ADDRESS 04h RESET VALUE = 000000h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OFC7 OFC6 OFC5 OFC4 OFC3 OFC2 OFC1 OFC0

OFC1—Offset Calibration Coefficient Register 1

OFC1 - ADDRESS 05h RESET VALUE = 000000h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC9 OFC8

OFC2—Offset Calibration Coefficient Register 2

OFC2 - ADDRESS 06h RESET VALUE = 000000h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16

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SBAS453F –JULY 2009–REVISED APRIL 2012

ADS1147 AND ADS1148 DETAILED REGISTER DEFINITIONS (continued)

FSC[23:0]

These bits make up the full-scale calibration coefficient register.

FSC0—Full-Scale Calibration Coefficient Register 0

FSC0 - ADDRESS 07h RESET VALUE IS PGA DEPENDENT(1)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0

(1) The reset value for FSC is factory-trimmed for each PGA setting. Note that the factory-trimmed FSC reset value is automatically loaded

whenever the PGA setting is changed.

FSC1—Full-Scale Calibration Coefficient Register 1

FSC1 - ADDRESS 08h RESET VALUE IS PGA DEPENDENT(1)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8

(1) The reset value for FSC is factory-trimmed for each PGA setting. Note that the factory-trimmed FSC reset value is automatically loaded

whenever the PGA setting is changed.

FSC2—Full-Scale Calibration Coefficient Register 2

FSC2 - ADDRESS 09h RESET VALUE IS PGA DEPENDENT(1)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16

(1) The reset value for FSC is factory-trimmed for each PGA setting. Note that the factory-trimmed FSC reset value is automatically loaded

whenever the PGA setting is changed.

IDAC0—IDAC Control Register 0

IDAC0 - ADDRESS 0Ah RESET VALUE = x0h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ID3 ID2 ID1 ID0 DRDY MODE IMAG2 IMAG1 IMAG0

Bits[7:4] ID[3:0]

Read-only, factory-programmed bits; used for revision identification.

Bit 3 DRDY MODE

This bit sets the DOUT/DRDY pin functionality. In either setting of the DRDY MODE bit, the DRDY

pin continues to indicate data ready, active low.

0 = DOUT/DRDY pin functions only as Data Out (default)

1 = DOUT/DRDY pin functions both as Data Out and Data Ready, active low

Bits[2:0] IMAG[2:0]

The ADS1147 and ADS1148 have two programmable current source DACs that can be used for

sensor excitation. The IMAG bits control the magnitude of the excitation current. The IDACs require

the internal reference to be on.

000 = off (default)

001 = 50μA

010 = 100μA

011 = 250μA

100 = 500μA

101 = 750μA

110 = 1000μA

111 = 1500μA

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ADS1147 AND ADS1148 DETAILED REGISTER DEFINITIONS (continued)

IDAC1—IDAC Control Register 1

IDAC1 - ADDRESS 0Bh RESET VALUE = FFh

DEVICE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ADS1148 I1DIR3 I1DIR2 I1DIR1 I1DIR0 I2DIR3 I2DIR2 I2DIR1 I2DIR0

ADS1147 0 0 I1DIR1 I1DIR0 0 0 I2DIR1 I2DIR0

The two IDACs on the ADS1147 and ADS1148 can be routed to either the IEXC1 and IEXC2 output pins or

directly to the analog inputs.

Bits[7:4] I1DIR[3:0]

These bits select the output pin for the first current source DAC.

0000 = AIN0

0001 = AIN1

0010 = AIN2

0011 = AIN3

0100 = AIN4 (ADS1148 only)

0101 = AIN5 (ADS1148 only)

0110 = AIN6 (ADS1148 only)

0111 = AIN7 (ADS1148 only)

10x0 = IEXT1 (ADS1148 only)

10x1 = IEXT2 (ADS1148 only)

11xx = Disconnected (default)

Bits[3:0] I2DIR[3:0]

These bits select the output pin for the second current source DAC.

0000 = AIN0

0001 = AIN1

0010 = AIN2

0011 = AIN3

0100 = AIN4 (ADS1148 only)

0101 = AIN5 (ADS1148 only)

0110 = AIN6 (ADS1148 only)

0111 = AIN7 (ADS1148 only)

10x0 = IEXT1 (ADS1148 only)

10x1 = IEXT2 (ADS1148 only)

11xx = Disconnected (default)

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ADS1147 AND ADS1148 DETAILED REGISTER DEFINITIONS (continued)

GPIOCFG—GPIO Configuration Register. The GPIO and analog pins are shared as follows:

GPIO0 shared with REFP0

GPIO1 shared with REFN0

GPIO2 shared with AIN2

GPIO3 shared with AIN3

GPIO4 shared with AIN4 (ADS1148)

GPIO5 shared with AIN5 (ADS1148)

GPIO6 shared with AIN6 (ADS1148)

GPIO7 shared with AIN7 (ADS1148)

GPIOCFG - ADDRESS 0Ch RESET VALUE = 00h

DEVICE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ADS1148 IOCFG7 IOCFG6 IOCFG5 IOCFG4 IOCFG3 IOCFG2 IOCFG1 IOCFG0

ADS1147 0 0 0 0 IOCFG3 IOCFG2 IOCFG1 IOCFG0

Bits[7:0] IOCFG[7:0]

These bits enable the GPIO because the GPIO pins are shared with the analog pins. Note that the

ADS1148 uses all the IOCFG bits, whereas the ADS1147 uses only bits 3:0.

0 = The pin is used as an analog input (default)

1 = The pin is used as a GPIO pin

GPIODIR—GPIO Direction Register

GPIODIR - ADDRESS 0Dh RESET VALUE = 00h

DEVICE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ADS1148 IODIR7 IODIR6 IODIR5 IODIR4 IODIR3 IODIR2 IODIR1 IODIR0

ADS1147 0 0 0 0 IODIR3 IODIR2 IODIR1 IODIR0

Bits[7:0] IODIR[7:0]

These bits control the direction of the GPIO when enabled by the IOCFG bits. Note that the

ADS1148 uses all the IODIR bits, whereas the ADS1147 uses only bits 3:0.

0 = The GPIO is an output (default)

1 = The GPIO is an input

GPIODAT—GPIO Data Register

GPIODAT - ADDRESS 0Eh RESET VALUE = 00h

DEVICE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ADS1148 IODAT7 IODAT6 IODAT5 IODAT4 IODAT3 IODAT2 IODAT1 IODAT0

ADS1147 0 0 0 0 IODAT3 IODAT2 IODAT1 IODAT0

Bits[7:0] IODAT[7:0]

If a GPIO pin is enabled in the GPIOCFG register and configured as an output in the GPIO

Direction register (GPIODIR), the value written to this register appears on the appropriate GPIO

pin. If a GPIO pin is configured as an input in GPIODIR, reading this register returns the value of

the digital I/O pins. Note that the ADS1148 uses all eight IODAT bits, while the ADS1147 uses only

bits 3:0.

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SPI COMMANDS

SPI COMMAND DEFINITIONS

The commands shown in Table 18 control the operation of the ADS1146/7/8. Some of the commands are stand-

alone commands (for example, RESET), whereas others require additional bytes (for example, WREG requires

command, count, and the data bytes).

Operands:

n = number of registers to be read or written (number of bytes – 1)

r = register (0 to 15)

x = don't care

Table 18. SPI Commands

COMMAND TYPE COMMAND DESCRIPTION 1st COMMAND BYTE 2nd COMMAND BYTE

WAKEUP Exit sleep mode 0000 000x (00h, 01h)

SLEEP Enter sleep mode 0000 001x (02h, 03h)

System Control SYNC Synchronize the A/D conversion 0000 010x (04h, 05h) 0000-010x (04,05h)

RESET Reset to power-up values 0000 011x (06h, 07h)

NOP No operation 1111 1111 (FFh)

RDATA Read data once 0001 001x (12h, 13h)

Data Read RDATAC Read data continuously 0001 010x (14h, 15h)

SDATAC Stop reading data continuously 0001 011x (16h, 17h)

Read Register RREG Read from register rrrr 0010 rrrr (2xh) 0000_nnnn

Write Register WREG Write to register rrrr 0100 rrrr (4xh) 0000_nnnn

SYSOCAL System offset calibration 0110 0000 (60h)

Calibration SYSGCAL System gain calibration 0110 0001 (61h)

SELFOCAL Self offset calibration 0110 0010 (62h)

Restricted command.

Restricted 1111 0001 (F1h)

Should never be sent to device.

Product Folder Link(s): ADS1146 ADS1147 ADS1148

DIN

SCLK

DRDY

Status

SLEEP

NormalMode SleepMode

FinishCurrentConversion

NormalMode

StartNewConversion

EighthSCLK

WAKEUP

0000001X 0000000X

Synchronization

OccursHere

2tOSC

SYNC

DIN

SCLK

0000010X 0000010X

SCLK

RESET

1 8

AnySPI

Command

DIN

0.6ms

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SYSTEM CONTROL COMMANDS

WAKEUP—Wake up from sleep mode that is set by the SLEEP command.

Use this command to awaken the device from sleep mode. After execution of the WAKEUP command, the

device wakes up on the rising edge of the eighth SCLK.

SLEEP—Set the device to sleep mode; issue the WAKEUP command to deactivate SLEEP mode.

This command places the part into a sleep (power-saving) mode. When the SLEEP command is issued, the

device completes the current conversion and then goes into sleep mode. Note that this command does not

automatically power-down the internal voltage reference; see the VREFCON bits in the MUX1 register for

each device for further details.

To exit sleep mode, issue the WAKEUP command. Single conversions can be performed by issuing a

WAKEUP command followed by a SLEEP command.

Both WAKEUP and SLEEP are the software command equivalents of using the START pin to control the device.

Figure 41. SLEEP and WAKEUP Commands Operation

SYNC—Synchronize DRDY.

This command resets the ADC digital filter and starts a new conversion. The DRDY pin from multiple devices

connected to the same SPI bus can be synchronized by issuing a SYNC command to all of devices

simultaneously.

Figure 42. SYNC Command Operation

RESET—Reset the device to power-up state.

This command restores the registers to the respective power-up values. This command also resets the digital

filter. RESET is the command equivalent of using the RESET pin to reset the device. However, the RESET

command does not reset the SPI interface. If the RESET command is issued when the SPI interface is in the

wrong state, the device will not reset. The CS pin can be used to reset SPI interface first, and then a RESET

command can be issued to reset the device. The RESET command holds the registers and the decimation

filter in a reset state for 0.6ms when the system clock frequency is 4.096MHz, similar to the hardware reset.

Therefore, SPI communication can be only be started 0.6ms after the RESET command is issued, as shown

in Figure 43.

Figure 43. SPI Communication After an SPI Reset

Product Folder Link(s): ADS1146 ADS1147 ADS1148

DIN

DOUT

DRDY

RDATAC

SCLK

16Bits

18116

NOP

0001010X

DIN

DRDY

0001011X

SDATAC

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DATA RETRIEVAL COMMANDS

RDATAC—Read data continuously.

The RDATAC command enables the automatic loading of a new conversion result into the output data

goes low by sending 16 SCLKs. It is not necessary to read back all the bits, as long as the number of bits

read out is a multiple of eight. The RDATAC command must be issued after DRDY goes low, and the

command takes effect on the next DRDY.

Be sure to complete data retrieval (conversion result or register read-back) before DRDY goes low, or the

resulting data will be corrupt. Successful register read operations in RDATAC mode require the knowledge of

when the next DRDY falling edge will occur.

Figure 44. Read Data Continuously

SDATAC—Stop reading data continuously.

The SDATAC command terminates the RDATAC mode. Afterwards, the conversion result is not

automatically loaded into the output shift register when DRDY goes low, and register read operations can be

performed without interruption from new conversion results being loaded into the output shift register. Use

the RDATA command to retrieve conversion data. The SDATAC command takes effect after the next DRDY.

Figure 45. Stop Reading Data Continuously

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SCLK

DIN

DOUT

DRDY

MSB

0001001X

LSB

1 8 1 16

NOP NOP

RDATA

SCLK

DOUT

DIN

DRDY

NOPNOP NOP RDATA NOP NOP

D[15] D[6] D[1] D[1] D[0]D[9] D[8] D[7]D[14] D[15] D[14]

2 1 29 107 8 15 16 15 16

D[0]

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RDATA—Read data once.

The RDATA command loads the most recent conversion result into the output register. After issuing this

command, the conversion result can be read out by sending 16 SCLKs, as shown in Figure 46. This

command also works in RDATAC mode.

When performing multiple reads of the conversion result, the RDATA command can be sent when the last

eight bits of the conversion result are being shifted out during the course of the first read operation by taking

advantage of the duplex communication nature of the SPI interface, as shown in Figure 47.

Figure 46. Read Data Once

Figure 47. Using RDATA in Full-Duplex Mode

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DIN

DOUT VBIAS

00100001 00000001

1st

Command

Byte

2nd

Command

Byte

MUX1

DataByte DataByte

DIN 01000010 00000001 MUX2 SYS0

1st

Command

2nd

Command

Data

Byte

Data

Byte

ADS1146

ADS1147

ADS1148

SBAS453F –JULY 2009–REVISED APRIL 2012

www.ti.com

USER REGISTER READ AND WRITE COMMANDS

RREG—Read from registers.

This command outputs the data from up to 16 registers, starting with the register address specified as part of

the instruction. The number of registers read is one plus the second byte. If the count exceeds the remaining

registers, the addresses wrap back to the beginning.

1st Command Byte: 0010 rrrr, where rrrr is the address of the first register to read.

2nd Command Byte: 0000 nnnn, where nnnn is the number of bytes to read –1.

It is not possible to use the full-duplex nature of the SPI interface when reading out the register data. For

example, a SYNC command cannot be issued when reading out the VBIAS and MUX1 data, as shown in

Figure 48. Any command sent during the readout of the register data is ignored. Thus, it is advisable to send

NOP through the DIN when reading out the register data.

Figure 48. Read from Register

WREG—Write to registers.

This command writes to the registers, starting with the register specified as part of the instruction. The

number of registers that are written is one plus the value of the second byte.

1st Command Byte: 0100 rrrr, where rrrr is the address of the first register to be written.

2nd Command Byte: 0000 nnnn, where nnnn is the number of bytes to be written – 1.

Data Byte(s): data to be written to the registers.

Figure 49. Write to Register

Product Folder Link(s): ADS1146 ADS1147 ADS1148

SCLK

DIN

DRDY

1 8

tCAL

Calibration

Command

Calibration

Starts

Calibration

Complete

ADS1146

ADS1147

ADS1148

www.ti.com

SBAS453F –JULY 2009–REVISED APRIL 2012

CALIBRATION COMMANDS

The ADS1146/7/8 provide system and offset calibration commands and a system gain calibration command.

SYSOCAL—Offset system calibration.

This command initiates a system offset calibration. For a system offset calibration, the input should be

externally set to zero. The OFC register is updated when this operation completes.

SYSGCAL—System gain calibration.

This command initiates the system gain calibration. For a system gain calibration, the input should be set to

full-scale. The FSC register is updated after this operation.

SELFOCAL—Self offset calibration.

This command initiates a self-calibration for offset. The device internally shorts the inputs and performs the

calibration. The OFC register is updated after this operation.

Figure 50. Calibration Command

Product Folder Link(s): ADS1146 ADS1147 ADS1148

DVDD

START

RESET

DRDY

SCLK

3 00 00 00

Conversionresult

forchannel1

Power-upsequence ADCinitialsetup Multiplexerchangeischannel2 DataRetrievalfor

Channel2Conversion

Initialsetting:

AIN0isthepositivechannel,

AIN1isthenegativechannel,

internalreferenceselected,

PGAgain=32,

datarate=2kSPS,

VBIASisconnectedtothe

negativepinsAIN1andAIN3.

AIN2isthepositivechannel,

AIN3isthenegativechannel.

Conversionresult

forchannel2

01 02 03

WREG WREG

DIN

DOUT

tDRDY

0.513ms

for

MUX0

Write

NOP

16ms(1)

ADS1146

ADS1147

ADS1148

SBAS453F –JULY 2009–REVISED APRIL 2012

www.ti.com

APPLICATION INFORMATION

SPI COMMUNICATION EXAMPLES negative terminal of both sensors (that is, channels

AIN1 and AIN3). All these settings can be changed

This section contains several examples of SPI by performing a block write operation on the first four

communication with the ADS1146/7/8, including the registers of the device. After the DRDY pin goes low,

power-up sequence. the conversion result can be immediately retrieved by

sending in 16 SPI clock pulses because the device

Channel Multiplexing Example defaults to RDATAC mode. As the conversion result

is being retrieved, the active input channels can be

This first example applies only to the ADS1147 and switched to AIN2 and AIN3 by writing into the MUX0

ADS1148. It explains a method to use the device with register in a full-duplex manner, as shown in

two sensors connected to two different analog Figure 51. The write operation is completed with an

channels. Figure 51 shows the sequence of SPI additional eight SPI clock pulses. The time from the

operations performed on the device. After power-up, write operation into the MUX0 register to the next

216 system clocks are required before communication DRDY low transition is shown in Figure 51 and is

may be started. During the first 216 system clock 0.513ms in this case. After DRDY goes low, the

cycles, the devices are internally held in a reset state. conversion result can be retrieved and the active

In this example, one of the sensors is connected to channel can be switched as before.

channels AIN0 and AIN1 and the other sensor is

connected to channels AIN2 and AIN3. The ADC is

operated at a data rate of 2kSPS. The PGA gain is

set to 32 for both sensors. VBIAS is connected to the

(1) For fOSC = 4.096MHz.

Figure 51. SPI Communication Sequence for Channel Multiplexing

Product Folder Link(s): ADS1146 ADS1147 ADS1148

DVDD

START

RESET

DRDY

SCLK

Conversionresult

forchannel1

Power-upsequence ADCinitialsetup

ADCisputtosleep

afterasingleconversion.

Dataareretrievedwhen

ADCissleeping.

Initialsetting:

AIN0isthepositivechannel,

AIN1isthenegativechannel,

internalreferenceselected,

PGAgain=32,

datarate=2kSPS,

VBIASisconnectedtothe

negativepins,AIN1andAIN3.

ADCenters

power-saving

sleepmode

01 02 03

WREG

DIN

DOUT

tDRDY

(0.575ms)

NOP

16ms(1)

ADS1146

ADS1147

ADS1148

www.ti.com

SBAS453F –JULY 2009–REVISED APRIL 2012

Sleep Mode Example be changed by performing a block write operation on

the first four registers of the device. After performing

This second example deals with performing one the block write operation, the START pin can be

conversion after power-up and then entering into the taken low. The device enters the power-saving sleep

power-saving sleep mode. In this example, a sensor mode as soon as DRDY goes low 0.575ms after

is connected to input channels AIN0 and AIN1. writing into the SYS0 register. The conversion result

Commands to set up the devices must occur at least can be retrieved even after the device enters sleep

216 system clock cycles after powering up the mode by sending 16 SPI clock pulses.

devices. The ADC operates at a data rate of 2kSPS.

The PGA gain is set to 32 for both sensors. VBIAS is

connected to the negative terminal of both the

sensors (that is, channel AIN1). All these settings can

(1) For fOSC = 4.096MHz.

Figure 52. SPI Communication Sequence for Entering Sleep Mode After a Conversion

Product Folder Link(s): ADS1146 ADS1147 ADS1148

ADS1146

ADS1147

ADS1148

SBAS453F –JULY 2009–REVISED APRIL 2012

www.ti.com

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (April 2012) to Revision F Page

• Added QFN-32 to listed packages available for the ADS1148 in Description section ......................................................... 1

• Added ADS1148, QFN-32 row to Package/Ordering Information table ............................................................................... 2

• Corrected ADS1148 Pin Description table name ............................................................................................................... 11

Changes from Revision D (October 2011) to Revision E Page

• Added RHB pin configuration ............................................................................................................................................... 6

Changes from Revision C (April 2001) to Revision D Page

• Added footnote to Analog Inputs, Full-scale input voltage parameter typical specification in Electrical Characteristics

table ...................................................................................................................................................................................... 3

• Deleted Analog Inputs, Mux leakage current parameter from Electrical Characteristics table ............................................ 3

• Updated Figure 1 to show tCSPW timing ............................................................................................................................... 12

• Added tCSPW to Timing Characteristics for Figure 1 ............................................................................................................ 12

• Changed tDTS minimum specification in Timing Characteristics for Figure 2 ...................................................................... 12

• Added Figure 7,Figure 8,Figure 9, and Figure 10 ............................................................................................................ 15

• Added Figure 11,Figure 14,Figure 15, and Figure 16 ...................................................................................................... 16

• Corrected Figure 19 to remove constant short ................................................................................................................... 18

• Added Table 3 to Analog Input Impedance section ............................................................................................................ 19

• Corrected Figure 26 and Figure 27 .................................................................................................................................... 21

• Added details to Bias Voltage Generation section ............................................................................................................. 23

• Added details to Calibration section ................................................................................................................................... 25

• Added Equation 8 to Calibration section ............................................................................................................................ 25

• Added details to Calibration Commands section ................................................................................................................ 26

• Added Channel Cycling and Overload Recovery section ................................................................................................... 28

• Corrected Table 12 ............................................................................................................................................................. 29

• Added details to Digital Interface section ........................................................................................................................... 30

• Added Restricted command to Table 18 ............................................................................................................................ 44

Product Folder Link(s): ADS1146 ADS1147 ADS1148

PACKAGE OPTION ADDENDUM

www.ti.com 20-Apr-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

ADS1146IPW ACTIVE TSSOP PW 16 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

ADS1146IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

ADS1147IPW ACTIVE TSSOP PW 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS1147IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS1148IPW ACTIVE TSSOP PW 28 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS1148IPWR ACTIVE TSSOP PW 28 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS1148IRHBR ACTIVE QFN RHB 32 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

ADS1148IRHBT ACTIVE QFN RHB 32 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

PACKAGE OPTION ADDENDUM

www.ti.com 20-Apr-2012

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADS1146IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

ADS1147IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

ADS1148IPWR TSSOP PW 28 2000 330.0 16.4 7.1 10.4 1.6 12.0 16.0 Q1

ADS1148IRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2

ADS1148IRHBT QFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 8-Aug-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS1146IPWR TSSOP PW 16 2000 367.0 367.0 35.0

ADS1147IPWR TSSOP PW 20 2000 367.0 367.0 38.0

ADS1148IPWR TSSOP PW 28 2000 367.0 367.0 38.0

ADS1148IRHBR QFN RHB 32 3000 367.0 367.0 35.0

ADS1148IRHBT QFN RHB 32 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 8-Aug-2012

Pack Materials-Page 2

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