CY62136EV30 MoBL®
2-Mbit (128 K × 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05569 Rev. *E Revised June 16, 2011
2-Mbit (128 K × 16) Static RAM
Features
■Very high speed: 45 ns
■Wide voltage range: 2.20 V to 3.60 V
■Pin compatible with CY62136CV30
■Ultra low standby power
❐Typical standby current: 1 A
❐Maximum standby current: 7 A
■Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■Easy memory expansion with CE and OE features
■Automatic power down when deselected
■Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
■Offered in a Pb-free 48-ball very fine ball grid array (VFBGA)
and 44-pin thin small outline package (TSOP II) packages
Functional Description
The CY62136EV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. The device can
also be put into standby mode reducing power consumption by
more than 99% when deselected (CE HIGH). The input/output
pins (I/O0 through I/O15) are placed in a high impedance state
when: deselected (CE HIGH), outputs are disabled (OE HIGH),
both Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from I/O pins (I/O0 through I/O7), is written into
the location specified on the address pins (A0 through A16). If
Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8
through I/O15) is written into the location specified on the address
pins (A0 through A16).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appear on I/O8 to I/O15. See the Truth Table on page 11
for a complete description of read and write modes.
128K x 16
RAM Array
I/O0–I/O7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12
A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3I/O8–I/O15
CE
WE
BLE
BHE
A16
A0
A1
A9
A10
Logic Block Diagram
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Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
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Pin Configuration
Figure 1. 48-ball VFBGA (Top View) [1, 2] Figure 2. 44-pin TSOP II (Top View) [1]
WE
A11
A10
A6
A0
A3CE
I/O
10
I/O
8
I/O
9
A4
A5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A9
A8
OE
Vss
A7
I/O
0
BHE
NC
NC
A2
A1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5I/O
6
I/O
7
A15
A14
A13
A
12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
A16
NC
Vcc
WE
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
VCC
A15
A14
A13
A4
A3
OE
VSS
A5
I/O15
A2
CE
I/O2
I/O0
I/O1
BHE
A1
A0
18
17
20
19
I/O3
27
28
25
26
22
21
23
24
VSS
I/O6
I/O4
I/O5
I/O7
A6
A7
BLE
VCC
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
A12 NC
NC
A16
Product Portfolio
Product [3] VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA) Standby ISB2 (A)
f = 1 MHz f = fmax
Min Typ [3] Max Typ [3] Max Typ [3] Max Typ [3] Max
CY62136EV30LL 2.2 3.0 3.6 45 2 2.5 15 20 1 7
Notes
1. NC pins are not connected on the die.
2. Pins D3, H1, G2, H6 and H3 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb and 64 Mb respectively.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C.
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Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature with
power applied ......................................... –55 °C to + 125 °C
Supply voltage to ground
potential ........................... –0.3 V to 3.9 V (VCC MAX + 0.3 V)
DC voltage applied to outputs
in High Z state [4, 5] .......... –0.3 V to 3.9 V (VCC MAX + 0.3 V)
DC input voltage [4, 5] ....... –0.3 V to 3.9 V (VCC MAX + 0.3 V)
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage ......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch up current ..................................................... > 200 mA
Operating Range
Device Range Ambient
Temperature VCC[6]
CY62136EV30LL Industrial –40 °C to +85 °C 2.2 V - 3.6 V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions 45 ns Unit
Min Typ [7] Max
VOH Output HIGH voltage IOH = –0.1 mA VCC = 2.20 V 2.0 – – V
IOH = –1.0 mA VCC = 2.70 V 2.4 – – V
VOL Output LOW voltage IOL = 0.1 mA VCC = 2.20 V – – 0.4 V
IOL = 2.1 mA VCC = 2.70 V – – 0.4 V
VIH Input HIGH voltage VCC = 2.2 V to 2.7 V 1.8 – VCC + 0.3 V
VCC= 2.7 V to 3.6 V 2.2 – VCC + 0.3 V
VIL Input LOW voltage VCC = 2.2 V to 2.7 V –0.3 – 0.6 V
VCC= 2.7 V to 3.6 V –0.3 – 0.8 V
IIX Input leakage current GND < VI < VCC –1 – +1 A
IOZ Output leakage current GND < VO < VCC, output disabled –1 – +1 A
ICC VCC operating supply
current
f = fmax = 1/tRC VCC = VCCmax, IOUT = 0 mA
CMOS levels
–1520mA
f = 1 MHz – 2 2.5
ISB1[8] Automatic CE
power-down current —
CMOS inputs
CE > VCC0.2 V,
VIN > VCC – 0.2 V, VIN< 0.2 V
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = 3.60 V
–17A
ISB2 [8] Automatic CE
power-down current —
CMOS inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2V, f = 0,
VCC = 3.60 V
–17A
Notes
4. VIL(min.) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C.
8. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating.
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Capacitance
Parameter [9] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz, VCC = VCC(typ) 10 pF
COUT Output capacitance 10 pF
Thermal Resistance
Parameter [9] Description Test Conditions 48-ball VFBGA
Package
44-pin TSOP II
Package Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
75 77 C/W
JC Thermal resistance
(junction to case) 10 13 C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
VCC VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT VTH
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Parameters 2.50 V 3.0 V Unit
R1 16667 1103
R2 15385 1554
RTH 8000 645
VTH 1.20 1.75 V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
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Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ [10] Max Unit
VDR VCC for data retention 1.0 – – V
ICCDR [11] Data retention current VCC= 1.0 V, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
–0.83A
tCDR[12] Chip deselect to data
retention time
0––ns
tR[13] Operation recovery time 45 – – ns
Data Retention Waveform
Figure 4. Data Retention Waveform [14]
VCC(min)
VCC(min)
tCDR
VDR >1.0 V
DATA RETENTION MODE
tR
VCC
CE
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C.
11. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s.
14. BHE.BLE is the AND of both BHE and BLE. The chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
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Switching Characteristics
Over the Operating Range
Parameter [15, 16] Description 45 ns Unit
Min Max
Read Cycle
tRC Read cycle time 45 – ns
tAA Address to data valid – 45 ns
tOHA Data hold from address change 10 – ns
tACE CE LOW to data valid – 45 ns
tDOE OE LOW to data valid – 22 ns
tLZOE OE LOW to Low Z [17] 5–ns
tHZOE OE HIGH to High Z [17, 18] –18ns
tLZCE CE LOW to Low Z [17] 10 – ns
tHZCE CE HIGH to High Z [17, 18] –18ns
tPU CE LOW to power-up 0 – ns
tPD CE HIGH to power-down – 45 ns
tDBE BLE/BHE LOW to data valid – 22 ns
tLZBE BLE/BHE LOW to Low Z [17] 5–ns
tHZBE BLE/BHE HIGH to High Z [17, 18] –18ns
Write Cycle [19]
tWC Write cycle time 45 – ns
tSCE CE LOW to write end 35 – ns
tAW Address setup to write end 35 – ns
tHA Address hold from write end 0 – ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 35 – ns
tBW BLE/BHE LOW to write end 35 – ns
tSD Data setup to write end 25 – ns
tHD Data hold from write end 0 – ns
tHZWE WE LOW to High Z [17, 18] –18ns
tLZWE WE HIGH to Low Z [17] 10 – ns
Notes
15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in Figure 3 on page 5.
16. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Refer application note AN13842 for more information.
17. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
19. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and BLE = VIL. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
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Switching Waveforms
Figure 5. Read Cycle 1: Address Transition Controlled [20, 21]
Figure 6. Read Cycle No. 2: OE Controlled [21, 22]
.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
DATA OUT HIGH IMPEDANCE IMPEDANCE
I
CC
I
SB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
CC
SUPPLY
CURRENT
t
HZBE
BHE/BLE t
LZOE
ADDRESS
t
DBE
t
DOE
Notes
20. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
21. WE is HIGH for read cycle.
22. Address valid prior to or coincident with CE and BHE, BLE transition LOW.
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Figure 7. Write Cycle No. 1: WE Controlled [23, 24, 25]
Figure 8. Write Cycle No. 2: CE Controlled [23, 24, 25]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
DATA I/O
ADDRESS
CE
WE
OE
tHZOE
DATAIN
NOTE 26
BHE/BLE tBW
tSCE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN
CE
ADDRESS
WE
DATA I/O
OE
NOTE 26
BHE/BLE tBW
tSA
Notes
23. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and BLE = VIL. All signals must be ACTIVE to initiate a write and any of
these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates
the write.
24. Data I/O is high impedance if OE = VIH.
25. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
26. During this period, the I/Os are in output state and input signals should not be applied.
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Figure 9. Write Cycle No. 3: WE Controlled, OE LOW [27]
Figure 10. Write Cycle No. 4: BHE/BLE Controlled, OE LOW [27]
Switching Waveforms (continued)
DATAIN
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATAI/O NOTE 28
tBW
BHE/BLE
DATA I/O
ADDRESS
t
SD
t
SA
t
HA
t
AW
tWC
CE
WE
DATA
IN
NOTE 28
t
BW
BHE/BLE
tSCE
t
PWE
tHZWE tHD
tLZWE
Notes
27. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state
28. During this period, the I/Os are in output state and input signals should not be applied.
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Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
H[29] XXX
[29] X[29] High Z Deselect/power-down Standby (ISB)
L X X H H High Z Output disabled Active (ICC)
L H L L L Data out (I/OO–I/O15) Read Active (ICC)
LHLHLData out (I/O
O–I/O7);
I/O8–I/O15 in High Z
Read Active (ICC)
L H L L H Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read Active (ICC)
L H H L L High Z Output disabled Active (ICC)
L H H H L High Z Output disabled Active (ICC)
L H H L H High Z Output disabled Active (ICC)
L L X L L Data in (I/OO–I/O15) Write Active (ICC)
L L X H L Data in (I/OO–I/O7);
I/O8–I/O15 in High Z Write Active (ICC)
L L X L H Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write Active (ICC)
Note
29. Chip enable (CE) and Byte enables (BHE and BLE) must be at fixed CMOS levels (not floating). Intermediate voltage levels on these pins is not permitted.
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Ordering Code Definitions
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
45 CY62136EV30LL-45BVXI 51-85150 48-ball Very Fine-Pitch Ball Grid Array (Pb-free) Industrial
CY62136EV30LL-45ZSXI 51-85087 44-pin Thin Small Outline Package II (Pb-free)
Contact your local Cypress sales representative for availability of other parts
Temperature Grade: I = Industrial
Pb-free
Package Type: XX = BV or ZS
BV = 48-ball VFBGA
ZS = 44-pin TSOP II
Speed Grade: 45 ns
Low Power
Voltage Range: 3 V typical
Process Technology: 90 nm
Bus width = × 16
Density = 2-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
CY -XX
621 36ELL I
45 X
V30
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Acronyms Document Conventions
Units of Measure
Figure 12. 44-pin TSOP Z44-II, 51-85087
Package Diagrams (continued)
51-85087 *C
Acronym Description
BLE byte low enable
BHE byte high enable
CE chip enable
CMOS complementary metal oxide semiconductor
I/O input/output
OE output enable
SRAM static random access memory
TSOP thin small outline package
VFBGA very fine-pitch ball grid array
WE write enable
Symbol Unit of Measure
°C degree Celsius
MHz Mega Hertz
Amicro Amperes
smicro seconds
mA milli Amperes
mm milli meter
ns nano seconds
ohms
%percent
pF pico Farads
VVolts
WWatts
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Document History Page
Document Title: CY62136EV30 MoBL®, 2-Mbit (128 K × 16) Static RAM
Document Number: 38-05569
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 237432 AJU See ECN New Data Sheet
*A 419988 RXU See ECN Converted from Advanced Information to Final.
Changed the address of Cypress Semiconductor Corporation on Page #1 from
“3901 North First Street” to “198 Champion Court”
Removed 35ns Speed Bin
Removed “L” version of CY62136EV30
Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from
1.5 mA to 2 mA at f=1 MHz
Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax
Changed ISB1 and ISB2 Typ. values from 0.7 A to 1 A and Max. values from
2.5 A to 7 A.
Changed the AC test load capacitance from 50pF to 30pF on Page# 4
Changed VDR from 1.5V to 1V on Page# 4.
Changed ICCDR from 2.5 A to 3 A.
Added ICCDR typical value.
Changed tOHA , tLZCE and tLZWE from 6 ns to 10 ns
Changed tLZBE from 6 ns to 5 ns
Changed tLZOE from 3 ns to 5 ns
Changed tHZOE, tHZCE, tHZBE and tHZWE from 15 ns to 18 ns
Changed tSCE,tAW and tBW from 40 ns to 35 ns
Changed tPWE from 30 ns to 35 ns
Changed tSD from 20 ns to 25 ns
Corrected typo in the Truth Table on Page# 9
Updated the package diagram 48-pin VFBGA from *B to *D
Updated the ordering Information table and replaced the Package Name
column with Package Diagram.
*B 427817 NXR See ECN Minor change: Moved datasheet to external web
*C 2604685 VKN/PYRS 11/12/08 Added footnote 8 related to ISB2 and ICCDR
Added footnote 12 related to AC timing parameters
*D 3144174 RAME 01/17/2011 Added Acronyms and Units of Measure.
Added Ordering Code Definitions.
Update Package Diagrams 51-85150 from *D to *F
Converted all tablenotes into footnotes.
Added TOC
Updated datasheet as per new template.
*E 3284728 AJU 06/16/2011 Removed the Note “For best practice recommendations, refer to the Cypress
application note “SRAM System Design Guidelines” on
http://www.cypress.com.” in page 1 and its reference in Functional Description.
Updated in new template.
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Document #: 38-05569 Rev. *E Revised June 16, 2011 Page 16 of 16
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY62136EV30 MoBL®
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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