128Mb: x16, x32 Mobile SDRAM Features Mobile SDRAM MT48LC8M16LF, MT48V8M16LF, MT48LC4M32LF, MT48V4M32LF Features Options * Temperature-compensated self refresh (TCSR) * Fully synchronous; all signals registered on positive edge of system clock * Internal pipelined operation; column address can be changed every clock cycle * Internal banks for hiding row access/precharge * Programmable burst lengths: 1, 2, 4, 8, or full page * Auto precharge, includes concurrent auto precharge, and auto refresh modes * Self refresh mode; standard and low power (not available on AT devices) * Auto refresh - 64ms, 4,096-cycle refresh (15.6s/row) (commercial and industrial) - 16ms, 4,096-cycle refresh (3.9s/row) (automotive) * LVTTL-compatible inputs and outputs * Low voltage power supply * Partial-array self refresh (PASR) power-saving mode * VDD/VDDQ - 3.3V/3.3V - 2.5V/2.5-1.8V * Configurations - 8 Meg x 16 (2 Meg x 16 x 4 banks) - 4 Meg x 32 (1 Meg x 32 x 4 banks) * Package/ball out - 54-ball VFBGA (8mm x 8mm)1 - 54-ball VFBGA (8mm x 8mm)1 Pb-free - 90-ball VFBGA (8mm x 13mm)2 - 90-ball VFBGA (8mm x 13mm)2 Pb-free - 54-pin TSOP II (400 mil) - 54-pin TSOP II (400 mil) Pb-free * Timing (cycle time) - 7.5ns @ CL = 3 (133 MHz) - 8ns @ CL = 3 (125 MHz) - 10ns @ CL = 3 (100 MHz) * Temperature - Commercial (0C to +70C) - Industrial (-40C to +85C) - Automotive (-40C to +105C) * Design revision Notes: 1. x16 only. 2. x32 only. 3. Contact Micron for availability. Table 1: Key Timing Parameters CL = CAS (READ) latency Access Time Speed Clock Grade Frequency CL = 1 CL = 2 CL = 3 tRCD -75M -8 -10 -75M -8 -10 -8 -10 133 MHz 125 MHz 100 MHz 100 MHz 100 MHz 83 MHz 50 MHz 40 MHz - - - - - - 19ns 22ns - - - 6 8ns 8ns - - 5.4 7ns 7ns - - - - - 19ns 20ns 20ns 19ns 20ns 20ns 20ns 20ns tRP 19ns 20ns 20ns 19ns 20ns 20ns 20ns 20ns Table 2: Mark LC V 8M16 4M32 F4 B4 F5 B5 TG3 P3 -75M3 -8 -103 None IT AT3 :G Configurations Configuration Refresh count Row addressing Bank addressing Column addressing 8 Meg x 16 4 Meg x 32 2 Meg x 16 x 4 banks 4K 4K (A0-A11) 4 (BA0, BA1) 512 (A0-A8) 1 Meg x 32 x 4 banks 4K 4K (A0-A11) 4 (BA0, BA1) 256 (A0-A7) Part Number Example: MT48V8M16LFB4-8:G PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_1.fm - Rev. M 1/09 EN 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 128Mb: x16, x32 Mobile SDRAM Table of Contents Table of Contents FBGA Part Marking Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Automotive Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Pin/Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Burst Length (BL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Write Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Temperature-Compensated Self Refresh (TCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Partial-Array Self Refresh (PASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 COMMAND INHIBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 NO OPERATION (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 ACTIVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 AUTO REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 SELF REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 BANK/ROW ACTIVATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 CLOCK SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Burst Read/Single Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 CONCURRENT Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 READ with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32MobileTOC.fm - Rev. M 12/08 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM List of Figures List of Figures Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Figure 55: Figure 56: Figure 57: Functional Block Diagram 8 Meg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Functional Block Diagram 4 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 90-Ball FBGA Pin Assignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 54-Pin TSOP Pin Assignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 54-Ball VFBGA Pin Assignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 READ-to-WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Clock Suspend During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Example Temperature Test Point Location, 54-Pin TSOP: Top View . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Example Temperature Test Point Location, 54-Ball VFBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . .51 Example Temperature Test Point Location, 90-Ball VFBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . .51 Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 READ - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Read - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Single Read - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Single Read - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Read - Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Read - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Write - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Write - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Single Write - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Single Write - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Alternating Bank Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Write - Full-page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Write - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 54-Ball FBGA, "F4/B4" Package (x16 Device), 8mm x 8mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32MobileLOF.fm - Rev. M 12/08 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM List of Figures Figure 58: Figure 59: 90-Ball FBGA, "F5/B5" Package (x32 Device), 8mm x 13mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 54-Pin Plastic TSOP (400 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32MobileLOF.fm - Rev. M 12/08 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Ball Descriptions: 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Ball Descriptions: 90-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Pin Descriptions: 54-Pin TSOP (x16 Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Truth Table - Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Truth Table - CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Truth Table - Current State Bank n, Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Truth Table - CURRENT STATE BANK n, COMMAND tO BANK m . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Thermal Impedance Simulated Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 DC Electrical Characteristics and Operating Conditions (LC Version). . . . . . . . . . . . . . . . . . . . . . . . . .52 DC Electrical Characteristics and Operating Conditions (V Version) . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .53 AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 IDD Specifications and Conditions (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 IDD7 Self Refresh Current Options (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 IDD Specifications And Conditions (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 IDD7 Self Refresh Current Options (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Capacitance (FBGA Pacakge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Capacitance (TSOP Pacakge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32MobileLOT.fm - Rev. M 12/08 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM FBGA Part Marking Decoder Figure 1: 128Mb SDRAM Part Numbers Example Part Number: MT48V4M32LFF5-10XT MT48 VDD/ VDDQ Configuration LF Package Speed Temperature Revision Voltage (VDD/VDDQ) Rev 3.3V/ 3.3V LC 2.5V / 2.5V-1.8V V :G Revision Operating Temp Configuration Standard 8 Meg x 16 8M16 IT Industrial 4 Meg x 32 4M32 AT Automotive Speed Grade Package 54-ball VFBGA (8 x 8mm) 54-ball VFBGA (8 x 8mm) lead-free 90-ball VFBGA (8 x 13mm) 90-ball VFBGA (8 x 13mm) lead-free 54-pin TSOP II (400 mil) 54-pin TSOP II (400 mil) Lead-Free Notes: F4 B4 F5 B5 TG2 P2 -75M2 t -8 t -102 t CK = 7.5ns, CL = 3 CK = 8ns, CL = 3 CK = 10ns, CL = 3 1. Not all speeds and configurations are available. 2. Contact Micron for availability. FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron's new FBGA Part Marking Decoder makes it easier to understand that part marking. Visit the Web site at www.micron.com/decoder. General Description The Micron(R) 128Mb SDRAM device is a high-speed CMOS, dynamic random access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16's 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. Each of the x32's 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM General Description The 128Mb SDRAM device uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also enables the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless high-speed, random-access operation. The 128Mb SDRAM device is designed to operate in 3.3V or 2.5V low-power memory systems. The 2.5V version is compatible with 1.8V I/O interface. An auto refresh mode is provided along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. Automotive Temperature The automotive temperature (AT) option adheres to the following specifications: * 16ms refresh rate * Self refresh not supported * Ambient and case temperature cannot be less than -40C or greater than +105C PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM General Description Figure 2: Functional Block Diagram 8 Meg x 16 SDRAM CKE CLK COMMAND DECODE CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 MODE REGISTER REFRESH 12 COUNTER 12 ROWADDRESS MUX 12 12 BANK0 ROWADDRESS LATCH & DECODER 4096 BANK0 MEMORY ARRAY (4,096 x 512 x 16) 2 DQML, DQMH SENSE AMPLIFIERS 16 4,096 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 2 A0-A11, BA0, BA1 14 ADDRESS REGISTER 2 BANK CONTROL LOGIC DATA OUTPUT REGISTER 16 16 512 (x16) 2 DQ0DQ15 DATA INPUT REGISTER COLUMN DECODER 9 PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN COLUMNADDRESS COUNTER/ LATCH 9 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM General Description Figure 3: Functional Block Diagram 4 Meg x 32 SDRAM CKE CLK COMMAND DECODE CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 BANK0 MODE REGISTER REFRESH 12 COUNTER 12 ROWADDRESS MUX 12 12 BANK0 ROWADDRESS 4,096 LATCH & DECODER BANK0 MEMORY ARRAY (4,096 x 256 x 32) 4 DQM0- DQM3 SENSE AMPLIFIERS 32 4096 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 2 A0-A11, BA0, BA1 14 ADDRESS REGISTER 2 BANK CONTROL LOGIC DATA OUTPUT REGISTER 32 32 256 (x32) 4 DQ0- DQ31 DATA INPUT REGISTER COLUMN DECODER 8 PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN COLUMNADDRESS COUNTER/ LATCH 8 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Pin/Ball Assignments and Descriptions Pin/Ball Assignments and Descriptions Figure 4: 90-Ball FBGA Pin Assignments (Top View) 1 2 3 DQ26 DQ24 DQ28 4 5 6 7 8 9 VSS VDD DQ23 DQ21 VDDQ VSSQ VDDQ VSSQ DQ19 VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ VDDQ DQ31 NC NC DQ16 VSSQ VSS DQM3 A3 A2 DQM2 VDD A4 A5 A6 A10 A0 A1 A7 A8 NC NC BA1 A11 CLK CKE A9 BA0 CS# RAS# DQM1 NC NC CAS# WE# DQM0 VDDQ DQ8 VSS VDD DQ7 VSSQ VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 DQ13 DQ15 VSS VDD DQ0 DQ2 A B C D E F G H J K L M N P R PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Pin/Ball Assignments and Descriptions Figure 5: 54-Pin TSOP Pin Assignments (Top View) x16 x16 VDD DQ0 VDDQ DQ1 DQ2 VssQ DQ3 DQ4 VDDQ DQ5 DQ6 VssQ DQ7 VDD DQML WE# CAS# RAS# CS# BA0 BA1 A10 A0 A1 A2 A3 VDD Notes: Figure 6: 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Vss DQ15 VssQ DQ14 DQ13 VDDQ DQ12 DQ11 VssQ DQ10 DQ9 VDDQ DQ8 Vss NC DQMH CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss 1. The # symbol indicates signal is active LOW. 54-Ball VFBGA Pin Assignments (Top View) 1 2 3 A VSS DQ15 B DQ14 C 4 5 6 7 8 9 VSSQ VDDQ DQ0 VDD DQ13 VDDQ VSSQ DQ2 DQ1 DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 E DQ8 NC VSS VDD LDQM DQ7 F UDQM CLK CKE CAS# RAS# WE# G NC/A12 A11 A9 BA0 BA1 CS# H A8 A7 A6 A0 A1 A10 J VSS A5 A4 A3 A2 VDD Top View (Ball Down) PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Pin/Ball Assignments and Descriptions Table 3: Ball Descriptions: 54-Ball VFBGA 54-Ball VFBGA Symbol Type Description F2 CLK Input F3 CKE Input G9 CS# Input F7, F8, F9 CAS#, RAS#, WE# LDQM, UDQM Input G7, G8 BA0, BA1 Input H7, H8, J8, J7, J3, J2, H3, H2, H1, G3, H9, G2 A0-A6 A7-A11 Input A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2 E2, G1 DQ0-DQ5 DQ6-DQ11 DQ12-DQ15 NC I/O Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides precharge power-down and SELF REFRESH operation (all banks idle), active power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already in progress will continue and DQM will retain its DQ mask capability while CS# remains HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command inputs: CAS#, RAS#, and WE# (along with CS#) define the command being entered. Input/Output mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (2-clock latency) during a READ cycle. LDQM corresponds to DQ0- DQ7, and UDQM corresponds to DQ8-DQ15. LDQM and UDQM are considered same state when referenced as DQM. Bank address input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command. Address inputs: A0-A11 are sampled during the ACTIVE command (rowaddress A0-A11) and READ/WRITE command (column-address A0-A8; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Data input/output: Data bus. A7, B3, C7, D3 A3, B7, C3, D7 A9, E7, J9 A1, E3, J1 VDDQ VSSQ VDD VDD Supply Supply Supply Supply E8, F1 PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN Input - No connect: These pins should be left unconnected. G1 is a no connect for this part but may be used as A12 in future designs. DQ power: Isolated DQ power on the die to improve noise immunity. DQ ground: Isolated DQ power on the die to improve noise immunity. Power supply: Voltage dependant on option. Ground. 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Pin/Ball Assignments and Descriptions Table 4: Ball Descriptions: 90-Ball VFBGA 90-Ball FBGA Symbol Type Description J1 CLK Input J2 CKE Input J8 CS# Input J9, K7, K8 Input K9, K1, F8, F2 RAS#, CAS#, WE# DQM0-3 Input J7, H8 BA0, BA1 Input G8, G9, F7, F3, G1, G2, G3, H1, H2, J3, G7, H9 A0-A5 A6-A11 Input R8, N7, R9, N8, P9, M8, M7, L8, L2, M3, M2, P1, N2, R1, N3, R2, E8, D7, D8, B9, C8, A9, C7, A8, A2, C3, A1, C2, B1, D2, D3, E2 E3, E7, H3, H7, K2, K3 DQ0-DQ5 DQ6-DQ11 DQ12-DQ17 DQ18-DQ23 DQ24-DQ29 DQ30-DQ31 NC I/O Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides precharge power-down and SELF REFRESH operation (all banks idle), active power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already in progress will continue and DQM will retain its DQ mask capability while CS# remains HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. Input/Output mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (2-clock latency) during a READ cycle. DQM0 corresponds to DQ0- DQ7, DQM1 corresponds to DQ8-DQ15, DQM2 corresponds to DQ16- DQ23, and DQM3 corresponds to DQ24-DQ31. DQM0-3 are considered same state when referenced as DQM. Bank address input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command. Address inputs: A0-A11 are sampled during the ACTIVE command (rowaddress A0-A11) and READ/WRITE command (column-address A0-A7; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Data input/output: Data bus. B2, B7, C9, D9, E1, L1, M9, N9, P2, P7 B8, B3, C1, D1, E9, L9, M1, N1, P3, P8 A7, F9, L7, R7 A3, F1, L3, R3 VDDQ No connect: These pins should be left unconnected. H3 is a no connect for this part, but may be used as A12 in future designs. Supply DQ power: Isolated DQ power on the die to improve noise immunity. VSSQ Supply DQ ground: Isolated DQ power on the die to improve noise immunity. VDD VSS Supply Power supply: Voltage dependant on option. Supply Ground. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN - 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Pin/Ball Assignments and Descriptions Table 5: Pin Descriptions: 54-Pin TSOP (x16 Only) 54-Pin TSOP Symbol Type Description 38 CLK Input 37 CKE Input 19 CS# Input 16, 17, 18 WE#, CAS#, RAS# DQML, DQMH Input 20, 21 BA0, BA1 Input 23, 24, 25, 29, 30, 31, 32, 33, 34, 22, 35 A0-A5 A6-A11 Input 2, 4, 5, 7, 8, 10, 11, 13, 42, 49, 45, 47, 48, 50, 51 36, 40 DQ0-DQ7 DQ8-DQ15 NC I/O Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides precharge power-down and SELF REFRESH operation (all banks idle), active power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already in progress will continue and DQM will retain its DQ mask capability while CS# remains HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command inputs: WE#, CAS#, and RAS# (along with CS#) define the command being entered. Input/Output mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (2-clock latency) during a READ cycle. DQM0 corresponds to DQ0- DQ7, DQM1 corresponds to DQ8-DQ15, DQM2 corresponds to DQ16- DQ23, and DQM3 corresponds to DQ24-DQ31. LDQM corresponds to DQ0-DQ7, and UDQM corresponds to DQ8-DQ15. LDQM and UDQM are considered same state when referenced as DQM. Bank address input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command. Address inputs: A0-A11 are sampled during the ACTIVE command (rowaddress A0-A11) and READ/WRITE command (column-address A0-A7; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Data input/output: Data bus (x16 only). 3, 9, 43, 49 6, 12, 46, 52 1, 14, 27 28, 41, 54 VDDQ VSSQ VDD VSS Supply Supply Supply Supply 15, 39 PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN Input - No connect: These pins should be left unconnected. Pin 36 is a no connect for this part, but may be used as A12 in future designs. DQ power: Isolated DQ power on the die to improve noise immunity. DQ ground: Isolated DQ power on the die to improve noise immunity. Power supply: Voltage dependant on option. Ground. 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Functional Description Functional Description In general, the 128Mb SDRAMs (2 Meg x 16 x 4 banks and 1 Meg x 32 x 4 banks) are quadbank DRAMs that operate at 3.3V or 2.5V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16's 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. Each of the x32's 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A11 select the row). The address bits (x16: A0-A8; x32: A0-A7) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. After power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100s delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100s period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands must be applied. After the 100s delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it must be loaded prior to applying any operational command. If desired, the two AUTO REFRESH commands can be issued after the LOAD MODE REGISTER (LMR) command. The recommended power-up sequence for SDRAMs: 1. Simultaneously apply power to VDD and VDDQ. 2. Assert and hold CKE at a LVTTL logic LOW. 3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing constraints specified for the clock pin. 4. Wait at least 100s prior to issuing any command other than a COMMAND INHIBIT or NOP. 5. Starting at some point during this 100s period, bring CKE HIGH. Continuing at least through the end of this period, one or more COMMAND INHIBIT or NOP commands must be applied. 6. Perform a PRECHARGE ALL command. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Register Definition 7. Wait at least tRP time; during this time, NOPs or DESELECT commands must be given. All banks will complete their precharge, thereby placing the device in the all banks idle state. 8. Issue an AUTO REFRESH command. 9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands are allowed. 10. Issue an AUTO REFRESH command. 11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands are allowed. 12. The SDRAM is now ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded with desired bit values prior to applying any operational command. Using the LMR command, program the mode register. The mode register is programmed via the MODE REGISTER SET command with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again or the device loses power. Not programming the mode register upon initialization will result in default settings, which may not be desired. Outputs are guaranteed High-Z after the LMR command is issued. Outputs should be High-Z already before the LMR command is issued. 13. Wait at least tMRD time, during which only NOP or DESELECT commands are allowed. 14. Using the LMR command, program the extended mode register. The low-power extended mode register is programmed via the MODE REGISTER SET command with BA1 = 1, BA0 = 0 and retains the stored information until it is programmed again or the device loses power. Not programming the extended mode register upon initialization will result in default settings for the low-power features. The extended mode will default with the temperature sensor enabled, full drive strength, and full array refresh. 15. Wait at least tMRD time, during which only NOP or DESELECT commands are allowed. At this point, the DRAM is ready for any valid command. Note: If desired, more than two AUTO REFRESH commands can be issued in the sequence. After steps 9 and 10 are complete, repeat them until the desired number of AUTO REFRESH + tRFC loops is achieved. Register Definition Mode Register To achieve low power consumption, there are two mode registers in the Mobile component: mode register and extended mode register. Mode register is discussed in this section. Extended mode register is discussed on page 21. The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of BL, a burst type, CL, an operating mode, and a write burst mode, as shown in Figure 7 on page 18. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0-M2 specify BL, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify CL, M7 and M8 specify the operating mode, M9 specify the write burst mode (single or programmed burst length), M10 and M11 are reserved and must be set to zero. To address the mode register, M12 and M13 must be set to zero. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Register Definition The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length (BL) Read and write accesses to the SDRAM are burst oriented, with BL being programmable, as shown in Figure 8 on page 20. BL determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential mode. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. If a full page burst is not terminated at the end of the page, it could wrap to column zero and continue. Reserved states cannot be used because unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to BL is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1- A8 (x16) or A1-A7 (x32) when BL = 2; by A2-A8 (x16) or A2-A7 (x32) when BL = 4; and by A3-A8 (x16) or A3-A7 (x32) when BL = 8. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Burst Type Accesses within a given burst may be programmed either to be sequential or interleaved; this is referred to as the burst type and is selected via bit M3. Note only a sequential burst is allowed for full page bursts. The ordering of accesses within a burst is determined by BL, the burst type, and the starting column address, as shown in Table 6 on page 19. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Register Definition Figure 7: Mode Register Definition BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 MR Reserved WB Op Mode CAS Latency BT Burst Length Mode Register Definition M13 M12 0 0 1 0 Mode Register (Mx) Burst Length Program Mode Register M2 M1 M0 M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 Operating Mode 1 0 0 Reserved Reserved Program Extended Mode Register M11 M10 M9 M8 M7 M6-M0 0 0 Valid 0 0 Valid Normal Operation 1 0 1 Reserved Reserved - - - - - - All other states reserved 1 1 0 Reserved Reserved 1 1 1 Reserved Reserved M6 M5 M4 CAS Latency M9 Write Burst Mode 0 Programmed Burst Length 0 0 0 Reserved Single Location Access 0 0 1 1 M3 0 1 0 2 0 Sequential 0 1 1 3 1 Interleaved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved 0 PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 18 Burst Type Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Register Definition Table 6: Burst Definition Burst Length 2 4 8 Full page (y) Starting Column Address A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 n = A0-A8 for x16, A0- A7 for x32 (location 0-y) Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2, Cn + 3, Cn + 4..., ...Cn - 1, Cn... 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not supported NOTE: Notes: 1. For full-page accesses: y = 512 (x16), y = 256 (x32). 2. For BL = 2, A1-A8 (x16) or A1-A7 (x32) select the block-of-two burst; A0 selects the starting column within the block. 3. For BL = 4, A2-A8 (x16) or A2-A7 (x32) select the block-of-four burst; A0-A1 select the starting column within the block. 4. For BL = 8, A3-A8 (x16) or A3-A7 (x32) select the block-of-eight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected, and A0-A8 (x16) or A0-A7 (x32) select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For BL = 1, A0-A8 (x16) or A0-A7 (x32) select the unique column to be accessed, and mode register bit M3 is ignored. CAS Latency (CL) CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to 1, 2, or 3 clocks. If a READ command is registered at clock edge n and the latency is m clocks, the data will be available by clock edge n + m. The DQ will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at T0 and the PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Register Definition latency is programmed to 2 clocks, the DQ will start driving after T1, and the data will be valid by T2, as shown in Figure 8. Table 7 indicates the operating frequencies at which each CL setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 8: CAS Latency T0 T1 T2 READ NOP CLK COMMAND tLZ tOH DOUT DQ tAC CL = 1 T0 T1 T2 T3 READ NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CL = 2 T0 T1 T2 T3 T4 READ NOP NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CL = 3 DON'T CARE UNDEFINED Table 7: CAS Latency Allowable Operating Frequency (MHz) Speed CL = 1 CL = 2 CL = 3 -75M -8 -10 - 50 40 100 100 83 133 125 100 Write Burst Mode When M9 = 0, BL programmed into M0-M2 applies to both READ and WRITE burst. If M9 = 1, all WRITE bursts will only be single location access regardless of the BL setting in the mode register. READ burst lengths are unaffected by the state of M9. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Register Definition Operating Mode The normal operating mode is selected by setting M7, M8, M10, and M11 to zero; all the other combinations of values for M7, M8, M10, and M11 are reserved for future use and/ or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Extended Mode Register The extended mode register controls the functions beyond those controlled by the mode register. These additional functions are special features of the Mobile device. They include TCSR and PASR. Figure 9: Extended Mode Register BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 13 12 11 10 EMR E13 E12 Mode Register Definition 9 8 7 6 5 set to "0" 4 3 TCSR 2 1 PASR 0 Extended Mode Register (Ex) Maximum Case Temp. E4 E3 Partial-Array Self Refresh Coverage E2 E1 E0 0 0 Mode Register 85C 1 1 FullArray (All Banks) 0 0 0 0 1 Reserved 70C 0 0 Half Array (BA1 = 0) 0 0 1 1 0 Extended Mode Register 45C 0 1 Quarter Array (BA1 = BA0 = 0) 0 1 0 1 1 Resereved 15C 1 0 RFU 0 1 1 RFU 1 0 0 RFU 1 0 1 RFU 1 1 0 RFU 1 1 1 E11 E10 E9 0 0 0 - - - E8 0 - E7 0 - Notes: E6 0 - E5 0 - E4 E3 E2 E1 E0 Valid - Operating Mode Normal Operation All other states reserved 1. E13 and E12 (BA1 and BA0) must be "1, 0" to select the extended mode register (vs. the base mode register). 2. RFU: reserved for future use. The extended mode register is programmed via the MODE REGISTER SET command (BA1 = 1, BA0 = 0) and retains the stored information until it is programmed again or the device loses power. The extended mode register must be programmed with E5 through E11 set to "0." The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements results in unspecified operation. The extended mode register must be programmed to ensure proper operation. Temperature-Compensated Self Refresh (TCSR) TCSR allows the controller to program the refresh interval during self refresh mode, according to the case temperature of the Mobile device. This allows great power savings during self refresh during most operating temperature ranges. Only during extreme temperatures would the controller have to select a higher TCSR level that will guarantee data during self refresh. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Register Definition Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. Historically, during self refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range, expected. Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high because the refresh rate was set to accommodate the higher temperatures. Setting E4 and E3 allows the DRAM to accommodate more specific temperature regions during self refresh. There are four temperature settings, which will vary the self refresh current according to the selected temperature. This selectable refresh rate will save power when the DRAM is operating at normal temperatures. Partial-Array Self Refresh (PASR) For further power savings during self refresh, the PASR feature allows the controller to select the amount of memory that will be refreshed during self refresh. The refresh options are all banks (banks 0, 1, 2, and 3); two banks (banks 0 and 1); and one bank (bank 0). WRITE and READ commands occur to any bank selected during standard operation, but only the selected banks in PASR will be refreshed during self refresh. It's important to note that data in banks 2 and 3 will be lost when the two-bank option is used. Data will be lost in banks 1, 2, and 3 when the one-bank option is used. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Register Definition Commands Table 8 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following the Operation section; these tables provide current state/next state information. Table 8: Truth Table - Commands and DQM Operation Note 1 applies to entire table Name (Function) CS# COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write enable/output enable Write inhibit/output High-Z Notes: RAS# CAS# WE# DQM Addr DQ Notes H L L L L L L L X H L H H H L L X H H L L H H L X H H H L L L H X X X L/H8 L/H8 X X X X X Bank/row Bank/col Bank/col X Code X X X X X Valid Active X X 4 5, 6 L - - L - - L - - L - - X L H Op-code - - X Active High-Z 7 8 8 2 3 3 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A0-A11 provide row address, and BA0, BA1 determine which bank is made active. 3. A0-A8 (x16) or A0-A7 (x32) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. 4. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are "Don't Care." 5. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 6. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. 7. A0-A10 define the op-code written to the mode register. BA0-BA1 either select mode register or the extended mode register (BA0 = BA1 = 0 select the mode register, BA1 = 1, BA0 = 0 selects the extended mode register, all other combinations of BA0-BA1 are reserved). 8. Activates or deactivates the DQ during WRITEs (0-clock delay) and READs (2-clock delay). For x16, LDQM controls DQ0-DQ7, and UDQM controls DQ8-DQ15. For x32, DQM0 controls DQ0-DQ7, DQM1 controls DQ8-DQ15, DQM2 controls DQ16-23, and DQM3 controls DQ24- DQ31. COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct the selected SDRAM to perform a NOP (RAS#, CAS#, and WE# are HIGH, and CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Register Definition LOAD MODE REGISTER The mode register is loaded via inputs A0-A11. Refer to "Mode Register Definition" on page 18. The LOAD MODE REGISTER and LOAD EXTENDED MODE REGISTER commands can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A8 (x16) or A0-A7 (x32) selects the starting column location. The value on input A10 determines whether auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the DQ subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQ will be High-Z two clocks later; if the DQM signal was registered LOW, the DQ will provide valid data. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A8 (x16) or A0-A7 (x32) selects the starting column location. The value on input A10 determines whether auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." After a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. Auto Precharge Auto precharge is a feature that performs the same individual-bank precharge function described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Register Definition automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode where auto precharge does not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in "Operation" on page 26. BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet. The BURST TERMINATE command does not precharge the row; the row will remain open until a PRECHARGE command is issued. AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE command as shown in the operation section. The addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. Regardless of device width, the 128Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (commercial and industrial) or 16ms (automotive). Providing a distributed AUTO REFRESH command every 15.625s (commercial and industrial) or 3.906s (automotive) will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms (commercial and industrial) or 16ms (automotive). SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). After the SELF REFRESH command is registered, all the inputs to the SDRAM become "Don't Care" with the exception of CKE, which must remain LOW. After self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of 2 clocks, regardless of clock frequency) for tXSR because time is required for the completion of any internal refresh in progress. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Register Definition Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every 15.625s or less because both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. Self refresh is not supported on automotive temperature (AT) devices. Operation BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 10). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 11 on page 27, which covers any case where 2 < tRCD (MIN)/tCK 3. (The same procedure is used to convert other specification limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. Figure 10: Activating a Specific Row in a Specific Bank CLK CKE HIGH CS# RAS# CAS# WE# A0-A10, A11 BA0, BA1 ROW ADDRESS BANK ADDRESS DON'T CARE PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs Figure 11: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< 3 T0 T1 T2 T3 NOP NOP T4 CLK COMMAND ACTIVE READ or WRITE tRCD DON'T CARE READs READ bursts are initiated with a READ command, as shown in Figure 12. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following CL after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 13 on page 28 shows general timing for each possible CL setting. Figure 12: READ Command CLK CKE HIGH CS# RAS# CAS# WE# x16: A0-A8 x32: A0-A7 COLUMN ADDRESS A9, A11 ENABLE AUTO PRECHARGE A10 DISABLE AUTO PRECHARGE BA0,BA1 BANK ADDRESS DON'T CARE PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs Upon completion of a burst, assuming no other commands have been initiated, the DQ will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst either follows the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. Figure 13: CAS Latency T0 T1 T2 READ NOP CLK COMMAND tLZ tOH DOUT DQ tAC CL = 1 T0 T1 T2 T3 READ NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CL = 2 T0 T1 T2 T3 T4 READ NOP NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CL = 3 DON'T CARE UNDEFINED This is shown in Figure 14 on page 29 for CL = 2 and CL = 3; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 128Mb SDRAM uses a pipelined architecture and, therefore, does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Figure 15 on page 30, or each subsequent READ may be performed to a different bank. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs Figure 14: Consecutive READ Bursts T0 T1 T2 T3 T4 T5 CLK COMMAND READ NOP NOP READ NOP NOP X = 0 cycles ADDRESS BANK, COL n BANK, COL b DOUT n DQ DOUT n+2 DOUT n+1 DOUT n+3 DOUT b CL = 1 T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP READ NOP NOP NOP X = 1 cycle BANK, COL b DOUT n DQ DOUT n+2 DOUT n+1 DOUT n+3 DOUT b CL = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP READ NOP NOP NOP NOP X = 2 cycles BANK, COL b DOUT n DQ DOUT n+1 DOUT n+2 DOUT n+3 DOUT b CL = 3 TRANSITIONING DATA Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN DON'T CARE 1. Each READ command may be to either bank. DQM is LOW. Shown with BL = 4. 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs Figure 15: Random READ Accesses T0 T1 T2 T3 T4 CLK COMMAND READ READ READ READ ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m DOUT n DQ NOP DOUT x DOUT a DOUT m CL = 1 T0 T1 T2 T3 T4 T5 CLK COMMAND READ READ READ READ ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m DOUT n DQ NOP NOP DOUT x DOUT a DOUT m CL = 2 T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ READ READ READ ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m NOP DOUT n DQ NOP DOUT a DOUT x NOP DOUT m CL = 3 TRANSITIONING DATA Notes: DON'T CARE 1. Each READ command may be to either bank. DQM is LOW. 2. BL = 1, 2, 4, 8, or full page (if BL > 1, the following READ interrupts the previous). Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQ go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs Figure 16: READ-to-WRITE T0 T1 T2 T3 T4 CLK DQM COMMAND READ ADDRESS BANK, COL n NOP NOP NOP WRITE BANK, COL b tCK tHZ DOUT n DQ DIN b tDS TRANSITIONING DATA Notes: DON'T CARE 1. CL = 3 is used for illustration. 2. The READ command may be to any bank, and the WRITE command may be to any bank. 3. If a burst of 1 is used, then DQM is not required. The DQM input is used to avoid I/O contention, as shown in Figure 16 and Figure 17. The DQM signal must be asserted (HIGH) at least 2 clocks prior to the WRITE command (DQM latency is 2 clocks for output buffers) to suppress data-out from the READ. After the WRITE command is registered, the DQ will go High-Z (or remain High-Z), regardless of the state of the DQM signal, provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 17, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is 0 clocks for input buffers) to ensure that the written data is not masked. Figure 16 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 17 shows the case where the additional NOP is needed. Figure 17: READ-to-WRITE with Extra Clock Cycle T0 T1 T2 T3 T4 T5 CLK DQM COMMAND READ ADDRESS BANK, COL n NOP NOP NOP NOP WRITE BANK, COL b tHZ DOUT n DQ DIN b tDS TRANSITIONING DATA Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN DON'T CARE 1. CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a fullpage burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 18 on page 33 for each possible CL; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs Figure 18: READ-to-PRECHARGE T0 T1 T2 T3 T4 T5 T6 T7 CLK t RP COMMAND READ NOP NOP PRECHARGE NOP NOP NOP ACTIVE X = 0 cycles ADDRESS BANK (a or all) BANK a, COL n DOUT n DQ DOUT n+2 DOUT n+1 BANK a, ROW DOUT n+3 CL = 1 T0 T1 T2 T3 T4 T5 T6 T7 CLK t RP COMMAND READ NOP NOP PRECHARGE NOP NOP NOP ACTIVE X = 1 cycle ADDRESS BANK (a or all) BANK a, COL n DOUT n DQ BANK a, ROW DOUT n+2 DOUT n+1 DOUT n+3 CL = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t RP COMMAND READ NOP NOP PRECHARGE NOP NOP NOP ACTIVE X = 2 cycles ADDRESS BANK (a or all) BANK a, COL n DOUT n DQ DOUT n+1 BANK a, ROW DOUT n+2 DOUT n+3 CL = 3 TRANSITIONING DATA Notes: DON'T CARE 1. Assumes tRAS(MIN) has been satisfied prior to the PRECHARGE command. 2. N + 3 is either the last data element of a BL = 4 or the last desired data element of a longer burst. 3. DQM is LOW. Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 19 on page 34 for each possible CL; data element n + 3 is the last desired data element of a longer burst. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs Figure 19: Terminating a READ Burst T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP BURST TERMINATE NOP NOP NOP X = 0 cycles DOUT n DQ DOUT n+2 DOUT n+1 DOUT n+3 CL = 1 T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP BURST TERMINATE NOP NOP NOP X = 1 cycle DOUT n+2 DOUT n+1 DOUT n DQ DOUT n+3 CL = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP BURST TERMINATE NOP NOP NOP NOP X = 2 cycles DOUT n DQ DOUT n+1 DOUT n+2 DOUT n+3 CL = 3 TRANSITIONING DATA Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN DON'T CARE 1. Page remains open after a BURST TERMINATE command. 2. N + 3 is either the last data element of BL = 4 or the last desired data element of a longer burst. 3. DQM is LOW. 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 20. The starting column and bank addresses are provided with the WRITE command, and auto precharge either is enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQ will remain High-Z, and any additional input data will be ignored (see Figure 21 on page 36). A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Figure 20: WRITE Command CLK CKE HIGH CS# RAS# CAS# WE# x16: A0-A8 x32: A0-A7 COLUMN ADDRESS A9, A11 ENABLE AUTO PRECHARGE A10 DISABLE AUTO PRECHARGE BA0,1 BANK ADDRESS VALID ADDRESS DON'T CARE Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 21 on page 36. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. The 128Mb SDRAM uses a pipelined architecture and, therefore, does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 22 on page 36, or each subsequent WRITE may be performed to a different bank. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs Figure 21: WRITE Burst T0 T1 T2 T3 COMMAND WRITE NOP NOP NOP ADDRESS BANK, COL n CLK DQ DIN n DIN n+1 DON'T CARE TRANSITIONING DATA Notes: Figure 22: 1. BL = 2. DQM is LOW. WRITE-to-WRITE T0 T1 T2 COMMAND WRITE NOP WRITE ADDRESS BANK, COL n CLK DQ DIN n BANK, COL b DIN n+1 TRANSITIONING DATA Notes: DIN b DON'T CARE 1. DQM is LOW. Each WRITE command may be to any bank. Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by a READ command. After the READ command is registered, the data inputs will be ignored, and writes will not be executed. An example is shown in Figure 24 on page 37. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is registered. The auto precharge mode requires a tWR of at least one clock plus time, regardless of frequency. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 25 on page 38. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. The PRECHARGE can be issued coincident with the second clock (see Figure 25 on page 38). PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Figure 23: Random WRITE Cycles T0 T1 T2 T3 COMMAND WRITE WRITE WRITE WRITE ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m DIN n DIN a DIN x DIN m CLK DQ TRANSITIONING DATA Notes: Figure 24: DON'T CARE 1. Each WRITE command may be to any bank. 2. DQM is LOW. 3. Example shows BL = 1 or an interrupting BL > 1. WRITE-to-READ T0 T1 T2 T3 T4 T5 COMMAND WRITE NOP READ NOP NOP NOP ADDRESS BANK, COL n DOUT b DOUT b+1 CLK DQ DIN n BANK, COL b DIN n+1 TRANSITIONING DATA Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 1. 2. 3. 4. DON'T CARE The WRITE command may be to any bank, and the READ command may be to any bank. DQM is LOW. CL = 2 for illustration. Data n + 1 is either the last data of BL = 1 or the last desired of a longer burst. 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs Figure 25: WRITE-to-PRECHARGE T0 T1 T2 T3 T4 T5 T6 NOP ACTIVE NOP CLK tWR@ tCK 15ns DQM t RP COMMAND ADDRESS WRITE NOP NOP PRECHARGE BANK (a or all) BANK a, COL n BANK a, ROW t WR DQ DIN n DIN n+1 tWR@ tCK < 15ns DQM t RP COMMAND ADDRESS WRITE NOP NOP PRECHARGE NOP BANK (a or all) BANK a, COL n NOP ACTIVE BANK a, ROW t WR DQ DIN n+1 DIN n TRANSITIONING DATA Notes: DON'T CARE 1. DQM could remain LOW in this example if the WRITE burst is a fixed length of two. Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 26, where data n is the last desired data element of a longer burst. Figure 26: Terminating a WRITE Burst T0 T1 T2 COMMAND WRITE BURST TERMINATE ADDRESS BANK, COL n (ADDRESS) DIN n (DATA) CLK DQ TRANSITIONING DATA Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN NEXT COMMAND DON'T CARE 1. DQMs are LOW. 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs Figure 27: PRECHARGE Command CLK CKE HIGH CS# RAS# CAS# WE# A0-A9 All Banks A10 Bank Selected BA0, BA1 BANK ADDRESS VALID ADDRESS DON'T CARE PRECHARGE The PRECHARGE command (see Figure 27) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care." After a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. POWER-DOWN Power-down occurs if CKE is registered low coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (tREF or tREFAT ) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS). See Figure 28 on page 40. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs Figure 28: Power-Down (( )) (( )) CLK tCKS CKE > tCKS (( )) COMMAND (( )) (( )) NOP NOP tRCD tRAS All banks idle Input buffers gated off Enter power-down mode. ACTIVE Exit power-down mode. tRC DON'T CARE CLOCK SUSPEND The clock suspend mode occurs when a column access/burst is in progress and CKE is registered low. In the clock suspend mode, the internal clock is deactivated, "freezing" the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented as long as the clock is suspended. (See examples in Figure 29 and in Figure 30 on page 41.) Figure 29: Clock Suspend During WRITE Burst T0 T1 NOP WRITE T2 T3 T4 T5 NOP NOP DIN n+1 DIN n+2 CLK CKE INTERNAL CLOCK COMMAND ADDRESS DIN BANK, COL n DIN n TRANSITIONING DATA Notes: DON'T CARE 1. For this example, burst length = 4 or greater, and DM is LOW. Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs Burst Read/Single Write The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of 1), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0). Figure 30: Clock Suspend During READ Burst T0 T1 T2 T3 T4 T5 T6 CLK CKE INTERNAL CLOCK COMMAND READ ADDRESS BANK, COL n DQ NOP NOP DOUT n NOP DOUT n+1 TRANSITIONING DATA Notes: NOP NOP DOUT n+2 DOUT n+3 DON'T CARE 1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW. CONCURRENT Auto Precharge An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports concurrent auto precharge. Micron SDRAMs support concurrent auto precharge. Four cases where concurrent auto precharge occurs are defined below. READ with Auto Precharge * Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, CL later. The precharge to bank n will begin when the READ to bank m is registered (Figure 31 on page 42). * Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used 2 clocks prior to the WRITE command to prevent bus contention. The precharge to bank n will begin when the WRITE to bank m is registered (Figure 32 on page 42). PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs Figure 31: READ With Auto Precharge Interrupted by a READ T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n Internal States NOP Page Active READ - AP BANK n READ - AP BANK m NOP READ with Burst of 4 NOP NOP NOP Idle Interrupt Burst, Precharge t RP - BANK n Page Active BANK m tRP - BANK m Precharge READ with Burst of 4 BANK n, COL a ADDRESS NOP BANK m, COL d DOUT a+1 DOUT a DQ DOUT d DOUT d+1 CL = 3 (BANK n) CL = 3 (BANK m) TRANSITIONING DATA Notes: Figure 32: DON'T CARE 1. DQM is LOW, BL = 4 or greater, and CL = 3. READ With Auto Precharge Interrupted by a WRITE T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n Internal States READ - AP BANK n Page Active NOP NOP NOP READ with Burst of 4 WRITE - AP BANK m NOP NOP Interrupt Burst, Precharge Idle tRP - BANK n Page Active BANK m ADDRESS NOP Write-Back WRITE with Burst of 4 BANK n, COL a t WR - BANK m BANK m, COL d 1 DQM DOUT a DQ DIN d DIN d+1 DIN d+2 DIN d+3 CAS Latency = 3 (BANK n) TRANSITIONING DATA Notes: DON'T CARE 1. DQM is HIGH at T2 to prevent DOUT a + 1 from contending with DIN d at T4. WRITE with Auto Precharge * Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CL later. The precharge to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered 1 clock prior to the READ to bank m (Figure 33 on page 43). PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs * Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered 1 clock prior to a WRITE to bank m (Figure 34). Figure 33: WRITE With Auto Precharge Interrupted by a READ T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n Internal States NOP WRITE - AP BANK n Page Active READ - AP BANK m NOP WRITE with Burst of 4 DIN a DQ NOP Precharge tWR - BANK n tRP - BANK n NOP tRP - BANK m READ with Burst of 4 BANK n, COL a ADDRESS NOP Interrupt Burst, Write-Back Page Active BANK m NOP BANK m, COL d DOUT d+1 DOUT d DIN a+1 CL = 3 (BANK m) TRANSITIONING DATA Notes: Figure 34: DON'T CARE 1. DQM is LOW. WRITE With Auto Precharge Interrupted by a WRITE T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n Internal States NOP WRITE - AP BANK n Page Active NOP NOP WRITE with Burst of 4 WRITE - AP BANK m NOP Interrupt Burst, Write-Back tWR - BANK n BANK m ADDRESS DQ Page Active PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN Precharge t WR - BANK m Write-Back BANK m, COL d DIN a+1 DIN a+2 DIN d DIN d+1 TRANSITIONING DATA Notes: NOP tRP - BANK n WRITE with Burst of 4 BANK n, COL a DIN a NOP DIN d+2 DIN d+3 DON'T CARE 1. DQM is LOW. 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs Table 9: Truth Table - CKE Notes 1-4 apply to entire table CKEn - 1 CKEn Current State Comandn Action Notes L L L H L Maintain power-down Maintain self refresh Maintain clock suspend Exit power-down Exit self refresh Exit clock suspend Power-down entry self refresh entry Clock suspend entry H H X X X COMMAND INHIBIT or NOP COMMAND INHIBIT or NOP X COMMAND INHIBIT or NOP AUTO REFRESH WRITE or NOP See Table 10 on page 45 5 6 7 H Power-down Self refresh Clock suspend Power-down Self refresh Clock suspend All banks idle All banks idle Reading or writing Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 1. CKEn is the logic state of CKE at clock edge n; CKEn - 1 was the state of CKE at the previous clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that tCKS is met). 6. Exiting self refresh at clock edge n will put the device in the all banks idle state after tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period. 7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1. 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs Table 10: Truth Table - Current State Bank n, Command to Bank n Notes 1-6 apply to entire table; notes appear below table Current State Any Idle Row active Read (auto precharge disabled) Write (auto precharge disabled) CS# H L L L L L L L L L L L L L L L L RAS# CAS# WE# Command (Action) X H L L L L H H L H H L H H H L H Notes: X H H L L H L L H L L H H L L H H X H H H L L H L L H L L L H L L L Notes COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) ACTIVE (Select and activate row) AUTO REFRESH LOAD MODE REGISTER PRECHARGE READ (Select column and start READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Deactivate row in bank or banks) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Truncate READ burst, start PRECHARGE) BURST TERMINATE READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE (Truncate WRITE burst, start PRECHARGE) BURST TERMINATE 7 7 11 10 10 8 10 10 8 9 10 10 8 9 1. This table applies when CKEn - 1 was HIGH and CKEnis HIGH (see Table 9 on page 44) and after tXSR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted; that is, the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Table 10 and according to Table 11 on page 47. Precharging: Starts with registration of a PRECHARGE command and ends when t RP is met. After tRP is met, the bank will be in the idle state. Row activating: Starts with registration of an ACTIVE command and ends when tRCD is met. After tRCD is met, the bank will be in the row active state. Read w/auto Starts with registration of a READ command with auto precharge precharge enabled: enabled and ends when tRP has been met. AFter tRP is met, the bank will be in the idle state. Write w/auto Starts with registration of a WRITE command with auto precharge precharge enabled: enabled and ends when tRP has been met. After tRP is met, the bank will be in the idle state. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 45 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing starts with registration of an AUTO REFRESH command and ends when tRFC is met. After tRFC is met, the SDRAM will be in the all banks idle state. Accessing mode Starts with registration of a LOAD MODE REGISTER command and register: ends when tMRD has been met. After tMRD is met, the SDRAM will be in the all banks idle state. Precharging all: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. After tRP is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank. 10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 11. Does not affect the state of the bank and acts as a NOP to that bank. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs Table 11: Truth Table - CURRENT STATE BANK n, COMMAND tO BANK m Notes 1-6 apply to entire table; notes appear below and on next page Current State CS# RAS# CAS# WE# Any H L X L L L L L L L L L L L L L L L L L L L L X H X L H H L L H H L L H H L L H H L L H H L X H X H L L H H L L H H L L H H L L H H L L H X H X H H L L H H L L H H L L H H L L H H L L Idle Row Activating, active, or precharging Read (auto precharge disabled) Write (auto precharge disabled) Read (with auto precharge) Write (with auto precharge) Notes: Command (Action) COMMAND INHIBIT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) Any command otherwise allowed to bank m ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE Notes 7 7 7, 10 7, 11 9 7, 12 7, 13 9 7, 8, 14 7, 8, 15 9 7, 8, 16 7, 8, 17 9 1. This table applies when CKEn - 1 was HIGH and CKEnis HIGH (see Table 9 on page 44) and after tXSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted; that is, the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Read w/auto Starts with registration of a READ command with auto precharge precharge enabled: enabled and ends when tRP has been met. After tRP is met, the bank will be in the idle state. Write w/auto Starts with registration of a WRITE command with auto precharge precharge enabled: enabled and ends when tRP has been met. After tRP is met, the bank will be in the idle state. 4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 47 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM READs 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m's burst. 9. Burst in bank n continues as initiated. 10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CL later (see Figure 14 on page 29). 11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (see Figure 16 and Figure 17 on page 31). DQM should be used one clock prior to the WRITE command to prevent bus contention. 12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (see Figure 24 on page 37) with the data-out appearing CL later. The last valid WRITE to bank n will be data-in registered 1 clock prior to the READ to bank m. 13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank will interrupt the WRITE on bank n when registered (see Figure 22 on page 36). The last valid WRITE to bank n will be data-in registered 1 clock prior to the READ to bank m. 14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n will begin when the READ to bank m is registered (see Figure 31 on page 42). 15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used 2 clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (see Figure 32 on page 42). 16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CL later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in registered 1 clock prior to the READ to bank m (see Figure 33 on page 43). 17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered 1 clock to the WRITE to bank m (see Figure 34 on page 43). PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 12 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 12: Absolute Maximum Ratings Parameter Min Max Rating Voltage on VDD/VDDQ supply relative to VSS (LC devices) Relative to VSS (V devices) Voltage on inputs, NC or I/O pins relative to VSS (LC devices) Relative to VSS (V devices) Operating temperature TA (commercial) TA (industrial) TA (automotive) Storage temperature (plastic) -1 0.5 -1 -0.5 +4.6 +3.6 +4.6 +3.6 V V V V C 0 -40 -40 -55 +70 +85 +105 +150 C Temperature and Thermal Impedance It is imperative that the Mobile SDRAM device's temperature specifications, shown in Table 13 on page 50, be maintained to ensure the junction temperature is in the proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device's thermal impedances correctly. The thermal impedances are listed in Table 14 on page 50 for the applicable die revision and packages being made available. These thermal impedance values vary according to the density, package, and particular design used for each device. Incorrectly using thermal impedances can produce significant errors. Read Micron technical note TN-00-08, "Thermal Applications" prior to using the thermal impedances listed in Table 14 on page 50. To ensure the compatibility of current and future designs, contact Micron Applications Engineering to confirm thermal impedance values. The SDRAM device's safe junction temperature range can be maintained when the TC specification is not exceeded. In applications where the device's ambient temperature is too high, use of forced air and/or heat sinks may be required to satisfy the case temperature specifications. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 49 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Electrical Specifications Table 13: Temperature Limits Parameter Symbol Table 14: 0 -40 -40 80 90 105 0 -40 -40 85 95 110 0 -40 -40 - 70 85 105 260 TJ TA TPEAK Units Notes C 1, 2, 3, 4 C 3 C 3, 5 C 1. MAX operating case temperature, TC, is measured in the center of the package on the top side of the device, as shown in Figures 35, 36, and 37 on page 51. 2. Device functionality is not guaranteed if the device exceeds maximum TC during operation. 3. All temperature specifications must be satisfied. 4. The case temperature should be measured by gluing a thermocouple to the top center of the component. This should be done with a 1mm bead of conductive epoxy, as defined by the JEDEC EIA/JESD51 standards. Care should be taken to ensure the thermocouple bead is touching the case. 5. Operating ambient temperature surrounding the package. Thermal Impedance Simulated Values Die Revision G Max TC Operating case temperature: Commercial Industrial Automotive Junction temperature: Commercial Industrial Automotive Ambient temperature: Commercial Industrial Automotive Peak reflow temperature Notes: Min Package Substrate JA (C/W) Airflow = 0m/s 54-pin TSOP4 2-layer 4-layer 2-layer 4-layer 2-layer 4-layer 86.2 58.9 72.1 54.5 64.6 48.2 54-ball VFBGA 90-ball VFBGA Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN JA (C/W) Airflow = 1m/s JA (C/W) Airflow = 2m/s JB (C/W) JC (C/W) 67.8 50.7 57.3 46.6 50.8 41.1 62 47.6 50.6 42.8 45.3 38.1 46.9 41.5 36.0 35.5 37.5 32.1 11.3 4.1 1.8 1. For designs expected to last beyond the die revision listed, contact Micron Applications Engineering to confirm thermal impedance values. 2. Thermal resistance data is sampled from multiple lots, and the values should be viewed as typical. 3. These are estimates; actual results may vary. 4. Thermal impedance values were obtained using the 128Mb SDRAM 54-pin TSOP. 50 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Electrical Specifications Figure 35: Example Temperature Test Point Location, 54-Pin TSOP: Top View 22.22mm 11.11mm Test point 10.16mm 5.08mm Figure 36: Example Temperature Test Point Location, 54-Ball VFBGA: Top View 8.00mm 4.00mm Test point 8.00mm 4.00mm Figure 37: Example Temperature Test Point Location, 90-Ball VFBGA: Top View 8.00mm 4.00mm Test point 13.00mm 6.50mm PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 51 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Electrical Specifications Table 15: DC Electrical Characteristics and Operating Conditions (LC Version) Notes 1, 6 apply to entire table; notes appear on page 57; VDD = +3.3V 0.3V, VDDQ = +3.3V 0.3V Parameter/Condition Supply voltage I/O supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Data output high voltage: Logic 1; All inputs Data output low voltage: Logic 0; All inputs Input leakage current: Any input 0V VIN VDD (All other pins not under test = 0V) Output leakage current: DQ are disabled; 0V VOUT VDDQ Table 16: Symbol Min Max Units VDD VDDQ VIH VIL VOH VOL II 3 3 2 -0.3 2.4 - -5 3.6 3.6 VDD + 0.3 0.8 - 0.4 5 V V V V V V A IOZ -5 5 A Notes 22 22 DC Electrical Characteristics and Operating Conditions (V Version) Notes 1, 6 apply to entire table; notes appear on page 57; VDD = 2.5 0.2V, VDDQ = +2.5V 0.2V or +1.8V 0.15V Parameter/Condition Symbol Supply voltage I/O supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Data output high voltage: Logic 1; All inputs Data output low voltage: Logic 0; All inputs Input leakage current: Any input 0V VIN VDD (All other pins not under test = 0V) Output leakage current: DQ are disabled; 0V VOUT VDDQ PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 52 Min 2.3 VDD 1.65 VDDQ 1.25 VIH (DQ) 1.25 VIH (non-DQ) VIL -0.3 VOH VDDQ - 0.2 VOL - II -5 IOZ -5 Max Units Notes 2.7 2.7 VDDQ + 0.3 VDD + 0.3 +0.55 - 0.2 5 V V V 22 V V V A 5 A 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Electrical Specifications Table 17: Electrical Characteristics and Recommended AC Operating Conditions Notes 5, 6, 7, 8, 9, 11 apply to entire table; notes appear on page 57 Ac Characteristics -75M Parameter Symbol CL = 3 CL = 2 CL = 1 t AC (3) AC (2) t AC (1) t AH Address hold time tAS Address setup time t CH CLK high-level width t CL CLK low-level width CL = 3 tCK (3) Clock cycle time CL = 2 tCK (2) CL = 1 tCK (1) tCKH CKE hold time tCKS CKE setup time tCMH CS#, RAS#, CAS#, WE#, DQM hold time tCMS CS#, RAS#, CAS#, WE#, DQM setup time tDH Data-in hold time tDS Data-in setup time CL = 3 tHZ (3) Data-out High-Z time CL = 2 tHZ (2) CL = 1 tHZ (1) tLZ Data-out Low-Z time tOH Data-out hold time (load) t OHN Data-out hold time (no load) tRAS ACTIVE-to-PRECHARGE command tRC ACTIVE-to-ACTIVE command period tRCD ACTIVE-to-READ or WRITE delay tREF Refresh period (4,096 rows) t REFAT Refresh period - (AT) (4,096 rows) tRFC AUTO REFRESH command period tRP PRECHARGE command period tRRD ACTIVE bank a to ACTIVE bank b command t T Transition time t WR (a) WRITE recovery time Auto precharge mode (a) t Manual precharge mode (m) WR (m) tXSR Exit SELF REFRESH to ACTIVE command Access time from CLK (positive edge) PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN t Min Max -8 Min -10 Max Min Max - 5.4 - 7 - 7 - 6 - 8 - 8 - na - 19 - 22 0.8 - 1 - 1 - 1.5 - 2.5 - 2.5 - 3 - 3 - 3 - 2.5 - 3 - 3 - 7.5 - 8 - 10 - 9.6 - 9.6 - 12 - n/a - 20 - 25 - 1 - 1 - 1 - 2.5 - 2.5 - 2.5 - 0.8 - 1 - 1 - 1.5 - 2.5 - 2.5 - 0.8 - 1 - 1 - 1.5 - 2.5 - 2.5 - - 5.4 - 7 - 7 - 6 - 8 - 8 - na - 19 - 22 1 - 1 - 1 - 2.5 - 2.5 - 2.5 - 1.8 - 1.8 - 1.8 - 44 120,000 48 120,000 50 120,000 66 - 80 - 100 - 19 - 20 - 20 - - 64 - 64 - 64 - 16 - 16 - 16 66 - 80 - 100 - 19 - 20 - 20 - 2 - 2 - 2 - 0.3 1.2 0.5 1.2 0.5 1.2 1 CLK - 1 CLK - 1 CLK - +7.5ns +7ns +5ns 15 - 15 - 15 - 67 - 80 - 100 - 53 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns tCK ns - ns ns Notes 23 23 23 10 10 10 27 7 24 25 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Electrical Specifications Table 18: AC Functional Characteristics Notes 5, 6, 7, 8, 9, 11 apply to entire table; notes appear on page 57 Parameter Symbol READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data High-Z during READs WRITE command to input data delay Data-in to ACTIVE command Data-in to PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command CL = 3 Data-out to High-Z from PRECHARGE command CL = 2 CL = 1 PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 54 t -75M -8 -10 Units Notes CCD CKED t PED t DQD tDQM t DQZ t DWD t DAL t DPL t BDL t CDL tRDL tMRD 1 1 1 0 0 2 0 5 2 1 1 2 2 1 1 1 0 0 2 0 5 2 1 1 2 2 1 1 1 0 0 2 0 5 2 1 1 2 2 t CK CK t CK t CK tCK t CK t CK t CK t CK t CK t CK tCK tCK 17 14 14 17 17 17 17 15, 21 16, 21 17 17 16, 21 26 tROH(3) 3 2 3 2 1 3 2 1 tCK 17 17 17 t tROH(2) tROH(1) t tCK tCK Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Electrical Specifications Table 19: IDD Specifications and Conditions (x16) Notes 1, 3, 6, 11, 13, 31 apply to entire table; notes appear on page 57; VDD = VDDQ = +3.3V 0.3V or VDD = VDDQ = 2.5V 0.2V or VDD = +2.5V 0.2V, VDDQ = +1.8V 0.15V Max Parameter/Condition Operating current: Active mode; Burst = 2; READ or WRITE; tRC = tRC (MIN) Standby current: Power-down mode; All banks idle; CKE = LOW Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No accesses in progress Operating current: Burst mode; Page burst; READ or WRITE; All banks active tRFC = tRFC (MIN) Auto refresh current: CKE = HIGH; tRFC = 15.625s CS# = HIGH tRFC = 3.906s(AT) Table 20: Symbol -75M -8 -10 Units Notes IDD1 130 130 100 mA 18, 19 IDD2 450 450 450 A 12, 33 IDD3 40 40 35 mA 19 IDD4 115 100 95 mA 18, 19 IDD5 IDD6 IDD6 225 3 6 210 3 6 170 3 6 mA mA mA 12, 18, 19, 32, 33 IDD7 Self Refresh Current Options (x16) Note 4 applies to entire table; note appears on page 57; VDD = VDDQ = +3.3V 0.3V or VDD = VDDQ = 2.5V 0.2V or VDD = +2.5V 0.2V, VDDQ = +1.8V 0.15V Temperature-Compensated Self Refresh (TCSR) Parameter/Condition Self refresh current: CKE < 0.2V (E4 = 1, E3 = 1) Self refresh current: CKE < 0.2V (E4 = 0, E3 = 0) Self refresh current: CKE < 0.2V (E4 = 0, E3 = 1) Self refresh current: CKE < 0.2V (E4 = 1, E3 = 0) PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 55 Max Temperature -75M/-8/-10 Units 85C 70C 45C 15C 800 500 350 300 A A A A Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Electrical Specifications Table 21: IDD Specifications And Conditions (x32) Notes 1, 3, 6, 11, 13, 31 apply to entire table; notes appear on page 57; VDD = VDDQ = +3.3V 0.3V or VDD = VDDQ = 2.5V 0.2V or VDD = +2.5V 0.2V, VDDQ = +1.8V 0.15V Max Parameter/Condition Operating current: Active mode; Burst = 2; READ or WRITE; tRC = tRC (MIN) Standby current: Power-down mode; All banks idle; CKE = LOW Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No accesses in progress Operating current: Burst mode; Page burst; READ or WRITE; All banks active t RFC = tRFC (MIN) Auto refresh current: CKE = HIGH; tRFC = 15.625s CS# = HIGH tRFC = 3.906s(AT) Table 22: Symbol -75M -8 -10 Units Notes IDD1 150 150 120 mA 18, 19 IDD2 IDD3 450 45 450 45 450 40 A mA 12, 33 19 IDD4 130 115 110 mA 18, 19 IDD5 IDD6 IDD6 235 3 6 220 3 6 180 3 6 mA mA mA 12, 18, 19, 32, 33 IDD7 Self Refresh Current Options (x32) Note 4 applies to entire table; notes appear on page 57; VDD = VDDQ = +3.3V 0.3V or VDD = VDDQ = 2.5V 0.2V or VDD = +2.5V 0.2V, VDDQ = +1.8V 0.15V Temperature-Compensated Self Refresh (TCSR) Parameter/Condition Self refresh current: CKE < 0.2V (E4 = 1, E3 = 1) Self refresh current: CKE < 0.2V (E4 = 0, E3 = 0) Self refresh current: CKE < 0.2V (E4 = 0, E3 = 1) Self refresh current: CKE < 0.2V (E4 = 1, E3 = 0) Table 23: Max Temperature -75M/-8/-10 Units 85C 70C 45C 15C 1000 550 400 350 A A A A Capacitance (FBGA Pacakge) Note 2 applies to entire table; notes appear on page 57 Parameter Symbol Min Max Units Notes CI1 CI2 CIO 1.5 1.5 3.0 3.5 3.8 6.0 pF pF pF 28 29 30 Symbol Min Max Units Notes CI1 CI2 CIO 2.5 2.5 4.0 3.5 3.8 6.0 pF pF pF 28 29 30 Input capacitance: CLK Input capacitance: All other input-only pins Input/Output capacitance: DQ Table 24: Capacitance (TSOP Pacakge) Note 2 applies to entire table; notes appear on page 57 Parameter Input capacitance: CLK Input capacitance: All other input-only pins Input/Output capacitance: DQ PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 56 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Notes Notes 1. All voltages are referenced to Vss. 2. This parameter is sampled. VDD, VDDQ = +3.3V; TA = 25C; pin under test biased at 1.4V, f = 1 MHz. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured (0C TA +70C (commercial), - 40C TA +85C (industrial), and -40C TA +105C (automotive)). 6. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured at 1.5V (for LC devices) or at 1.25V (V devices) with equivalent load: Q 30pF 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and IDD tests use established values for VIL and VIH, with timing referenced to VIH/2 crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL(MAX) and VIH(MIN) and no longer at the VIH/2 crossover point. Established tester values follow: VIL = 0V, VIH = 3.0V for LC devices and VIH = 2.3V for V devices. 12. Other input signals are allowed to transition no more than once every 2 clocks and are otherwise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. Address transitions average one transition every 2 clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 125MHz for -8 and tCK = 100MHz for -10. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 57 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Notes 22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width 3ns, and the pulse width cannot be greater than one-third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 3ns and cannot be greater than one-third of the cycle rate. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins at 5.4ns for -8 after the first clock delay after the last WRITE is executed. 25. Manual precharge mode only. 26. JEDEC and PC100 specify 3 clocks. 27. Parameter guaranteed by design. 28. PC100 specifies a maximum of 4pF. 29. PC100 specifies a maximum of 5pF. 30. PC100 specifies a maximum of 6.5pF. 31. For -75M, CL = 3 and tCK = 7.5ns; for -8, CL = 3 and tCK = 8ns; for -10, CL = 3 and t CK = 10ns. 32. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. 33. Specified with I/Os in steady state condition. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 58 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Timing Diagrams Figure 38: Initialize and Load Mode Register T1 T0 CLK (( )) (( )) tCK T3 T5 T7 T9 T19 T29 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) tCKS tCKH CKE (( )) (( )) COMMAND1,2 (( )) (( )) tCMS tCMH NOP PRE (( )) (( )) (( )) (( )) LMR3 (( )) (( )) (( )) (( )) A0-A9, A11 (( )) (( )) (( )) (( )) CODE (( )) (( )) A10 (( )) (( )) (( )) (( )) CODE (( )) (( )) DQML, DQMU5 (( )) (( )) LMR3 (( )) (( )) PRE (( )) (( )) AR (( )) (( )) AR4 (( )) (( )) ACT (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) CODE (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) RA CODE ( ( ALL BANKS )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) RA (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) BA (( )) (( )) (( )) (( )) tMRD tRP tAS tAH BA0, BA1 DQ ALL BANKS tAS tAH (( )) (( )) (( )) (( )) (( )) tAS High-Z tAH BA0 = L, BA1 = H tAS (( )) (( )) (( )) (( )) tRP tMRD BA0 = L, BA1 = L tAH T = 100s Power-up: VDD and CLK stable Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN Load Extended Mode Register Load Mode Register tRFC tRFC DON'T CARE 1. The two AUTO REFRESH commands at T9 and T19 may be applied either before LOAD MODE REGISTER (LMR) command. 2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = row address, and BA = bank address. 3. The LOAD MODE REGISTER both for mode register and for extended mode register, and two AUTO REFRESH commands can be in any order. However, all must occur prior to an ACTIVE command. 4. Optional REFRESH command. 5. Although not required, to prevent bus contention, it is suggested to keep DQM HIGH during the initialization sequence. See Table 17 on page 53. 59 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Figure 39: Power-down Mode T0 CLK T1 T2 tCK tCKS tCH CKE1 tCKS PRECHARGE Tn + 2 tCKS (( )) tCKH tCMS tCMH COMMAND Tn + 1 (( )) (( )) tCL NOP (( )) (( )) NOP NOP ACTIVE DQML, DQMU (( )) (( )) A0-A9, A11 (( )) (( )) ROW (( )) (( )) ROW (( )) (( )) BANK ALL BANKS A10 SINGLE BANK tAS BA0, BA1 tAH BANK(S) High-Z (( )) DQ Two clock cycles Input buffers gated off while in power-down mode Precharge all active banks All banks idle, enter power-down mode All banks idle Exit power-down mode DON'T CARE Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 1. Violating refresh requirements during power-down may result in a loss of data. See Table 17 on page 53. 60 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Figure 40: Clock Suspend Mode T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 NOP WRITE T9 tCL tCK tCH tCKS tCKH CKE tCKS tCKH tCMS tCMH COMMAND1 READ NOP NOP NOP NOP NOP tCMS tCMH DQMU, DQML tAS A0-A9, A112 tAH COLUMN m 2 tAS tAH tAS tAH COLUMN e 2 A10 BA0, BA1 BANK BANK tAC tOH tAC DQ tLZ DOUT m tHZ DOUT m + 1 tDS tDH DIN e DIN e + 1 UNDEFINED Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN DON'T CARE 1. For this example, BL = 2, CL = 3, and auto precharge is disabled. 2. x16: A9 and A11 = "Don't Care." x32: A8, A9 and A11 = "Don't Care." See Table 17 on page 53. 61 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Figure 41: Auto Refresh Mode T0 CLK T1 tCK T2 (( )) (( )) tCH Tn + 1 (( )) (( )) tCL (( )) CKE COMMAND tCKS tCKH tCMS tCMH PRECHARGE NOP AUTO REFRESH (( )) NOP( ( NOP )) (( )) AUTO REFRESH NOP (( )) (( )) DQMU, DQML A0-A9, A11 ALL BANKS A10 SINGLE BANK tAS BA0, BA1 (( )) (( )) (( )) (( )) ROW (( )) (( )) (( )) (( )) ROW (( )) (( )) (( )) tRP tRFC1, 2 Precharge all active banks PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN ACTIVE (( )) (( )) (( )) (( )) High-Z Notes: (( )) ( ( NOP )) tAH BANK(S) DQ To + 1 BANK (( )) tRFC1, 2 DON'T CARE 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required. See Table 17 on page 53. 2. tRFC must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during tRFC. 62 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Figure 42: Self Refresh Mode T0 CLK T1 tCK tCL tCH T2 tCKS tCKH tCMS tCMH COMMAND PRECHARGE Tn + 1 > tRAS1 CKE tCKS (( )) (( )) (( )) (( )) (( )) NOP AUTO REFRESH (( )) (( )) (( )) NOP ( ( (( )) (( )) A0-A9, A11 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) ALL BANKS A10 SINGLE BANK DQ AUTO REFRESH )) (( )) (( )) BA0, BA1 To + 2 (( )) DQMU, DQML tAS To + 1 tAH BANK(S) High-Z (( )) (( )) tRP Precharge all active banks tXSR2 Enter self refresh mode Exit self refresh mode (Restart refresh time base) DON'T CARE CLK stable prior to exiting self refresh mode Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN No maximum time limit for self refresh. tRAS (MAX) only applies to non-self refresh mode. requires a minimum of 2 clocks regardless of frequency or timing. As a general rule, any time self refresh is exited, the DRAM may not reenter the self refresh mode until all rows have been refreshed via the AUTO REFRESH command at the distributed refresh rate, (tREF/number of rows), or faster. However, the following exception is allowed. Self refresh mode may be reentered any time after exiting if the following conditions are all met: 3a. The DRAM has been in the self refresh mode for a minimum of 64ms prior to exiting. 3b. tXSR has not been violated. 3c. At least two AUTO REFRESH commands are performed during each 15.625s interval while the DRAM remains out of the self refresh mode. See Table 17 on page 53. 4. Self refresh is not supported on automotive temperature (AT) devices. 1. 2. 3. tXSR 63 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Figure 43: READ - Without Auto Precharge T0 CLK T1 tCK tCKS T2 T3 T4 T5 NOP NOP T6 T7 T8 NOP ACTIVE tCL tCH tCKH CKE tCMS tCMH COMMAND ACTIVE NOP READ NOP PRECHARGE tCMS tCMH DQMU, DQML tAS A0-A9, A11 tAS COLUMN m2 ROW tAH ALL BANKS ROW A10 tAS BA0, BA1 tAH ROW ROW tAH BANK DISABLE AUTO PRECHARGE SINGLE BANKS BANK BANK(S) tAC tOH tAC DQ tLZ tRCD DOUT m tAC tOH DOUT m+1 BANK tAC tOH DOUT m+2 tOH DOUT m+3 tHZ tRP CAS Latency tRAS tRC DON'T CARE UNDEFINED Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. x16: A9 and A11 = "Don't Care." x32: A8, A9, and A11 = "Don't Care." See Table 17 on page 53. 64 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Figure 44: Read - With Auto Precharge T0 CLK tCKS T1 T2 T3 T4 T5 NOP NOP T6 T7 T8 NOP ACTIVE tCL tCK tCKH tCH CKE tCMS tCMH COMMAND ACTIVE NOP READ tCMS NOP NOP tCMH DQMU, DQML tAS A0-A9, A11 tAH ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 COLUMN m2 ROW tAS A10 tAH ROW tAH BANK BANK BANK tAC tOH tAC DQ DOUT m tLZ tRCD tAC tOH tAC tOH DOUT m + 1 DOUT m + 2 tOH DOUT m + 3 tHZ tRP CAS Latency tRAS tRC DON'T CARE UNDEFINED Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 1. For this example, BL = 4 and CL = 2. 2. x16: A9 and A11 = "Don't Care." x32: A8, A9, and A11 = "Don't Care." See Table 17 on page 53. 65 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Figure 45: Single Read - Without Auto Precharge T0 CLK T1 tCK tCKS T2 T3 T4 T5 NOP 3 NOP 3 T6 T7 T8 tCL tCH tCKH CKE tCMS tCMH COMMAND ACTIVE NOP READ PRECHARGE NOP ACTIVE NOP tCMS tCMH DQMU, DQML tAS A0-A9, A11 tAS COLUMN m2 ROW tAH ALL BANKS ROW ROW A10 tAS BA0, BA1 tAH ROW DISABLE AUTO PRECHARGE tAH SINGLE BANKS BANK BANK BANK(S) tOH tAC DQ tLZ tRCD BANK DOUT m tHZ tRP CAS Latency tRAS tRC UNDEFINED Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN DON'T CARE 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. x16: A9 and A11 = "Don't Care." x32: A8, A9, and A11 = "Don't Care." 3. PRECHARGE command not allowed or tRAS would be violated. See Table 17 on page 53. 66 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Figure 46: Single Read - With Auto Precharge T0 CLK tCKS T1 T2 T3 T4 T5 T6 NOP3 READ NOP T7 T8 tCL tCK tCKH tCH CKE tCMS tCMH COMMAND ACTIVE NOP NOP3 tCMS NOP ACTIVE NOP tCMH DQMU, DQML tAS A0-A9, A11 tAS A10 COLUMN m2 tAH ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 tAH ROW ROW tAH BANK BANK BANK tAC t OH DOUT m DQ tRCD CAS Latency tHZ tRP tRAS tRC UNDEFINED Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN DON'T CARE 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. x16: A9 and A11 = "Don't Care." x32: A8, A9, and A11 = "Don't Care." 3. PRECHARGE command not allowed or tRAS would be violated. See Table 17 on page 53. 67 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Figure 47: Alternating Bank Read Accesses T0 T1 CLK tCK tCKS tCKH tCMS tCMH T2 T3 T4 T5 T6 T7 T8 READ NOP ACTIVE tCL tCH CKE COMMAND ACTIVE NOP READ tCMS NOP NOP ACTIVE tCMH DQMU, DQML tAS A0-A9, A11 tAS A10 COLUMN m 2 tAH COLUMN b 2 ROW ENABLE AUTO PRECHARGE ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 tAH ROW ROW ROW tAH BANK 0 BANK 0 BANK 3 BANK 3 tAC tOH tAC DOUT m DQ tAC tOH DOUT m + 1 BANK 0 tAC tOH DOUT m + 2 tAC tOH DOUT m + 3 tAC tOH DOUT b tLZ tRCD - BANK 0 tRP - BANK 0 CAS Latency - BANK 0 tRCD - BANK 0 tRAS - BANK 0 tRC - BANK 0 tRCD - BANK 3 tRRD CAS Latency - BANK 3 UNDEFINED Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN DON'T CARE 1. For this example, BL = 4 and CL = 2. 2. x16: A9 and A11 = "Don't Care." x32: A8, A9, and A11 = "Don't Care." See Table 17 on page 53. 68 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Figure 48: Read - Full-Page Burst T0 T1 CLK tCK tCKS tCL T2 T3 T4 T5 T6 (( )) (( )) tCH tCMH ACTIVE NOP READ tCMS NOP NOP NOP tAS tCMH tAS NOP BURST TERM NOP NOP (( )) (( )) COLUMN m 2 tAH (( )) (( )) ROW tAS BA0, BA1 Tn + 4 (( )) (( )) tAH ROW (( )) (( )) NOP DQMU, DQML A10 Tn + 3 (( )) (( )) tCMS A0-A9, A11 Tn + 2 tCKH CKE COMMAND Tn + 1 tAH BANK (( )) (( )) BANK tAC tAC DQ tAC tOH tOH DOUT m DOUT m+1 tLZ tRCD CAS Latency tAC ( ( tOH ) ) (( )) (( )) DOUT m+2 tAC tAC tOH tOH tOH DOUT m-1 DOUT m DOUT m+1 tHZ 512 (x16) locations within same row Full page completed Full-page burst does not self-terminate. 3 Can use BURST TERMINATE command. UNDEFINED Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN DON'T CARE 1. For this example, CL = 2. 2. x16: A9 and A11 = "Don't Care." x32: A8, A9, and A11 = "Don't Care." 3. Page left open; no tRP. See Table 17 on page 53. 69 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Figure 49: Read - DQM Operation T0 CLK T1 tCKS tCK tCKH tCMS tCMH T2 T3 T4 T5 NOP NOP T6 T7 T8 NOP NOP tCL tCH CKE COMMAND ACTIVE NOP READ tCMS NOP NOP tCMH DQMU, DQML tAS A0-A9, A11 tAS A10 COLUMN m 2 tAH ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 tAH ROW DISABLE AUTO PRECHARGE tAH BANK BANK tAC tOH DQ tAC DOUT m tLZ tRCD tHZ tAC tOH tOH DOUT m + 2 tLZ DOUT m + 3 tHZ CAS Latency UNDEFINED Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN DON'T CARE 1. For this example, CL = 2. 2. x16: A9 and A11 = "Don't Care." x32: A8, A9, and A11 = "Don't Care." See Table 17 on page 53. 70 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Figure 50: Write - Without Auto Precharge T0 CLK T1 tCKS tCK tCKH tCMS tCMH T2 tCL T3 T4 T5 T6 T7 T8 T9 NOP NOP NOP NOP PRECHARGE NOP ACTIVE tCH CKE COMMAND ACTIVE NOP WRITE tCMS tCMH DQMU, DQML tAS A0-A9, A11 ROW tAH ALL BANKS ROW tAS BA0, BA1 COLUMN m 3 ROW tAS A10 tAH ROW tAH DISABLE AUTO PRECHARGE SINGLE BANK BANK BANK BANK tDS tDH DIN m DQ tDS tDH DIN m + 1 tDS tDH DIN m + 2 tDS tDH DIN m + 3 t WR 2 tRCD tRAS BANK tRP tRC UNDEFINED Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN DON'T CARE 1. For this example, BL = 4, and the WRITE burst is followed by a "manual" PRECHARGE. 2. 15ns is required between <DIN m + 3> and the PRECHARGE command regardless of frequency. 3. x16: A9 and A11 = "Don't Care." x32: A8, A9, and A11 = "Don't Care." See Table 17 on page 53. 71 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Figure 51: Write - With Auto Precharge T0 CLK T1 tCKS tCK tCKH tCMS tCMH T2 tCL T3 T4 T5 T6 T7 T8 T9 NOP NOP NOP NOP NOP NOP ACTIVE tCH CKE COMMAND ACTIVE NOP WRITE tCMS tCMH DQMU, DQML tAS A0-A9, A11 tAH ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 COLUMN m 2 ROW tAS A10 tAH ROW tAH BANK BANK tDS tDH DIN m DQ BANK tDS tDH DIN m + 1 tDS tDH DIN m + 2 tDS tDH DIN m + 3 tRCD tRAS tWR tRP tRC DON'T CARE Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 1. For this example, BL = 4. 2. x16: A9 and A11 = "Don't Care." x32: A8, A9, and A11 = "Don't Care." See Table 17 on page 53. 72 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Figure 52: Single Write - Without Auto Precharge T0 CLK T1 tCKS tCK tCKH tCMS tCMH tCL T2 T3 T4 NOP 4 NOP 4 T5 T6 T7 T8 ACTIVE NOP tCH CKE COMMAND ACTIVE NOP WRITE tCMS PRECHARGE NOP tCMH DQMU, DQML tAS A0-A9, A11 COLUMN m 3 ROW tAS tAH ALL BANKS ROW A10 tAS BA0, BA1 tAH ROW tAH DISABLE AUTO PRECHARGE SINGLE BANK BANK BANK BANK tDS BANK tDH DIN m DQ tRCD tRAS tRP t WR 2 tRC DON'T CARE Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 1. For this example, BL = 1, and the WRITE burst is followed by a "manual" PRECHARGE. 2. 15ns is required between <DIN m> and the PRECHARGE command regardless of frequency. 3. x16: A9 and A11 = "Don't Care." x32: A8, A9, and A11 = "Don't Care." 4. PRECHARGE command not allowed or tRAS would be violated. See Table 17 on page 53. 73 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Figure 53: Single Write - With Auto Precharge T0 CLK T1 tCKS tCK tCKH tCMS tCMH tCL T2 T3 T4 T5 T6 T7 NOP3 WRITE NOP NOP NOP T8 T9 tCH CKE COMMAND NOP3 ACTIVE NOP3 tCMS ACTIVE NOP tCMH DQMU, DQML tAS A0-A9, A11 tAH ROW ENABLE AUTO PRECHARGE ROW ROW tAS BA0, BA1 COLUMN m2 ROW tAS A10 tAH tAH BANK BANK tDS BANK tDH DIN m DQ tRCD tRAS tWR tRP tRC DON'T CARE Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 1. For this example, BL = 1, and the WRITE burst is followed by a "manual" PRECHARGE. 2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency. 3. x16: A9 and A11 = "Don't Care." x32: A8, A9, and A11 = "Don't Care." 4. WRITE command not allowed or tRAS would be violated. See Table 17 on page 53. 74 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Figure 54: Alternating Bank Write Accesses T0 T1 CLK T2 tCL tCK tCKS tCKH tCMS tCMH T3 T4 T5 T6 T7 T8 T9 NOP NOP ACTIVE tCH CKE COMMAND ACTIVE NOP WRITE tCMS NOP ACTIVE NOP WRITE tCMH DQMU, DQML tAS A0-A9, A11 tAS A10 COLUMN m 2 tAH COLUMN b 2 ROW ENABLE AUTO PRECHARGE ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 tAH ROW ROW ROW tAH BANK 0 BANK 0 tDS tDH DIN m DQ BANK 1 tDS tDH DIN m + 1 tDS tDH DIN m + 2 BANK 1 tDS tDH DIN m + 3 tDS tDH DIN b tWR - BANK 0 tRCD - BANK 0 BANK 0 tDS tDH DIN b + 1 tDS tDH DIN b + 2 tRP - BANK 0 tDS tDH DIN b + 3 tRCD - BANK 0 tRAS - BANK 0 tRC - BANK 0 tRCD - BANK 1 tRRD tWR - BANK 1 DON'T CARE Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 1. For this example, BL = 4. 2. x16: A9 and A11 = "Don't Care." x32: A8, A9, and A11 = "Don't Care." See Table 17 on page 53. 75 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Figure 55: Write - Full-page Burst T0 T1 CLK T2 tCL tCK tCKS T3 T4 T5 (( )) (( )) tCH tCKH COMMAND tCMH ACTIVE NOP WRITE NOP NOP NOP tCMS tCMH tAS A10 (( )) (( )) NOP BURST TERM NOP (( )) (( )) COLUMN m 1 tAH (( )) (( )) ROW tAS BA0, BA1 tAH ROW tAS Tn + 3 (( )) (( )) DQMU, DQML A0-A9, A11 Tn + 2 (( )) (( )) CKE tCMS Tn + 1 tAH BANK (( )) (( )) BANK tDS tDH DIN m DQ tDS tDH DIN m + 1 tRCD tDS tDH DIN m + 2 tDS tDH DIN m + 3 (( )) (( )) tDS tDH DIN m - 1 512 (x16) locations within same row Full page completed Full-page burst does not self-terminate. Can use BURST TERMINATE command to stop.2, 3 DON'T CARE Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 1. x16: A9 and A11 = "Don't Care." x32: A8, A9, and A11 = "Don't Care." 2. tWR must be satisfied prior to PRECHARGE command. 3. Page left open; no tRP. See Table 17 on page 53. 76 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Timing Diagrams Figure 56: Write - DQM Operation T0 CLK T1 tCKS tCK tCKH tCMS tCMH tCL T2 T3 T4 T5 NOP NOP NOP T6 T7 NOP NOP tCH CKE COMMAND ACTIVE NOP WRITE tCMS tCMH DQMU, DQML tAS A0-A9, A11 tAS A10 COLUMN m 2 tAH ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 tAH ROW tAH DISABLE AUTO PRECHARGE BANK BANK tDS tDH tDS DIN m DQ tDH DIN m + 2 tDS tDH DIN m + 3 tRCD DON'T CARE Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 1. For this example, BL = 4. 2. x16: A9 and A11 = "Don't Care." x32: A8, A9, and A11 = "Don't Care." See Table 17 on page 53. 77 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Package Dimensions Package Dimensions Figure 57: 54-Ball FBGA, "F4/B4" Package (x16 Device), 8mm x 8mm 0.65 0.05 SEATING PLANE SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR 96.5% Sn, 3% Ag, 0.5% Cu SOLDER MASK DEFINED BALL PADS: O0.40 SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC C 0.10 C 54X O0.45 0.05 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PREREFLOW DIAMETER IS 0.42. 6.40 0.80 TYP BALL A1 ID BALL A1 ID BALL A1 4.00 0.05 BALL A9 6.40 CL 8.00 0.10 3.20 0.80 TYP CL 3.20 4.00 0.05 1.00 MAX 8.00 0.10 Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 1. All dimensions are in millimeters. 2. Recommended pad size for PCB is 0.40mm. 3. Topside part marking decoder can be found at www.micron.com/decoder. 78 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Package Dimensions Figure 58: 90-Ball FBGA, "F5/B5" Package (x32 Device), 8mm x 13mm 0.65 0.05 SEATING PLANE SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR 96.5% Sn, 3%Ag, 0.5% Cu A 0.10 A 90X O0.45 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. THE PREREFLOW DIAMETER IS 0.42 ON A 0.40 SMD BALL PAD SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC 6.40 0.80 TYP BALL A1 ID BALL A1 ID BALL A1 BALL A9 11.20 0.10 CL 13.00 0.10 5.60 0.05 6.50 0.05 CL 3.20 1.00 MAX 4.00 0.05 8.00 0.10 Notes: PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 1. All dimensions are in millimeters. 2. Recommended pad size for PCB is 0.4mm 0.025mm. 3. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 4. Topside part marking decoder can be found at www.micron.com/decoder. 79 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved. 128Mb: x16, x32 Mobile SDRAM Package Dimensions Figure 59: 54-Pin Plastic TSOP (400 mil) 22.22 0.08 SEE DETAIL A 0.71 0.80 TYP 0.375 0.075 11.76 0.20 10.16 0.08 0.15 +0.03 -0.02 PIN #1 ID GAGE PLANE 0.25 0.10 1.2 MAX 0.10 LEAD FINISH: TIN/LEAD PLATE PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC PACKAGE WIDTH AND LENGTH DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. Notes: +0.10 -0.05 0.50 0.10 0.80 TYP DETAIL A 1. All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 80 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001 Micron Technology, Inc. All rights reserved.