PIC18F87K90 FAMILY PIC18F87K90 Family Silicon Errata and Data Sheet Clarification The PIC18F87K90 Family devices that you have received conform functionally to the current Device Data Sheet (DS39957D), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. The errata described in this document will be addressed in future revisions of the PIC18F87K90 Family silicon. Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (B3, C1). Data Sheet clarifications and corrections start on page 5, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB(R) IDE and Microchip's programmers, debuggers, and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 2 or PICkitTM 3: 1. 2. 3. 4. Note: The DEVREV values for the various PIC18F87K90 Family silicon revisions are shown in Table 1. Revision ID for Silicon Revision(2) Device ID(1) A3 PIC18F65K90 524h PIC18F66K90 520h PIC18F85K90 52Ah PIC18F86K90 526h PIC18F67K90 510h PIC18F87K90 514h 2: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. SILICON DEVREV VALUES Part Number Note 1: Using the appropriate interface, connect the device to the MPLAB ICD 2 programmer/ debugger or PICkitTM 3. From the main menu in MPLAB IDE, select Configure>Select Device, and then select the target part number in the dialog box. Select the MPLAB hardware tool (Debugger>Select Tool). Perform a "Connect" operation to the device (Debugger>Connect). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. B1 B3 C1 10h 3h 4h 5h The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration memory space. They are shown in hexadecimal in the format "DEVID DEVREV". Refer to the "PIC18F6XKXX/8XKXX Family Flash Microcontroller Programming Specification" (DS39947) for detailed information on Device and Revision IDs for your specific device. 2012 Microchip Technology Inc. DS80500D-page 1 PIC18F87K90 FAMILY TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Affected Revisions(1) Issue Summary A3 B1 B3 C1 Analog-toDigital Converter A/D Offset 1. The 12-bit A/D performance is outside of the data sheet's A/D Converter specifications. X Ports Leakage 2. I/O port leakage is higher than the D060 spec in the data sheet. X X X X High/LowVoltage Detect HLVD Trip 3. X X X X ECCP Auto-Shutdown 4. The tri-state setting of the auto-shutdown feature in the enhanced PWM will not successfully drive the pin to tri-state. X X X X EUSART Synchronous Transmit 5. When using the Synchronous Transmit mode, transmitted data may become corrupted if using the TXxIF bit to determine when to load the TXREGx register. X X X X IPD IDD Maximum Limit 6. Maximum current limits may be higher than specified in Table 31-2 of the data sheet. X 7. Entering Ultra Low-Power Sleep mode, by setting RETEN = 0 and SRETEN = 1, will cause the part to not be programmable through ICSPTM. X X X X Ultra LowSleep Entry Power Sleep The high-to-low (VDIRMAG = 0) setting of the HLVD may send initial interrupts. Resets (BOR) Enable/Disable 8. An unexpected Reset may occur if the Brown-out Reset module (BOR) is disabled, and then re-enabled, when the High/Low-Voltage Detection module (HLVD) is not enabled (HLVDCON<4> = 0). RG5 Pin Leakage 9. RG5 will cause excess pin leakage whenever it is driven low. Note 1: X X X X Only those issues indicated in the last two columns apply to the current silicon revision. DS80500D-page 2 2012 Microchip Technology Inc. PIC18F87K90 FAMILY Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (B3, C1). 1. Module: Analog-to-Digital Converter (A/D) The A/D will meet the Microchip standard A/D specification when used as a 10-bit A/D. When used as a 12-bit A/D, the possible issues include high offset error (up to a maximum of 50 LSBs), high DNL error (up to a maximum of 4 LSBs) and multiple missing codes (up to a maximum of 20). Users should evaluate the 12-bit A/D performance in their application using the suggested work around below. The 12-bit A/D issues will be fixed in a future revision of this part. A/D Offset 3. Module: High/Low Voltage Detect (HLVD) The high-to-low (VDIRMAG = 0) setting of the HLVD may send initial interrupts. High trip points that are close to the intended operating voltage are susceptible to this behavior. Work around Select a lower trip voltage that allows consistent start-up or clear any initial interrupts from the HLVD on start-up. Affected Silicon Revisions A1 B1 B3 C1 X X X X 4. Module: ECCP The tri-state setting of the auto-shutdown feature in the enhanced PWM will not successfully drive the pin to tri-state. The pin will remain an output and should not be driven externally. All tri-state settings will be affected. The A/D may have high offset error, up to a maximum of 50 LSB; it can be used if the A/D is calibrated for the offset. Work around Work around Affected Silicon Revisions Method to Calibrate for Offset: In Single-Ended mode, connect A/D +ve input to ground and take the A/D reading. This will be the offset of the device and can be used to compensate for the subsequent A/D readings on the actual inputs. Affected Silicon Revisions A1 B1 B3 C1 X Use one of the other two auto-shutdown states available, as outlined in the data sheet. A1 B1 B3 C1 X X X X 5. Module: EUSART In Synchronous Transmit mode, data may be corrupted if using the TXxIF bit to determine when to load the TXREGx register. One or more of the intended transmit messages may be incorrect. Work around 2. Module: Ports The input leakage will not match the D060 specification in the data sheet. The leakage will meet the 200 nA specification at TA = 25C. At TA = 85C, the leakage will be up to a maximum of 2 A. Work around Affected Silicon Revisions X B1 while(!TXSTAxbits.TRMT); // wait to load TXREGx until TRMT is set Affected Silicon Revisions None. A1 A fixed delay added before loading the TXREGx may not be a reliable work around. When loading the TXREGx, check that the TRMT bit inside of the TXSTAx register is set instead of checking the TXxIF bit. The following code can be used: B3 C1 X X 2012 Microchip Technology Inc. A1 B1 B3 C1 X X X X DS80500D-page 3 PIC18F87K90 FAMILY 6. Module: IPD and IDD The IPD and IDD limits will not match the data sheet. The values, in bold in Table 31-2, reflect the updated silicon maximum limits. TABLE 31-2: DC CHARACTERISTICS: PIC18F87K90 Family (Industrial) Param No. POWER-DOWN AND SUPPLY CURRENT PIC18F87K90 FAMILY (INDUSTRIAL) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Typ Max Units Conditions Power-Down Current (IPD) Sleep Mode PIC18FXXK90 PIC18FXXK90 PIC18FXXK90 10 500 nA -40C 20 500 nA +25C 120 600 nA +60C 630 2000 nA +85C 50 700 nA -40C 60 900 nA +25C 170 1100 nA +60C 700 5000 nA +85C 350 1300 nA -40C 400 1400 nA +25C 550 1500 nA +60C 1350 4000 nA +85C VDD = 1.8V, Regulator Disabled VDD = 3.3V, Regulator Disabled VDD = 5V, Regulator Enabled Supply Current (IDD) PIC18FXXK90 PIC18FXXK90 PIC18FXXK90 PIC18FXXK90 PIC18FXXK90 PIC18FXXK90 3.7 8.5 A -40C 5.4 10 A +25C 6.60 13 A +85C 8.7 18 A -40C 10 20 A +25C 12 35 A +85C 60 150 A -40C 90 190 A +25C 100 240 A +85C 1.2 4 A -40C 1.7 5 A +25C +85C 2.6 6 A 1.6 7 A -40C 2.8 9 A +25C 4.1 17 A +85C 60 160 A -40C 80 180 A +25C 100 240 A +85C VDD = 1.8V, Regulator Disabled VDD = 3.3V, Regulator Disabled Fosc = 32 kHz, SEC_RUN mode, SOSCSEL = 01 VDD = 5V, Regulator Enabled VDD = 1.8V, Regulator Disabled VDD = 3.3V, Regulator Disabled Fosc = 32 kHz, SEC_IDLE mode, SOSCSEL = 01 VDD = 5V, Regulator Enabled Work around None. Affected Silicon Revisions A1 B1 B3 C1 X DS80500D-page 4 2012 Microchip Technology Inc. PIC18F87K90 FAMILY 7. Module: Ultra Low-Power Sleep 8. Module: Resets (BOR) Entering Ultra Low-Power Sleep mode, by setting RETEN = 0 and SRETEN = 1, will cause the part to not be programmable through ICSP. This issue occurs when the RETEN fuse bit in CONFIG1L<0> is cleared to `0', the SRETEN bit in the WDTCON register is set to `1' and a SLEEP instruction is executed within the first 350 s of code execution, or whenever the above Sleep mode is entered and MCLR is disabled. Discontinue use of the MCLR disabled RG5 mode if ICSP reprogramming is necessary. An unexpected Reset may occur if the Brown-out Reset module (BOR) is disabled, and then reenabled, when the High/Low-Voltage Detection module (HLVD) is not enabled (HLVDCON<4> = 0). This issue affects BOR modes: BOREN<1:0> = 10 and BOREN<1:0> = 01. In both of these modes, if the BOR module is re-enabled while the device is active, unexpected Resets may be generated. Work around If BOR is required, and power consumption is not an issue, use BOREN<1:0> = 11. For BOREN<1:0> = 10 mode, either switch to BOREN<1:0> = 11 mode or enable the HLVD (HLVDCON<4> = 1) prior to entering Sleep. If power consumption is an issue and low power is desired, do not use BOREN<1:0> = 10 mode. Instead, use BOREN<1:0> = 01 and follow the steps below when entering and exiting Sleep. Work around Use normal Sleep and Low-Power Sleep modes only, or on any Reset, ensure at least 350 s passes before executing a SLEEP instruction when ULP is enabled. To ensure the Ultra LowPower Sleep mode is not enabled, the RETEN fuse bit in CONFIG1L<0> should be set to a `1', and the SRETEN bit in the WDTCON register should be cleared to a `0'. The following code can be used: //This will ensure the RETEN fuse is set to 1 1. WDTCONbits.SBOREN = 0; 2. #pragma config RETEN = OFF //This will ensure the SRETEN bit is 0 Affected Silicon Revisions A1 B1 X X B3 Enter Sleep mode (if desired). Sleep(); 3. After exiting Sleep mode (if entered), enable the HLVD (HLVDCON<4> = 1). 4. Wait for the internal reference voltage (TIRVST) to stabilize (typically 25 us). 5. Re-enable BOR (RCON<6> = 1). WDTCONbits.SRETEN = 0; If the Ultra Low-Power Sleep mode is needed, then the user must ensure that the minimum time, before the first SLEEP instruction is executed, is greater than 350 s. Disable BOR by clearing SBOREN (RCON<6> = 0). HLVDCONbits.HLVDEN = 1; while(!HLVDCONbits.IRVST); C1 by setting SBOREN WDTCONbits.SBOREN = 1; X 6. Disable the HLVD (HLVDCON<4> = 0). by clearing HLVDEN HLVDCONbits.HLVDEN = 0; Affected Silicon Revisions 2012 Microchip Technology Inc. A1 B1 B3 C1 X X X X DS80500D-page 5 PIC18F87K90 FAMILY 9. Module: RG5 Pin RG5 will cause excess pin leakage whenever it is driven low. When RG5 is held at 0V, the pin will typically source an additional 160 A of current. Work around In power-sensitive applications, using RG5 as an input, ensure that any input attached to this pin Idles high. Affected Silicon Revisions A1 B1 B3 C1 X DS80500D-page 6 2012 Microchip Technology Inc. PIC18F87K90 FAMILY Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39957D): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: Electrical Characteristics Table 31-25: A/D Converter Characteristics has been corrected. The changes are shown in bold in the table and figure below: TABLE 31-25: A/D CONVERTER CHARACTERISTICS: PIC18F87K90 FAMILY (INDUSTRIAL) Param No. Sym Characteristic A01 NR Resolution A03 EIL Integral Linearity Error A04 EDL Differential Linearity Error A06 EOFF Offset Error A07 EGN Gain Error Monotonicity (1) A10 -- A20 VREF Reference Voltage Range (VREFH - VREFL) Min Typ Max Units -- -- 12 bit VREF 5.0V -- 1 6.0 LSB VREF 5.0V -- 1 +3.0/-1.0 LSB VREF 5.0V -- 1 18.0 LSB VREF 5.0V -- 1 8.0 LSB VREF 5.0V -- -- -- -- 3 -- VDD - VSS V A21 VREFH Reference Voltage High VSS + 3.0V -- VDD + 0.3V V A22 VREFL Reference Voltage Low VSS - 0.3V -- VDD - 3.0V V A25 VAIN Analog Input Voltage VREFL -- VREFH V A30 ZAIN Recommended Impedance of Analog Voltage Source -- -- 2.5 k A50 IREF VREF Input Current(2) -- -- -- -- 5 150 A A Note 1: 2: Conditions VSS VAIN VREF During VAIN acquisition. During A/D conversion cycle. The A/D conversion result never decreases with an increase in the input voltage. VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from the RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source. 2. Module: Voltage Regulator Pins (ENVREG and VCAP/VDDCORE) In Section 2.4 "Voltage Regulator Pins (ENVREG and VCAP/VDDCORE)", the description of the Regulator Disabled mode has changed. The changes are shown in bold below: When the regulator is disabled, the VCAP/VDDCORE pin must only be tied to a 0.1 F capacitor. Refer to Section 31.0 "Electrical Characteristics" for information on VDD and VDDCORE. 2012 Microchip Technology Inc. DS80500D-page 7 PIC18F87K90 FAMILY 3. Module: DC Characteristics (Injection Current) The following table of specifications for current injected into the microcontroller will be added to Section 31.0 "Electrical Characteristics". 31.4 DC Characteristics: PIC18F87K90 Family (Industrial) Standard Operating Conditions: 1.8V to 5.5V Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended DC CHARACTERISTICS Param No. Symbol Characteristic Min Typ Max Units Conditions D160a IICL Input Low Injection Current 0 -- -5(1) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO D160b IICH Input High Injection Current 0 -- +5(1) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO D160c AIICT Total Input Injection Current (sum of all I/O and control pins) -20(1,2) -- +20(1,2) mA Absolute instantaneous sum of all input injection currents from all I/O pins ( IICL + IICH) IICT Note 1: 2: Injection currents > 0 can affect the A/D results. Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted. DS80500D-page 8 2012 Microchip Technology Inc. PIC18F87K90 FAMILY APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (5/2010) Initial release of this document. Silicon issues 1 (A/D), 2 (BOR), 3 (HLVD). and 4 (Ports). Rev B Document (11/2010) Added data sheet clarifications 1-3 (Voltage Regulator Pins - ENVREG and VCAP/VDDCORE). Removed Silicon issue 2 (Brown-out Reset). Changes were made to Silicon issue 3 (HLVD). Added Silicon issues 4 (ECCP), 5 (EUSART) and 6 (IPD and IDD). Rev C Document (4/2011) Added silicon issues 7 (Ultra Low-Power Sleep), 8 (Resets - BOR) and 9 (RG5 Pin). Removed data sheet clarifications 1-3 (Voltage Regulator Pins (ENVREG and VCAP/VDDCORE). Added data sheet clarification 1 (Electrical Characteristics). Rev D Document (2/2012) Added data sheet clarification 2 (Voltage Regulator Pins - ENVREG and VCAP/VDDCORE) and 3 (DC Characteristics - Injection Current). 2012 Microchip Technology Inc. DS80500D-page 9 PIC18F87K90 FAMILY NOTES: DS80500D-page 10 2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62076-028-4 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2012 Microchip Technology Inc. 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