SLOS369B – JULY 2002 – REVISED DECEMBER 2002
FEATURES
DMaximum Battery Life and Minimum Heat
– Efficiency With an 8-Ω Speaker:
– 84% at 400 mW
– 79% at 100 mW
– 2.8-mA Quiescent Current
– 0.5-µA Shutdown Current
DOnly Three External Components
– Optimized PWM Output Stage Eliminates
LC Output Filter
– Internally Generated 250-kHz Switching
Frequency Eliminates Capacitor and
Resistor
– Improved PSRR (–71 dB at 217 Hz) and
Wide Supply Voltage (2.5 V to 5.5 V)
Eliminates Need for a Voltage Regulator
– Fully Differential Design Reduces RF
Rectification and Eliminates Bypass
Capacitor
– Improved CMRR Eliminates Two Input
Coupling Capacitors
APPLICATIONS
DIdeal for Wireless or Cellular Handsets and
PDAs
DESCRIPTION
The TPA2005D1 is a 1.1-W high efficiency filter-free
class-D audio power amplifier in a MicroStar Junior
BGA package that requires only three external
components.
Features like 84% efficiency, –71-dB PSRR at 217 Hz,
improved RF-rectification immunity, and 15 mm2 total
PCB area make the TPA2005D1 ideal for cellular
handsets. A fast start-up time of 9 ms with minimal pop
makes the TP2005D1 ideal for PDA applications.
In cellular handsets, the earpiece, speaker phone, and
melody ringer can each be driven by the TPA2005D1.
The device allows independent gain control by
summing the signals from each function while
minimizing noise to only 48 µVRMS.
APPLICATION CIRCUIT
_
+
IN–
IN+
PWM H–
Bridge
VO+
VO–
Internal
Oscillator CS
To Battery
VDD
GND
Bias
Circuitry
RI
RI
+
–
Differential
Input
TPA2005D1
SHUTDOWN
Actual Solution Size
2.5 mm
CS
RI
RI
6 mm
(MicroStar JuniorBGA)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright 2002, Texas Instruments Incorporated
MicroStar Junior is a trademark of Texas Instruments.
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
2
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ORDERING INFORMATION
TAPACKAGE PART NUMBER SYMBOL
40°Cto85°C
MicroStar Junior (GQY) TPA2005D1GQYR(1) PB051
–40°C to 85°CPlastic small outline (DRB) TPA2005D1DRBR BIQ
(1) The GQY package is only available taped and reeled.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPA2005D1 UNIT
Sllt V
In active mode –0.3 V to 6 V V
Supply voltage, VDD In SHUTDOWN mode –0.3 V to 7 V V
Input voltage, VI–0.3 V to VDD + 0.3 V V
Continuous total power dissipation See Dissipation Rating Table
Operating free-air temperature, TA–40 to 85 °C
Operating junction temperature, TJ–40 to 150 °C
Storage temperature, Tstg –65 to 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, an d
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Supply voltage, VDD 2.5 5.5 V
High-level input voltage, VIH SHUTDOWN 2 VDD V
Low-level input voltage, VIL SHUTDOWN 0 0.8 V
Input resistor, RIGain ≤ 20 V/V (26 dB) 15 kΩ
Common mode input voltage range, VIC VDD = 2.5 V, 5.5 V, CMRR ≤ –49 dB 0.5 VDD–0.8 V
Operating free-air temperature, TA–40 85 °C
PACKAGE DISSIPATION RATINGS
PACKAGE DERATING
FACTOR TA ≤25°C
POWER RATING TA = 70°C
POWER RATING TA = 85°C
POWER RATING
GQY 16 mW/°C2 W 1.28 W 1.04 W
DRB 21.8 mW/°C2.7 W 1.7 W 1.4 W
MicroStar Junior is a trademark of Texas Instruments Incorporated.
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
3
ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOS|Output of fset voltage (measured
differentially) VI = 0 V, A V = 2 V/V, VDD = 2.5 V to 5.5 V 25 mV
PSRR Power supply rejection ratio VDD = 2.5 V to 5.5 V –75 –55 dB
CMRR Common mode rejection ratio VDD = 2.5 V to 5.5 V, VIC = VDD/2 to 0.5 V
VIC = VDD/2 to VDD – 0.8 V –68 –49 dB
IIHHigh-level input current VDD = 5.5 V, VI = 5.8 V 50 µA
IILLow-level input current VDD = 5.5 V, VI = 0.3 V 1µA
VDD = 5.5 V, no load 3.4 4.5
I
(
Q
)
Quiescent current VDD = 3.6 V, no load 2.8 mA
I(Q)
Quiescent
current
VDD = 2.5 V, no load 2.2 3.2
mA
I(SD) Shutdown current V(SHUTDOWN)= 0.8 V, VDD = 2.5 V to 5.5 V 0.5 2 µA
VDD = 2.5 V 770
rDS
(
on
)
Static drain-source on-state resistance VDD = 3.6 V 590 mΩ
rDS(on)
Static
drain source
on state
resistance
VDD = 5.5 V 500
mΩ
Output impedance in SHUTDOWN V(SHUTDOWN) = 0.8 V >1 kΩ
f(sw) Switching frequency VDD = 2.5 V to 5.5 V 200 250 300 kHz
Gain 285 kW
RI
300 kW
RI
315 kW
RIV
V
OPERATING CHARACTERISTICS
TA = 25°C, Gain = 2 V/V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
THD N 1% f 1 kH
VDD = 5 V 1.18
POOutput power THD + N= 1%, f = 1 kHz,
RL=8Ω
VDD = 3.6 V 0.58 W
PO
Out ut
ower
R
L =
8
Ω
VDD = 2.5 V 0.26
W
VDD = 5 V, PO = 1 W, RL = 8 Ω, f = 1 kHz 0.18%
THD+N Total harmonic distortion plus noise VDD = 3.6 V, PO = 0.5 W, RL = 8 Ω, f = 1 kHz 0.19%
THD+N
Total
harmonic
distortion
lus
noise
VDD = 2.5 V, PO = 200 mW, RL = 8 Ω, f = 1 kHz 0.20%
kSVR Supply ripple rejection ratio VDD = 3.6 V,
Inputs ac-grounded
with Ci = 2 µF
f = 217 Hz,
V(RIPPLE) = 200 mVpp –71 dB
SNR Signal-to-noise ratio VDD = 5 V, PO = 1 W, RL = 8 Ω 97 dB
V
Ot t lt i
VDD = 3.6 V,
f = 20 Hz to 20 kHz
,
No weighting 48
V
VnOutput voltage noise
f
=
20
Hz
to
20
kHz
,
Inputs ac-grounded with
Ci = 2 µFA weighting 36 µVRMS
CMRR Common mode rejection ratio VDD = 3.6 V
VIC = 1 Vpp f = 217 Hz –63 dB
ZIInput impedance 142 150 158 kΩ
Start-up time from shutdown VDD = 3.6 V 9 ms
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
4
(A1)
(B1) (A4)
(C4)
(D4)
(SIDE VIEW)
MicroStar Juniort (GQY) Package
(TOP VIEW)
NC VDD
SHUTDOWN
IN+
IN–
VO–
VDD
VO+
NOTES:A. The shaded terminals are used for electrical and thermal connections to the ground plane. All the shaded terminals need to be electrical
connected to ground. No connect (NC) terminals still need a pad and trace.
B. The thermal pad of the DRB package should be electrically and thermally connected to a ground plane.
(C1)
(D1)
(B4)
GND
8
SHUTDOWN
NC
IN+
IN–
VO–
GND
VDD
VO+
DRB PACKAGE
(TOP VIEW)
7
6
5
1
2
3
4
NC – No internal connection
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME GQY DRB I/O DESCRIPTION
IN–D1 4 I Negative dif ferential input
IN+ C1 3 I Positive differential input
VDD B4, C4 6 I Power supply
VO+ D4 5 O Positive BTL output
GND
A2, A3,
B3, C2,
C3 D2,
D3
7 I High-current ground
VO–A4 8 O Negative BTL output
SHUTDOWN A1 1 I Shutdown terminal (active low logic)
NC B1 2 No connect
FUNCTIONAL BLOCK DIAGRAM
_
+_
+_
+_
+
150 kΩ
150 kΩ
_
+
_
+
Deglitch
Logic
Deglitch
Logic
Gate
Drive
Gate
Drive
VDD
OC
Detect
Startup
Protection
Logic
Ramp
Generator
Biases
and
References
TTL
Input
Buffer
SD
Gain = 2 V/V B4, C4
VDD
A4VO–
D4VO+
†GND
D1
IN–
C1
IN+
A1
SHUTDOWN
†A2, A3, B3, C2, C3, D2, D3
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
5
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS FIGURE
Efficiency vs Output power 1, 2
PDPower dissipation vs Output power 3
Supply current vs Output power 4, 5
I(Q) Quiescent current vs Supply voltage 6
I(SD) Shutdown current vs Shutdown voltage 7
P
Output power
vs Supply voltage 8
POOutput power vs Load resistance 9, 10
vs Output power 11, 12
THD+N Total harmonic distortion plus noise vs Frequency 13, 14, 15, 16
THD+N
Total
harmonic
distortion
lus
noise
vs Common-mode input voltage 17
K
Supply voltage rejection ratio
vs Frequency 18, 19, 20
KSVR Supply voltage rejection ratio vs Common-mode input voltage 21
GSM power supply rejection
vs Time 22
GSM power supply rejection vs Frequency 23
CMRR
Common mode rejection ratio
vs Frequency 24
CMRR Common-mode rejection ratio vs Common-mode input voltage 25
TEST SET-UP FOR GRAPHS
TPA2005D1
IN+
IN–
OUT+
OUT–
VDD GND
CI
CI
RI
RI
Measurement
Output
+
–
1 µF
+
–
VDD
Load 30 kHz
Low Pass
Filter
Measurement
Input
+
–
Notes:
(1) CI was Shorted for any Common-Mode input voltage measurement
(2) A 33-µH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements.
(3) The 30-kHz low-pass filter is required even if the analyzer has a low-pass filter. An RC filter (100 Ω, 47 nF) is used on
each output for the data sheet graphs.
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
6
TYPICAL CHARACTERISTICS
Figure 1
0
10
20
30
40
50
60
70
80
90
100
0 0.1 0.2 0.3 0.4 0.5 0.6
PO – Output Power – W
Efficiency – %
EFFICIENCY
vs
OUTPUT POWER
VDD = 3.6
RL = 32 Ω, 33 µH
RL = 16 Ω, 33 µH
RL = 8 Ω, 33 µH
Class-AB,
RL = 8 Ω
Figure 2
0
10
20
30
40
50
60
70
80
90
0 0.2 0.4 0.6 0.8 1 1.2
VDD = 2.5 V,
RL= 8 Ω, 33 µH
VDD = 5 V,
RL = 8 Ω, 33 µH
Class-AB,
VDD = 5 V,
RL = 8 Ω
PO – Output Power – W
Efficiency – %
EFFICIENCY
vs
OUTPUT POWER
Figure 3
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 0.2 0.4 0.6 0.8 1 1.2
– Power Dissipation – W
POWER DISSIPATION
vs
OUTPUT POWER
PD
PO – Output Power – W
Class-AB, VDD = 5 V, RL = 8 Ω
Class-AB,
VDD = 3.6 V,
RL = 8 Ω
VDD = 3.6 V,
RL = 8 Ω, 33 µH
VDD = 5 V,
RL = 8 Ω, 33 µH
Figure 4
0
50
100
150
200
250
0 0.1 0.2 0.3 0.4 0.5 0.6
RL = 8 Ω, 33 µH
VDD = 3.6 V
RL = 32 Ω, 33 µH
Supply Current – mA
SUPPLY CURRENT
vs
OUTPUT POWER
PO – Output Power – W
Figure 5
0
50
100
150
200
250
300
0 0.2 0.4 0.6 0.8 1 1.2
SUPPLY CURRENT
vs
OUTPUT POWER
PO – Output Power – W
VDD = 2.5 V,
RL = 8 Ω, 33 µH
VDD = 3.6 V,
RL = 8 Ω, 33 µH
VDD = 5 V,
RL = 8 Ω, 33 µH
Supply Current – mA
Figure 6
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
2.5 3 3.5 4 4.5 5 5.5
I(Q)– Quiescent Current – mA
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
VDD – Supply Voltage – V
No Load
RL = 8 Ω, 33 µH
Figure 7
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
VDD = 2.5 V
VDD = 3.6 V
VDD = 5 V
Shutdown Voltage – V
– Shutdown Current –
SHUTDOWN CURRENT
vs
SHUTDOWN VOLTAGE
I(SD) Aµ
Figure 8
2.5 3 3.5 4 4.5 5
VDD – Supply Voltage – V
– Output Power – W
OUTPUT POWER
vs
SUPPLY VOLTAGE
PO
RL = 8 Ω
f = 1 kHz
Gain = 2 V/V
THD+N = 1%
THD+N = 10%
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
Figure 9
0
0.2
0.4
0.6
0.8
1
1.2
1.4
8 121620 28
RL – Load Resistance – Ω
OUTPUT POWER
vs
LOAD RESISTANCE
– Output Power – WPO
3224
f = 1 kHz
THD+N = 1%
Gain = 2 V/V
VDD = 2.5 V
VDD = 3.6 V
VDD = 5 V
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
7
TYPICAL CHARACTERISTICS
Figure 10
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
8 121620242832
VDD = 5 V
VDD = 3.6 V
VDD = 2.5 V
RL – Load Resistance – Ω
OUTPUT POWER
vs
LOAD RESISTANCE
– Output Power – WPO
f = 1 kHz
THD+N = 10%
Gain = 2 V/V
Figure 11
0.1
30
0.2
0.5
1
2
5
10
20
0.01 20.02 0.1 1
PO – Output Power – W
THD+N – Total Harmonic Distortion + Noise – %
T OTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
5 V
3.6 V
2.5 V
RL = 8 Ω,
f = 1 kHz,
Gain = 2 V/V
Figure 12
0.1
30
0.2
0.5
1
2
5
10
20
0.01 20.02 0.1 1
PO – Output Power – W
THD+N – Total Harmonic Distortion + Noise – %
T OTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
5 V
3.6 V
2.5 V
RL = 16 Ω,
f = 1 kHz,
Gain = 2 V/V
Figure 13
0.008
10
0.02
0.05
0.1
0.2
0.5
1
2
5
20 50 100 200 500 1 k 2 k 20 k
f – Frequency – Hz
T OTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD+N – Total Harmonic Distortion + Noise – %
50 mW
250 mW
1 W
VDD = 5 V
CI = 2 µF
RL = 8 Ω
Gain = 2 V/V
Figure 14
1
2
5
10
0.5
0.2
0.1
0.05
0.02
0.0120 50 100 200 500 1 k 2 k 20 k
f – Frequency – Hz
T OTAL HARMONIC DISTORTION + NOIS
E
vs
FREQUENCY
THD+N – Total Harmonic Distortion + Noise – %
VDD = 3.6 V
CI = 2 µF
RL = 8 Ω
Gain = 2 V/V
500 mW 25 mW
125 mW
Figure 15
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.0120 50 100 200 600 1 k 2 k 20 k
f – Frequency – Hz
T OTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD+N – Total Harmonic Distortion + Noise – %
15 mW
VDD = 2.5 V
CI = 2 µF
RL = 8 Ω
Gain = 2 V/V
75 mW
200 mW
Figure 16
VDD = 3.6 V
CI = 2 µF
RL = 16 Ω
Gain = 2 V/V
f – Frequency – Hz
T OTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD+N – Total Harmonic Distortion + Noise – %
1
2
5
10
0.5
0.2
0.1
0.05
0.02
0.0120 50 100 200 500 1 k 2 k 20 k
15 mW
75 mW
200 mW
Figure 17
0.1
1
10
0 0.5 1 1.5 2 2.5 3 3.5
VDD = 2.5 V
VDD = 3.6 V
f = 1 kHz
PO = 200 mW
VIC – Common Mode Input Voltage – V
T OTAL HARMONIC DISTORTION + NOIS
E
vs
COMMON MODE INPUT VOLTAGE
THD+N – Total Harmonic Distortion + Noise – %
Figure 18
–80
–70
–60
–50
–40
–30
–20
–10
0
20 100 1 k 20 k
f – Frequency – Hz
– Supply Voltage Rejection Ratio – dB
SUPPLY VOL TAGE REJECTION RATIO
vs
FREQUENCY
kSVR
50 200 600 2 k
CI = 2 µF
RL = 8 Ω
Vp-p = 200 mV
Inputs ac-Grounded
Gain = 2 V/V
VDD = 5 V
VDD = 3.6 V
VDD =2. 5 V
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
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8
TYPICAL CHARACTERISTICS
Figure 19
–80
–70
–60
–50
–40
–30
–20
–10
0
f – Frequency – Hz
– Supply Voltage Rejection Ratio – dB
SUPPLY VOL TAGE REJECTION RATIO
vs
FREQUENCY
kSVR
20 100 1 k 20 k50 200 600 2 k
Gain = 5 V/V
CI = 2 µF
RL = 8 Ω
Vp-p = 200 mV
Inputs ac-Grounded
VDD = 5 V
VDD = 2. 5 V
VDD = 3.6 V
Figure 20
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
f – Frequency – Hz
– Supply Voltage Rejection Ratio – dB
SUPPLY VOL TAGE REJECTION RATIO
vs
FREQUENCY
kSVR
VDD = 3.6 V
CI = 2 µF
RL = 8 Ω
Inputs Floating
Gain = 2 V/V
20 100 1 k 20 k50 200 600 2 k
Figure 21
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VIC – Common Mode Input Voltage – V
SUPPLY VOL TAGE REJECTION RATIO
vs
COMMON-MODE INPUT VOLTAGE
f = 217 Hz
RL = 8 Ω
Gain = 2 V/V
VDD = 2.5 V
– Supply Voltage Rejection Ratio – dBkSVR
VDD = 3.6 V
VDD = 5 V
Figure 22
C1 – Duty
12.6%
C1 –
Frequency
216.7448 Hz
C1 – Amplitude
512 mV
C1 – High
3.544 V
Voltage – V
t – Time – ms
GSM POWER SUPPLY REJECTION
vs
TIME
VDD
VOUT
Figure 23
–150
–100
–50
0 400 800 1200 1600 2000
–150
–100
–50
0
0
f – Frequency – Hz
– Output Voltage – dBVVO
– Supply Voltage – dBVVDD
VDD Shown in Figure 22
CI = 2 µF,
Inputs ac-grounded
Gain = 2V/V
GSM POWER SUPPLY REJECTION
vs
FREQUENCY
Figure 24
–70
–60
–50
–40
–30
–20
–10
0
f – Frequency – Hz
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
CMRR – Common Mode Rejection Ratio – dB
20 100 1 k 20 k50 200 600 2 k
VDD = 2.5 V to 5 V
VIC = 1 Vp–p
RL = 8 Ω
Gain = 2 V/V
Figure 25
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
RL = 8 Ω
Gain = 2 V/V
VIC – Common Mode Input Voltage – V
COMMON-MODE REJECTION RATIO
vs
COMMON-MODE INPUT VOLTAGE
CMRR – Common Mode Rejection Ratio – dB
VDD = 5 V
VDD = 2.5 V VDD = 3.6 V
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
9
APPLICATION INFORMATION
FULLY DIFFERENTIAL AMPLIFIER
The TPA2005D1 is a fully d i fferential amplifier with differential inputs and outputs. The fully dif ferential amplifier
consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that the
amplifier outputs a differential voltage on the output that is equal to the differential input times the gain. The
common-mode feedback ensures that the common-mode voltage at the output is biased around VDD/2
regardless of the common-mode voltage at the input. The fully differential TPA2005D1 can still be used with
a single-ended input; however, the TPA2005D1 should be used with differential inputs when in a noisy
environment, like a wireless handset, to ensure maximum noise rejection.
Advantages of Fully DIfferential Amplifiers
DInput-coupling capacitors not required:
–The fully differential amplifier allows the inputs to be biased at voltage other than mid-supply. For
example, if a codec has a midsupply lower than the midsupply of the TPA2005D1, the common-mode
feedback circuit will adjust, and the TPA2005D1 outputs will still be biased at midsupply of the
TPA2005D1. The inputs of the TPA2005D1 can be biased from 0.5V to VDD – 0.8 V. If the inputs are
biased outside of that range, input-coupling capacitors are required.
DMidsupply bypass capacitor, C(BYPASS), not required:
–The fully differential amplifier does not require a bypass capacitor. This is because any shift in the
midsupply affects both positive and negative channels equally and cancels at the differential output.
DBetter RF–immunity:
–GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. The
transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the
signal much better than the typical audio amplifier.
COMPONENT SELECTION
Figure 26 shows the TPA2005D1 typical schematic with differential inputs and Figure 27 shows the
TPA2005D1 with differential inputs and input capacitors, and Figure 28 shows the TPA2005D1 with
single-ended inputs. Dif ferential inputs should be used whenever possible because the single-ended inputs are
much more susceptible to noise.
Table 1. Typical Component Values
REF DES VALUE EIA SIZE MANUFACTURER PART NUMBER
RI150 kΩ (±0.5%) 0402 Panasonic ERJ2RHD154V
CS1 µF (+22%, –80%) 0402 Murata GRP155F50J105Z
CI(1) 3.3 nF (±10%) 0201 Murata GRP033B10J332K
(1) CI is only needed for single-ended input or if VICM is not between 0.5 V and VDD – 0.8 V. CI = 3.3 nF
(with RI = 150 kΩ) gives a high-pass corner frequency of 321 Hz.
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
10
_
+
IN–
IN+
PWM H–
Bridge
VO+
VO–
Internal
Oscillator CS
To Battery
VDD
GND
Bias
Circuitry
RI
RI
+
–
Differential
Input
TPA2005D1
Filter-Free Class D
SHUTDOWN
Figure 26. Typical TPA2005D1 Application Schematic With Differential Input for a Wireless Phone
_
+
IN–
IN+
PWM H–
Bridge
VO+
VO–
Internal
Oscillator CS
To Battery
VDD
GND
Bias
Circuitry
RI
RI
Differential
Input
TPA2005D1
Filter-Free Class D
SHUTDOWN
CI
CI
Figure 27. TPA2005D1 Application Schematic With Differential Input and Input Capacitors
_
+
IN–
IN+
PWM H–
Bridge
VO+
VO–
Internal
Oscillator CS
To Battery
VDD
GND
Bias
Circuitry
RI
RI
Single-ended
Input
TPA2005D1
Filter-Free Class D
SHUTDOWN
CI
CI
Figure 28. TPA2005D1 Application Schematic With Single-Ended Input
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
11
Input Resistors (RI)
The input resistors (RI) set the gain of the amplifier according to equation (1).
Gain +300 kW
RIǒV
VǓ
Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic
distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or
better to keep the performance optimized. Matching is more important than overall tolerance. Resistor arrays
with 1% matching can be used with a tolerance greater than 1%.
Place the input resistors very close to the TPA2005D1 to limit noise injection on the high-impedance nodes.
For optimal performance the gain should be set to 2 V/V or lower. Lower gain allows the TPA2005D1 to operate
at its best, and keeps a high voltage at the input making the inputs less susceptible to noise.
Decoupling Capacitor (CS)
The TPA2005D1 is a high-performance class-D audio amplifier that requires adequate power supply decoupling
to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients,
spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically
1 µF, placed as close as possible to the device VDD lead works best. Placing this decoupling capacitor close
to the TPA2005D1 is very important for the efficiency of the class-D amplifier, because any resistance or
inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering
lower-frequency noise signals, a 10 µF or greater capacitor placed near the audio power amplifier would also
help, but it is not required in most applications because of the high PSRR of this device.
Input Capacitors (CI)
The TPA2005D1 does not require input coupling capacitors if the design uses a dif ferential source that is biased
from 0.5 V to VDD – 0.8 V (shown in Figure 26). If the input signal is not biased within the recommended
common–mode input range, if needing to use the input as a high pass filter (shown in Figure 27), or if using
a single-ended source (shown in Figure 28), input coupling capacitors are required.
The input capacitors and input resistors form a high-pass filter with the corner frequency, fc, determined in
equation (2).
fc+1
ǒ2pRICIǓ
The value of the input capacitor is important to consider as it directly affects the bass (low frequency)
performance of t h e circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the
corner frequency can be set to block low frequencies in this application.
Equation (3) is reconfigured to solve for the input coupling capacitance.
CI+1
ǒ2pRIfcǓ
If the corner frequency is within the audio band, the capacitors should have a tolerance of ±10% or better,
because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below.
For a flat low-frequency response, use large input coupling capacitors (1 µF). However, in a GSM phone the
ground s i gnal is fluctuating at 217 Hz, but the signal from the codec does not have the same 217 Hz fluctuation.
The difference between the two signals is amplified, sent to the speaker, and heard as a 217 Hz hum.
(1)
(2)
(3)
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
12
SUMMING INPUT SIGNALS WITH THE TPA2005D1
Most wireless phones or PDAs need to sum signals at the audio power amplifier or just have two signal sources
that need separate gain. The TPA2005D1 makes it easy to sum signals or use separate signal sources with
different gains. Many phones now use the same speaker for the earpiece and ringer , where the wireless phone
would require a much lower gain for the phone earpiece than for the ringer. PDAs and phones that have stereo
headphones require summing of the right and left channels to output the stereo signal to the mono speaker.
Summing Two Differential Input Signals
Two extra resistors are needed for summing differential signals (a total of 5 components). The gain for each
input source can be set independently (see equations (4) and (5), and Figure 29).
Gain 1 +VO
VI1 +300 kW
RI1 ǒV
VǓ
Gain 2 +VO
VI2 +300 kW
RI2 ǒV
VǓ
If summing left and right inputs with a gain of 1 V/V, use RI1 = RI2 = 300 kΩ.
If summing a ring tone and a phone signal, set the ring-tone gain to Gain 2 = 2 V/V, and the phone gain to
gain 1 = 0.1 V/V. The resistor values would be. . .
RI1 = 3 MΩ, and = RI2 = 150 kΩ.
_
+
IN–
IN+
PWM H–
Bridge
VO+
VO–
Internal
Oscillator CS
To Battery
VDD
GND
Bias
Circuitry
RI2
RI2
+
–
Differential
Input 1
SHUTDOWN
RI1
RI1
+
–
Differential
Input 2
Filter-Free Class D
Figure 29. Application Schematic With TPA2005D1 Summing Two Differential Inputs
(4)
(5)
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
13
Summing a Differential Input Signal and a Single-Ended Input Signal
Figure 30 shows how to sum a differential input signal and a single-ended input signal. Ground noise can couple
in through IN+ with this method. It is better to use differential inputs. The corner frequency of the single-ended
input is set by CI2, shown in equation (8). To assure that each input is balanced, the single-ended input must
be driven by a low-impedance source even if the input is not in use
Gain 1 +VO
VI1 +300 kW
RI1 ǒV
VǓ
Gain 2 +VO
VI2 +300 kW
RI2 ǒV
VǓ
CI2 +1
ǒ2pRI2 fc2Ǔ
If summing a ring tone and a phone signal, the phone signal should use a differential input signal while the ring
tone might be limited to a single-ended signal. Phone gain is set at gain 1 = 0.1 V/V, and the ring-tone gain is
set to gain 2 = 2 V/V, the resistor values would be…
RI1 = 3 MΩ, and = RI2 = 150 kΩ.
The high paMs corner frequency of the single-ended input is set by CI2. If the desired corner frequency is less
than 20 Hz...
CI2 u1
ǒ2p150kW20HzǓ
CI2 u53pF
_
+
IN–
IN+
PWM H–
Bridge
VO+
VO–
Internal
Oscillator CS
To Battery
VDD
GND
Bias
Circuitry
RI2
RI2
Differential
Input 1
Filter-Free Class D
SHUTDOWN
RI1
RI1
Single-Ended
Input 2
CI2
CI2
Figure 30. Application Schematic With TPA2005D1 Summing Differential Input and
Single-Ended Input Signals
(6)
(7)
(8)
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
14
Summing Two Single-Ended Input Signals
Four resistors and three capacitors are needed for summing single-ended input signals. The gain and corner
frequencies (fc1 and fc2) for each input source can be set independently (see equations (9) through (12), and
Figure 31). Resistor, RP, and capacitor, CP, are needed on the IN+ terminal to match the impedance on the IN–
terminal. The single-ended inputs must be driven by low inpedance sources even if one of the inputs is not
outputting an ac signal.
Gain 1 +VO
VI1 +300 kW
RI1 ǒV
VǓ
Gain 2 +VO
VI2 +300 kW
RI2 ǒV
VǓ
CI1 +1
ǒ2pRI1 fc1Ǔ
CI2 +1
ǒ2pRI2 fc2Ǔ
CP+CI1 )CI2
RP+RI1 RI2
ǒRI1 )RI2Ǔ
_
+
IN–
IN+
PWM H–
Bridge
VO+
VO–
Internal
Oscillator CS
To Battery
VDD
GND
Bias
Circuitry
RI2
RP
Filter-Free Class D
SHUTDOWN
RI1
Single-Ended
Input 2
CI2
CP
Single-Ended
Input 1
CI1
Figure 31. Application Schematic With TPA2005D1 Summing Two Single-Ended Inputs
(9)
(10)
(11)
(12)
(13)
(14)
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
15
EFFICIENCY AND THERMAL INFORMATION
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor
for the 2.5-mm x 2.5-mm MicroStar Junior package is shown in the dissipation rating table. Converting this to
θJA:
qJA +1
Derating Factor +1
0.016 +62.5°CńW
Given θJA of 62.5°C/W, the maximum allowable junction temperature of 150°C, and the maximum internal
dissipation of 0.2 W (worst case 5-V supply), the maximum ambient temperature can be calculated with the
following equation.
TAMax +TJMax *qJAPDmax +150 *62.5 (0.2) +137.5°C
Equation (16) shows that the calculated maximum ambient temperature is 137.5°C at maximum power
dissipation with a 5-V supply; however, the maximum ambient temperature of the package is limited to 85°C.
Because of the e fficiency of the TPA2005D1, it can be operated under all conditions to an ambient temperature
of 85°C. The TPA2005D1 is designed with thermal protection that turns the device off when the junction
temperature surpasses 150°C to prevent damage to the IC. Also, using speakers more resistive than 8-Ω
dramatically increases the thermal performance by reducing the output current and increasing the efficiency
of the amplifier.
BOARD LAYOUT
Component Location
Place all the external components very close to the TPA2005D1. The input resistors need to be very close to
the TPA2005D1 input pins so noise does not couple on the high impedance nodes between the input resistors
and the input amplifier of the TPA2005D1. Placing the decoupling capacitor, CS, close to the TPA2005D1 is
important for the ef ficiency of the class-D amplifier. Any resistance or inductance in the trace between the device
and the capacitor can cause a loss in efficiency.
Trace Width
Make the high current traces going to pins VDD, GND, VO+ and VO– of the TPA2005D1 have a minimum width
of 0. 7 m m . I f t h e s e t r a c e s a r e t o o t h i n , t h e T PA2005D1’s performance and output power will decrease. The input
traces do not need to be wide, but do need to run side-by-side to enable common-mode noise cancellation.
(15)
(16)
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
16
MicroStar Junior BGA Layout
Use the following MicroStar Junior BGA ball diameters:
D0.25 mm diameter solder mask
D0.28 mm diameter solder paste mask/stencil
D0.38 mm diameter copper trace
Figure 7 shows how to lay out a board for the TPA2005D1 MicroStar Junior BGA.
0.28
mm
0.38
mm
0.25
mm
SD
NC
IN+
IN–
GND GND
GND
GND GND
GND GND
VDD
VDD
Vo+
Vo–
Solder Mask
Paste Mask
Copper Trace
Figure 32. TPA2005D1 MicroStar Junior BGA Board Layout (Top View)
ELIMINATING THE OUTPUT FILTER WITH THE TPA2005D1
This section focuses on why the user can eliminate the output filter with the TPA2005D1.
Effect on Audio
The class-D amplifier outputs a pulse-width modulated (PWM) square wave, which is the sum of the switching
waveform and the amplified input audio signal. The human ear acts as a band-pass filter such that only the
frequencies between approximately 20 Hz and 20 kHz are passed. The switching frequency components are
much greater than 20 kHz, so the only signal heard is the amplified input audio signal.
Traditional Class-D Modulation Scheme
The traditional class-D modulation scheme, which is used in the TPA005Dxx family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VDD. Therefore,
the differential pre-filtered output varies between positive and negative VDD, where filtered 50% duty cycle
yields 0 volts across the load. The traditional class-D modulation scheme with voltage and current waveforms
is shown in Figure 33. Note that even at an average of 0 volts across the load (50% duty cycle), the current
to the load is high causing a high loss and thus causing a high supply current.
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
17
0 V
–5 V
+5 V
Current
OUT+
Differential Voltage
Across Load
OUT–
Figure 33. Traditional Class-D Modulation Scheme’s Output Voltage and
Current Waveforms Into an Inductive Load With no Input
TPA2005D1 Modulation Scheme
The TPA2005D1 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUT+ and OUT– are now in phase with each other with no input. The duty cycle of OUT+ is greater
than 50% and OUT– is less than 50% for positive voltages. The duty cycle of OUT+ is less than 50% and OUT–
is greater than 50% for negative voltages. The voltage across the load sits at 0 volts throughout most of the
switching period greatly reducing the switching current, which reduces any I2R losses in the load.
0 V
–5 V
+5 V
Current
OUT+
OUT–
Differential
Voltage
Across
Load
0 V
–5 V
+5 V
Current
OUT+
OUT–
Differential
Voltage
Across
Load
Output = 0 V
Output > 0 V
Figure 34. The TPA2005D1 Output Voltage and Current Waveforms Into an Inductive Load
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
18
Efficiency: Why You Must Use a Filter With the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform
results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple
current is large for the traditional modulation scheme because the ripple current is proportional to voltage
multiplied by the time at that voltage. The differential voltage swing is 2 ×VDD and the time at each voltage
is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current
from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both
resistive and reactive, whereas an LC filter is almost purely reactive.
The TPA2005D1 modulation scheme has very little loss in the load without a filter because the pulses are very
short and the change in voltage is VDD instead of 2 ×VDD. As the output power increases, the pulses widen
making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but
for most applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to
flow th r ough the filter instead of the load. The filter has less resistance than the speaker that results in l es s p ow er
dissipated, which increases efficiency.
Effects of Applying a Square Wave Into a Speaker
If the amplitude of a square wave is high enough and the frequency of the square wave is within the bandwidth
of the speaker, a square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil.
A 250-kHz switching frequency, however, is not significant because the speaker cone movement is proportional
to 1/f2 for frequencies beyond the audio band. Therefore, the amount of cone movement at the switching
frequency is very small. However, damage could occur to the speaker if the voice coil is not designed to handle
the additional power. To size the speaker for added power, the ripple current dissipated in the load needs to
be calculated by subtracting the theoretical supplied power , P SUP THEORETICAL, from the actual supply power,
PSUP, at maximum output power, POUT. The switching power dissipated in the speaker is the inverse of the
measured efficiency, ηMEASURED, minus the theoretical efficiency, ηTHEORETICAL.
PSPKR +PSUP–PSUP THEORETICAL (at max output power)
PSPKR +PSUP
POUT–PSUP THEORETICAL
POUT (at max output power)
PSPKR +POUT ǒ1
hMEASURED *1
hTHEORETICALǓ(at max output power)
hTHEORETICAL +RL
RL)2rDS(on) (at max output power)
The maximum efficiency of the TPA2005D1 with a 3.6 V supply and an 8-Ω load is 86% from equation (20).
Using equation (19) with the efficiency at maximum power (84%), we see that there is an additional 17 mW
dissipated in the speaker. The added power dissipated in the speaker is not an issue as long as it is taken into
account when choosing the speaker.
(17)
(18)
(19)
(20)
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
19
When to Use an Output Filter
Design the TPA2005D1 without an output filter if the traces from amplifier to speaker are short. The TPA2005D1
passed FCC and CE radiated emissions with no shielding with speaker trace wires 100 mm long or less.
Wireless handsets and PDAs are great applications for class-D without a filter.
A ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter, and the
frequency sensitive circuit is greater than 1 MHz. This is good for circuits that just have to pass FCC and CE
because FCC and CE only test radiated emissions greater than 30 MHz. If choosing a ferrite bead, choose one
with high impedance at high frequencies, but very low impedance at low frequencies.
Use an LC output filter if there are low frequency (< 1 MHz) EMI sensitive circuits and/or there are long leads
from amplifier to speaker.
Figure 35 and Figure 36 show typical ferrite bead and LC output filters.
1 nF
Ferrite
Chip Bead
OUTP
OUTN
Ferrite
Chip Bead
1 nF
Figure 35. Typical Ferrite Chip Bead Filter (Chip bead example: NEC/Tokin: N2012ZPS121)
1 µF
1 µF
33 µH
33 µH
OUTP
OUTN
Figure 36. Typical LC Output Filter, Cutoff Frequency of 27 kHz
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
20
MECHANICAL DATA
DRB (S-PDSO-N8) PLASTIC SMALL OUTLINE
Seating Plane
4203482/B 03/02
1,00
0,80
0,05
Pin 1 Index Area
Top and Bottom
3,25
0,00
0,08
2,75
2,75
3,25
0,20 REF.
0,25
0,37
0,65
0,45
Exposed Thermal Die Pad
(See Nore D)
1
1,85 MAX
1,59 MAX
0,10
4
85
1,95
Exposed Metalized
Feature (4x)
8X
8X
0,65
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Small Outline No-lead (SON) package configuration.
D. The package thermal performance may be enhanced by bonding the thermal die pad to an external thermal plane.
SLOS369B – JULY 2002 – REVISED DECEMBER 2002
www.ti.com
21
MECHANICAL DATA
GQY (S-PBGA-N15) PLASTIC BALL GRID ARRAY
0,50
0,08
M
0,05
0,50
4201436/B 10/00
2,60
2,40
1,00 MAX
0,25
0,35
1
Seating Plane
1,50 TYP
A
1,50 TYP
0,21
0,11
2 3
B
C
0,68
0,62
D
4
SQ
0,25
0,25
(BOTTOM VIEW)
NOTES: A. All l i near dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar Junior configuration
D. Falls within JEDEC MO-225
MicroStar Junior is a trademark of Texas Instruments.
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