Products and specifications discussed herein are subject to change by Micron without notice.
128Mb: x16, x32 Mobile SDRAM
Features
PDF: 09005aef807f4885/Source: 09005aef8071a76b Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
128Mbx16x32Mobile_1.fm - Rev. L 10/07 EN 1©2001 Micron Technology, Inc. All rights reserved.
Mobile SDRAM
MT48LC8M16LF, MT48V8M16LF, MT48LC4M32LF, MT48V4M32LF
Features
• Temperature-compensated self refresh (TCSR)
• Fully synchronous; all sig nals regist ered on positiv e
edge of system clock
• Internal pipe lined operation; col umn addres s can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• A uto prechar ge, includes concurr ent auto precharge ,
and auto refresh modes
• Self refresh mode; standard and low power
• 64ms, 4,096-cycle refresh (15.6µs/row)
• LVTTL-compatible inputs and outputs
• Low voltage power supply
• Partial-array self refresh (PASR) power-saving mo de
Notes: 1. x16 only.
2. x32 only.
3. Contact Micron for availability.
Options Mark
•VDD/VDDQ
–3.3V/3.3V LC
–2.5V/2.5–1.8V V
• Configurations
–8 Me g x 16 (2 Meg x 16 x 4 banks) 8M16
–4 Me g x 32 (1 Meg x 32 x 4 banks) 4M32
• Package/ball out
–54-ball VFBGA (8mm x 8mm)1F4
–54-ball VFBGA (8mm x 8mm)1 Pb-free B4
–90-ball VFBGA (8mm x 13mm)2F5
–90-ball VFBGA (8mm x 13mm)2 Pb-free B5
–54-pin TSOP II (400 mil) TG3
–54-pin TSOP II (400 mil) Pb-free P3
• Timing (cycle time)
–7.5ns @ CL = 3 (133 MHz) -75M3
–8ns @ CL = 3 (125 MHz) -8
–10ns @ CL = 3 (100 MHz) -103
•Temperature
–Commercial (0°C to +70°C) None
–Industrial (–40°C to +85°C) IT
–Extended (–25°C to +75°C) XT3
•Design revision :G
Part Num ber Example:
MT48V8M16LFB4-8:G
Table 1: Configurations
8 Meg x 16 4 Meg x 32
Configuration 2 Meg x 16 x 4
banks 1 Meg x 32 x 4
banks
Refresh count 4K 4K
Row addressing 4K (A0–A11) 4K (A0–A11)
Bank addressing 4 (BA0, BA1) 4 (BA0, BA1)
Column
addressing 512 (A0–A8) 256 (A0–A7)
Table 2: Key Timing Parameters
CL = CAS (READ) latency
Speed
Grade Clock
Frequency
Access Time
tRCD tRPCL = 1 CL = 2 CL = 3
-75M 133 MHz – – 5.4 19ns 19ns
-8 125 MHz – – 7ns 20ns 20ns
-10 100 MHz – – 7ns 20ns 20ns
-75M 100 MHz – 6 – 19ns 19ns
-8 100 MHz – 8ns – 20ns 20ns
-10 83 MHz – 8ns – 20ns 20ns
-8 50 MHz 19ns – – 20ns 20ns
-10 40 MHz 22ns – – 20ns 20ns
PDF: 09005aef807f4885/Source: 09005aef8071a76b Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
128Mbx16x32MobileTOC.fm - Rev. L 10/07 EN 2©2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
Table of Contents
Table of Contents
FBGA Part Marking Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pin/Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Burst Length (BL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Write Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Temperature-Compensated Self Refresh (TCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Partial-Array Self Refresh (PASR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
COMMAND INHIBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
NO OPERATION (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
ACTIVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
BURST TERMINATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
AUTO REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
SELF REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
BANK/ROW ACTIVATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
WRITEs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
CLOCK SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Burst Read/Single Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
CONCURRENT Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
READ with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Temperature and Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
PDF: 09005aef807f4885/Source: 09005aef8071a76b Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
128Mbx16x32MobileLOF.fm - Rev. L 10/07 EN 3©2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
List of Figur es
List of Figures
Figure 2: Functional Block Diagram 8 Meg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 3: Functional Block Diagram 4 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 4: 90-Ball FBGA Pin Ass ignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5: 54-Pin TSOP Pin Assignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 6: 54-Ball VFBGA Pin Assig nments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 7: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 8: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 9: Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 10: Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 11: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 12: READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 13: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 14: Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 15: Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 16: READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 17: READ-to-WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 18: READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 19: Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 20: WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 21: WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 22: WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 23: Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Figure 24: WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Figure 25: WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 26: Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 27: PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 28: Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 29: Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 30: Clock Suspend Duri ng REA D Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 31: READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 32: READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 33: WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 34: WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 35: Example Temperature Test Point Location, 54- P in TSOP: Top View . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Figure 36: Example Temperature Test Point Location, 54-Ball VFBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . .50
Figure 37: Example Temperature Test Point Location, 90-Ball VFBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . .50
Figure 38: Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Figure 39: Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Figure 40: Clock Susp end Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Figure 41: Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Figure 42: Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Figure 43: READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Figure 44: Read – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Figure 45: Single Read – Wi thout Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Figure 46: Single Read – Wi th Aut o Precha rge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Figure 47: Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 48: Read – Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Figure 49: Read – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Figure 50: Write – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Figure 51: Write – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Figure 52: Single Write – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Figure 53: Single Write – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Figure 54: Alternating Bank Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Figure 55: Write – Full-page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Figure 56: Write – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Figure 57: 54-Ball FBGA, “F4/B4” Package (x16 Device), 8mm x 8mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
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128Mbx16x32MobileLOF.fm - Rev. L 10/07 EN 4©2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
List of Figur es
Figure 58: 90-Ball FBGA, “F5/B5” Package (x32 Device), 8mm x 13mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 59: 54-Pin Plastic TSOP (400 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
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128Mbx16x32MobileLOT.fm - Rev. L 10/07 EN 5©2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
List of Tables
List of Tables
Table 1: Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 2: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 3: Ball Descriptions: 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 4: Ball Descriptions: 90-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 5: Pin Descriptions: 54-Pin TSOP (x16 Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 6: Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 7: CAS Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 8: Truth Table – Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 9: Truth Table – CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Table 10: Truth Table – Current State Bank n, Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 11: Truth Table – CURRENT STATE BANK n, COMMAND tO BANK m . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 12: Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 13: Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 14: Thermal Impedance Simulated Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 15: DC Electrical Characteristics and Operating Conditions (LC Version). . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 16: DC Electrical Characteristics and Operating Conditions (V Version). . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 17: Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .52
Table 18: AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 19: IDD Specifications and Conditions (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 20: IDD7 Self Refresh Current Options (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 21: IDD Specifications And Conditions (x32). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 22: IDD7 Self Refresh Current Options (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 23: Capacitance (FBGA Pacakge). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 24: Capacitance (TSOP Pacakge). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
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128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN 6©2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
FBGA Part Marking Decoder
Figure 1: 128Mb SDRAM Part Numbers
Notes: 1. Not all speeds and con f ig urations are available.
2. Contact Micron for availability.
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part
marking that is different from the part number. Micron’s new FBGA Part Mar kin g
Decoder makes it easier to understand that part marking. Visit the Web site at
www.micron.com/decoder.
General Description
The Micron® 128Mb SDRAM device is a high-speed CMOS, dynamic random access
memory con tain ing 134,2 17,7 28 bits. It is internally configured as a quad-bank DRAM
with a synchronous interface (all signals are registered on the positive edge of the clock
signal, CLK). Each of the x16’s 33,554,432-bit banks is organized as 4,096 rows by 512
columns by 16 bits . Each of the x32’s 33,554,432-bit banks is organized as 4,096 rows by
256 columns by 32 bits .
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses beg in with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A11 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8
locations, or the full page, with a burst terminate option. An auto precharge function
may be enabled to provide a self-timed row pr echarge that is initiated at the end of the
burst sequence.
-
Configuration MT4 8 Package Speed T emperature
Configuration
8 Meg x 16
4 Meg x 32 8M16
4M32
Package
54-ball VFBGA (8 x 8mm)
54-ball VFBGA (8 x 8mm) lead-free
90-ball VFBGA (8 x 13mm)
90-ball VFBGA (8 x 13mm) lead-free
54-pin TSOP II (400 mil)
54-pin TSOP II (400 mil) Lead-Free
IT
XT
Operating T emp
Standard
Industrial T emp
Extended T emp
Example Part Number: MT48V4M32LFF5-10XT
Voltage (V
DD
/V
DD
Q)
3.3V/ 3.3V
2.5V / 2.5V–1.8V
LC
V
V
DD
/
V
DD
Q L F
F4
B4
F5
B5
TG
2
P
2
Revision
:G
Rev
Revision
Speed Grade
t
CK = 7.5ns, CL = 3
t
CK = 8ns, CL = 3
t
CK = 10ns, CL = 3
-75M
2
-8
-10
2
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128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN 7©2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
General Description
The 128Mb SDRAM device uses an internal pipelined ar chitectur e to achieve high-speed
operation. This ar chitecture is compatible with the 2n rule of prefetch architectures, but
it also enables the column address to be changed on every clock cycle to achieve a high-
speed, fully random access . P r echar ging one bank while access ing one of the other three
banks will hide th e precharge cycl es an d provide seamless high- sp ee d, random-access
operation.
The 128Mb SDRAM device is designed to operate in 3.3V or 2.5V low-power memory
systems. The 2.5V version is compatible with 1.8V I/O interface. An auto refresh mode is
provided along with a power-saving, power-down m ode. All inputs and outputs are
LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating perfor mance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave be tween internal banks to hide pre charge time, and
the capability to randomly change column addresses on each clock cycl e during a burst
access.
Figure 2: Functional Block Diagram 8 Meg x 16 SDRAM
12
RAS#
CAS#
ROW-
ADDRESS
MUX
CLK
CS#
WE#
CKE
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
MODE REGISTER
9
COMMAND
DECODE
A0-A11,
BA0, BA1
DQML,
DQMH
12
ADDRESS
REGISTER
14
512
(x16)
4,096
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(4,096 x 512 x 16)
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
4096
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
DQ0-
DQ15
16
DATA
INPUT
REGISTER
DATA
OUTPUT
REGISTER
16
12
BANK1BANK2 BANK3
12
9
2
2 2
2
REFRESH
COUNTER
16
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128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN 8©2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
General Description
Figure 3: Functional Block Diagram 4 Meg x 32 SDRAM
12
RAS#
CAS#
CLK
CS#
WE#
CKE
8
A0–A11,
BA0, BA1
DQM0–
DQM3
14
256
(x32)
4096
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(4,096 x 256 x 32)
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
4,096
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
DQ0–
DQ31
32
DATA
INPUT
REGISTER
DATA
OUTPUT
REGISTER
32
BANK1
BANK0
BANK2 BANK3
12
8
2
4 4
2
REFRESH
COUNTER
12
12
MODE REGISTER
CONTROL
LOGIC
COMMAND
DECODE
ROW-
ADDRESS
MUX
ADDRESS
REGISTER
COLUMN-
ADDRESS
COUNTER/
LATCH
32
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128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN 9©2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
Pin/Ball Assignments and Descriptions
Pin/Ball Assignments and Descriptions
Figure 4: 90-Ball FBGA Pin Assignments (Top View)
1234 67895
DQ26
DQ28
V
SS
Q
V
SS
Q
V
DD
Q
V
SS
A4
A7
CLK
DQM1
V
DD
Q
V
SS
Q
V
SS
Q
DQ11
DQ13
DQ24
V
DD
Q
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQ8
DQ10
DQ12
V
DD
Q
DQ15
V
SS
V
SS
Q
DQ25
DQ30
NC
A3
A6
NC
A9
NC
V
SS
DQ9
DQ14
V
SS
Q
V
SS
V
DD
V
DD
Q
DQ22
DQ17
NC
A2
A10
NC
BA0
CAS#
V
DD
DQ6
DQ1
V
DD
Q
V
DD
DQ21
DQ19
V
DD
Q
V
DD
Q
V
SS
Q
V
DD
A1
A11
RAS#
DQM0
V
SS
Q
V
DD
Q
V
DD
Q
DQ4
DQ2
DQ23
V
SS
Q
DQ20
DQ18
DQ16
DQM2
A0
BA1
CS#
WE#
DQ7
DQ5
DQ3
V
SS
Q
DQ0
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
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128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN 10 ©2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
Pin/Ball Assignments and Descriptions
Figure 5: 54-Pin TSOP Pin Assignments (Top View)
Notes: 1. The # symbol indicates signal is active LOW.
Figure 6: 54-Ball VFBGA Pin Assignments (Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VssQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VssQ
DQ7
VDD
DQML
WE#
CAS#
RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ15
VssQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VssQ
DQ10
DQ9
VDDQ
DQ8
Vss
NC
DQMH
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
x16 x16
A
B
C
D
E
F
G
H
J
1 2 3 4 5 6 7 8
Top View
(Ball Down)
VSS
DQ14
DQ12
DQ10
DQ8
UDQM
NC/A12
A8
VSS
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
A6
A4
VDDQ
VSSQ
VDDQ
VSSQ
VDD
CAS#
BA0
A0
A3
DQ0
DQ2
DQ4
DQ6
LDQM
RAS#
BA1
A1
A2
VDD
DQ1
DQ3
DQ5
DQ7
WE#
CS#
A10
VDD
9
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128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN 11 ©2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
Pin/Ball Assignments and Descriptions
Table 3: Ball Descriptions: 54-Ball VFBGA
54-Ball VFBGA Symbol Type Description
F2 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output regi st ers.
F3 CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides precharge power-down and SELF
REFRESH operation (all banks idle), active power-down (row active in any
bank), or CLOCK SUSPEND operation (burst/access in progress). CKE is
synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during power-down
and self refresh modes, providing low standby power. CKE may be tied
HIGH.
G9 CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH, but READ/WRITE bursts already in progress will continue and DQM
will retain its DQ mask capability while CS# remains HIGH. CS# provides
for external bank selection on systems with multiple banks. CS# is
considered part of the command code.
F7, F8, F9 CAS#, RAS#,
WE# Input Command inputs: CAS#, RAS#, and WE# (alon g with CS#) define the
command being entered.
E8, F1 LDQM,
UDQM Input Input/Output mask: DQM is sampled HI GH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z
state (2-clock latency) duri ng a READ cycle. LDQM corresponds to DQ0–
DQ7, and UDQM corresponds to DQ8–DQ15. LDQM and UDQM are
considered same state when referenced as DQM.
G7, G8 BA0, BA1 Input Bank address input(s): BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. These pins also
provide the op-code during a LOAD MODE REGISTER command.
H7, H8, J8, J7, J3, J2, H3,
H2, H1, G3, H9, G2 A0–A6
A7–A11 Input Address inputs: A0–A11 are sampled during the ACTIVE command (row-
address A0–A11) and READ/WRITE command (column-address A0–A8;
with A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine whether all banks are to be
precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address
inputs also provide the op-code during a LOAD MODE REGISTER
command.
A8, B9, B8, C9, C8, D9,
D8, E9, E1, D2, D1, C2,
C1, B2, B1, A2
DQ0–DQ5
DQ6–DQ11
DQ12–DQ15
I/O Data input/output: Data bus.
E2, G1 NC – No connect: These pins should be left unconnected. G1 is a no connect
for this part but may be used as A12 in future designs.
A7, B3, C7, D3 VDDQ Supply DQ power: Isolated DQ power on the die to improve noise immunity.
A3, B7, C3, D7 VSSQ Supply DQ ground: Isolated DQ power on the die to improve noise immunity.
A9, E7, J9 VDD Supply Power supply: Voltage dependant on option.
A1, E3, J1 VDD Supply Ground.
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128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN 12 ©2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
Pin/Ball Assignments and Descriptions
Table 4: Ball Descriptions: 90-Ball VFBGA
90-Ball FBGA Symbol Type Description
J1 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output regi st ers.
J2 CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides precharge power-down and SELF
REFRESH operation (all banks idle), active power-down (row active in any
bank), or CLOCK SUSPEND operation (burst/access in progress). CKE is
synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during power-down
and self refresh modes, providing low standby power. CKE may be tied
HIGH.
J8 CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH, but READ/WRITE bursts already in progress will continue and DQM
will retain its DQ mask capability while CS# remains HIGH. CS# provides
for external bank selection on systems with multiple banks. CS# is
considered part of the command code.
J9, K7, K8 RAS#, CAS#,
WE# Input Command inputs: RAS#, CAS#, and WE# (alon g with CS#) define the
command being entered.
K9, K1, F8, F2 DQM0–3 Input Input/Output mask: DQM is sampled HIGH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z
state (2-clock latency) duri ng a READ cycle. DQM0 corresponds to DQ0–
DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–
DQ23, and DQM3 corresponds to DQ24–DQ3 1. DQM0–3 are considered
same state when referenced as DQM.
J7, H8 BA0, BA1 Input Bank address input(s): BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. These pins also
provide the op-code during a LOAD MODE REGISTER command.
G8, G9, F7, F3, G1, G2,
G3, H1, H2, J3, G7, H9 A0–A5
A6–A11 Input Address inputs: A0–A11 are sampled during the ACTIVE command (row-
address A0–A11) and READ/WRITE command (column-address A0–A7;
with A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine whether all banks are to be
precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address
inputs also provide the op-code during a LOAD MODE REGISTER
command.
R8, N7, R9, N8, P9, M8,
M7, L8, L2, M3, M2, P1,
N2, R1, N3, R2, E8, D7,
D8, B9, C8, A9, C7, A8,
A2, C3, A1, C2, B1, D2,
D3, E2
DQ0–DQ5
DQ6–DQ11
DQ12–DQ17
DQ18–DQ23
DQ24–DQ29
DQ30–DQ31
I/O Data input/output: Data bus.
E3, E7, H3, H7, K2, K3 NC – No connect: These pins should be left unconnected. H3 is a no connect
for this part, but may be used as A12 in future designs.
B2, B7, C9, D9, E1, L1,
M9, N9, P2, P7 VDDQ Supply DQ power: Isolated DQ power on the die to improve noise immunity.
B8, B3, C1, D1, E9, L9,
M1, N1, P3, P8 VSSQ Supply DQ ground: Isolated DQ power on the die to improve noise immunity.
A7, F9, L7, R7 VDD Supply Power supply: Voltage dependant on option.
A3, F1, L3, R3 VSS Supply Ground.
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128Mb: x16, x32 Mobile SDRAM
Pin/Ball Assignments and Descriptions
Table 5: Pin Descriptions: 54-Pin TSOP (x16 Only)
54-Pin TSOP Symbol Type Description
38 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output regi st ers.
37 CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides precharge power-down and SELF
REFRESH operation (all banks idle), active power-down (row active in any
bank), or CLOCK SUSPEND operation (burst/access in progress). CKE is
synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during power-down
and self refresh modes, providing low standby power. CKE may be tied
HIGH.
19 CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH, but READ/WRITE bursts already in progress will continue and DQM
will retain its DQ mask capability while CS# remains HIGH. CS# provides
for external bank selection on systems with multiple banks. CS# is
considered part of the command code.
16, 17, 18 WE#, CA S#,
RAS# Input Command inputs: WE#, CAS#, and RAS# (along with CS#) define the
command being entered.
15, 39 DQML,
DQMH Input Input/Output mask: DQM is sampled HI GH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z
state (2-clock latency) duri ng a READ cycle. DQM0 corresponds to DQ0–
DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–
DQ23, and DQM3 corresponds to DQ24–DQ31. LDQM corresponds to
DQ0–DQ7, and UDQM corresponds to DQ8–DQ15. LDQM and UDQM are
considered same state when referenced as DQM.
20, 21 BA0, BA1 Input Bank address input(s): BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. These pins also
provide the op-code during a LOAD MODE REGISTER command.
23, 24, 25, 29, 30,
31, 32, 33, 34, 22, 35 A0–A5
A6–A11 Input Address inputs: A0–A11 are sampled during the ACTIVE command (row-
address A0–A11) and READ/WRITE command (column-address A0–A7;
with A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine whether all banks are to be
precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address
inputs also provide the op-code during a LOAD MODE REGISTER
command.
2, 4, 5, 7, 8, 10, 11, 13,
42, 49, 45, 47, 48, 50, 51 DQ0–DQ7
DQ8–DQ15 I/O Data input/output: Dat a bus (x16 only).
36, 40 NC – No connect: These pins should b e left unconnected. Pin 36 is a no connect
for this part, but may be used as A12 in future designs.
3, 9, 43, 49 VDDQ Supply DQ power: Isolated DQ power on the die to improve noise immun ity.
6, 12, 46, 52 VSSQ Supply DQ ground: Isolated DQ power on the die to improve noise immunity.
1, 14, 27 VDD Supply Power supply: Volt age dependant on option.
28, 41, 54 VSS Supply Ground.
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128Mb: x16, x32 Mobile SDRAM
Functional Description
Functional Description
In general, the 128Mb SDRAMs (2 M eg x 16 x 4 banks and 1 Meg x 32 x 4 banks) are quad-
bank DRAMs that operate at 3.3V or 2.5V and include a synchronous interface (all
signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s
33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. Each of the
x32’s 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses beg in with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A11 select the row). The address bits (x16: A0–A8; x32: A0–A7) regis-
tered coincident with the READ or WRITE command are used to select the starting
column location for the burst access.
Prior to normal ope ration, the SDR AM must be initialized . The fo ll owing sections
provide detailed information covering device initialization, register definition,
command descriptions, and device operation.
Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may r esult in undefined operation. After power is
applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is
defined as a signal cycling within timing constraints specified for the clock pin), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least
through the end of this pe riod, C O MMAND INHIBIT or NOP commands must be
applied.
After the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be pr echarged, thereby placing the device in the all banks idle state.
Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the
AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an unknown state, it must be loaded
prior to applying any operational command. If desired, the two AUTO REFRESH
commands can be issued after the LOAD MODE REGISTER (LMR) command.
The recommended power-up sequence for SDRAMs:
1. Simultaneously apply power to VDD and VDDQ.
2. Assert and hold CKE at a LVTTL logic LOW.
3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing
constraints speci fie d for th e c loc k pin.
4. Wait at least 100µs prior to issuing any command other than a COMMAND INHIBIT
or NOP.
5. S tarting at some point during this 100µs period, bring CKE HIGH. Continuing at least
through the end of this period, one or more COMMAND INHIBIT or NOP commands
must be applied.
6. Perform a PRECHARGE ALL command.
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128Mb: x16, x32 Mobile SDRAM
Register Definition
7. Wait at least tRP time; during this time, NOPs or DESELECT commands must be
given. All banks will complete their precharge, thereby placing the device in the all
banks idle state.
8. Issue an AUTO REFRESH command.
9. Wait at least tRFC time, during which only NOP s or COMMAND INHIBIT commands
are allowed.
10. Issue an AUTO REFRESH command.
11. Wait at least tRFC time , during which only NOPs or COMMAND INHIBIT commands
are allowed.
12. The SDRAM is now ready for mode register progr a mming. Because the mode register
will power up in an unknown state, it should be loaded with desired bit values prior to
applying any operational command. Using the LMR command, program the mode
register. The mode r egister is programmed via the MODE REGISTER SET command
with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again
or the device loses power. Not programming the mode re gister upon initialization will
result in default settings, which may not be desired. Outputs are guaranteed High-Z
after the LMR command is issued. Outputs should be High-Z already before the LMR
command is issued.
13. Wait at least tMRD time, during which only NOP or DESELECT commands are
allowed.
14. Using the LMR command, program the extended mode register. The low-power
extended mode r e gister is pr ogra mmed via the MODE REGISTER SET command with
BA1 = 1, BA0 = 0 and retains the stored information until it is programmed again or
the device loses power. Not programming the extended mod e register upon initializa-
tion will re sult in default settings for the low-power features. The extend ed mode will
default with the temper ature sensor enabled, full drive strength, and full array refr e sh.
15. Wait at least tMRD time, during which only NOP or DESELECT commands are
allowed.
At this poi n t, the DRAM is ready for any valid command.
Note: If desired, more than two AUTO REFRESH commands can b e is sue d in th e se que n c e.
After steps 9 and 10 are complete, repeat them until the desired number of AUTO
REFRESH + tRFC loops is achieved.
Register Definition
Mode Register
To achieve low power co nsumption, there are two mode registers in the Mobile compo-
nent: mode regi ster and extended mode re gister. Mode registe r is discussed in this
section. Extended mode register is discussed on page 20. The mode register is used to
define the specific mode of operation of the SDRAM. This definition includes the selec-
tion of BL, a burst type, CL, an operating mode , and a write burst mode, as shown in
Figure 7 on page 17. The mode register is progr a mmed via the LOAD MODE REGISTER
command and w il l retain the stored information until it is programmed again or the
device loses power.
Mode r egister bits M0–M2 specify BL, M3 specifies the type of burst (sequential or inter-
leaved), M4–M6 specify CL, M7 and M8 specify the operating mode , M9 specify the write
burst mode (single or programme d burs t le ngth), M10 and M11 are reserved an d mus t
be set to zero. To address the mode register, M12 and M13 must be set to zero.
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128Mb: x16, x32 Mobile SDRAM
Register Definition
The mode regi ster must be loaded when all banks are idle, and the controller mus t wait
the specified time before initiating the subs equent operation. Violating either of these
requirements will result in unspecified operation.
Burst Length (BL)
Re ad and write access es to the SDRAM ar e bur st oriented, wi th BL being progr ammable,
as shown in Figure8 on page 19. BL determines the maximum number of column loca-
tions that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4,
or 8 locations ar e available for b oth the sequenti al and the interleave d burst types , and a
full-page burst is available for the sequential mode. The full-page burst is used in
conjunction with the BURST TERMINATE command to generate arbitrary burst lengths.
If a full page burst is not terminated at the end of the page, it could wrap to column zer o
and continue.
Reserved states cannot be used because unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to BL is effectively
selected. All accesses for that burst take place within this block, meaning that the burst
will wrap within the block if a boundary is reached. The block i s uniquely selected b y A1–
A8 (x16) or A1–A7 (x32) when BL = 2; by A2–A8 (x16) or A2–A7 (x32) when BL = 4; and by
A3–A8 (x16) or A3–A7 (x32) when BL = 8. The remaining (least significant) address bit(s)
is (are) used to select the starting location within the block. Full-page bursts wrap within
the page if the boundary is reached.
Burst Type
Accesses wi thin a given burst may be programmed either to be sequential or interleaved;
this is r eferre d to as the burst type and is selected via bi t M3. N ote only a sequential burst
is allo wed for full page bursts.
The ordering of accesses within a burst is determined by BL, the burst type, and the
starting column address, as shown in Table 6 on page 18.
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128Mb: x16, x32 Mobile SDRAM
Register Definition
Figure 7: Mode Register Definition
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
0
1
0
0
Mode
Register (Mx)
Address Bus
9 7 6 5 4 3 8 2 1
Burst Length CAS Latency BT
Op Mode WB Reserved
A11
M11
A10
M10
A9
M9
A8
M8
A7
M7
A6
M6
A5
M5
A4
M4
A3
M3
A2
M2
A1
M1
A0
M0
10 11 12
BA0
M12
BA1
M13
MR
13 0
M11
0
–
M10
0
–
M9
Valid
–
M8
0
–
M7
0
–
M6–M0
Valid
–
Operating Mode
Normal Operation
All other states reserved
Mode Register Definition
Program Mode Register
Program Extended Mode Register
M13 M12
0
0
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
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128Mb: x16, x32 Mobile SDRAM
Register Definition
NOTE: Notes: 1. For full-page accesses: y = 512 (x16), y = 256 (x32).
2. For BL = 2, A1–A8 (x16) or A1–A7 (x32) select the block-of-two burst; A0 selects the starting
column within the block.
3. For BL = 4, A2–A8 (x16) or A2–A7 (x32) select the block-of-four burst; A0–A1 select the start-
ing column within the block.
4. For BL = 8, A3–A8 (x16) or A3–A7 (x32) select the block-of-eight burst; A0–A2 selec t the
starting column within the block.
5. For a full-page burst, the full row is selected, and A0–A8 (x16) or A0–A7 (x32) select the
starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the following
access wraps within the block.
7. For BL = 1, A0–A8 (x16) or A0–A7 (x32) select the unique column to be accessed, and mode
register bit M3 is ignored.
CAS Latency (CL)
CL is the delay, in clock cycles, between the registration of a READ command and the
availability of the first pi ece of output data. The latency can be set to 1, 2, or 3 clocks.
If a READ command is registered at clock edge n and the latency is m clocks, the data will
be available by clock edge n + m. The DQ will start driving as a result of the clock edge
one cycle earlier ( n + m - 1), and pro vided that the relevant access times ar e met, the data
will be val id b y clock edge n + m. For example, assuming that the clock cycle time is such
that all relevant access times are met, if a re ad command is registered at T0 and the
Table 6: Burst Definition
Burst Length Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
2A0
00-1 0-1
11-0 1-0
4A1 A0
0 0 0-1-2-3 0-1-2-3
0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
8A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Full page (y) n = A0–A8 for x16, A0–
A7 for x32
(location 0–y)
Cn, Cn + 1,
Cn + 2,
Cn + 3, Cn + 4...,
…Cn - 1,
Cn…
Not supported
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128Mb: x16, x32 Mobile SDRAM
Register Definition
latency i s pr og r ammed t o 2 c loc ks , the DQ wil l st art driv ing af ter T1 , and the data wil l be
valid by T2, as shown in Figure8. Table 7 indicates the operating frequencies at which
each CL setting can be use d.
Reserved states should not be used as unkno wn operation or incompatibility with future
versions may result.
Figure 8: CAS Latency
Write Burst Mode
When M9 = 0, BL programmed into M0–M2 applies to both READ and WRITE burst. If
M9 = 1, all WRITE bursts will only be single loc ation access r egar dless of the BL setti ng in
the mode register. READ burst lengths are unaffected by the state of M9.
Table 7: CAS Latency
Speed
Allowable Operating Frequency (MHz)
CL = 1 CL = 2 CL = 3
-75M – ≤ 100 ≤ 133
-8 ≤ 50 ≤ 100 ≤ 125
-10 ≤ 40 ≤ 83 ≤ 100
CLK
DQ
T2T1 T3T0
CL = 3
LZ
D
OUT
tOH
t
COMMAND NOPREAD
tAC
NOP
T4
NOP
DON’T CARE
UNDEFINED
CLK
DQ
T2T1T0
CL = 1
LZ
D
OUT
tOH
t
COMMAND NOPREAD
tAC
CLK
DQ
T2T1 T3T0
CL = 2
LZ
D
OUT
tOH
t
COMMAND NOPREAD
tAC
NOP
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128Mb: x16, x32 Mobile SDRAM
Register Definition
Operating Mode
The normal operating mode is selected by setting M7, M8, M10, and M11 to zero; all the
other combinations of values for M7, M8, M10, and M11 are re served for future use and/
or test modes.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
Extended Mode Register
The extended mode re gister controls the functions beyond those controll ed by the mode
register. These additional functions are special features of the Mobile device. They
include TCSR and PASR.
Figure 9: Extended Mode Register
Notes: 1. M13 and M12 (BA1 and BA0) must be “1, 0” to select the extended mode register (vs. the
base mode register).
2. RFU: reserved for future use.
The extended mode register is programmed via the MODE REGISTER SET command
(BA1 = 1, BA0 = 0) and retains the stored information until it is progr ammed again or the
device loses power.
The extended mode re gister must be progra mmed with E5 through E11 set to “0.” The
extended mode register must be loaded when all banks are idle and no bursts are in
progress, and the controller must wait the specified time before initiating any subse-
quent operation. Violating either of thes e r equir ements results in unspecified operation.
The extended mode re gister must be programmed to ensure proper operation.
Temperature-Compensated Self Refresh (TCSR)
TCSR all ows the controller to program the refresh interval during self refresh mode,
according to the case temperature of the Mobile device. This allows great power savings
during self refresh during most operating temperature ranges. Only during extreme
temperatures would the controller have to select a higher TCSR level that will guarantee
data during sel f refresh.
9 7 6 5 4 3 8 2 1
PASR TCSR set to “0” EMR
E13 E12
A11
E11
A10
E10
A9
E9
A8
E8
A7
E7
A6
E6
A5
E5
A4
E4
A3
E3
A2
E2
A1
E1
A0
E0
10 11 12 13
Partial-Array Self Refresh Coverage
FullArray (All Banks)
Half Array (BA1 = 0)
Quarter Array (BA1 = BA0 = 0)
RFU
RFU
RFU
RFU
RFU
BA1 BA0
M13
0
0
1
1
Mode Register Definition
Mode Register
Reserved
Extended Mode Register
Resereved
M12
0
1
0
1
0
E11
0
–
E10
0
–
E9
0
–
E8
0
–
E7
0
–
E4 E3 E2 E1 E0
Valid
–
Operating Mode
Normal Operation
All other states reserved
Extended Mode
Register (Ex)
E6
0
–
E5
0
–
E2
0
0
0
0
1
1
1
1
E1
0
0
1
1
0
0
1
1
E0
0
1
0
1
0
1
0
1
Maximum Case Temp.
85°C
70°C
45°C
15°C
E4
1
0
0
1
E3
1
0
1
0
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128Mb: x16, x32 Mobile SDRAM
Register Definition
Every cell in the DRAM requires refreshing due to the capacitor losing its charge over
time. The refresh rate is dependent on temperature. At higher temperatures a capacitor
loses charge quicker than at lower temperatures , r equiring the cells to be refr eshed more
often. Historically, during self refresh, the refresh rate has been set to accom modate the
worst case, or highest temperature range, expected.
Thus, during ambient temperatures, the power consume d during refresh was unneces-
sarily high because the refresh rate was set to accommodate the higher temperatures.
Setting E4 and E3 allows the DRAM to accommodate more specific temperature regions
during self refresh. There are four temperature settings, which will vary the self r efresh
current accor ding to the selected temperature. This selectable refresh rate will save
power when the DRAM is operating at normal temperatures .
Partial-Array Self Refresh (PASR)
Fo r further power savings during self refresh, the PA SR feature allows the controller to
select the amount of memory that will be refreshed during self refresh. The refresh
options are all banks (banks 0, 1, 2, and 3); two banks (banks 0 and 1); and one bank
(bank 0). WRITE and READ commands occur to any bank selected during standard
operation, but only the selected banks in PASR will be refr eshed during self refresh. It’s
important to note that data in banks 2 and 3 will be lost when the two-bank optio n is
used. Data will be lost in banks 1, 2, and 3 when the one-bank option is used.
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Register Definition
Commands
Table 8 provides a quick re ference of available commands. This is followed by a written
description of each command. Three additional Truth Tables appear following the Oper-
ation section; these tables provide current state/next state information.
Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
3. A0–A8 (x16) or A0–A7 (x32) provide column address; A10 HIGH enables the auto precharge
feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1
determine which bank is being read from or written to.
4. A10 LOW : BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged
and BA0, BA1 are “Don’t Care.”
5. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
6. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
for CKE.
7. A0–A10 define the op-code written to the mode register. BA0–BA1 either select mode regis-
ter or the extended mode register (BA0 = BA1 = 0 select the mode register, BA1 = 1, BA0 = 0
selects the extended mode register, all other combinations of BA0-BA1 are reserved).
8. Activates or deactivates the DQ during WRITEs (0-clock delay) and READs (2-clock delay). For
x16, LDQM controls DQ0–DQ7, and UDQM controls DQ8–DQ15. For x32, DQM0 controls
DQ0–DQ7, DQM1 controls DQ8–DQ15, DQM2 controls DQ16–23, and DQM3 controls DQ24–
DQ31.
COMMAND INHIBIT
The COMMAND INHIBIT function pr ev ents new commands from being executed b y the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected SDRAM to
perform a NOP (RAS#, CAS#, and WE# are HIGH, and CS# is LOW). This prevents
unwanted commands from be ing registered during id le or wait states. Operations
already in progress are not affected.
Table 8: Truth Table – Commands and DQM Operation
Note 1 applies to entire table
Name (Function) CS# RAS# CAS# WE# DQM Addr DQ Notes
COMMAND INHIBIT (NOP) HXXXX X X
NO OPERATION (NOP) LHHHX X X
ACTIVE (Select bank and act iva t e ro w) L L H H X Bank/row X 2
READ (Select bank and column, and start READ burst) L H L H L/H8Bank/col X 3
WRITE (Select bank and column, and start WRITE burst) L H L L L/H8Bank/col Valid 3
BURST TERMINATE LHHLX X Active
PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 4
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode) LLLHX X X 5, 6
LOAD MODE REGISTER LLLLXOp-codeX 7
Write enable/output enable ––––L – Active8
Write inhibit/output High-Z ––––H –High-Z8
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Register Definition
LOAD MODE REGISTER
The mode register is loaded via inputs A0–A11 . Refer to “Mod e Register Defin iti on” on
page 17. The LOAD MODE REGISTER and LOAD EXTENDED MODE REGISTER
commands can only be issued when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA0, BA1 inputs selects the bank, and the addr ess
provided on inputs A0–A11 s elec ts the row. This row remains active (or open) for
accesses until a PRECHARGE command is issued to that bank. A PRECHARGE
command must be issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst r ead access to an activ e row. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A8 (x16) or
A0–A7 (x32) selects the starting column location. The value on input A1 0 determines
whether auto precharge is used. If auto precharge is selected, the row being accessed will
be precharged at the end of the read burst; if auto precharge is not selected, the row will
remain open for subsequent accesses . Read data appears on the DQ subject to the logic
level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH,
the corresponding DQ will be High-Z two clocks later; if the DQM signal was registered
LOW, the DQ will provide valid data.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A8 (x16)
or A0–A7 (x32) selects the starting column location. The value on input A10 determines
whether auto precharge is used. If auto precharge is selected, the row being accessed will
be pr echar ged at the end of the write burst; if auto precharge is not selected, the row will
remain open for subsequent accesses. Input data appearing on the DQ is written to the
memor y array subject to the DQM input logic le ve l appe aring coincide nt with the data.
If a given DQM signal is registered LOW, the corresponding data will be written to
memory; if the DQM signal is registered HIGH, the corresponding data inputs will be
ignored, and a write will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specifie d time (tRP) after the PRECHARGE command is issued. Input A10 determines
whether one or all banks ar e to be precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” After a bank has been precharged, it is in the idle state and must be acti-
vated prior to any READ or WRITE commands being issued to that bank.
Auto Precharge
Auto precharge is a feature that performs the same individual-bank precharge function
described above, without requiring an expl ic it command. This is accompl ished b y using
A10 to enable auto precharge in conjunction with a specific READ or WRITE command.
A prechar ge of the bank/row that is addressed with the READ or WRITE command is
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Register Definition
automatically performed upon completion of the READ or WRITE burst, except in the
full-page burst mode where auto prec har ge does not apply. Auto precharge is nonpersis-
tent in that it is either enabled or disabled for each individual read or write command.
Auto precharge ensures that the pr echarge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharge
time (tRP) is completed. This is determined as if an explicit PRECHARGE command was
issued at the earliest possible time, as described for each burst type in “Operation” on
page 25.
BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-length or full-page
bursts. The most recently re gistered READ or WRITE command prior to the BURST
TERMINATE command will be truncated, as shown in the Op er ation se ction of this data
sheet. The BURST TERMINATE command does not precharge the row; the row will
remain open until a PRECHARGE command is issued.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in conv entional DRAMs. This command is nonper-
sistent, so it must be issued each time a refresh is required. All active banks must be
PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH
command should not be issued until the minimum tRP has been met after the
PRECHAR GE command as shown in the operation section.
The addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. The 128Mb SDRAM requires
4,096 AUTO REFRESH cycles every 64ms (tREF), regardless of width option. Providing a
distributed AUTO REFRESH command every 15.625µs will meet the refresh r equir ement
and ensure that each row is refreshed. Alternatively, 4,096 AUT O REFRESH commands
can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms.
SELF REFRESH
The SELF REFRESH co mm and can be use d to retain data in the SDRAM, even if the rest
of the system is powered down. When in the self r efresh mode, the SDRAM retains data
without external clo ck ing. The SELF REF RESH com m and is initiated like an AU TO
REFRESH command except CKE is disabled (LOW). After the SELF REFRESH command
is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of
CKE, which must remain LOW.
After self refr esh mode is engaged, the SDRAM provides its own internal clocking,
causing it to perform its o wn auto r e fr esh cy cles . The SDRAM must r emain in self r efr esh
mode for a minimum period equal to tRAS and may remain in self refresh mode for an
indefinite period beyond that.
The procedur e for exit ing self r efresh requir es a se quence of commands. First, CLK must
be stable (stable clock is defined as a signal cycling within timing constraints specified
for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SD RA M mus t
have NOP commands issued (a minimum of 2 clocks, regardless of clock frequency) for
tXSR because time is required for the completion of any inter nal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every
15.625µs or less because both SELF REFRESH and AUTO REFRESH utilize the row
refresh counter.
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Register Definition
Operation
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row
in that bank must be “opened.” This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see Figure 10).
After opening a ro w (issuing an A CTIVE command), a RE AD or WRITE command may be
issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a tRCD specifi cation of 20ns with a 125 MHz clock (8ns period)
results in 2.5 clocks, rounded to 3. This is r eflected in F igure 11 on page 26, which co vers
any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same procedure is used to convert other
specificati o n limits from time units to clock cycles.)
A subsequent ACTIVE command to a differ ent row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which resul ts in a r eduction of total r o w-access o verhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
tRRD.
Figure 10: Activating a Specific Row in a Specific Bank
CS#
WE#
CAS#
RAS#
CKE
CLK
A0–A10, A11
ROW
ADDRESS
DON’T CARE
HIGH
BA0, BA1
BANK
ADDRESS
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READs
Figure 11: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< 3
READs READ bursts are initiated with a READ command, as shown in Figure12.
The starting column and bank addresses are provided with the READ command, and
auto precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst. For the
READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following CL after the READ command. Each subsequent data-out element
will be valid by the next positive clock edge. F igur e13 on page 27 shows genera l timing
for each possible CL setting.
Figure 12: READ Command
CLK
T2T1 T3T0
t
COMMAND NOPACTIVE READ or
WRITE
T4
NOP
RCD
DON’T CARE
DON’T CARE
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
x16: A0–A8
x32: A0–A7
A10
BA0,BA1
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ADDRESS
A9, A11
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READs
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go High-Z . A full-page burst will continue until terminated. (At the end of the page , it
will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a subsequent READ com ma nd, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst either follows the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ
command should be issued x cycles before the clock edge at which the last desir ed data
element is valid, where x = CL - 1.
Figure 13: CAS Latency
This is shown in Figure 14 on page 28 for CL = 2 and CL = 3; data element n+ 3 is either
the last of a burst of four or the last desired of a longer burst. The 128Mb SDRAM uses a
pipelined architecture and, therefore, does not require the 2n rule associated with a
prefetch architecture. A READ command can be initiated on any clock cycle following a
previous READ command. Full-speed random read accesses can be performed to the
same bank, as shown in Figure 15 on page 29, or each subsequent READ may be
performed to a different bank.
CLK
DQ
T2T1 T3T0
CL = 3
LZ
DOUT
tOH
t
COMMAND NOPREAD
tAC
NOP
T4
NOP
DON’T CARE
UNDEFINED
CLK
DQ
T2T1T0
CL = 1
LZ
DOUT
tOH
t
COMMAND NOPREAD
tAC
CLK
DQ
T2T1 T3T0
CL = 2
LZ
DOUT
tOH
t
COMMAND NOPREAD
tAC
NOP
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READs
Figure 14: Consecutive READ Bursts
Notes: 1. Each READ command may be to either bank. DQM is LOW. Shown with BL = 4.
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READs
Figure 15: Random READ Accesses
Notes: 1. Each READ command may be to either b ank. DQM is LOW.
2. BL = 1, 2, 4, 8, or full page (if BL > 1, the following READ interrupts the previous).
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burs t may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). Th e WRI TE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, ther e may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQ go High-Z. In this case , at least a single-cycle delay should occur
between the last read data and the WRITE command.
CLK
DQ
T2T1 T4T3 T6T5T0
COMMAND
ADDRESS
READ NOP NOP
BANK,
COL n
DON’T CARE
DOUT
nDOUT
aDOUT
xDOUT
m
READ READ READ NOP
BANK,
COL aBANK,
COL xBANK,
COL m
CLK
DQ DOUT
n
T2T1 T4T3 T5T0
COMMAND
ADDRESS
READ NOP
BANK,
COL n
DOUT
aDOUT
xDOUT
m
READ READ READ NOP
BANK,
COL aBANK,
COL xBANK,
COL m
CLK
DQ DOUT
n
T2T1 T4T3T0
COMMAND
ADDRESS
READ NOP
BANK,
COL n
DOUT
aDOUT
xDOUT
m
READ READ READ
BANK,
COL aBANK,
COL xBANK,
COL m
CL = 1
CL = 2
CL = 3
TRANSITIONING DATA
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READs
Figure 16: READ-to-WRITE
Notes: 1. CL = 3 is used for illustration.
2. The READ command may be to any bank, an d the WRITE command may be to any bank.
3. If a burst of 1 is used, then DQM is not required.
The DQM input is used to avoid I/O contention, as shown in Figure16 and Figure 17.
The DQM signal must be asserted (HIGH) at least 2 clocks prior to the WRITE command
(DQM latency is 2 clocks for output buffers) to suppress data-out from the READ. After
the WRITE command is registered, the DQ will go High-Z (or remain High-Z), regardless
of the state of the DQM signal, provided the DQM was activ e on the clock just prior to
the WRITE command that truncated the READ command. If not, the second WRITE will
be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 17, then the
WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
0 clocks for input buffers) to ensure that the written data is not masked. Figure 16 shows
the case where the clock fre quency allows for bus contention to be avoided witho u t
adding a NOP cycle, and Figure 17 shows the case where the additional NOP is needed.
Figure 17: READ-to-WRITE with Extra Clock Cycle
Notes: 1. CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE com-
mand may be to any bank.
DON’T CARE
READ NOP NOP WRITE
NOP
CLK
T2T1 T4T3T0
DQM
DQ
D
OUT
n
COMMAND
D
IN
b
ADDRESS
BANK,
COL nBANK,
COL b
DS
t
HZ
t
t
CK
TRANSITIONING DATA
DON’T CARE
READ NOP NOPNOP NOP
DQM
CLK
DQ
D
OUT
n
T2T1 T4T3T0
COMMAND
ADDRESS
BANK,
COL n
WRITE
D
IN
b
BANK,
COL b
T5
DS
t
HZ
t
TRANSITIONING DATA
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READs
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE
command to the same bank (provided that auto precharge was not activated), and a full-
page burst may be truncated with a PRECHARGE command to the same bank. The
PRECHAR GE command should be issued x cycles before the clock edge at which the last
desired data element is valid, where x = CL - 1. This is shown in Figure 18 on page 32 for
each possible CL; data element n + 3 is either the last of a burst of four or the last desired
of a longer burst. Following the PRECHARGE command, a subsequent command to the
same bank cannot be issued until tRP is met. Note that part of the row precharge time is
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as desc ribed abov e) provi des the same operation
that would result from the same fixed-length burst with auto precharge. The disadvan-
tage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARG E command is that it can be used to truncate fixed-leng th or full-page bursts .
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READs
Figure 18: READ-to-PRECHARGE
Notes: 1. Assumes tRAS(MIN) has been satisfied prior to the PRECH A R G E co m m and.
2. N + 3 is either the last data element of a BL = 4 or the last desired data element of a longer
burst.
3. DQM is LOW.
Full-page READ bursts can be truncated with the BURST TERMINATE command, and
fixed-length READ bursts may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x = CL - 1. This is shown in Figure19 on page 33 for each possible CL; data
element n + 3 is the last desired data element of a longer burst.
CLK
DQ D
OUT
n
T2T1 T4T3 T6T5T0
COMMAND
ADDRESS
READ NOP NOP NOP NOPNOP
D
OUT
n + 1 D
OUT
n + 2 D
OUT
n + 3
PRECHARGE ACTIVE
tRP
T7
CLK
DQ D
OUT
n
T2T1 T4T3 T6T5T0
COMMAND
ADDRESS
READ NOP NOP NOP NOPNOP
D
OUT
n + 1 D
OUT
n + 2 D
OUT
n + 3
PRECHARGE ACTIVE
tRP
T7
CLK
DQ D
OUT
n
T2T1 T4T3 T6T5T0
COMMAND
ADDRESS
READ NOP NOP NOP NOP
BANK a,
COL n
NOP
D
OUT
n + 1 D
OUT
n + 2 D
OUT
n + 3
PRECHARGE ACTIVE
tRP
T7
BANK a,
ROW
BANK
(a or all)
DON’T CARE
X = 0 cycles
CL = 1
X = 1 cycle
CL = 2
CL = 3
BANK a,
COL
n
BANK a,
ROW
BANK
(a or all)
BANK a,
COL
n
BANK a,
ROW
BANK
(a or all)
X = 2 cycles
TRANSITIONING DATA
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READs
Figure 19: Terminating a READ Burst
Notes: 1. Page remains open after a BURST TERMINATE command.
2. N + 3 is either the last data element of BL = 4 or the last desired data element of a longer
burst.
3. DQM is LOW.
DON’T CARE
CLK
DQ
DOUT
n
T2T1 T4T3 T6T5T0
COMMAND
ADDRESS
READ NOP NOP NOP NOP
BANK,
COL n
NOP
DOUT
n + 1 DOUT
n + 2 DOUT
n + 3
BURST
TERMINATE NOP
T7
CLK
DQ
DOUT
n
T2T1 T4T3 T6T5T0
COMMAND
ADDRESS
READ NOP NOP NOP
BANK,
COL n
NOP
DOUT
n + 1 DOUT
n + 2 DOUT
n + 3
BURST
TERMINATE NOP
CLK
DQ
DOUT
n
T2T1 T4T3 T6T5T0
COMMAND
ADDRESS
READ NOP NOP NOP
BANK,
COL n
NOP
DOUT
n + 1 DOUT
n + 2 DOUT
n + 3
BURST
TERMINATE NOP
X = 0 cycles
CL = 1
X = 1 cycle
CL = 2
CL = 3
X = 2 cycles
TRANSITIONING DATA
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READs
WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure 20.
The starting column and bank addresses are provided with the WRITE command, and
auto prechar ge either is enabled or disabled for that access . I f auto pr echarge is enab led,
the row being accessed is precharged at the completion of the burst. For the WRITE
commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixe d-length burst, assuming no other
commands have been initiated, the DQ will remain High-Z, and any additional input
data will be ignored (see Figure21 on page 35) . A full-page burst will continue until
terminated. (At the end of the page, it will wrap to column 0 and continue.)
Figure 20: WRITE Command
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRI TE burst may be immediately followed by data for a WRITE
command. The new WRITE command can b e issued on any c lock follo wi ng the pr evious
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Fi gur e21 on page 35. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. The 128Mb SDRAM uses a pipe-
lined architecture and, therefore, does not require the 2n rule associated with a prefetch
architec tur e. A WRITE com mand can be initiated on any clock cycle fol lo wing a pr evious
WRITE command. Full-speed random write accesses within a page can be performed to
the same bank, as shown in Figure22 on page 35, or each subsequent WRITE may be
performed to a different bank.
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
DON’T CARE
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ADDRESS
x16: A0–A8
x32: A0–A7
A10
BA0,1
A9, A11
VALID ADDRESS
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READs
Figure 21: WRITE Burst
Notes: 1. BL = 2. DQM is LOW.
Figure 22: WRITE-to-WRITE
Notes: 1. DQM is LOW . Each WRITE command may be to any bank.
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed -length WRITE burst m ay be imme diately fol lowed by a REA D command.
After the READ command is registered, the data inputs will be ignor ed, and writes will
not be executed. An example is shown in Figure 24 on page 36. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a
PRECHARGE command to the same bank (provided that auto pr echarge was not acti-
vated), and a full-page WRITE burst may be truncated with a PRECHARGE command to
the same bank. The PRECHARGE command should be issued tWR after the clock edge at
which the last desired input data element is registered. The auto precharge mode
requires a tWR of at least one clock plus time, regardless of frequency.
In addi tion, when truncating a WRITE burst, the DQM signal must be used to mask
input data for the clock edge prior to, and the clock edge coincident with, the
PRECHARG E command. An example is shown in Figure25 on page 37. Data n + 1 is
either the last of a burst of two or the last desired of a longer burst. Following the
PRECHAR GE command, a subsequent command to the same bank cannot be issued
until tRP is met. The PRECHARGE can be issued coincident with the second clock (see
Figure 25 on page37).
CLK
DQ
D
IN
n
T2T1 T3T0
COMMAND
ADDRESS
NOP NOPWRITE
D
IN
n + 1
NOP
BANK,
COL n
DON’T CARE
TRANSITIONING DATA
DON’T CARE
CLK
DQ
T2T1T0
COMMAND
ADDRESS
NOPWRITE WRITE
BANK,
COL nBANK,
COL b
D
IN
nD
IN
n + 1 D
IN
b
TRANSITIONING DATA
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In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as desc ribed abov e) provi des the same operation
that would result from the same fixed-length burst with auto precharge. The disadvan-
tage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARG E command is that it can be used to truncate fixed-leng th or full-page bursts .
Figure 23: Random WRITE Cycles
Notes: 1. Each WRITE command may be to any bank.
2. DQM is LOW.
3. Example shows BL = 1 or an interrupting BL > 1.
Figure 24: WRITE-to-READ
Notes: 1. The WRITE command may be to any bank, and the READ command may be to any bank.
2. DQM is LOW.
3. CL = 2 for illustration.
4. Data n + 1 is either the last data of BL = 1 or the last desired of a longer burst.
DON’T CARE
CLK
DQ
D
IN
n
T2T1 T3T0
COMMAND
ADDRESS
WRITE
BANK,
COL n
D
IN
aD
IN
xD
IN
m
WRITE WRITE WRITE
BANK,
COL aBANK,
COL xBANK,
COL m
TRANSITIONING DATA
DON’T CARE
CLK
DQ
T2T1 T3T0
COMMAND
ADDRESS
NOPWRITE
BANK,
COL n
DIN
nDIN
n + 1 DOUT
b
READ NOP NOP
BANK,
COL b
NOP
DOUT
b + 1
T4 T5
TRANSITIONING DATA
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Figure 25: WRITE-to-PRECHARGE
Notes: 1. DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE
command. When truncating a WRITE burst, the inpu t data applied coincident with the
BURST TERMINATE command will be ignored. The last data written (provided that
DQM is LOW at that time) will be the input data applied one clock previous to the
BURST TERMINATE command. This is shown in Figure26, where data n is the last
desir ed data element of a longer burst.
Figure 26: Terminating a WRITE Burst
Notes: 1. DQMs are LOW.
DQM
CLK
DQ
T2T1 T4T3T0
COMMAND
ADDRESS
BANK a,
COL n
T5
NOPWRITE PRECHARGE NOPNOP
D
IN
n
D
IN
n
+ 1
ACTIVE
tRP
BANK
(a or all)
tWR
BANK a,
ROW
DQM
DQ
COMMAND
ADDRESS
BANK a,
COL n
NOPWRITE PRECHARGE NOPNOP
D
IN
nD
IN
n + 1
ACTIVE
tRP
DON’T CARE
BANK
(a or all)
tWR
BANK a,
ROW
T6
NOP
NOP
tWR@ tCK 15ns
tWR@ tCK < 15ns
TRANSITIONING DATA
CLK
DQ
T2T1T0
COMMAND
ADDRESS
BANK,
COL n
WRITE BURST
TERMINATE NEXT
COMMAND
D
IN
n
(ADDRESS)
(DATA)
TRANSITIONING DATA DON’T CARE
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Figure 27: PRECHARGE Command
PRECHARGE
The PRECHARGE command (see Figure 27) is used to deactivate the open row in a
particular bank or the open row in all banks. The bank(s) will be available for a subse-
quent row access some specified time (tRP) after the prec harge command is issued.
Input A10 determines whether one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all
banks are to be pr echarged, inputs BA0, BA1 ar e tr eated as “ Don’t Car e.” After a bank has
been pre charged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank.
POWER-DOWN
Power-down occurs if CKE is registered low coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power -down; if power-down occurs when
there is a ro w activ e in any bank, this mode is referred to as active power-down. Entering
power-down deactivates the input and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not remain in the power-down state
longer than the refresh period (64ms) since no refresh operati o ns are pe rformed in this
mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting tCKS). See Figure28 on page 39.
CS#
WE#
CAS#
RAS#
CKE
CLK
A10
DON’T CARE
HIGH
All Banks
Bank Selected
A0-A9
BA0, BA1
BANK
ADDRESS
VALID ADDRESS
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Figure 28: Power-Down
CLOCK SUSPEND
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered low. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
Fo r each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data pr esent on the input pins at the time of a
suspended internal clock edge is ignored; any data pre sent on the DQ pins remai n s
driven; and burst counters are not incremented as long as the clock is suspended. (See
examples in Figure 29 and in Figure 30 on page 40.)
Figure 29: Clock Suspend During WRITE Burst
Notes: 1. For this example, burst length = 4 or greater, and DM is LOW.
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
DON’T CARE
tRAS
tRCD
tRC
All banks idle Input buffers gated off
Exit power-down mode.
()()
()()
()()
tCKS > tCKS
COMMAND
NOP ACTIVE
Enter power-down mode.
NOP
CLK
CKE
()()
()()
DON’T CARE
D
IN
COMMAND
ADDRESS
WRITE
BANK,
COL n
D
IN
n
NOPNOP
CLK
T2T1 T4T3 T5T0
CKE
INTERNAL
CLOCK
NOP
D
IN
n + 1 D
IN
n + 2
TRANSITIONING DATA
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Burst Read/Single Write
The burst read/single write mode is entered by progr a mming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single col umn location (burst of 1), regardless of the programmed burst
length. READ commands access columns according to the programmed burst length
and sequence, just as in the normal mode of operation (M9 = 0).
Figure 30: Clock Suspend During READ Burst
Notes: 1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
CONCURRENT Auto Precharge
An access command (READ or WRITE) to another bank while an access command with
auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM
supports con current auto precharge. Micron SDRAMs support concurrent auto
precharge. Four cases where concurrent auto precharge occurs are defined below.
READ with Auto Precharge
• Interrupted b y a READ (with or without auto precharge): A READ to bank m will inter-
rupt a READ on bank n, CL later. The precharge to bank n will be gin when the READ
to bank m is registered (Figure31 on page 41).
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a READ on bank n when registered. DQM should be used 2 clocks prior to
the WRITE command to prevent bus conten tion. The precharge to bank n will begin
when the WRITE to bank m is registered (Figure 32 on page 41).
DON’T CARE
CLK
DQ
DOUT
n
T2T1 T4T3 T6T5T0
COMMAND
ADDRESS
READ NOP NOP NOP
BANK,
COL n
NOP
DOUT
n + 1 DOUT
n + 2 DOUT
n + 3
CKE
INTERNAL
CLOCK
NOP
TRANSITIONING DATA
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Figure 31: READ With Auto Precharge Interrupted by a READ
Notes: 1. DQM is LOW, BL = 4 or greater, and CL = 3.
Figure 32: READ With Auto Precharge Interrupted by a WRITE
Notes: 1. DQM is HIGH at T2 to prevent D OUT a + 1 from contending with DIN d at T4.
WRITE with Auto Precharge
• Interrupted b y a READ (with or without auto precharge): A READ to bank m will inter-
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after tWR is met, where tWR begins when the READ to
bank m is registered. The last valid WRITE to bank n will be data-in registered 1 clock
prior to the READ to bank m (Figure 33 on page 42).
DON’T CARE
CLK
DQ
D
OUT
a
T2T1 T4T3 T6T5T0
COMMAND
READ - AP
BANK nNOP NOPNOPNOP
D
OUT
a + 1 D
OUT
dD
OUT
d + 1
NOP
T7
BANK n
CL = 3 (BANK m)
BANK m
ADDRESS
Idle
NOP
BANK n,
COL aBANK m,
COL d
READ - AP
BANK m
Internal
States
t
Page Active READ with Burst of 4 Interrupt Burst, Precharge
Page Active READ with Burst of 4 Precharge
RP - BANK ntRP - BANK m
CL = 3 (BANK n)
TRANSITIONING DATA
CLK
DQ
D
OUT
a
T2T1 T4T3 T6T5T0
COMMAND
NOPNOPNOPNOP
D
IN
dD
IN
d + 2 D
IN
d + 3
NOP
T7
BANK n
BANK m
ADDRESS
Idle
NOP
DQM
BANK n,
COL aBANK m,
COL d
WRITE - AP
BANK m
Internal
States
t
Page
Active READ with Burst of 4 Interrupt Burst, Precharge
Page Active WRITE with Burst of 4 Write-Back
RP -
BANK
ntWR -
BANK
m
CAS Latency = 3 (BANK n)
READ - AP
BANK n
1
DON’T CARE
TRANSITIONING DATA
D
IN
d + 1
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• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after tWR is met, where tWR begins when the WRITE to bank m is registered. The last
valid data WRITE to bank n will be data registered 1 clock prior to a WRITE to bank m
(Figure 34).
Figure 33: WRITE With Auto Precharge Interrupted by a READ
Notes: 1. DQM is LOW.
Figure 34: WRITE With Auto Precharge Interrupted by a WRITE
Notes: 1. DQM is LOW.
DON’T CARE
CLK
DQ
T2T1 T4T3 T6T5T0
COMMAND WRITE - AP
BANK nNOPNOPNOPNOP
D
IN
a + 1
D
IN
a
NOP NOP
T7
BANK n
BANK m
ADDRESS
BANK n,
COL aBANK m,
COL d
READ - AP
BANK m
Internal
States t
Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
Page Active READ with Burst of 4
ttRP - BANK m
D
OUT
dD
OUT
d + 1
CL = 3 (BANK m)
RP - BANK n
WR - BANK n
TRANSITIONING DATA
DON’T CARE
CLK
DQ
T2T1 T4T3 T6T5T0
COMMAND WRITE - AP
BANK nNOPNOPNOPNOP
DIN
d + 1
DIN
d
DIN
a + 1 DIN
a + 2
DIN
aDIN
d + 2 DIN
d + 3
NOP
T7
BANK n
BANK m
ADDRESS
NOP
BANK n,
COL aBANK m,
COL d
WRITE - AP
BANK m
Internal
States
t
Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
Page Active WRITE with Burst of 4 Write-Back
WR - BANK ntRP - BANK ntWR - BANK m
TRANSITIONING DATA
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Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn - 1 was the state of CKE at the previous
clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COM-
MANDn.
4. All states and se quences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for
clock edge n + 1 (provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the devi ce in the all banks idle state after tXSR is
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring
during the tXSR period. A minimum of two NOP commands must be provided during tXSR
period.
7. After exiting clock suspend at clock edge n, the de vice will re sume op eration an d recogn ize
the next command at clock edge n + 1.
Table 9: Truth Table – CKE
Notes 1–4 apply to entire table
CKEn - 1 CKEnCurrent State ComandnAction Notes
L L Power-down X Maintain power -down
Self refresh X Maintain self refresh
Clock suspend X Maintain clock suspend
L H Power-down COMMAND INHIBIT or NOP Exit power-down 5
Self refresh COMMAND INHIBIT or NOP Exit self refresh 6
Clock suspend X Exit clock suspend 7
H L All banks idle COMMAND INHIBIT or NOP Power-down entry
All banks idle AUTO REFRESH self refresh entry
Reading or writing WRITE or NOP Clock suspend entry
H H See Table 10 on page 44
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Notes: 1. This table applies when CKEn - 1 was HIGH and CKEnis HIGH (see Table 9 on page 43) and
after tXSR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted; that is, the current state is for a specific
bank and the commands shown are those allowed to be issued to that bank when in that
state. Exceptions are covered in the notes below.
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. COM-
MAND INHIBIT or NOP commands or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determi ned by its current st ate and Table 10 and according to Table 11 on
page 46.
Table 10: Truth Table – Current State Bank n, Command to Bank n
Notes 1–6 apply to entire table; notes appear below table
Current
State CS# RAS# CAS# WE# Command (Action) Notes
Any HXXX
COMMAND INHIBIT (NOP/Continue previous operation)
LHHH
NO OPERATION (NOP/Continu e previous operation)
Idle L L H H ACTIVE (Select and activate row)
LLLH
AUTO REFRESH 7
LLLL
LOAD MODE REGISTER 7
LLHL
PRECHARGE 11
Row activeLHLH
READ (Select column and start READ burst) 10
LHLL
WRITE (Select column and start WRITE burst) 10
LLHL
PRECHARGE (Deactivate row in bank or banks) 8
Read (auto
precharge
disabled)
LHLH
READ (Select column and start new READ burst) 10
LHLL
WRITE (Select column and start WRITE burst) 10
LLHL
PRECHARGE (Truncate READ burst, start PRECHARGE) 8
LHHL
BURST TER MINATE 9
Write (auto
precharge
disabled)
LHLH
READ (Select column and start READ burst) 10
LHLL
WRITE (Select column and start new WRITE burst) 10
LLHL
PRECHARGE (Truncate WRITE burst, start PRECHARGE) 8
LHHL
BURST TER MINATE 9
Idle: The bank has been precharged, and tRP ha s been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not
yet terminated or been terminate d.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
Precharging: Starts with registration of a PRECHARGE command and ends when
tRP is met. After tRP is met, the bank will be in the idle state.
Row activating: St arts with registration of an ACTIVE command and ends when tRCD
is met. After tRCD is met, the bank will be in the row active state.
Read w/auto
precharge enabled: Starts with registration of a READ command with auto precharge
enabled and ends when tRP has been met. AFter tRP is met, the bank
will be in the idle state.
Write w/auto
precharge enabled: Starts with registration of a WRITE command with auto precharge
enabled and ends when tRP has been met. After tRP is met, the bank
will be in the idle state.
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5. The following states must not be interrupted by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these states.
Refreshing starts with registration of an AUTO REFRESH command and ends when tRFC is
met. After tRFC is met, the SDRAM will be in the all banks idle state.
6. All states and se quences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid
state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regard-
less of bank.
10. READs or WRITEs listed in the Command (Action) c olumn include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
Accessing mode
register: Starts with registration of a LOAD MODE REGISTER command and
ends when tMRD has been met. After tMRD is met, the SDRAM will
be in the all banks idle state.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends
when tRP is met. After tRP is met, all banks will be in the idle state.
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Notes: 1. This table applies when CKEn - 1 was HIGH and CKEnis HIGH (see Table 9 on page 43) and
after tXSR has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted; that is, the current state
is for bank n and the commands shown are those allowed to be is sued to ba nk m (assuming
that bank m is in such a state that the given command is allowable). Exceptions are covered
in the notes below.
3. Current state definitions:
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued
when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
Table 11: Truth Table – CURRENT STATE BANK n, COMMAND tO BANK m
Notes 1–6 apply to entire table; notes appear below and on next page
Current State CS# RAS# CAS# WE# Command (Action) Notes
Any HXXX
COMMAND INHIBIT (NOP/continue previous operation)
LHHH
NO OPERATION (NOP/continue previous operation)
Idle XXXX
Any command otherwise allowed to bank m
Row
Activating,
active, or
precharging
LLHH
ACTIVE (Select and activate row)
LHLH
READ (Select column and start READ burst) 7
LHLL
WRITE (Select column and start WRITE burst) 7
LLHL
PRECHARGE
Read
(auto
precharge
disabled)
LLHH
ACTIVE (Select and activate row)
LHLH
READ (Select column and start new READ burst ) 7, 10
LHLL
WRITE (Select column and start WRITE burst) 7, 11
LLHL
PRECHARGE 9
Write
(auto
precharge
disabled)
LLHH
ACTIVE (Select and activate row)
LHLH
READ (Select column and start READ burst) 7, 12
LHLL
WRITE (Select column and start new WRITE burst) 7, 13
LLHL
PRECHARGE 9
Read
(with auto
precharge)
LLHH
ACTIVE (Select and activate row)
LHLH
READ (Select column and start new READ burst ) 7, 8, 14
LHLL
WRITE (Select column and start WRITE burst) 7, 8, 15
LLHL
PRECHARGE 9
Write
(with auto
precharge)
LLHH
ACTIVE (Select and activate row)
LHLH
READ (Select column and start READ burst) 7, 8, 16
LHLL
WRITE (Select column and start new WRITE burst) 7, 8, 17
LLHL
PRECHARGE 9
Idle: The bank has been precharged, and tRP ha s been met.
Row active: A row in the bank has been activate d, and tRCD has been met. No
data bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and
has not yet te r minated or bee n te r m i n at e d.
Write: A WRITE burst has been initiated, with auto precharge disabled, and
has not yet te r minated or bee n te r m i n at e d.
Read w/auto
precharge enabled: Starts with registration of a READ command with auto precharge
enabled and ends when tRP has been met. After tRP is met, the bank
will be in the idle state.
Write w/auto
precharge enabled: Starts with registration of a WRITE command with auto precharge
enabled and ends when tRP has been met. After tRP is met, the bank
will be in the idle state.
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READs
6. All states and se quences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) col umn incl ud e READs or
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
burst has been interrupted by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the READ on bank n, CL later (see Figure 14 on
page 28).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
charge), th e WR ITE to bank m will interrupt th e READ on bank n when registered (see
Figure 16 and Figure 17 on page 30). DQM should be used one clock prior to the WRITE
command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the WRITE on bank n when registered (see
Figure 24 on page 36) with the data-out appearing CL later. The last valid WRITE to ba nk n
will be data-in registered 1 clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
charge), th e WR IT E to bank will interrupt the WRITE on bank n when registered (see
Figure 22 on page 35). The last valid WRITE to bank n will be data-in registered 1 clock prior
to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n
will begin when the READ to bank m is registered (see Figure 31 on page 41).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be
used 2 clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to
bank n will begi n when the WRITE to bank m is registere d (see Figure 32 on page 41).
16. For a WRITE with auto precharge inter rupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CL later. The PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in
registered 1 clock prior to the READ to bank m (see Figure 33 on page 42).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto prech arge),
the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE
to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is reg-
istered. The last valid WRITE to bank n will be data registered 1 clock to the WRITE to bank
m (see Figure 34 on page 42).
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Electrical Specifications
Electrical Specifications
Stresses greater than those listed in Table 12 may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi tions for extended periods may
affect reli ability.
Temperature and Thermal Impedance
I t is imperative that the Mobile SDRAM device’s temperature specifications, shown in
Table 13 on page 49, be maintained to ensure the junction temperature is in the pr oper
operating range to meet data sheet specifications. An important step in maintaining the
proper junction temperature is using the device’s thermal impedances correctly. The
thermal im pe d ance s are listed in Ta bl e 14 on page 49 for the applicable die revision and
packages being made availa ble. These thermal impedance values vary according to the
density, package, and particular design used for each device.
Incorr ectly using thermal impedances can produce significant errors. Read Micron tech-
nical note TN-00-08, “Thermal Applications” prior to using the thermal impedances
listed in Table 14 on page 49. To ensure the compatibility of current and future designs ,
contact Micron Applications Engineering to confirm thermal impedance values.
The SDRAM device’s safe junction temperature range can be maintained when the TC
specification is not exceeded. In applications where the device’s ambient temperature is
too high, use of forced air and/or heat sinks may be required to satisfy the case tempera-
ture specifications.
Table 12: Absolute Maximum Ratings
Parameter Min Max Rating
Voltage on VDD/VDDQ supply relative to VSS (LC devices) –1 +4.6 V
Relative to VSS (V devices) 0.5 +3.6 V
Voltage on inputs, NC or I/O pins relative to VSS (LC devices) –1 +4.6 V
Relative to VSS (V devices) –0.5 +3.6 V
Operating temperature
TA (commercial)
TA (industrial)
TA (extended)
0
–40
–25
+70
+85
+75
°C
Storage temperature (plastic) –55 +150 °C
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Electrical Specifications
Notes: 1. MAX operating case temperature, TC, is measured in the center of the package on the top
side of the device, as shown in Figures 35, 36, and 37 on page 50.
2. Device functionality is not guaranteed if the device exceeds maximum TC during operation.
3. All temperature specifications must be satisfied.
4. The case temperature should be measured by gluing a thermocouple to the top center of
the component. This should be done with a 1mm bead of conductive epoxy, as defi ned by
the JEDEC EIA/JESD51 standards. Care should be taken to ensure the thermocouple bead is
touching the case.
5. Operating ambient temperature surrounding the package.
Notes: 1. For designs expected to last beyond the die revision listed, contact Micron Applications
Engineering to confirm thermal impedance values.
2. Thermal resistance data is sampled from multiple lots, and the values should be viewed as
typical.
3. These are estimates; actual results may var y.
4. Thermal impedance values were obtained using the 128Mb SDRAM 54-pin TSOP.
Table 13: Temperature Limits
Parameter Symbol Min Max Units Notes
Operating case temperature:
Commercial
Industrial
TC0
–40 80
90
°C 1, 2, 3, 4
Junction temperature:
Commercial
Industrial
TJ0
–40 85
95
°C 3
Ambient temperature:
Commercial
Industrial
TA0
–40 70
85
°C 3, 5
Peak reflow temperature TPEAK –260°C
Table 14: Thermal Impedance Simulated Values
Die Revision Package Substrate
θ JA (°C/W)
Airflow =
0m/s
θ JA (°C/W)
Airflow =
1m/s
θ JA (°C/W)
Airflow =
2m/s θ JB (°C/W) θ JC (°C/W)
G54-pin
TSOP42-layer 86.2 67.8 62 46.9 11.3
4-layer 58.9 50.7 47.6 41.5
54-ball
VFBGA 2-layer 72.1 57.3 50.6 36.0 4.1
4-layer 54.5 46.6 42.8 35.5
90-ball
VFBGA 2-layer 64.6 50.8 45.3 37.5 1.8
4-layer 48.2 41.1 38.1 32.1
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Electrical Specifications
Figure 35: Example Temperature Test Point Location, 54-Pin TSOP: Top View
Figure 36: Example Temperature Test Point Location, 54-Ball VFBGA: Top View
Figure 37: Example Temperature Test Point Location, 90-Ball VFBGA: Top View
22.22mm
11.11mm
Test point
10.16mm
5.08mm
8.00mm
4.00mm
Test point
4.00mm
8.00mm
Test point
6.50mm
13.00mm
4.00mm
8.00mm
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Electrical Specifications
Table 15: DC Electrical Characteristics and Operating Conditions (LC Version)
Notes 1, 6 apply to entire table; notes appear on page 56; VDD = +3.3V ±0.3V, VDDQ = +3.3V ±0.3V
Parameter/Condition Symbol Min Max Units Notes
Supply voltage VDD 33.6V
I/O supply voltage VDDQ3 3.6 V
Input high voltage: Logic 1; All inputs VIH 2VDD + 0.3 V 22
Input low voltage: Logic 0; All inputs VIL –0.3 0.8 V 22
Data output high voltage: Logic 1; All inputs VOH 2.4 – V
Data output low voltage: Logic 0; All inputs VOL –0.4V
Input leakage current:
Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) II–5 5 µA
Output leakage current: DQ are disabled; 0V ≤ VOUT ≤ VDDQIOZ –5 5 µA
Table 16: DC Electrical Characteristics and Operating Conditions (V Version)
Notes 1, 6 apply to entire table; notes appear on page 56; VDD = 2.5 ±0.2V, VDDQ = +2.5V ±0.2V or +1.8V
±0.15V
Parameter/Condition Symbol Min Max Units Notes
Supply voltage VDD 2.3 2.7 V
I/O supply voltage VDDQ1.65 2.7 V
Input high voltage: Logic 1; All inputs VIH (DQ) 1.25 VDDQ + 0.3 V 22
VIH (non-DQ) 1.25 VDD + 0.3
Input low voltage: Logic 0; All inputs VIL –0.3 +0.55 V 22
Data output high voltage: Logic 1; All inputs VOH VDDQ - 0.2 – V
Data output low voltage: Logic 0; All inputs VOL –0.2V
Input leakage current:
Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) II–5 5 µA
Output leakage current: DQ are disabled; 0V ≤ VOUT ≤ VDDQIOZ –5 5 µA
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Electrical Specifications
Table 17: Electrical Characteristics and Recommended AC Operating Conditions
Notes 5, 6, 7, 8, 9, 11 apply to entire table; notes appear on page 56
Ac Characteristics
Symbol
-75M -8 -10
Units NotesParameter Min Max Min Max Min Max
Access time from CLK (positive
edge) CL = 3 tAC (3) – 5.4 – 7 – 7 ns
CL = 2 tAC (2)–6–8– 8ns
CL = 1 tAC (1) – na – 19 – 22 ns
Address hold time tAH0.8–1–1–ns
Address setup time tAS 1.5 – 2.5 – 2.5 – ns
CLK high-level width tCH3–3–3–ns
CLK low-level width tCL2.5–3–3–ns
Clock cycle time CL = 3 tCK (3) 7.5 – 8 – 10 – ns 23
CL = 2 tCK (2) 9.6 – 9.6 – 12 – ns 23
CL = 1 tCK (1) n/a – 20 – 25 – ns 23
CKE hold time tCKH1–1–1–ns
CKE setup time tCKS 2.5 – 2.5 – 2.5 – ns
CS#, RAS#, CAS#, WE#, DQM hold time tCMH0.8–1–1–ns
CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 – 2.5 – 2.5 – ns
Data-in hold time tDH0.8–1–1–ns
Data-in setup time tDS 1.5 – 2.5 – 2.5 – ns
Data-out High-Z time CL = 3 tHZ (3) – 5.4 – 7 – 7 ns 10
CL = 2 tHZ (2)– 6–8–8ns10
CL = 1 tHZ (1) – na – 19 – 22 ns 10
Data-out Low-Z time tLZ1–1–1–ns
Data-out hold time (load) tOH 2.5 – 2.5 – 2.5 – ns 27
Data-out hold time (no load) tOHN1.8 – 1.8 – 1.8 – ns
ACTIVE-to-PRECHARGE command tRAS 44 120,000 48 120,000 50 120,000 ns
ACTIVE-to-ACTIVE command period tRC 66 – 80 – 100 – ns
ACTIVE-to-READ or WRITE delay tRCD19–20–20–ns
Refresh period (4,096 rows) tREF – 64 – 64 – 64 ms
AUTO REFRESH command period tRFC 66 – 80 – 100 – ns
PRECHARGE command period tRP 19 – 20 – 20 – ns
ACTIVE bank a to ACTIVE bank b command tRRD2–2–2–
tCK
Transition time tT 0.3 1.2 0.5 1.2 0.5 1.2 ns 7
WRITE recovery time
Auto precharge mode (a)
Manual precharge mode (m)
tWR (a) 1 CLK
+7.5ns –1 CLK
+7ns –1 CLK
+5ns ––24
tWR (m)15–15–15–ns25
Exit SELF REFRESH to ACTIVE command tXSR 67 – 80 – 100 – ns 20
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Electrical Specifications
Table 18: AC Functional Characteristics
Notes 5, 6, 7, 8, 9, 11 apply to entire table; notes appear on page 56
Parameter Symbol -75M -8 -10 Units Notes
READ/WRITE command to READ/WRITE command tCCD111
tCK 17
CKE to clock disable or power-down entry mode tCKED111
tCK 14
CKE to clock enable or power-down exit setup mode tPED 1 1 1 tCK 14
DQM to input data delay tDQD000
tCK 17
DQM to data mask during WRITEs tDQM000
tCK 17
DQM to data High-Z during READs tDQZ222
tCK 17
WRITE command to input data delay tDWD000
tCK 17
Data-in to ACTIVE command tDAL 5 5 5 tCK 15, 21
Data-in to PRECHARGE command tDPL222
tCK 16, 21
Last data-in to burst STOP command tBDL111
tCK 17
Last data-in to new READ/WRITE command tCDL111
tCK 17
Last data-in to PRECHARGE command tRDL222
tCK 16, 21
LOAD MODE REGISTER command to ACTIVE or REFRESH
command
tMRD222
tCK 26
Data-out to High-Z from PRECHARGE command CL = 3 tROH(3)333
tCK 17
CL = 2 tROH(2)222
tCK 17
CL = 1 tROH(1) 1 1 tCK 17
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Electrical Specifications
Table 19: IDD Specifications and Conditions (x16)
Notes 1, 3, 6, 11, 13, 31 apply to entire table; notes appear on page 56; VDD = VDDQ = +3.3V ±0.3V or VDD =
VDDQ = 2.5V ±0.2V or VDD = +2.5V ±0.2V, VDDQ = +1.8V ±0.15V
Parameter/Condition Symbol
Max
Units Notes-75M -8 -10
Operating current: Active mode; Burst = 2; READ or WRITE;
tRC = tRC (MIN) IDD1 130 130 10 0 mA 18, 19
Standby current: Power-down mode; All banks idle;
CKE = LOW IDD2 450 450 450 µA 12, 33
Standby current: Active mode; CKE = HIGH; CS# = HIGH; All
banks active after tRCD met; No accesses in progress IDD3 40 40 35 mA 19
Operating current: Burst mode; Page burst; READ or WRITE;
All banks active IDD4 115 100 95 mA 18, 19
Auto refresh current: CKE = HIGH;
CS# = HIGH
tRFC = tRFC (MIN) IDD5 225 210 170 mA 12, 18,
19, 32,
33
tRFC = 15.625µs IDD6 333mA
Table 20: IDD7 Self Refresh Current Options (x16)
Note 4 applies to entire table; note appears on page 56; VDD = VDDQ = +3.3V ±0.3V or VDD = VDDQ = 2.5V
±0.2V or VDD = +2.5V ±0.2V, VDDQ = +1.8V ±0.15V
Temperature-Compensated Self Refresh (TCSR)
Parameter/Condition Max
Temperature -75M/-8/-10 Units
Self refresh current: CKE < 0.2V (E4 = 1, E3 = 1) 85ºC 800 µA
Self refresh current: CKE < 0.2V (E4 = 0, E3 = 0) 70ºC 500 µA
Self refresh current: CKE < 0.2V (E4 = 0, E3 = 1) 45ºC 350 µA
Self refresh current: CKE < 0.2V (E4 = 1, E3 = 0) 15ºC 300 µA
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Electrical Specifications
Table 21: IDD Specifications And Conditions (x32)
Notes 1, 3, 6, 11, 13, 31 apply to entire table; notes appear on page 56; VDD = VDDQ = +3.3V ±0.3V or VDD =
VDDQ = 2.5V ±0.2V or VDD = +2.5V ±0.2V, VDDQ = +1.8V ±0.15V
Parameter/Condition Symbol
Max
Units Notes-75M -8 -10
Operating current: Active mode; Burst = 2;
READ or WRITE; tRC = tRC (MIN) IDD1 150 150 120 mA 18, 19
Standby current: Power-down mode; All banks idle; CKE = LOW IDD2 450 450 450 µA 12, 33
Standby current: Active mode; CKE = HIGH; CS# = HIGH; All
banks active after tRCD met; No accesses in progress IDD3 45 45 40 mA 19
Operating current: Burst mode; Page burst;
READ or WRITE; All banks active IDD4 130 115 110 mA 18, 19
Auto refresh current: CKE = HIGH;
CS# = HIGH
tRFC = tRFC (MIN) IDD5 235 220 180 mA 12, 18,
19, 32,
33
tRFC = 15.625µs IDD6 333mA
Table 22: IDD7 Self Refresh Current Options (x32)
Note 4 applies to entire table; notes appear on page 56; VDD = VDDQ = +3.3V ±0.3V or VDD = VDDQ = 2.5V
±0.2V or VDD = +2.5V ±0.2V, VDDQ = +1.8V ±0.15V
Temperature-Compensated Self Refresh (TCSR)
Parameter/Condition Max
Temperature -75M/-8/-10 Units
Self refresh current: CKE < 0.2V (E4 = 1, E3 = 1) 85ºC 1000 µA
Self refresh current: CKE < 0.2V (E4 = 0, E3 = 0) 70ºC 550 µA
Self refresh current: CKE < 0.2V (E4 = 0, E3 = 1) 45ºC 400 µA
Self refresh current: CKE < 0.2V (E4 = 1, E3 = 0) 15ºC 350 µA
Table 23: Capacitance (FBGA Pacakge)
Note 2 applies to entire table; notes appear on page 56
Parameter Symbol Min Max Units Notes
Input capacitance: CLK CI1 1.5 3.5 pF 28
Input capacitance: All other input-only pin s CI2 1.5 3.8 pF 29
Input/Output capacitance: DQ CIO 3.0 6.0 pF 30
Table 24: Capacitance (TSOP Pacakge)
Note 2 applies to entire table; notes appear on page 56
Parameter Symbol Min Max Units Notes
Input capacitance: CLK CI1 2.5 3.5 pF 28
Input capacitance: All other input-only pin s CI2 2.5 3.8 pF 29
Input/Output capacitance: DQ CIO 4.0 6.0 pF 30
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Notes
Notes 1. All voltages are referenced to Vss.
2. This parameter is sampled. VDD, VDDQ = +3.3V ; TA = 25°C; pin under test biased at
1.4V, f = 1 MHz.
3. IDD is dependent on output loading and cy cle rates. Specified value s are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full operational temperature range is ensured (TA = commercial,
IT, or XT).
6. An initial paus e of 100µs is required after power-up, followed by two AUTO REFRESH
commands, before prope r devi ce operation is ensured. (VDD and VDDQ must be pow-
ered up simultaneously. VSS and VSSQ must be at sam e po te nti a l.) The two AU TO
REFRESH command wake-ups should be repeated any time the tREF re fresh require-
ment is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
sit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured at 1.5V (for LC devices) or at 1.25V (V devices) with equivalent
load:
10. tHZ defines the time at which the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data elemen t will meet tOH befor e going
High-Z.
11. A C timing and IDD tests use established val ues for VIL and VIH, with timing r eferenced
to VIH/2 crossover point. If the input transition time is longer than 1ns, then the tim-
ing is referenced at VIL(MAX) and V IH(MIN) and no longer at the VIH/2 crossover point.
Established tester values follow: VIL = 0V, VIH = 3.0V for LC devices and VIH = 2.3V for V
devices.
12. Other input signals ar e allo wed to transition no mor e than once every 2 clocks and are
otherwise at valid VIH or VIL level s.
13. IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) sp ec ified as a reference only at minimum
cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a referen ce on ly a t
minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and ar e not dependent on any
timing parameter.
18. The IDD current will increase or decrease proportionally according to the amount of
frequency alteration for the test condition.
19. Addre ss transitions average one transition every 2 clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 125MHz for -8 and tCK = 100MHz for -10.
Q30pF
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Notes
22. VIH overshoot: VIH (MA X) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one-thir d of the cycle rate . VIL undershoot: VIL (MIN) = –2V for
a pulse width ≤ 3ns and cannot be greater than one-thir d of the cy cle rate.
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be
used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (tRP) begins at 5.4ns for -8
after the first clock delay after the last WRITE is executed.
25. M anual precharge mode only.
26. JEDEC and PC100 specify 3 clocks.
27. Parameter guaranteed by design.
28. PC100 specifies a maximum of 4pF.
29. PC100 specifies a maximum of 5pF.
30. PC100 specifies a maximum of 6.5pF.
31. Fo r -75M, CL = 3 and tCK = 7.5ns; for -8, CL = 3 and tCK = 8ns; for -10, CL = 3 and
tCK = 10ns.
32. CKE is HIGH during r e fresh command period tRFC (MIN) else CKE is LOW. The IDD6
limit is actually a nomina l value and does not result in a fail value.
33. Specified with I/Os in steady state condition.
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Timing Diagrams
Timing Diagrams
Figure 38: Initialize and Load Mode Register
Notes: 1. The two AUTO REFRESH commands at T9 and T19 may be applied either be fore LOAD
MODE REGISTER (LMR) command.
2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH
command, ACT = ACTIVE command, RA = row address, and BA = bank address.
3. The LOAD MODE REGISTER both for mode register and for extended mode register, and
two AUTO REFRESH command s can be in any order. However, all must occur prior to an
ACTIVE command.
4. Optional REFRESH command.
5. Although not required, to prevent bus contention, it is suggested to keep DQM HIGH dur-
ing the initialization sequence. See Table 17 on page 52.
CLK
t
CK
T0 T1 T3 T5 T7 T9 T19 T29
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
CKE
BA0, BA1
Load Extended
Mode Register Load Mode
Register
t
CKS
Power-up:
V
DD
and
CLK stable
T = 100µs
t
CKH
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
DQML, DQMU
5
()()
()()
()()
()()
DQ
High-Z
A0–A9, A11
RA
A10
RA
ALL BANKS
LMR
3
NOP PRE
LMR
3
AR
AR
4
ACT
t
CMS
t
CMH
BA0 = L,
BA1 = H
tAS tAH
t
AS
t
AH
BA0 = L,
BA1 = L
()()
()()
CODE CODE
tAS tAH
CODE CODE
()()
()()
PRE
ALL BANKS
t
AS
tAH
()()
()()
DON’T CARE
BA
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()()()()()()()()()
t
RP
t
MRD
t
MRD
t
RP
t
RFC
t
RFC
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
COMMAND
1,2
()()
()()
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Timing Diagrams
Figure 39: Power-down Mode
Notes: 1. Violating refresh requirements during power-down may result in a loss of data.
See Table 17 on page 52.
tCH
tCL
tCK
Two clock cycles
CKE
1
CLK
DQ
All banks idle, enter
power-down mode
Precharge all
active banks
Input buffers gated off while in
power-down mode
Exit power-down mode
()()
DON’T CARE
tCKS tCKS
COMMAND
tCMH
tCMS
PRECHARGE NOP NOP ACTIVENOP
()()
()()
All banks idle
BA0, BA1
BANK
BANK(S)
()()
()()
High-Z
tAH
tAS
tCKH
tCKS
DQML, DQMU
()()
()()
()()
()()
A0–A9, A11
ROW
()()
()()
ALL BANKS
SINGLE BANK
A10
ROW
()()
()()
T0 T1 T2 Tn + 1 Tn + 2
()()
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Timing Diagrams
Figure 40: Clock Suspend Mode
Notes: 1. For this example, BL = 2, CL = 3, and auto precharge is disabled.
2. x16: A9 and A11 = “Don’t Care.”
x32: A8, A9 and A11 = “Don’t Care.”
See Table 17 on page 52.
tCH
tCL
tAC
tLZ
DQMU, DQML
CLK
A0-A9, A11
2
DQ
BA0, BA1
A10
tOH
DOUT m
tAH
tAS
tAH
tAS
tAH
tAS
BANK
tDH
DIN e
tAC tHZ
DOUT m + 1
COMMAND
1
tCMH
tCMS
NOPNOP NOP NOPNOPREAD WRITE
CKE
tCKS tCKH
BANK
COLUMN m
tDS
DIN e + 1
NOP
tCKH
tCKS
tCMH
tCMS
2
COLUMN e
2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK
DON’T CARE
UNDEFINED
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Timing Diagrams
Figure 41: Auto Refresh Mode
Notes: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not
required. See Table 17 on page 52.
2. tRFC must not be interrupted by any executable command; COMM AND INHIBIT or NOP
commands must be applied on each po sitive clock edge du ring tRFC.
()()
()()
()()
()()
()()
()()
()()
()()
ALL BANKS
()()
()()
()()
()()()()
()()
()()
()()
()()
()()
tCH
tCL
tCK
CKE
CLK
DQ
tRFC1, 2
tRP
COMMAND
tCMH
tCMS
NOPNOP
BANK
ACTIVE
AUTO
REFRESH NOPNOPPRECHARGE
Precharge all
active banks
AUTO
REFRESH
tRFC1, 2
High-Z
BA0, BA1 BANK(S) ()()
()()
()()
tAH
tAS
tCKH
tCKS
NOP
()()
()()
()()
DQMU, DQML
A0–A9, A11 ROW
()()
()()
SINGLE BANK
A10 ROW
()()
T0 T1 T2 Tn + 1 To + 1
DON’T CARE
()()
()()
()()
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128Mb: x16, x32 Mobile SDRAM
Timing Diagrams
Figure 42: Self Refresh Mode
Notes: 1. No maximum time limit for self refresh. tRAS (MAX) only applies to non-self refresh mode.
2. tXSR requires a minimum of 2 clocks regardless of frequency or timing.
3. As a general rule, any time self refresh is exited, the DRAM may not reenter the self refresh
mode until all rows have been refreshed via the AUTO REFRESH command at the distrib-
uted refresh rate, (tREF/number of rows), or faster. However, the following exception is
allowed. Self refresh mode may be reentered any time after exiting if the followi ng condi-
tions are all met:
3a. The DRAM has been in the self refresh mode for a minimum of 64ms prior to exiting.
3b. tXSR has not been violated.
3c. At least two AUTO REFRESH commands are performed during each 15.625µs interval
while the DRAM remains out of the self refresh mode. See Table 17 on page 52.
DON’T CARE
tCH
tCL
tCK
tRP
CKE
CLK
DQ
Enter self refresh mode
Precharge all
active banks
tXSR
2
CLK stable prior to exiting
self refresh mode
Exit self refresh mode
(Restart refresh time base)
()()
()()
()()()()
()()
()()
COMMAND
tCMH
tCMS
AUTO
REFRESH
PRECHARGE NOP NOP
()()
()()
()()
()()
BA0, BA1 BANK(S)
High-Z
tCKS
AH
AS
AUTO
REFRESH
> tRAS
1
()()
()()
tCKH
tCKS
DQMU, DQML
()()
()()
tt
A0–A9, A11
()()
()()
ALL BANKS
SINGLE BANK
A10
()()
()()
()()
()()
()()
()()
()()
()()
()()
()()
T0 T1 T2 Tn + 1 To + 1 To + 2
()()
()()
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128Mb: x16, x32 Mobile SDRAM
Timing Diagrams
Figure 43: READ – Without Auto Precharge
Notes: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. x16: A9 and A11 = “Don’t Care.”
x32: A8, A9, and A11 = “Don’t Care.”
See Table 17 on page 52.
ALL BANKS
tCH
tCL
tAC
tLZ
tRP
tRAS
tRCD CAS Latency
tRC
tOH
D
OUT
m
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
ROW
BANK BANK(S) BANK
ROW
ROW
BANK
tHZ
tOH
D
OUT
m+3
tAC tOH
tAC tOH
tAC
D
OUT
m+2D
OUT
m+1
tCMH
tCMS
PRECHARGE
NOPNOP NOPACTIVE NOP READ NOP
ACTIVE
DISABLE AUTO PRECHARGE
SINGLE BANKS
DON’T CARE
UNDEFINED
COLUMN m
2
tCKH
tCKS
T0 T1 T2 T3 T4 T5 T6 T7 T8
DQMU, DQML
CKE
CLK
A0–A9, A11
DQ
BA0, BA1
A10
COMMAND
tCK
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Timing Diagrams
Figure 44: Read – With Auto Precharge
Notes: 1. For this example, BL = 4 and CL = 2.
2. x16: A9 and A11 = “Don’t Care.”
x32: A8, A9, and A11 = “Don’t Care.”
See Table 17 on page 52.
ENABLE AUTO PRECHARGE
tCH
tCL
tAC
tLZ
tRP
tRAS
tRCD CAS Latency
tRC
DQMU, DQML
CKE
CLK
A0–A9, A11
DQ
BA0, BA1
A10
tOH
DOUT m
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
ROW
BANK BANK
ROW
ROW
BANK
DON’T CARE
UNDEFINED
tHZ
tOH
DOUT m + 3
tAC tOH
tAC tOH
tAC
DOUT m + 2DOUT m + 1
COMMAND
tCMH
tCMS
NOPNOP NOPACTIVE NOP READ NOP ACTIVENOP
tCKH
tCKS
COLUMN m2
T0 T1 T2 T4T3 T5 T6 T7 T8
tCK
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Timing Diagrams
Figure 45: Single Read – Without Auto Precharge
Notes: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. x16: A9 and A11 = “Don’t Care.”
x32: A8, A9, and A11 = “Don’t Care.”
3. PRECHARGE command not allowed or tRAS would be violated.
See Table 17 on page 52.
ALL BANKS
tCH
tCL
tAC
tLZ
tRP
tRAS
tRCD CAS Latency
tRC
tOH
D
OUT
m
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
ROW
BANK
BANK(S) BANK
ROW
ROW
BANK
tHZ
tCMH
tCMS
NOPNOPNOP
PRECHARGE
ACTIVE NOP READ ACTIVE
NOP
DISABLE AUTO PRECHARGE
SINGLE BANKS
DON’T CARE
UNDEFINED
COLUMN m
2
tCKH
tCKS
T0 T1 T2 T3 T4 T5 T6 T7 T8
DQMU, DQML
CKE
CLK
A0–A9, A11
DQ
BA0, BA1
A10
COMMAND
33
tCK
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Timing Diagrams
Figure 46: Single Read – With Auto Precharge
Notes: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. x16: A9 and A11 = “Don’t Care.”
x32: A8, A9, and A11 = “Don’t Care.”
3. PRECHARGE command not allowed or tRAS would be violated.
See Table 17 on page 52.
tAC
ENABLE AUTO PRECHARGE
tCH
tCL
tRP
tRAS
tRCD CAS Latency
tRC
DQMU, DQML
CKE
CLK
A0–A9, A11
DQ
BA0, BA1
A10
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
ROW
BANK BANK
ROW
ROW
BANK
tHZ
tOH
D
OUT
m
COMMAND
tCMH
tCMS
NOP3READACTIVE NOP NOP3ACTIVENOP
tCKH
tCKS
COLUMN m2
T0 T1 T2 T4T3 T5 T6 T7 T8
NOP NOP
DON’T CAREUNDEFINED
tCK
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Timing Diagrams
Figure 47: Alternating Bank Read Accesses
Notes: 1. For this example, BL = 4 and CL = 2.
2. x16: A9 and A11 = “Don’t Care.”
x32: A8, A9, and A11 = “Don’t Care.”
See Table 17 on page 52.
ENABLE AUTO PRECHARGE
tCH
tCL
tAC
tLZ
DQMU, DQML
CLK
A0–A9, A11
DQ
BA0, BA1
A10
tOH
DOUT m
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
ROW
ROW
ROW
tOH
DOUT m + 3
tAC tOH
tAC tOH
tAC
DOUT m + 2DOUT m + 1
COMMAND
tCMH
tCMS
NOP NOPACTIVE NOP READ NOP ACTIVE
tOH
DOUT b
tAC tAC
READ
ENABLE AUTO PRECHARGE
ROW
ACTIVE
ROW
BANK 0 BANK 0 BANK 3 BANK 3 BANK 0
CKE
tCKH
tCKS
COLUMN m
2
COLUMN b
2
T0 T1 T2 T4T3 T5 T6 T7 T8
tRP - BANK 0
tRAS - BANK 0
tRCD - BANK 0 tRCD - BANK 0
CAS Latency - BANK 0
tRCD - BANK 3 CAS Latency - BANK 3
t
tRC - BANK 0
RRD
tCK
DON’T CARE
UNDEFINED
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Timing Diagrams
Figure 48: Read – Full-Page Burst
Notes: 1. For this example, CL = 2.
2. x16: A9 and A11 = “Don’t Care.”
x32: A8, A9, and A11 = “Don’t Care.”
3. Page left open; no tRP.
See Table 17 on page 52.
tAC
tLZ
tRCD CAS Latency
DQMU, DQML
CKE
CLK
A0–A9, A11
DQ
BA0, BA1
A10
tOH
D
OUT
m
tCMH
tCMS
tAH
tAS
tAH
tAS
tAC tOH
D
OUT
m+1
ROW
ROW
tHZ
tAC tOH
D
OUT
m+1
tAC tOH
D
OUT
m+2
tAC tOH
D
OUT
m-1
tAC tOH
D
OUT
m
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
()()
()()
()()
()()
()()
()()
()()
Full page completed
512 (x16) locations within same row
COMMAND
tCMH
tCMS
NOPNOP NOPACTIVE NOP READ NOP BURST TERMNOP NOP
()()
()()
NOP
()()
()()
tAH
tAS
BANK
()()
()()
BANK
tCKH
tCKS
()()
()()
()()
()()
COLUMN m
2
3
T0 T1 T2 T4T3 T5 T6 Tn + 1 Tn + 2 Tn + 3 Tn + 4
DON’T CARE
UNDEFINED
tCH
tCK tCL
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Timing Diagrams
Figure 49: Read – DQM Operation
Notes: 1. For this example, CL = 2.
2. x16: A9 and A11 = “Don’t Care.”
x32: A8, A9, and A11 = “Don’t Care.”
See Table 17 on page 52.
tCH
tCL
tRCD CAS Latency
DQMU, DQML
CKE
CLK
A0–A9, A11
DQ
BA0, BA1
A10
tCMS
ROW
BANK
ROW
BANK
tAC
LZ
D
OUT
m
tOH
D
OUT
m + 3D
OUT
m + 2
ttHZ LZ
t
tCMH
COMMAND NOPNOP NOPACTIVE NOP READ NOPNOP NOP
tHZ
tAC tOH
tAC tOH
tAH
tAS
tCMS tCMH
tAH
tAS
tAH
tAS
tCKH
tCKS
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
COLUMN m
2
T0 T1 T2 T4T3 T5 T6 T7 T8
tCK
DON’T CARE
UNDEFINED
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Timing Diagrams
Figure 50: Write – Without Auto Precharge
Notes: 1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <DIN m + 3> and the PRECHARGE command regardless of fre-
quency.
3. x16: A9 and A11 = “Don’t Care.”
x32: A8, A9, and A11 = “Don’t Care.”
See Table 17 on page 52.
DISABLE AUTO PRECHARGE
ALL BANKS
tCH
tCL
tRP
tRAS
tRCD
tRC
DQMU, DQML
CKE
CLK
A0–A9, A11
DQ
BA0, BA1
A10
tCMH
tCMS
tAH
tAS
ROW
ROW
BANK
BANK BANK
ROW
ROW
BANK
tWR
D
IN
m
tDH
tDS
D
IN
m + 1 D
IN
m + 2
D
IN
m + 3
COMMAND
tCMH
tCMS
NOPNOP
NOP
ACTIVE NOP WRITE
NOPPRECHARGE ACTIVE
tAH
tAS
tAH
tAS
tDH
tDS tDH
tDS tDH
tDS
SINGLE BANK
tCKH
tCKS
COLUMN m
3
2
T0 T1 T2 T4T3 T5 T6 T7 T8 T9
NOP
DON’T CAREUNDEFINED
tCK
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Timing Diagrams
Figure 51: Write – With Auto Precharge
Notes: 1. For this example, BL = 4.
2. x16: A9 and A11 = “Don’t Care.”
x32: A8, A9, and A11 = “Don’t Care.”
See Table 17 on page 52.
ENABLE AUTO PRECHARGE
tCH
tCL
tRP
tRAS
tRCD
tRC
DQMU, DQML
CKE
CLK
A0–A9, A11
DQ
BA0, BA1
A10
tCMH
tCMS
tAH
tAS
ROW
ROW
BANK
BANK
ROW
ROW
BANK
tWR
DIN m
tDH
tDS
DIN m + 1 DIN m + 2 DIN m + 3
COMMAND
tCMH
tCMS
NOPNOP
NOP
ACTIVE NOP WRITE
NOP ACTIVE
tAH
tAS
tAH
tAS
tDH
tDS tDH
tDS tDH
tDS
tCKH
tCKS
NOP
NOP
COLUMN m
2
T0 T1 T2 T4T3 T5 T6 T7 T8 T9
DON’T CARE
tCK
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Timing Diagrams
Figure 52: Single Write – Without Auto Precharge
Notes: 1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <DIN m> and the PRECHARGE command regardless of frequency.
3. x16: A9 and A11 = “Don’t Care.”
x32: A8, A9, and A11 = “Don’t Care.”
4. PRECHARGE command not allowed or tRAS would be violated.
See Table 17 on page 52.
DISABLE AUTO PRECHARGE
ALL BANKS
tCH
tCL
tRP
tRAS
tRCD
tRC
D
QMU, DQML
CKE
CLK
A0–A9, A11
DQ
BA0, BA1
A10
tCMH
tCMS
tAH
tAS
ROW
BANK
BANK BANK
ROW
ROW
BANK
tWR
D
IN
m
tDH
tDS
COMMAND
tCMH
tCMS
NOP
4
NOP
4
PRECHARGE
ACTIVE NOP WRITE
ACTIVENOP NOP
tAH
tAS
tAH
tAS
SINGLE BANK
tCKH
tCKS
COLUMN m
3
2
T0 T1 T2 T4T3 T5 T6 T7 T8
DON’T CAR
E
tCK
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Timing Diagrams
Figure 53: Single Write – With Auto Precharge
Notes: 1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. x16: A9 and A11 = “Don’t Care.”
x32: A8, A9, and A11 = “Don’t Care.”
4. WRITE command not allowed or tRAS would be violated.
See Table 17 on page 52.
ENABLE AUTO PRECHARGE
tCH
tCL
tRP
tRAS
tRCD
tRC
DQMU, DQML
CKE
CLK
A0–A9, A11
DQ
BA0, BA1
A10
tCMH
tCMS
tAH
tAS
ROW
ROW
BANK BANK
ROW
ROW
BANK
tWR
D
IN
m
COMMAND
tCMH
tCMS
NOP3
NOP3
NOP
ACTIVE NOP3
WRITE NOP
ACTIVE
tAH
tAS
tAH
tAS
tDH
tDS
tCKH
tCKS
NOP
NOP
COLUMN m2
T0 T1 T2 T4T3 T5 T6 T7 T8 T9
DON’T CARE
tCK
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Timing Diagrams
Figure 54: Alternating Bank Write Accesses
Notes: 1. For this example, BL = 4.
2. x16: A9 and A11 = “Don’t Care.”
x32: A8, A9, and A11 = “Don’t Care.”
See Table 17 on page 52.
DON’T CARE
tCH
tCL
CLK
DQ D
IN
m
tDH
tDS
DIN m + 1 DIN m + 2 DIN m + 3
COMMAND
tCMH
tCMS
NOP
NOP
ACTIVE NOP WRITE
NOP NOP ACTIVE
tDH
tDS tDH
tDS tDH
tDS
ACTIVE WRITE
DIN b
tDH
tDS
DIN b + 1 DIN b + 3
tDH
tDS tDH
tDS
ENABLE AUTO PRECHARGE
DQMU, DQML
A0–A9, A11
BA0, BA1
A10
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
ROW
ROW
ROW
ENABLE AUTO PRECHARGE
ROW
ROW
BANK 0 BANK 0 BANK 1
BANK 0
BANK 1
CKE
tCKH
tCKS
DIN b + 2
tDH
tDS
COLUMN b
2
COLUMN m
2
t
tRAS - BANK 0
tRCD - BANK 0 t
t
RCD - BANK 0
tWR - BANK 0
WR - BANK 1
tRCD - BANK 1
t
tRC - BANK 0
RRD
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
tCK
RP - BANK 0
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128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN 75 ©2001 Micron Technology, Inc. All rights reserved.
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Timing Diagrams
Figure 55: Write – Full-page Burst
Notes: 1. x16: A9 and A11 = “Don’t Care.”
x32: A8, A9, and A11 = “Don’t Care.”
2. tWR must be sati sf ied prior to PRECHARGE command.
3. Page left open; no tRP.
See Table 17 on page 52.
tRCD
DQMU, DQML
CKE
CLK
A0–A9, A11
BA0, BA1
A10
tCMS
tAH
tAS
tAH
tAS
ROW
ROW
Full-page burst does not
self-terminate. Can use
BURST TERMINATE
command to stop.
2, 3
()()
()()
()()
()()
Full page completed
DON’T CARE
COMMAND
tCMH
tCMS
NOPNOP NOPACTIVE NOP WRITE BURST TERMNOP NOP
()()
()()
()()
()()
DQ
D
IN
m
tDH
tDS
D
IN
m + 1 D
IN
m + 2 D
IN
m + 3
tDH
tDS tDH
tDS tDH
tDS
D
IN
m - 1
tDH
tDS
tAH
tAS
BANK
()()
()()
BANK
tCMH
tCKH
tCKS
()()
()()
()()
()()
()()
()()
512 (x16) locations within same row
COLUMN m
1
T0 T1 T2 T3 T4 T5 Tn + 1 Tn + 2 Tn + 3
tCH
tCL
tCK
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128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN 76 ©2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
Timing Diagrams
Figure 56: Write – DQM Operation
Notes: 1. For this example, BL = 4.
2. x16: A9 and A11 = “Don’t Care.”
x32: A8, A9, and A11 = “Don’t Care.”
See Table 17 on page 52.
DON’T CARE
tRCD
DQMU, DQML
CKE
CLK
A0-A9, A11
DQ
BA0, BA1
A10
tCMS
tAH
tAS
ROW
BANK
ROW
BANK
ENABLE AUTO PRECHARGE
D
IN
m + 3
tDH
tDS
D
IN
mD
IN
m + 2
tCMH
COMMAND
NOPNOP NOPACTIVE NOP WRITE NOPNOP
tCMS tCMH
tDH
tDS
tDH
tDS
tAH
tAS
tAH
tAS
DISABLE AUTO PRECHARGE
tCKH
tCKS
COLUMN m
2
T0 T1 T2 T3 T4 T5 T6 T7
tCH
tCL
tCK
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128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN 77 ©2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
Package Dimensions
Package Dimensions
Figure 57: 54-Ball FBGA, “F4/B4” Package (x16 Device), 8mm x 8mm
Notes: 1. All dimensions are in millimeters.
2. Recommended pad size for PCB is 0.40mm.
3. Topside part marking decoder can be found at http://www.micron.com/support/fbga/
decoder.aspx.
BALL A1 ID
0.65 ±0.05
SEATING PLANE
0.10 C
C
1.00 MAX
BALL A9
0.80
TYP
0.80 TYP
3.20
6.40
8.00 ±0.10
4.00 ±0.05
SOLDER BALL
DIAMETER REFERS
TO POST REFLOW
CONDITION. THE PRE-
REFLOW DIAMETER
IS 0.42.
54X Ø0.45 ±0.05
SOLDER BALL MATERIAL:
62% Sn, 36% Pb, 2% Ag OR
96.5% Sn, 3% Ag, 0.5% Cu
SOLDER MASK DEFINED BALL PADS:
Ø0.40
MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE MATERIAL: PLASTIC LAMINATE
6.40
3.20
4.00 ±0.05
8.00 ±0.10
C
L
C
L
BALL A1 ID
BALL A1
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128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN 78 ©2001 Micron Technology, Inc. All rights reserved.
128Mb: x16, x32 Mobile SDRAM
Package Dimensions
Figure 58: 90-Ball FBGA, “F5/B5” Package (x32 Device), 8mm x 13mm
Notes: 1. All dimensions are in millimeters.
2. Recommended pad size for PCB is 0.4mm ±0.025mm.
3. Package width and length do not include mold protrusion; allowable mold protrusion is
0.25mm per side.
4. Topside part marking decoder can be found at http://www.micron.com/support/fbga/
decoder.aspx.
BALL A1 ID
1.00 MAX
MOLD COMPOUND:
EPOXY NOVOLAC
SUBSTRATE MATERIAL:
PLASTIC LAMINATE
SOLDER BALL MATERIAL:
62% Sn, 36% Pb, 2% Ag OR
96.5% Sn, 3%Ag, 0.5% Cu
13.00 ±0.10
BALL A1
BALL A9 BALL A1 ID
0.80 TYP
6.50 ±0.05
8.00 ±0.10
4.00 ±0.053.20
5.60 ±0.05
0.65 ±0.05
SEATING PLANE
A
11.20 ±0.10
6.40
0.10 A
90X Ø0.45
DIMENSIONS APPLY
TO SOLDER BALLS POST
REFLOW. THE PRE-
REFLOW DIAMETER IS
0.42 ON A 0.40 SMD
BALL PAD
C
L
C
L
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology , Inc. All other trademarks ar e the property of
their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth
herein. Although considered final, these specifications are subject to change, as further product development and data
characterization sometimes occur.
128Mb: x16, x32 Mobile SDRAM
Package Dimensions
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Figure 59: 54-Pin Plastic TSOP (400 mil)
Notes: 1. All dimensions are in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is
0.25mm per side.
SEE DETAIL A
0.80 TYP 0.71
10.16 ±0.08
0.50 ±0.10
PIN #1 ID
DETAIL A
22.22 ±0.08
0.375 ±0.075
1.2 MAX
0.10
0.25
11.76 ±0.20
0.80
TYP
0.15 +0.03
-0.02
0.10 +0.10
-0.05
GAGE PLANE
PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC
LEAD FINISH: TIN/LEAD PLATE
PACKAGE WIDTH AND LENGTH DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE PROTRUSION
IS 0.25 PER SIDE.