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Design Idea DI-53
DPA-Switch
50 W DC-DC Dual Output Converter
July 2003
DI-53
Application
Telecom DPA425R 5 V & 3.3 V
Power Output
50 W Input Voltage Output Voltage Topology
Device 36-75 VDC Forward Sync. Rect.
Figure 1. DPA425R - 50 W, 5 V, 6 A and 3.3 V, 6 A DC-DC Converter.
.
®
™
Design Highlights
•High efficiency: 90% at 36 VDC using synchronous
rectification
•Dual output with tight cross-regulation ±4% from zero to
full load on both outputs
•Output overload, open loop and thermal protection
•300 kHz switching frequency to allow sufficient
transformer reset time with sync rectification
•3.85 x 2.25 x 0.6 inch (~9.62 W/in3)
Operation
DPA-Switch greatly simplifies the design compared to a discrete
implementation. This design uses a coupled output inductor and
synchronous rectification to achieve excellent cross-regulation
and high efficiency.
Resistor R1 programs the under/over voltages and linearly
reduces the maximum duty cycle with input voltage to prevent
core saturation during load transients. Components D1, D2, C9
and L2 implement a resonant clamp circuit to catch and
recirculate the transformer leakage energy during normal
operation, with Zener VR1 providing absolute clamping for
transient conditions.
Capacitor C21 charges the gate of Q2, the forward synchronous
rectifier MOSFET of the 5 V output. Resistor R21 limits gate
oscillation and R22 provides gate pull-down. Zener diode
VR20 limits the Q2 gate voltage during conduction and also
reverse charges C21 during the Q2 off time. The same drive
technique is used for the forward synchronous rectifier
MOSFET (Q4) of the 3.3 V output (with C22, R24, R25, and
VR21).
MOSFETs Q1 and Q3 are driven via resistors R23 and R26
from the transformer (T1) reset voltage and operate only
when Q2 and Q4 are off. Diodes D20 and D21 provide a
conduction path for the output inductor (L4) current when the
transformer reset is complete.
A winding on the coupled inductor L4, along with diode D4
and capacitor C9, provide the DPA-Switch bias voltage.
U1
DPA425R
D20
D4
D21
1
4,5
2,3
10
C5
0.22 µF
C9
4.7 µF
16 V
C7
1 nF
1.5 kV
C9
150 pF
200 V
VR1
SMBJ
150 A C6
68 µF
10 V
U2
PC267
N1T
R3
15 kΩ
1%
R1
619 kΩ
1%
R4
1.0 Ω
-VIN
L1
1 µH
2.5 A
C1-C3
1 µF
100 V
DL
SXF
C
CONTROL
CONTROL
PI-3561-072203
DPA-Switch
RTN
5 V, 6 A
(8 A pk)
3.3 V, 6 A
(8 A pk)
U2
D3
BAV19WS
U3
LM431
AIM3X
R9
220 Ω
R11
10.0 kΩ
1%
R12
15.9 kΩ
1%
R10
8.66 kΩ
1%
R12
5.1 Ω
R7
10 kΩ
C23-C26
100 µF
10 V
C21-C22
4700 pF
C20
3.3 nF
C27
1 µFC28
1 µF
C14
1 µF
C15
10 µF
10 V
C16
100 nF
R6
150 Ω
R21
10 Ω
+ VIN
36-75 VDC
8,9
T1
6,7
L2
220 µH
L4
3.5 µH
D1
ES1D
D2
ES1D
R20
3.3 Ω
R23
10 ΩR26
10 Ω
R24
10 Ω
R25
10 kΩ
R22
10 kΩ
VR21
15 V
VR20
15 V
Q1
Q3
Q4
Q2
9,10 7,8
1,2 3,4
56
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A
7/03
DI-53
Table 1. Transformer Design Parameters.
Figure 2. Efficiency vs. Output Power.
Key Design Points
•Capacitors C20, CQ1gs and CQ3gs will all load transformer
reset. Choose values to ensure sufficient reset at low line
and safe maximum drain voltage at high line. Also use
300 kHz operation for longest reset time.
•Capacitors C21 and C22 will capacitively drive MOSFET
gate capacitances CQ2gs and CQ4gs (respectively). C21 and
C22 should be chosen to ensure that gate drive voltage
attains turn-on threshold of MOSFET (VgTH), at worst case
conditions (low line for forward MOSFET).
•Reduce transformer leakage inductance by filling each
winding layer across the entire width of the bobbin.
•Higher efficiency (+1%) can be acheived by using a
DPA426R and increasing R3 to reduce the internal current
limit.
26841012
IOUT1 + IOUT2 (A)
Efficiency (%)
75
65
70
60
80
85
95
90
PI-3562-061603
36 VDC
54 VDC
72 VDC
TRANSFORMER PARAMETERS
Core Material
Bobbin
Winding Details
5 V (6, 7-8, 9), Primary (1-10), 3.3 V
(4.5-2.3)
Winding Order and
Pin Numbers
Primary Inductance
Primary Resonant
Frequency
Leakage Inductance
Primary 11T, 4 x 28 AWG
3.3 V 2T, 2 x 4 x 26 AWG
5 V 3T, 2 x 4 x 26 AWG
3.8 MHz (minimum)
Ferroxcube P/N: EFD25-3F3, ungapped
10-pin EFD25 surface mount bobbin
250 µH ±25% at 300 kHz
0.8 µH (maximum)
INDUCTOR PARAMETERS
Core Material
Bobbin
Winding Details
Inductance Pin (1, 2-3, 4): 3.5 µH ±10% at 300 kHz
5 V (9, 10-7, 8), 3.3 V (1, 2-3, 4),
Bias (FL1-FL2)
5 V 6T, 2 x 4 x 26 AWG
3.3 V 4T, 2 x 4 x 26 AWG
Bias 12T, 1 x 30 TIW
10-pin EFD20 surface mount bobbin
Ferroxcube P/N: EFD25-3F3 ungapped
Winding Order and
Pin Numbers
Table 1. Inductor Design Parameters.
