AD5339ARMZ - ANALOG DEVICES - Datasheet.Directory

2.5 V to 5.5 V, 250 μA, 2-Wire Interface,

Dual Voltage Output, 8-/10-/12-Bit DACs

AD5337/AD5338/AD5339

Rev. C

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FEATURES

AD5337

2 buffered 8-bit DACs in 8-lead MSOP

AD5338, AD5338-1

2 buffered 10-bit DACs in 8-lead MSOP

AD5339

2 buffered 12-bit DACs in 8-lead MSOP

Low power operation: 250 μA @ 3 V, 300 μA @ 5 V

2-wire (I2C-compatible) serial interface

2.5 V to 5.5 V power supply

Guaranteed monotonic by design over all codes

Power-down to 80 nA @ 3 V, 200 nA @ 5 V

3 power-down modes

Double-buffered input logic

Output range: 0 V to VREF

Power-on reset to 0 V

Simultaneous update of outputs (LDAC function)

Software clear facility

Data readback facility

On-chip rail-to-rail output buffer amplifiers

Temperature range: −40°C to +105°C

APPLICATIONS

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

Industrial process control

GENERAL DESCRIPTION

The AD5337/AD5338/AD5339 are dual 8-, 10-, and 12-bit

buffered voltage output DACs, respectively. Each part is housed

in an 8-lead MSOP package and operates from a single 2.5 V to

5.5 V supply, consuming 250 μA at 3 V. On-chip output amplifiers

allow rail-to-rail output swing with a slew rate of 0.7 V/μs. A 2-

wire serial interface operates at clock rates up to 400 kHz. This

interface is SMBus compatible at VDD < 3.6 V. Multiple devices

can be placed on the same bus.

The references for the two DACs are derived from one reference

pin. The outputs of all DACs can be updated simultaneously

using the software LDAC function. The parts incorporate a

power-on reset circuit to ensure that the DAC outputs power up

to 0 V and remain there until a valid write to the device takes

place. A software clear function resets all input and DAC

registers to 0 V. A power-down feature reduces the current

consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V).

The low power consumption of these parts in normal operation

makes them ideally suited to portable battery-operated equip-

ment. The power consumption is typically 1.5 mW at 5 V and

0.75 mW at 3 V, reducing to 1 μW in power-down mode.

FUNCTIONAL BLOCK DIAGRAM

SCL BUFFER

BUFFER

LDAC

SDA

GND

03756-001

INTERFACE

LOGIC

INPUT

DAC

STRING

DAC A

STRING

DAC B

VOUTA

VOUTB

POWER-DOWN

LOGIC

AD5337/AD5338/AD5339

POWER-ON

RESET

REFIN

Figure 1.

AD5337/AD5338/AD5339

Rev. C | Page 2 of 28

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Characteristics........................................................................ 5

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Terminology .................................................................................... 13

Theory of Operation ...................................................................... 15

Digital-to-Analog Converter Section ...................................... 15

Resistor String............................................................................. 15

DAC Reference Inputs ............................................................... 15

Output Amplifier........................................................................ 15

Power-on Reset ........................................................................... 15

Serial Interface............................................................................ 16

Write Operation.......................................................................... 17

Read Operation........................................................................... 18

Double-Buffered Interface ........................................................ 19

Power-Down Modes .................................................................. 19

Applications..................................................................................... 20

Typical Application Circuit....................................................... 20

Bipolar Operation....................................................................... 20

Multiple Devices on One Bus ................................................... 20

Product as a Digitally Programmable Window Detector ..... 21

Coarse and Fine Adjustment Capabilities............................... 21

Power Supply Decoupling ......................................................... 21

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

9/07—Rev. B to Rev. C

Changes to Features.......................................................................... 1

Changes to Table 4............................................................................ 7

Changes to Ordering Guide .......................................................... 25

9/06—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Figure 31...................................................................... 16

Changes to Table 6.......................................................................... 16

Changes to Table 10........................................................................ 23

Changes to Ordering Guide .......................................................... 25

10/04—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Added AD5338-1................................................................Universal

Changes to Specifications.................................................................4

Updated Outline Dimensions....................................................... 24

Changes to Ordering Guide.......................................................... 24

11/03—Rev. 0: Initial Version

AD5337/AD5338/AD5339

Rev. C | Page 3 of 28

SPECIFICATIONS

VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.

Table 1.

A Grade1B Grade1

Parameter2Min Typ Max Min Typ Max Unit Conditions/Comments

DC PERFORMANCE3, 4

AD5337

Resolution 8 8 Bits

Relative Accuracy ±0.15 ±1 ±0.15 ±0.5 LSB

Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB Guaranteed monotonic by

design over all codes

AD5338

Resolution 10 10 Bits

Relative Accuracy ±0.5 ±4 ±0.5 ±2 LSB

Differential Nonlinearity ±0.05 ±0.5 ±0.05 ±0.50 LSB Guaranteed monotonic by

design over all codes

AD5339

Resolution 12 12 Bits

Relative Accuracy ±2 ±16 ±2 ±8 LSB

Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB Guaranteed monotonic by

design over all codes

Offset Error ±0.4 ±3 ±0.4 ±3 % of FSR

Gain Error ±0.15 ±1 ±0.15 ±1 % of FSR

Lower Deadband 20 60 20 60 mV Lower deadband exists

only if offset error is

negative

Offset Error Drift5 −12 −12 ppm of

FSR/°C

Gain Error Drift5 −5 −5 ppm of

FSR/°C

Power Supply Rejection Ratio5 −60 −60 dB ∆VDD = ±10%

DC Crosstalk5 200 200 μV RL = 2 kΩ to GND or VDD

DAC REFERENCE INPUTS5

VREF Input Range 0.25 VDD 0.25 VDD V

VREF Input Impedance 37 45 37 45 kΩ Normal operation

>10 >10 MΩ Power-down mode

Reference Feedthrough −90 −90 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS5

Minimum Output Voltage6 0.001 0.001 V Measure of the minimum

drive capabilities of the

output amplifier

Maximum Output Voltage6 VDD −

0.001

VDD −

0.001

V Measure of the maximum

drive capabilities of the

output amplifier

DC Output Impedance 0.5 0.5 Ω

Short-Circuit Current 25 25 mA VDD = 5 V

16 16 mA VDD = 3 V

Power-Up Time 2.5 2.5 μs Coming out of power-

down mode, VDD = 5 V

5 5 μs

Coming out of power-

down mode, VDD = 3 V

AD5337/AD5338/AD5339

Rev. C | Page 4 of 28

A Grade1B Grade1

Parameter2Min Typ Max Min Typ Max Unit Conditions/Comments

LOGIC INPUTS (A0)5

Input Current ±1 ±1 μA

Input Low Voltage (VIL) 0.8 0.8 V VDD = 5 V ± 10%

0.6 0.6 V VDD = 3 V ± 10%

0.5 0.5 V VDD = 2.5 V

Input High Voltage (VIH) 2.4 2.4 V VDD = 5 V ± 10%

2.1 2.1 V VDD = 3 V ± 10%

2.0 2.0 V VDD = 2.5 V

Pin Capacitance 3 3 pF

LOGIC INPUTS (SCL, SDA)5

Input High Voltage (VIH) 0.7 ×

VDD

VDD +

0.3

0.7 ×

VDD

VDD +

0.3

V SMBus compatible at

VDD < 3.6 V

Input Low Voltage (VIL) −0.3

+0.3

VDD

–0.3 +0.3

VDD

V SMBus compatible at

VDD < 3.6 V

Input Leakage Current (IIN) ±1 ±1 μA

Input Hysteresis (VHYST) 0.05 ×

VDD

0.05 ×

VDD

Input Capacitance (CIN) 8 8 pF

Glitch Rejection 50 50 ns Input filtering suppresses

noise spikes of less than

50 ns

LOGIC OUTPUT (SDA)5

Output Low Voltage (VOL) 0.4 0.4 V ISINK = 3 mA

0.6 0.6 V ISINK = 6 mA

Three-State Leakage Current ±1 ±1 μA

Three-State Output Capacitance 8 8 pF

POWER REQUIREMENTS

VDD 2.5 5.5 2.5 5.5 V

IDD (Normal Mode)7 V

IH = VDD and VIL = GND

VDD = 4.5 V to 5.5 V 300 375 300 375 μA

VDD = 2.5 V to 3.6 V 250 350 250 350 μA

IDD (Power-Down Mode) VIH = VDD and VIL = GND

VDD = 4.5 V to 5.5 V 0.2 1.0 0.2 1.0 μA IDD = 4 μA (max) during 0

readback on SDA

VDD = 2.5 V to 3.6 V 0.08 1.00 0.08 1.00 μA IDD = 1.5 μA (max) during 0

readback on SDA

1 Temperature range for A Version and B Version: −40°C to +105°C; typical at 25°C.

2 See the Terminology section for explanations of the specific parameters.

3 DC specifications tested with the outputs unloaded.

4 Linearity is tested using a reduced code range: AD5337 (Code 8 to Code 248), AD5338, AD5338-1 (Code 28 to Code 995), AD5339 (Code 115 to Code 3981).

5 Guaranteed by design and characterization; not production tested.

6 For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive.

7 IDD specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.

AD5337/AD5338/AD5339

Rev. C | Page 5 of 28

AC CHARACTERISTICS

VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.

Table 2.

A Version and B Version1

Parameter2, 3Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time VREF = VDD = 5 V

AD5337 6 8 μs 1/4 scale to 3/4 scale change (0x40 to 0xC0)

AD5338 7 9 μs 1/4 scale to 3/4 scale change (0x100 to 0x300)

AD5339 8 10 μs 1/4 scale to 3/4 scale change (0x400 to 0xC00)

Slew Rate 0.7 V/μs

Major Code Transition Glitch Energy 12 nV-s 1 LSB change around major carry

Digital Feedthrough 1 nV-s

Digital Crosstalk 1 nV-s

DAC-to-DAC Crosstalk 3 nV-s

Multiplying Bandwidth 200 kHz VREF = 2 V ± 0.1 V p-p

Total Harmonic Distortion −70 dB VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz

1 Temperature range for A version and B version: −40°C to +105°C; typical at 25°C.

2 Guaranteed by design and characterization; not production tested.

3 See the Terminology section for explanations of the specific parameters.

AD5337/AD5338/AD5339

Rev. C | Page 6 of 28

TIMING CHARACTERISTICS

VDD = 2.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Limit at TMIN, TMAX

Parameter A Version and B Version Unit Conditions/Comments

fSCL 400 kHz max SCL clock frequency

t1 2.5 μs min SCL cycle time

t2 0.6 μs min tHIGH, SCL high time

t3 1.3 μs min tLOW, SCL low time

t4 0.6 μs min tHD, STA, start/repeated start condition hold time

t5 100 ns min tSU, DAT, data setup time

t610.9 μs max tHD, DAT, data hold time

0 μs min tHD, DAT, data hold time

t7 0.6 μs min tSU, STA, setup time for repeated start

t8 0.6 μs min tSU, STO, stop condition setup time

t9 1.3 μs min tBUF, bus free time between a stop and a start condition

t10 300 ns max tR, rise time of SCL and SDA when receiving

0 ns min tR, rise time of SCL and SDA when receiving (CMOS compatible)

t11 250 ns max tF, fall time of SDA when transmitting

0 ns min tF, fall time of SDA when receiving (CMOS compatible)

300 ns max tF, fall time of SCL and SDA when receiving

20 + 0.1 CB2ns min tF, fall time of SCL and SDA when transmitting

CB 400 pF max Capacitive load for each bus line

1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH min of the SCL signal) to bridge the undefined region of SCL’s falling edge.

2 CB is the total capacitance of one bus line in pF; tR and tF measured between 0.3 VDD and 0.7 VDD.

3756-002

SDA

SCL

START

CONDITION STOP

CONDITION

REPEATED

START

CONDITION

Figure 2. 2-Wire Serial Interface Timing Diagram

AD5337/AD5338/AD5339

Rev. C | Page 7 of 28

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7 V

SCL, SDA to GND −0.3 V to VDD + 0.3 V

A0 to GND −0.3 V to VDD + 0.3 V

Reference Input Voltage to GND −0.3 V to VDD + 0.3 V

VOUTA to VOUTB to GND −0.3 V to VDD + 0.3 V

Operating Temperature Range

Industrial (B Version) −40°C to +105°C

Storage Temperature Range −65°C to +150°C

Junction Temperature (TJ max) 150°C

MSOP Package

Power Dissipation (TJ max − TA) θJA

θJA Thermal Impedance 206°C/W

θJC Thermal Impedance 44°C/W

Lead Temperature JEDEC Industry Standard

Soldering J-STD-020

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Transient currents of up to 100 mA do not cause SCR latch-up.

ESD CAUTION

AD5337/AD5338/AD5339

Rev. C | Page 8 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

3756-003

DD 1

OUT

REFIN

SCL

SDA

GND

TOP VIEW

(Not to Scale)

AD5337/

AD5338/

AD5339

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 VDD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND.

2 VOUTA Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

3 VOUTB Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

4 REFIN Reference Input Pin for the Two DACs. It has an input range from 0.25 V to VDD.

5 GND Ground Reference Point for All Circuitry on the Parts.

6 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input shift

register. SDA is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor.

7 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input shift

8 A0 Address Input. Sets the least significant bit of the 7-bit slave address.

AD5337/AD5338/AD5339

Rev. C | Page 9 of 28

TYPICAL PERFORMANCE CHARACTERISTICS

INL ERROR (LSB)

–1.0

–0.5

0.5

1.0

0 50 100 150 200 250

CODE

TA= 25°C

VDD =5V

03756-006

Figure 4. AD5337 Typical INL Plot

–3

–2

–1

INL ERROR (LSB)

0 200 400 600 800 1000

CODE

TA= 25°C

VDD =5V

03756-007

Figure 5. AD5338 Typical INL Plot

–12

–8

–4

INL ERROR (LSB)

20001500500 10000 2500 3000 3500 4000

CODE

TA= 25°C

VDD =5V

03756-008

Figure 6. AD5339 Typical INL Plot

–0.3

–0.2

–0.1

0.1

0.2

0.3

DNL ERROR (LSB)

0 50 100 150 200 250

CODE

TA= 25°C

VDD =5V

03756-009

Figure 7. AD5337 Typical DNL Plot

–0.6

–0.4

–0.2

0.2

0.4

0.6

DNL ERROR (LSB)

0 200 400 600 800 1000

CODE

TA= 25°C

VDD =5V

03756-010

Figure 8. AD5338 Typical DNL Plot

DNL ERROR (LSB)

–1.0

–0.5

0.5

1.0

20001500500 10000 2500 3000 3500 4000

CODE

TA= 25°C

VDD =5V

03756-011

Figure 9. AD5339 Typical DNL Plot

AD5337/AD5338/AD5339

Rev. C | Page 10 of 28

ERROR (LSB)

–0.50

–0.25

0.25

0.50

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

REF

(V)

= 25°C

=5V

MAX INL

MAX DNL

MIN DNL

MIN INL

03756-012

Figure 10. AD5337 INL and DNL Error vs. VREF

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0.5

ERROR (LSB)

TEMPERATURE (°C)

0–40 40 80 120

VDD =5V

VREF =3V

MAX INL

MAX DNL

MIN DNL

MIN INL

03756-013

Figure 11. AD5337 INL and DNL Error vs. Temperature

ERROR (%)

–1.0

–0.5

0.5

1.0

TEMPERATURE (°C)

0–40 40 80 120

=5V

REF

=2V

GAIN ERROR

OFFSET ERROR

03756-014

Figure 12. AD5337 Offset Error and Gain Error vs. Temperature

–0.6

–0.5

–0.4

–0.3

–0.2

–0.1

ERROR (%)

0.1

0.2

2301 45

(V)

= 25°C

REF

=2V

GAIN ERROR

OFFSET ERROR

03756-015

Figure 13. Offset Error and Gain Error vs. VDD

OUT

(V)

2301 45

SINK/SOURCE CURRENT (mA)

5V SOURCE

3V SOURCE

5V SINK

3V SINK

03756-016

Figure 14. VOUT Source and Sink Current Capability

100

150

200

250

300

ZERO SCALE FULL SCALE

CODE

= 25°C

=5V

REF

=2V

03756-017

(µA)

Figure 15. Supply Current vs. Code

AD5337/AD5338/AD5339

Rev. C | Page 11 of 28

100

150

200

250

300

(µA)

3.5 4.02.5 3.0 4.5 5.0 5.5

(V)

+25°C

–40°C

+105°C

03756-018

Figure 16. Supply Current vs. Supply Voltage

0.1

0.2

0.3

0.4

0.5

(µA)

3.5 4.02.5 3.0 4.5 5.0 5.5

(V)

+25°C

–40°C

+105°C

03756-019

Figure 17. Power-Down Current vs. Supply Voltage

100

150

200

250

IDD (µA)

300

350

400

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

LOGIC

(V)

= 25°C

=5V

=3V

INCREASING

DECREASING

03756-020

Figure 18. Supply Current vs. Logic Input Voltage for SDA and SCL Voltage

Increasing and Decreasing

=25°C

=5V

REF

=5V

OUT

SCL

CH1

CH1 1V, CH2 5V, TIME BASE = 1µs/DIV

CH2

03756-021

Figure 19. Midscale Settling (¼ to ¾ Scale Code Change)

= 25°C

=5V

REF

=2V

OUT

CH1

CH1 2V, CH2 200mV, TIME BASE = 200µs/DIV

CH2

03756-022

Figure 20. Power-On Reset to 0 V

= 25°C

=5V

REF

=2V

OUT

SCL

CH1

CH1 500mV, CH2 5V, TIME BASE = 1µs/DIV

CH2

03756-023

Figure 21. Existing Power-Down to Midscale

AD5337/AD5338/AD5339

Rev. C | Page 12 of 28

=5VV

=3V

FREQUENCY

(µA)

150 200 250 300

03756-024

Figure 22. IDD Histogram with VDD = 3 V and VDD = 5 V

VOUT (V)

2.47

2.49

2.48

2.50

1µs/DIV

03756-025

Figure 23. AD5339 Major Code Transition Glitch Energy

–60

–50

–40

–30

–20

–10

1k 10k10 100 100k 1M 10M

FREQUENCY (Hz)

03756-026

Figure 24. Multiplying Bandwidth (Small-Signal Frequency Response)

FULL-SCALE ERROR (V)

–0.02

–0.01

0.01

0.02

2301 45

REF

(V)

= 25°C

=5V

03756-027

Figure 25. Full-Scale Error vs. VREF

1mV/DI

50ns/DIV

03756-028

Figure 26. DAC-to-DAC Crosstalk

AD5337/AD5338/AD5339

Rev. C | Page 13 of 28

TERMINOLOGY

Relative Accuracy (Integral Nonlinearity, INL)

For the DAC, relative accuracy, or integral nonlinearity (INL),

is a measure, in LSBs, of the maximum deviation from a straight

line passing through the endpoints of the DAC transfer function.

Typical INL vs. code plots can be seen in Figure 4, Figure 5, and

Figure 6.

Differential Nonlinearity (DNL)

The difference between the measured change and the ideal

1 LSB change between any two adjacent codes. A specified

differential nonlinearity of ±1 LSB maximum ensures mono-

tonicity. This DAC is guaranteed monotonic by design. Typical

DNL vs. code plots can be seen in Figure 7, Figure 8, and

Figure 9.

Offset Error

A measure of the offset error of the DAC and the output

amplifier, expressed as a percentage of the full-scale range.

Gain Error

A measure of the span error of the DAC. It is the deviation in

slope of the actual DAC transfer characteristic from the ideal,

expressed as a percentage of the full-scale range.

Offset Error Drift

A measure of the change in offset error with changes in

temperature. It is expressed in (ppm of full-scale range)/°C.

Gain Error Drift

A measure of the change in gain error with changes in

temperature. It is expressed in (ppm of full-scale range)/°C.

Power Supply Rejection Ratio (PSRR)

This indicates how the output of the DAC is affected by changes

in the supply voltage. PSRR is the ratio of the change in VOUT to

a change in VDD for full-scale output of the DAC. It is measured

in dB. VREF is held at 2 V and VDD is varied ±10%.

DC Crosstalk

The dc change in the output level of one DAC at midscale in

response to a full-scale code change (all 0s to all 1s and vice

versa) and output change of another DAC. It is expressed in μV.

Reference Feedthrough

The ratio of the amplitude of the signal at the DAC output to

the reference input when the DAC output is not being updated.

It is expressed in dB.

Major Code Transition Glitch Energy

The energy of the impulse injected into the analog output when

the code in the DAC register changes state. Normally specified

as the area of the glitch in nV-s, it is measured when the digital

code is changed by 1 LSB at the major carry transition (011...11

to 100...00 or 100...00 to 011...11).

Digital Feedthrough

A measure of the impulse injected into the analog output of the

DAC from the digital input pins of the device when the DAC

output is not being updated. Specified in nV-s and measured

with a worst-case change on the digital input pins, such as

changing from all 0s to all 1s or vice-versa.

Digital Crosstalk

The glitch impulse transferred to the output of one DAC at

midscale in response to a full-scale code change (all 0s to all 1s,

or vice versa) in the input register of another DAC. It is

expressed in nV-s.

DAC-to-DAC Crosstalk

The glitch impulse transferred to the output of one DAC due to

a digital code change and subsequent output change of another

DAC. This includes both digital and analog crosstalk. It is

measured by loading one of the DACs with a full-scale code

change (all 0s to all 1s, or vice versa) with the LDAC bit set low

and monitoring the output of another DAC. The energy of the

glitch is expressed in nV-s.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The

multiplying bandwidth is the frequency at which the output

amplitude falls to 3 dB below the input. A sine wave on the

reference (with full-scale code loaded to the DAC) appears on

the output.

Total Harmonic Distortion (THD)

The difference between an ideal sine wave and its attenuated

version using the DAC. The sine wave is used as the reference

for the DAC, and the THD is a measure of the harmonic

distortion present in the DAC output. It is measured in dB.

AD5337/AD5338/AD5339

Rev. C | Page 14 of 28

GAIN ERROR

PLUS

OFFSET ERROR

ACTUAL

IDEAL

DAC CODE

03756-004

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

ERROR

DEADBAND CODES

AMPLIFIER

FOOTROOM

(1mV)

NEGATIVE

OFFSET

ERROR

Figure 27. Transfer Function with Negative Offset

GAIN ERROR

PLUS

OFFSET ERROR

DAC CODE

ACTUAL

IDEAL

03756-005

OUTPUT

VOLTAGE

POSITIVE

OFFSET

Figure 28. Transfer Function with Positive Offset

AD5337/AD5338/AD5339

Rev. C | Page 15 of 28

THEORY OF OPERATION

The AD5337/AD5338/AD5339 are dual resistor string DACs

fabricated on a CMOS process with resolutions of 8, 10, and

12 bits, respectively. Each part contains two output buffer

amplifiers and is written to via a 2-wire serial interface. The

DACs operate from single supplies of 2.5 V to 5.5 V, and the

output buffer amplifiers provide rail-to-rail output swing with

a slew rate of 0.7 V/μs. The two DACs share a single reference

input pin. Each DAC has three programmable power-down

modes that allow the output amplifier to be configured with

either a 1 kΩ load to ground, a 100 kΩ load to ground, or as

a high impedance three-state output.

DIGITAL-TO-ANALOG CONVERTER SECTION

The architecture of one DAC channel consists of a resistor-

string DAC followed by an output buffer amplifier. The voltage

at the REFIN pin provides the reference voltage for the DAC.

Figure 29 shows a block diagram of the DAC architecture.

Because the input coding to the DAC is straight binary, the ideal

output voltage is given by

REF

OUT

where:

D is the decimal equivalent of the binary code, which is loaded

to the DAC register

0 to 255 for AD5337 (8 bits)

0 to 1023 for AD5338 and AD5338-1 (10 bits)

0 to 4095 for AD5339 (12 bits)

N is the DAC resolution.

INPUT

REFIN

OUTPUT BUFFER

AMPLIFIER

OUT

RESISTOR

STRING

DAC

03756-029

Figure 29. DAC Channel Architecture

RESISTOR STRING

The resistor string portion is shown in Figure 30. It is simply a

string of resistors, each of value R. The digital code loaded to

the DAC register determines the node at which the voltage is

tapped off and fed into the output amplifier. The voltage is

tapped off by closing one of the switches that connects the

string to the amplifier. Because the DAC comprises a string

of resistors, it is guaranteed to be monotonic.

03756-030

TO OUTPUT

AMPLIFIER

Figure 30. Resistor String

DAC REFERENCE INPUTS

There is a single reference input pin for the two DACs. The

reference input is unbuffered. The user can have a reference

voltage as low as 0.25 V and as high as VDD, because there is no

restriction due to headroom and foot room of any reference

amplifier.

It is recommended to use a buffered reference in the external

circuit, for example, REF192. The input impedance is typically

45 kΩ.

OUTPUT AMPLIFIER

The output buffer amplifier is capable of generating rail-to-rail

voltages on its output, which gives an output range of 0 V to

VDD when the reference is VDD. The amplifier is capable of driving

a load of 2 kΩ to GND or VDD in parallel with 500 pF to GND

or VDD. The source and sink capabilities of the output amplifier

can be seen in the plot in Figure 14.

The slew rate is 0.7 V/μs with a half-scale settling time to

±0.5 LSB (at 8 bits) of 6 μs.

POWER-ON RESET

The AD5337/AD5338/AD5339 power on in a defined state via a

power-on reset function. The power-on state is normal operation,

with output voltage set to 0 V.

Both input and DAC registers are filled with zeros until a valid

write sequence is made to the device. This is particularly useful

in applications where it is important to know the state of the

DAC outputs while the device is powering on.

AD5337/AD5338/AD5339

Rev. C | Page 16 of 28

SERIAL INTERFACE

The AD5337/AD5338/AD5339 are controlled via an I2C®-

compatible serial bus. The DACs are connected to this bus as

slave devices, that is, no clock is generated by the AD5337/

AD5338/AD5339 DACs. This interface is SMBus compatible

at VDD < 3.6 V.

The AD5337/AD5338/AD5339 have a 7-bit slave address. The

six MSBs are 000110, and the LSB is determined by the state of

the A0 pin. The facility of making hardwired changes to A0

allows the use of one or two of these devices on one bus. The

AD5338-1 has a unique 7-bit slave address. The six MSBs are

010001, and the LSB is determined by the state of the A0 pin.

Using a combination of AD5338 and AD5338-1 allows the user

to accommodate four of these dual 10-bit devices (eight

channels) on the same bus.

The 2-wire serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a start

condition when a high-to-low transition on the SDA line

occurs while SCL is high. The following byte is the address

byte, which consists of the 7-bit slave address, followed by

an R/W bit. (This bit determines whether data is read from

or written to the slave device.)

The slave with the address corresponding to the transmitted

address responds by pulling SDA low during the ninth

clock pulse (this is termed the acknowledge bit). At this

stage, all other devices on the bus remain idle while the

selected device waits for data to be written to or read from

its shift register.

2. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits, followed by an acknowledge

bit). The transitions on the SDA line must occur during the

low period of SCL and remain stable during the high period

of SCL.

3. When all data bits have been read from or written to, a stop

condition is established. In write mode, the master pulls

the SDA line high during the 10th clock pulse to establish a

stop condition. In read mode, the master issues a No

Acknowledge for the ninth clock pulse, that is, the SDA

line remains high. The master then brings the SDA line low

before the 10th clock pulse and high during the 10th clock

pulse to establish a stop condition.

Read/Write Sequence

For the AD5337/AD5338/AD5339, all write access sequences

and most read sequences begin with the device address (with

R/W = 0), followed by the pointer byte. This pointer byte specifies

which DAC is being accessed in the subsequent read/write

operation (see Figure 31). In a write operation, the data follows

immediately. In a read operation, the address is resent with

R/W = 1, and then the data is read back. However, it is also

possible to perform a read operation by sending only the

address with R/W = 1. The previously loaded pointer settings

are then used for the readback operation. See Figure 32 for a

graphical explanation of the interface.

LSBMSB

0 DACB DACA

03756-031

Figure 31. Pointer Byte

Tabl e 6 explains the individual bits that make up the pointer byte.

Table 6. Pointer Byte Bits

Pointer Byte Bit Description

X Don’t care bits.

0 This bit is reserved and must be set to 0

DACB 1: The following data bytes are for DAC B.

DACA 1: The following data bytes are for DAC A.

Input Shift Register

The input shift register is 16 bits wide. Data is loaded into the

device as two data bytes on the serial data line, SDA, under the

control of the serial clock input, SCL. The timing diagram for this

operation is shown in Figure 2. The two data bytes consist of four

control bits followed by 8, 10, or 12 bits of DAC data, depending

on the device type. The first two bits loaded are Bit PD1 and

Bit PD0, which control the mode of operation of the device.

See the Power-Down Modes section for a complete description.

Bit 13 is CLR, Bit 12 is LDAC, and the remaining bits are left-

justified DAC data bits, starting with the MSB (see Figure 32).

Table 7. Input Shift Register

CLR 0 All DAC registers and input registers are

filled with 0s on completion of the write

sequence.

1 Normal operation.

LDAC 0 The two DAC registers and, therefore, all

DAC outputs, simultaneously updated on

completion of the write sequence.

Addressed input register only is updated.

There is no change in the contents of the

DAC registers.

AD5337/AD5338/AD5339

Rev. C | Page 17 of 28

Default Readback Condition

All pointer byte bits power up to 0. Therefore, if the user

initiates a readback without writing to the pointer byte first, no

single DAC channel has been specified. In this case, the default

readback bits are all 0s, except for the CLR bit, which is 1.

Multiple DAC Write Sequence

Because there are individual bits in the pointer byte for each

DAC, it is possible to write the same data and control bits to two

DACs simultaneously by setting the relevant bits to 1.

Multiple DAC Read Back Sequence

If the user attempts to read back data from more than one DAC

at a time, the part reads back the default, power-on reset

conditions, that is, all 0s except for CLR, which is 1.

WRITE OPERATION

When writing to the AD5337/AD5338/AD5339 DACs, the user

must begin with an address byte (R/W = 0), after which the

DAC acknowledges that it is prepared to receive data by pulling

SDA low. This address byte is followed by the pointer byte,

which is also acknowledged by the DAC. Two bytes of data are

then written to the DAC, as shown in Figure 33. A stop

condition follows.

PD0 CLR LDAC D7 D6 D5 D4

PD1

LSB

MSB

PD0 CLR LDAC D9 D8 D7 D6PD1

PD0 D11 D10 D9 D8PD1

MOST SIGNIFICANT DATA BYTE

8-BIT AD5337

LSB

MSB 10-BIT AD5338

LSB

MSB 12-BIT AD5339

CLR LDAC

ST SIGNIFICANT DATA BYTE

8-BIT AD5337

D3 D2 D1 D0 X

D5 D4 D3 D2 D1 D0 X X

D7 D6 D5 D4 D3 D2 D1 D0

LSB

MSB

LSB

MSB 10-BIT AD5338

LSB

MSB 12-BIT AD5339

XXX

03756-032

Figure 32. Data Formats for Write and Read Back

000 11XX

SCL

SDA

SCL

SDA

03756-033

START

CONDITION

MASTER

ADDRESS BYTE

A0 R/W

MSB

MOST SIGNIFICANT DATA BYTE

LSB

ACK

AD533x

MSBACK

AD533x POINTER BYTE

LSB

ACK

AD533x

MSB

LEAST SIGNIFICANT DATA BYTE

LSB

ACK

AD533x

STOP

CONDITION

MASTER

Figure 33. Write Sequence

AD5337/AD5338/AD5339

Rev. C | Page 18 of 28

READ OPERATION

When reading data back from the AD5337/AD5338/AD5339

DACs, the user begins with an address byte (R/W = 0), after

which the DAC acknowledges that it is prepared to receive data

by pulling SDA low. This address byte is usually followed by the

pointer byte, which is also acknowledged by the DAC. Then, the

master initiates another start condition (repeated start) and the

address is resent with R/W = 1. This is acknowledged by the

DAC indicating that it is prepared to transmit data. Two bytes

of data are then read from the DAC as shown in Figure 34. A

stop condition follows.

Note that in a read sequence, data bytes are the same as those in

the write sequence, except that don’t cares are read back as 0s.

However, if the master sends an ACK and continues clocking

SCL (no stop is sent), the DAC retransmits the same two bytes

of data on SDA. This allows continuous read back of data from

the selected DAC register. Alternatively, the user can send a

start followed by the address with R/W = 1. In this case, the

previously loaded pointer settings are used and read back of

data can begin immediately.

LEAST SIGNIFICANT DATA BYTE

000 11 X X

SCL

SDA

SCL

SDA 000 110A0

SCL

SDA

03756-034

START

CONDITION

MASTER

ADDRESS BYTE

A0 R/W

MSBACK

AD533x POINTER BYTE

LSB

ACK

AD533x

ADDRESS BYTE

REPEATED

START

CONDITION

MASTER

R/W

ACK

AD533x

MSB

DATA BYTE

LSB

ACK

MASTER

STOP

CONDITION

MASTER

ACK

MASTER

LSBMSB

Figure 34. Read Sequence

AD5337/AD5338/AD5339

Rev. C | Page 19 of 28

DOUBLE-BUFFERED INTERFACE

The AD5337/AD5338/AD5339 DACs have a double-buffered

interface consisting of two banks of registers—an input register

and a DAC register per channel. The input register is directly

connected to the input shift register, and the digital code is

transferred to the relevant input register upon completion of a

valid write sequence. The DAC register contains the digital code

used by the resistor string.

Access to the DAC register is controlled by the LDAC bit.

When the LDAC bit is set high, the DAC register is latched

and therefore, the input register can change state without

affecting the DAC register. This is useful if the user requires

simultaneous updating of all DAC outputs. The user can write

to three of the input registers individually; by setting the LDAC

bit low when writing to the remaining DAC input register, all

outputs update simultaneously.

These parts contain an extra feature whereby the DAC register

is only updated if its input register has been updated since the

last time that LDAC was brought low, thereby removing

unnecessary digital crosstalk.

POWER-DOWN MODES

The AD5337/AD5338/AD5339 have very low power consumption,

typically dissipating 0.75 mW with a 3 V supply and 1.5 mW

with a 5 V supply. Power consumption can be further reduced

when the DACs are not in use by putting them into one of three

power-down modes, which are selected by Bit 15 and Bit 14

(PD1 and PD0) of the data byte. Table 8 shows how the state of

the bits corresponds to the mode of operation of the DAC.

Table 8. PD1/PD0 Operating Modes

PD1 PD0 Operating Mode

0 0 Normal operation

0 1 Power-down (1 kΩ load to GND)

1 0 Power-down (100 kΩ load to GND)

1 1 Power-down (three-state output)

When both bits are 0, the DAC works with its normal power

consumption of 300 μA at 5 V. However, for the three power-

down modes, the supply current falls to 200 nA at 5 V (80 nA

at 3 V). Not only does the supply current drop, but the output

stage is also internally switched from the output of the amplifier

to a resistor network of known values. This is advantageous in

that the output impedance of the part is known while the part is

in power-down mode, which provides a defined input condition

for whatever is connected to the output of the DAC amplifier.

There are three options. The output can be connected internally

to GND through a 1 kΩ resistor, a 100 kΩ resistor, or can be left

open-circuited (three-state). Resistor tolerance = ±20%. The

output stage is illustrated in Figure 35.

AMPLIFIER V

OUT

03756-035

RESISTOR

NETWORK

POWER-DOWN

CIRCUITRY

RESISTOR

STRING DAC

Figure 35. Output Stage During Power-Down

The bias generator, output amplifiers, resistor string, and all

other associated linear circuitry are shut down when power-

down mode is activated. However, the contents of the DAC

registers remain unchanged when power-down mode is activated.

The time to exit power-down is typically 2.5 μs for VDD = 5 V

and 5 μs when VDD = 3 V. This is the time from the rising edge

of the eighth SCL pulse to the time when the output voltage

deviates from its power-down voltage (see Figure 21 for a plot).

AD5337/AD5338/AD5339

Rev. C | Page 20 of 28

APPLICATIONS

TYPICAL APPLICATION CIRCUIT

The AD5337/AD5338/AD5339 can be used with a wide

range of reference voltages for full, one-quadrant multiplying

capability over a reference range of 0 V to VDD. More typically,

these devices are used with a fixed precision reference voltage.

Suitable references for 5 V operation are the AD780, the REF192,

and the ADR391 (2.5 V references). For 2.5 V operation, a

suitable external reference would be the AD589 or AD1580, a

1.23 V band gap reference. Figure 36 shows a typical setup for

the AD5337/AD5338/AD5339 when using an external reference.

Note that A0 can be high or low.

GND

SDA

0.1µF

REFIN

10µF

1µF

SCL

OUT

03756-036

=2.5

TO 5.5

AD780/REF192/ADR391

WITH V

=5V OR

AD589/AD1580 WITH

=2.5V

AD5337/

AD5338/

AD5339

SERIAL

INTERFACE

EXT

REF

OUT

Figure 36. AD5337/AD5338/AD5339 Using External Reference

If an output range of 0 V to VDD is required, the simplest

solution is to connect the reference input to VDD. Because this

supply can be inaccurate and noisy, the AD5337/AD5338/

AD5339 can be powered from a reference voltage, for example,

using a 5 V reference such as the REF195, which provides a

steady output supply voltage. With no load on the DACs, the

REF195 is required to supply 600 μA supply current to the DAC

and 112 μA to the reference input. When the DAC outputs are

loaded, the REF195 also needs to supply the current to the loads;

therefore, the total current required with a 10 kΩ load on each

output is

712 μA + 2 × (5 V/10 kΩ) = 1.7 mA

The load regulation of the REF195 is typically 2 ppm/mA,

which results in an error of 3.4 ppm (17 μV) for the 1.7 mA

current drawn from it. This corresponds to a 0.0009 LSB error

at 8 bits and a 0.014 LSB error at 12 bits.

BIPOLAR OPERATION

The AD5337/AD5338/AD5339 are designed for single-supply

operation, but a bipolar output range is also possible using the

circuit in Figure 37. This circuit gives an output voltage range of

±5 V. Rail-to-rail operation at the amplifier output is achievable

using an AD820 or an OP295 as the output amplifier.

+5V

–5V

10µF

6V TO 12V

AD5339

0.1µF

R1 = 10kΩ

±5V

R2 = 10kΩ

GND

AD1585

+5V

GND

1µF

03756-037

AD820/

OP295

2-WIRE

SERIAL

INTERFACE

SDA

SCL

REFIN V

OUT

Figure 37. Bipolar Operation with the AD5339

The output voltage for any input code can be calculated as

follows:

⎥

⎦

⎤

⎢

⎣

⎡×−

⎟

⎠

⎞

⎜

⎝

⎛×=

REFIN

R2R1D

REFINV N

OUT 2

where:

D is the decimal equivalent of the code loaded to the DAC.

N is the DAC resolution.

REFIN is the reference voltage input.

With REFIN = 5 V, R1 = R2 = 10 kΩ:

VOUT = (10 × D/2N) − 5

MULTIPLE DEVICES ON ONE BUS

Figure 38 shows two AD5339 devices on the same serial bus.

Each has a different slave address because the state of the A0 pin

is different. This allows each of four DACs to be written to or

read from independently.

PULL-UP

RESISTORS

SCL

SDA

AD5339

SCL

SDA

MICROCONTROLLER

03756-038

Figure 38. Multiple AD5339 Devices on One Bus

AD5337/AD5338/AD5339

Rev. C | Page 21 of 28

PRODUCT AS A DIGITALLY PROGRAMMABLE

WINDOW DETECTOR

Figure 39 shows a digitally programmable upper/lower limit

detector using the two DACs in the AD5337/AD5338/AD5339.

The upper and lower limits for the test are loaded into DAC A

and DAC B, which, in turn, set the limits on the CMP04. If the

signal at the VIN input is not within the programmed window,

an LED indicates the fail condition.

GND

REFIN

PASS/FAIL

1/6 74HC05

FAIL PASS

1kΩ

0.1µF

SCL

SDA

SCL

DIN

1kΩ

10µF

03756-039

REF

ADDITIONAL PINS OMITTED FOR CLARITY.

AD5337/

AD5338/

AD5339

OUT

1/2

CMP04

Figure 39. Window Detection

COARSE AND FINE ADJUSTMENT CAPABILITIES

The two DACs in the AD5337/AD5338/AD5339 can be paired

together to form a coarse and fine adjustment function, as

shown in Figure 40. DAC A is used to provide the coarse

adjustment while DAC B provides the fine adjustment. Varying

the ratio of R1 and R2 changes the relative effect of the coarse

and fine adjustments. With the resistor values and external

reference shown, the output amplifier has unity gain for the

DAC A output, thus, the output range is 0 V to 2.5 V − 1 LSB.

For DAC B, the amplifier has a gain of 7.6 × 10–3, giving DAC B

a range equal to 19 mV.

The circuit is shown with a 2.5 V reference, but reference

voltages up to VDD can be used. The op amps indicated allow

a rail-to-rail output swing.

1µF

REFIN

GND

OUT

0.1µF 10µF

OUT

GND

3756-040

OUT

AD820/

OP295

390Ω

51.2kΩ

ADDITIONAL PINS OMITTED FOR CLARITY.

EXT

REF

OUT

AD5337/

AD5338/

AD5339

390Ω

51.2kΩ

AD780/REF192/ADR391

WITH V

=5V

Figure 40. Coarse/Fine Adjustment

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure

the rated performance. The printed circuit board on which the

AD5337/AD5338/AD5339 are mounted should be designed so

that the analog and digital sections are separated and confined

to certain areas of the board. If the AD5337/AD5338/AD5339

are in a system where multiple devices require an AGND-to-

DGND connection, the connection should be made at one

point only. The star ground point should be established as close

as possible to the device. The AD5337/AD5338/AD5339 should

have ample supply bypassing of 10 μF in parallel with 0.1 μF on

the supply located as close to the package as possible, ideally

right up against the device. The 10 μF capacitors are the tantalum

bead type. The 0.1 μF capacitor should have low effective series

resistance (ESR) and low effective series inductance (ESI) to

provide a low impedance path to ground at high frequencies to

handle transient currents due to internal logic switching. The

power supply lines of the AD5337/AD5338/AD5339 should use

as large a trace as possible to provide low impedance paths and

reduce the effects of glitches on the power supply line. Fast

switching signals such as clocks should be shielded with digital

ground to avoid radiating noise to other parts of the board, and

they should never be run near the reference inputs. A ground

line routed between the SDA and SCL lines helps to reduce

crosstalk between them. This is not required on a multilayer

board because there is a separate ground plane, but separating

the lines does help.

Avoid crossover of digital and analog signals. Traces on opposite

sides of the board should run at right angles to each other. This

reduces the effects of feedthrough on the board. Using a microstrip

technique is the best solution, but its use is not always possible

with a double-sided board. In this technique, the component

side of the board is dedicated to the ground plane, while signal

traces are placed on the solder side.

AD5337/AD5338/AD5339

Rev. C | Page 22 of 28

Table 9. Overview of All AD53xx Serial Devices

Part No. Resolution (Bits) No. of DACs DNL (LSBs) Interface Settling Time (μs) Package No. of Pins

Single

AD5300 8 1 ±0.25 SPI 4 SOT-23, MSOP 6, 8

AD5310 10 1 ±0.50 SPI 6 SOT-23, MSOP 6, 8

AD5320 12 1 ±1.00 SPI 8 SOT-23, MSOP 6, 8

AD5301 8 1 ±0.25 2-Wire 6 SOT-23, MSOP 6, 8

AD5311 10 1 ±0.50 2-Wire 7 SOT-23, MSOP 6, 8

AD5321 12 1 ±1.00 2-Wire 8 SOT-23, MSOP 6, 8

Dual

AD5302 8 2 ±0.25 SPI 6 MSOP 8

AD5312 10 2 ±0.50 SPI 7 MSOP 8

AD5322 12 2 ±1.00 SPI 8 MSOP 8

AD5303 8 2 ±0.25 SPI 6 TSSOP 16

AD5313 10 2 ±0.50 SPI 7 TSSOP 16

AD5323 12 2 ±1.00 SPI 8 TSSOP 16

AD5337 8 2 ±0.25 2-Wire 6 MSOP 8

AD5338 10 2 ±0.50 2-Wire 7 MSOP 8

AD5338-1 10 2 ±0.50 2-Wire 7 MSOP 8

AD5339 12 2 ±1.00 2-Wire 8 MSOP 8

Quad

AD5304 8 4 ±0.25 SPI 6 MSOP 10

AD5314 10 4 ±0.50 SPI 7 MSOP 10

AD5324 12 4 ±1.00 SPI 8 MSOP 10

AD5305 8 4 ±0.25 2-Wire 6 MSOP 10

AD5315 10 4 ±0.50 2-Wire 7 MSOP 10

AD5325 12 4 ±1.00 2-Wire 8 MSOP 10

AD5306 8 4 ±0.25 2-Wire 6 TSSOP 16

AD5316 10 4 ±0.50 2-Wire 7 TSSOP 16

AD5326 12 4 ±1.00 2-Wire 8 TSSOP 16

AD5307 8 4 ±0.25 SPI 6 TSSOP 16

AD5317 10 4 ±0.50 SPI 7 TSSOP 16

AD5327 12 4 ±1.00 SPI 8 TSSOP 16

Octal

AD5308 8 8 ±0.25 SPI 6 TSSOP 16

AD5318 10 8 ±0.50 SPI 7 TSSOP 16

AD5328 12 8 ±1.00 SPI 8 TSSOP 16

AD5337/AD5338/AD5339

Rev. C | Page 23 of 28

Table 10. Overview of AD53xx Parallel Devices

Additional Pin Functions

Part No. Resolution (Bits) DNL (LSBs)

No. of

VREF Pins

Settling

Time (μs) BUF GAIN HBEN CLR Package No. of Pins

Single

AD5300 8 ±0.25 1 6 * * * TSSOP 20

AD5331 10 ±0.50 1 7 * * TSSOP 20

AD5340 12 ±1.00 1 8 * * * TSSOP 24

AD5341 12 ±1.00 1 8 * * * * TSSOP 20

Dual

AD5332 8 ±0.25 2 6 * TSSOP 20

AD5333 10 ±0.50 2 7 * * * TSSOP 24

AD5342 12 ±1.00 2 8 * * * TSSOP 28

AD5343 12 ±1.00 1 8 * * TSSOP 20

Quad

AD5334 8 ±0.25 2 6 * * TSSOP 24

AD5335 10 ±0.50 2 7 * * TSSOP 24

AD5336 10 ±0.50 4 7 * * TSSOP 28

AD5344 12 ±1.00 4 8 TSSOP 28

Octal

AD5346 8 ±0.25 4 6 * * * TSSOP, LFCSP 38, 40

AD5347 10 ±0.50 4 7 * * * TSSOP, LFCSP 38, 40

AD5348 12 ±1.00 4 8 * * * TSSOP, LFCSP 38, 40

AD5337/AD5338/AD5339

Rev. C | Page 24 of 28

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-187-AA

0.80

0.60

0.40

8°

0°

PIN 1

0.65 BSC

SEATING

PLANE

0.38

0.22

1.10 MAX

3.20

3.00

2.80

COPLANARITY

0.10

0.23

0.08

3.20

3.00

2.80

5.15

4.90

4.65

0.15

0.00

0.95

0.85

0.75

Figure 41. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD5337ARM −40°C to +105°C 8-Lead MSOP RM-8 D23

AD5337ARM-REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D23

AD5337ARMZ1−40°C to +105°C 8-Lead MSOP RM-8 D23#

AD5337ARMZ-REEL71−40°C to +105°C 8-Lead MSOP RM-8 D23#

AD5337BRM-REEL −40°C to +105°C 8-Lead MSOP RM-8 D20

AD5337BRM-REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D20

AD5337BRMZ1−40°C to +105°C 8-Lead MSOP RM-8 D20#

AD5337BRMZ-REEL1−40°C to +105°C 8-Lead MSOP RM-8 D20#

AD5337BRMZ-REEL71−40°C to +105°C 8-Lead MSOP RM-8 D20#

AD5338ARM −40°C to +105°C 8-Lead MSOP RM-8 D24

AD5338ARMZ1−40°C to +105°C 8-Lead MSOP RM-8 D5F

AD5338ARMZ-REEL71−40°C to +105°C 8-Lead MSOP RM-8 D5F

AD5338ARMZ-11−40°C to +105°C 8-Lead MSOP RM-8 D57

AD5338ARMZ-1REEL71−40°C to +105°C 8-Lead MSOP RM-8 D57

AD5338BRM −40°C to +105°C 8-Lead MSOP RM-8 D21

AD5338BRM-REEL −40°C to +105°C 8-Lead MSOP RM-8 D21

AD5338BRM-REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D21

AD5338BRMZ1−40°C to +105°C 8-Lead MSOP RM-8 D5H

AD5338BRMZ-11−40°C to +105°C 8-Lead MSOP RM-8 D58

AD5338BRMZ-1REEL71−40°C to +105°C 8-Lead MSOP RM-8 D58

AD5339ARM −40°C to +105°C 8-Lead MSOP RM-8 D25

AD5339ARMZ1−40°C to +105°C 8-Lead MSOP RM-8 D6P

AD5339ARMZ-REEL71−40°C to +105°C 8-Lead MSOP RM-8 D6P

AD5339BRM −40°C to +105°C 8-Lead MSOP RM-8 D22

AD5339BRM-REEL −40°C to +105°C 8-Lead MSOP RM-8 D22

AD5339BRM-REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D22

AD5339BRMZ1−40°C to +105°C 8-Lead MSOP RM-8 D6R

AD5339BRMZ-REEL1−40°C to +105°C 8-Lead MSOP RM-8 D6R

AD5339BRMZ-REEL71−40°C to +105°C 8-Lead MSOP RM-8 D6R

1 Z = RoHS Compliant Part. # denotes lead-free product may be top or bottom marked.

AD5337/AD5338/AD5339

Rev. C | Page 25 of 28

NOTES

AD5337/AD5338/AD5339

Rev. C | Page 26 of 28

NOTES

AD5337/AD5338/AD5339

Rev. C | Page 27 of 28

NOTES

AD5337/AD5338/AD5339

Rev. C | Page 28 of 28

NOTES

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent

Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

registered trademarks are the property of their respective owners.

D03756-0-9/07(C)