DATA SH EET
Product specification
File under Integrated Circuits, IC06 December 1990
INTEGRATED CIRCUITS
74HC/HCT158
Quad 2-input multiplexer; inverting
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
Quad 2-input multiplexer; inverting 74HC/HCT158
FEATURES
•Inverting data path
•Output capability: standard
•ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT158 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT158 are quad 2-input multiplexers which
select 4 bits of data from two sources and are controlled by
a common data select input (S). The four outputs present
the selected data in the inverted form. The enable input (E)
is active LOW.
When E is HIGH, all the outputs (1Y to 4Y) are forced
HIGH regardless of all other input conditions.
Moving the data from two groups of registers to four
common output buses is a common use of the “158”. The
state of S determines the particular register from which the
data comes. It can also be used as a function generator.
The device is useful for implementing highly irregular logic
by generating any four of the 16 different functions of two
variables with one variable common.
The ”158” is the logic implementation of a 4-pole,
2-position switch, where the position of the switch is
determined by the logic levels applied to S.
The logic equations for the output are:
1Y = E.(1l1.S +1l0.S)
2Y = E.(2l1.S +2l0.S)
3Y = E.(3l1.S +3l0.S)
4Y = E.(4l1.S +4l0.S)
The “158” is identical to the “157” but has inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr= tf= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW):
PD= CPD ×VCC2×fi+∑(CL×VCC2×fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑(CL×VCC2×fo) = sum of outputs
CL= output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC −1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay CL= 15 pF; VCC = 5 V
nI0, nI1to nY 12 13 ns
E to nY1416ns
S to nY1416ns
C
I
input capacitance 3.5 3.5 pF
CPD power dissipation capacitance per multiplexer notes 1 and 2 40 40 pF
December 1990 3
Philips Semiconductors Product specification
Quad 2-input multiplexer; inverting 74HC/HCT158
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1 S common data select input
2, 5, 11, 14 1I0to 4I0data inputs from source 0
3, 6, 10, 13 1I1to 4I1data inputs from source 1
4, 7, 9, 12 1Y to 4Y multiplexer outputs
8 GND ground (0 V)
15 E enable input (active LOW)
16 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 4
Philips Semiconductors Product specification
Quad 2-input multiplexer; inverting 74HC/HCT158
Fig.4 Functional diagram.
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
INPUTS OUTPUT
ESnI
0nI1nY
HXXX H
LLLX H
LLHX L
LHXL H
LHXH L
Fig.5 Logic diagram.
December 1990 5
Philips Semiconductors Product specification
Quad 2-input multiplexer; inverting 74HC/HCT158
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr= tf= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nI0,nI
1to nY 41
15
12
125
25
21
155
31
26
190
38
32
ns 2.0
4.5
6.0
Fig.7
tPHL/ tPLH propagation delay
E to nY 47
17
14
145
29
25
180
36
31
220
44
38
ns 2.0
4.5
6.0
Fig.6
tPHL/ tPLH propagation delay
S to nY 47
17
14
145
29
25
180
36
31
220
44
38
ns 2.0
4.5
6.0
Fig.7
tTHL/ tTLH output transition
time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Figs 6 and 7
December 1990 6
Philips Semiconductors Product specification
Quad 2-input multiplexer; inverting 74HC/HCT158
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To
determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr= tf= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
nI00.40
nI10.40
S 2.80
E 0.60
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nI0, nI1to nY 16 30 38 45 ns 4.5 Fig.7
tPHL/ tPLH propagation delay
E to nY 19 35 44 53 ns 4.5 Fig.6
tPHL/ tPLH propagation delay
S to nY 19 35 44 53 ns 4.5 Fig.7
tTHL/ tTLH output transition
time 7 15 19 22 ns 4.5 Figs 6 and 7
December 1990 7
Philips Semiconductors Product specification
Quad 2-input multiplexer; inverting 74HC/HCT158
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.6 Waveforms showing the enable input (E) to output (nY) propagation delays and the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the data input (nI0, nI1) to output (nY) propagation delays and the output transition
times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Philips Semiconductors - PIP - 74HC/HCT158; Quad 2-input multiplexer; inverting
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Product Information
74HC/HCT158;
Quad 2-input
multiplexer;
inverting
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General description
The 74HC/HCT158 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT158 are quad 2-input multiplexers which select 4 bits of data from two sources and are
controlled by a common data select input (S). The four outputs present the selected data in the inverted form.
The enable input (E) is active LOW.
When E is HIGH, all the outputs (1Y to 4Y) are forced HIGH regardless of all other input conditions.
Moving the data from two groups of registers to four common output buses is a common use of the '158'. The
state of S determines the particular register from which the data comes. It can also be used as a function
generator.
The device is useful for implementing highly irregular logic by generating any four of the 16 different functions
of two variables with one variable common.
The '158' is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is
determined by the logic levels applied to S.
The logic equations for the output are:
1Y = E.(1l1.S + 1l0.S)
2Y = E.(2l1.S + 2l0.S)
3Y = E.(3l1.S + 3l0.S)
4Y = E.(4l1.S + 4l0.S)
The '158' is identical to the '157' but has inverting outputs.
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Philips Semiconductors - PIP - 74HC/HCT158; Quad 2-input multiplexer; inverting
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Features
● Inverting data path
● Output capability: standard
● ICC category: MSI
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Datasheet
Type number Title Publication
release date Datasheet status Page
count File
size
(kB)
Datasheet
74HC/HCT158 Quad 2-input
multiplexer;
inverting
12/1/1990 Product
specification 7 43
Download
PDF
File
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Additional datasheet info
To complete the device datasheet with package and family information, also download the following PDF files.
The "Logic Package Information" document is required to determine in which package(s) this device is
available.
Document Description
1
Download
PDF
File
HCT_FAMILY_SPECIFICATIONS HC/T Family Specifications, The IC06 74HC/HCT/HCMOS
Logic Family Specifications
2
Download
PDF
File
HCT_PACKAGE_INFO HC/T Package Info, The IC06 74HC/HCT/HCMOS Logic
Package Information
3
Download
PDF
File
HCT_PACKAGE_OUTLINES HC/T Package Outlines, The IC06 74HC/HCT/HCMOS Logic
Package Outlines
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Parametrics
Type
number Package Description Propagation
Delay(ns) Voltage No.
of
Pins
Power
Dissipation
Considerations
Logic
Switching
Levels
Output
Drive
Capability
74HC158D SOT109
(SO16)
Quad 2-
Input
Multiplexer;
Inverting
15 5 Volts
+16 Low Power or
Battery
Applications CMOS Low
74HC158N SOT38-1
(DIP16)
Quad 2-
Input
Multiplexer;
Inverting
15 5 Volts
+16 Low Power or
Battery
Applications CMOS Low
74HCT158D SOT109
(SO16)
Quad 2-
Input
Multiplexer;
Inverting;
TTL
Enabled
15 5 Volts
+16 Low Power or
Battery
Applications TTL Low
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Philips Semiconductors - PIP - 74HC/HCT158; Quad 2-input multiplexer; inverting
74HCT158N SOT38-1
(DIP16)
Quad 2-
Input
Multiplexer;
Inverting;
TTL
Enabled
15 5 Volts
+16 Low Power or
Battery
Applications TTL Low
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Products, packages, availability and ordering
Type
number North
American
type number
Ordering code
(12NC) Marking/Packing
Download
PDF
File
Discretes
packing info
Package Device status Buy online
74HC158D 74HC158D 9337 137 60652 Standard Marking
* Bulk Pack,
CECC
SOT109
(SO16) Full production
-
74HC158D-
T 9337 137 60653 Standard Marking
* Reel Pack,
SMD, 13", CECC
SOT109
(SO16) Full production
-
74HC158N 74HC158N 9336 693 50652 Standard Marking
* Bulk Pack,
CECC
SOT38-1
(DIP16) Full production
-
74HCT158D 74HCT158D 9337 137 70652 Standard Marking
* Bulk Pack,
CECC
SOT109
(SO16) Full production
-
74HCT158D-
T 9337 137 70653 Standard Marking
* Reel Pack,
SMD, 13", CECC
SOT109
(SO16) Full production
-
74HCT158N 74HCT158N 9336 699 80652 Standard Marking
* Bulk Pack,
CECC
SOT38-1
(DIP16) Full production
-
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Support & tools
Download
PDF
File
HC/T Family Specifications, The IC06 74HC/HCT/HCMOS Logic Family Specifications(date 01-Mar-
98)
Download
PDF
File
HC/T User Guide(date 01-Nov-97)
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