Quad, 12-Bit, 50/65 MSPS,
Serial, LVDS, 3 V A/D Converter
AD9229
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005–2010 Analog Devices, Inc. All rights reserved.
FEATURES
Four ADCs in 1 package
Serial LVDS digital output data rates
to 780 Mbps (ANSI-644)
Data and frame clock outputs
SNR = 69.5 dB (to Nyquist)
Excellent linearity
DNL = ±0.3 LSB (typical)
INL = ±0.4 LSB (typical)
400 MHz full power analog bandwidth
Power dissipation
1,350 mW at 65 MSPS
985 mW at 50 MSPS
1 V p-p to 2 V p-p input voltage range
3.0 V supply operation
Power-down mode
Digital test pattern enable for timing alignments
APPLICATIONS
Digital beam-forming systems for ultrasound
Wireless and wired broadband communications
Communication test equipment
FUNCTIONAL BLOCK DIAGRAM
AD9229
12
12
12
12
VIN+A
VIN–A
D+A
D–A
SHA PIPELINE
ADC SERIAL
LVDS
DATA RATE
MULTIPLIER
REF
SELECT
VIN+B
VIN–B
D+B
D–B
SHA PIPELINE
ADC SERIAL
LVDS
VIN+C
VIN–C
D+C
D–C
SHA PIPELINE
ADC SERIAL
LVDS
VIN+D
VIN–D
VREF
SENSE
D+D
D–D
0.5V FCO+
FCO–
DCO+
DCO–
SHA PIPELINE
ADC SERIAL
LVDS
REFT
REFB
AGND CLKLVDSBIAS
PDWN DTP DRVDD DRGND
04418-001
Figure 1.
GENERAL DESCRIPTION
The AD9229 is a quad, 12-bit, 65 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The product operates at up to a 65 MSPS conversion rate and is
optimized for outstanding dynamic performance in applications
where a small package size is critical.
The ADC requires a single 3 V power supply and TTL-/CMOS-
compatible sample rate clock for full performance operation.
No external reference or driver components are required for
many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock (DCO) for
capturing data on the output and a frame clock (FCO) trigger
for signaling a new output byte are provided. Power-down is
supported and typically consumes 3 mW when enabled.
Fabricated with an advanced CMOS process, the AD9229 is
available in a Pb-free, 48-lead LFCSP package. It is specified
over the industrial temperature range of –40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Four ADCs are contained in a small, space-saving package.
2. A data clock out (DCO) is provided, which operates up to
390 MHz and supports double-data rate operation (DDR).
3. The outputs of each ADC are serialized LVDS with data
rates up to 780 Mbps (12 bits × 65 MSPS).
4. The AD9229 operates from a single 3.0 V power supply.
5. Packaged in a Pb-free, 48-lead LFCSP package.
6. The internal clock duty cycle stabilizer maintains
performance over a wide range of input clock duty cycles.
AD9229
Rev. B | Page 2 of 40
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Specifications .......................................................................... 4
Digital Specifications ................................................................... 5
Switching Specifications .............................................................. 6
Timing Diagram ............................................................................... 7
Absolute Maximum Ratings ............................................................ 8
Explanation of Test Levels ........................................................... 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Equivalent Circuits ......................................................................... 10
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 18
Analog Input Considerations ................................................... 18
Clock Input Considerations ...................................................... 19
Evaluation Board ............................................................................ 24
Power Supplies ............................................................................ 24
Input Signals................................................................................ 24
Output Signals ............................................................................ 24
Default Operation and Jumper Selection Settings ................. 25
Alternate Analog Input Drive Configuration ......................... 25
Outline Dimensions ....................................................................... 39
Ordering Guide .......................................................................... 39
REVISION HISTORY
5/10—Rev. A to Rev. B
Change to Item 47 in Table 11 ...................................................... 38
Updated Outline Dimensions ....................................................... 39
Change to Ordering Guide ............................................................ 39
9/05—Rev. 0 to Rev. A
Change to Specifications .................................................................. 3
Changes to Differential Input Configurations Section .............. 19
Changes to Exposed Paddle Thermal Heat Slug
Recommendations Section ........................................................ 23
Changes to Evaluation Board Section .......................................... 24
Changes to Table 11 ........................................................................ 36
3/05—Revision 0: Initial Version
AD9229
Rev. B | Page 3 of 40
SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 1.
AD9229-50 AD9229-65
Parameter Temperature
Test
Level Min Typ Max Min Typ Max Unit
RESOLUTION 12 12 Bits
ACCURACY
No Missing Codes Full VI Guaranteed Guaranteed
Offset Error Full VI ±5 ±25 ±5 ±25 mV
Offset Matching Full VI ±5 ±25 ±5 ±25 mV
Gain Error1 Full VI ±0.3 ±2.5 ±0.3 ±2.5 % FS
Gain Matching1 Full VI ±0.2 ±1.5 ±0.2 ±1.5 % FS
Differential Nonlinearity (DNL) 25°C V ±0.3 ±0.3 LSB
Full VI ±0.3 ±0.6 ±0.3 ±0.7 LSB
Integral Nonlinearity (INL) 25°C V ±0.6 ±0.4 LSB
Full VI ±0.6 ±1 ±0.4 ±1 LSB
TEMPERATURE DRIFT
Offset Error Full V ±2 ±3 ppm/°C
Gain Error1 Full V ±12 ±12 ppm/°C
Reference Voltage, VREF = 1 V Full V ±16 ±16 ppm/°C
REFERENCE
Output Voltage Error, VREF = 1 V Full VI ±10 ±30 ±10 ±30 mV
Load Regulation @ 1.0 mA, VREF = 1 V Full V 3 3 mV
Output Voltage Error, VREF = 0.5 V Full VI ±8 ±17 ±8 ±17 mV
Load Regulation @ 0.5 mA,
VREF = 0.5 V
Full V 0.2 0.2 mV
Input Resistance Full V 7 7 kΩ
ANALOG INPUTS
Differential Input Voltage Range
VREF = 1 V
Full VI 2 2 V p-p
Differential Input Voltage Range
VREF = 0.5 V
Full VI 1 1 V p-p
Common Mode Voltage Full V 1.5 1.5 V
Input Capacitance2 Full V 7 7 pF
Analog Bandwidth, Full Power Full V 400 400 MHz
POWER SUPPLY
AVDD Full IV 2.7 3.0 3.6 2.7 3.0 3.6 V
DRVDD Full IV 2.7 3.0 3.6 2.7 3.0 3.6 V
IAVDD Full VI 300 330 420 455 mA
DRVDD Full VI 28 31 29 33 mA
Power Dissipation3 Full VI 985 1083 1350 1465 mW
Power-Down Dissipation Full V 3 3 mW
CROSSTALK4 Full V –95 –95 dB
1 Gain error and gain temperature coefficients are based on the ADC only, with a fixed 1.0 V external reference and a 2 V p-p differential analog input.
2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.
3 Power dissipation measured with rated encode and 2.4 MHz analog input at –0.5 dBFS.
4 Typical specification over the first Nyquist zone.
AD9229
Rev. B | Page 4 of 40
AC SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 2.
AD9229-50 AD9229-65
Parameter Temperature
Test
Level Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz Full IV 69.5 70.4 69.0 70.2 dB
f
IN = 10.3 MHz 25°C V 70.4 70.2 dB
f
IN = 25 MHz Full VI 68.7 69.6 dB
f
IN = 30 MHz Full VI 68.0 69.5 dB
f
IN = 70 MHz 25°C V 67.2 67.1 dB
SIGNAL-TO-NOISE RATIO (SINAD) fIN = 2.4 MHz Full V 70.0 69.8 dB
f
IN = 10.3 MHz 25°C V 70.0 69.8 dB
f
IN = 25 MHz Full VI 68.4 69.4 dB
f
IN = 30 MHz Full VI 67.3 69.0 dB
f
IN = 70 MHz 25°C V 66.8 66.7 dB
EFFECTIVE NUMBER OF BITS
(ENOB)
fIN = 2.4 MHz Full V 11.3 11.3 Bits
f
IN = 10.3 MHz 25°C V 11.3 11.3 Bits
f
IN = 25 MHz Full VI 11.1 11.2 Bits
f
IN = 30 MHz Full VI 10.9 11.2 Bits
f
IN = 70 MHz 25°C V 10.8 10.8 Bits
SPURIOUS-FREE DYNAMIC RANGE
(SFDR)
fIN = 2.4 MHz Full V 85 85 dBc
f
IN = 10.3 MHz 25°C V 85 85 dBc
f
IN = 25 MHz Full VI 76 85 dBc
f
IN = 30 MHz Full VI 73 85 dBc
f
IN = 70 MHz 25°C V 78 77 dBc
WORST HARMONIC fIN = 2.4 MHz Full V –85 –85 dBc
(Second or Third) fIN = 10.3 MHz 25°C V –85 –85 dBc
f
IN = 25 MHz Full VI –85 –76 dBc
f
IN = 30 MHz Full VI –85 –73 dBc
f
IN = 70 MHz 25°C V –78 –77 dBc
WORST OTHER fIN = 2.4 MHz Full V –90 –90 dBc
(Excluding Second or Third) fIN = 10.3 MHz 25°C V –90 –90 dBc
f
IN = 25 MHz Full VI –88 –81.7 dBc
f
IN = 30 MHz Full VI –88 –79.7 dBc
f
IN = 70 MHz 25°C V –85 –83 dBc
TWO-TONE INTERMODULATION
DISTORTION (IMD)
fIN1 = 15 MHz 25°C V –73 –73 dBc
AIN1 and AIN2 = –7.0 dBFS fIN2 = 16 MHz
f
IN1 = 69 MHz 25°C V –68.5 –68.5 dBc
f
IN2 = 70 MHz
AD9229
Rev. B | Page 5 of 40
DIGITAL SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 3.
AD9229-50 AD9229-65
Parameter Temperature
Test
Level Min Typ Max Min Typ Max Unit
CLOCK INPUT
Logic Compliance TTL/CMOS TTL/CMOS
High Level Input Voltage Full IV 2.0 2.0 V
Low Level Input Voltage Full IV 0.8 0.8 V
High Level Input Current Full VI 0.5 ±10 0.5 ±10 µA
Low Level Input Current Full VI 0.5 ±10 0.5 ±10 µA
Input Capacitance 25°C V 2 2 pF
LOGIC INPUTS (PDWN)
Logic 1 Voltage Full IV 2.0 2.0 V
Logic 0 Voltage Full IV 0.8 0.8 V
High Level Input Current Full IV 0.5 ±10 0.5 ±10 µA
Low Level Input Current Full IV 0.5 ±10 0.5 ±10 µA
Input Capacitance 25°C V 2 2 pF
DIGITAL OUTPUTS (D+, D–)
Logic Compliance LVDS LVDS
Differential Output Voltage Full VI 260 440 260 440 mV
Output Offset Voltage Full VI 1.15 1.25 1.35 1.15 1.25 1.35 V
Output Coding Full VI Offset
binary
Offset
binary
AD9229
Rev. B | Page 6 of 40
SWITCHING SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 4.
AD9229-50 AD9229-65
Parameter Temp
Test
Level Min Typ Max Min Typ Max Unit
CLOCK
Maximum Clock Rate Full VI 50 65 MSPS
Minimum Clock Rate Full IV 10 10 MSPS
Clock Pulse Width High
(tEH)
Full VI 8 10 6.2 7.7 ns
Clock Pulse Width Low
(tEL)
Full VI 8 10 6.2 7.7 ns
OUTPUT PARAMETERS
Propagation Delay (tPD) Full VI 3.3 6.5 7.9 3.3 6.5 7.9 ns
Rise Time (tR)
(20% to 80%)
Full V 250 250 ps
Fall Time (tF)
(20% to 80%)
Full V 250 250 ps
FCO Propagation Delay
(tFCO)
Full V 6.5 6.5 ns
DCO Propagation Delay
(tCPD)
Full V tFCO +
(tSAMPLE/24)
t
FCO +
(tSAMPLE/24)
ns
DCO-to-Data Delay (tDATA) Full IV (tSAMPLE/24) –
250
(tSAMPLE/24) (tSAMPLE/24) +
250
(tSAMPLE/24) –
250
(tSAMPLE/24) (tSAMPLE/24) +
250
ps
DCO-to-FCO Delay (tFRAME) Full IV (tSAMPLE/24) –
250
(tSAMPLE/24) (tSAMPLE/24) +
250
(tSAMPLE/24) –
250
(tSAMPLE/24) (tSAMPLE/24) +
250
ps
Data-to-Data Skew
(tDATA-MAX – tDATA-MIN)
Full IV ±100 ±250 ±100 ±250 ps
Wake-Up Time 25°C V 4 4 ms
Pipeline Latency Full IV 10 10 CLK
cycles
APERTURE
Aperture Delay (tA) 25°C V 1.8 1.8 ns
Aperture Uncertainty
(Jitter)
25°C V <1 <1 ps
rms
OUT-OF-RANGE RECOVERY
TIME
25°C V 2 2 CLK
cycles
AD9229
Rev. B | Page 7 of 40
TIMING DIAGRAM
DCO–
DCO+
D–
D+
FCO–
FCO+
AIN
CLK
N–1
N
t
EH
t
CPD
t
DATA
MSB
(N – 10)
D10
(N–10)
D9
(N–10)
D8
(N – 10)
D7
(N – 10)
D6
(N – 10)
D5
(N – 10)
D4
(N–10)
D3
(N – 10)
D2
(N – 10)
D1
(N – 10)
D0
(N–10)
D10
(N – 9)
MSB
(N – 9)
t
FCO
t
PD
t
EL
t
A
04418-002
t
FRAME
Figure 2. Timing Diagram
AD9229
Rev. B | Page 8 of 40
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
With
Respect To Rating
ELECTRICAL
AVDD AGND –0.3 V to +3.9 V
DRVDD DRGND –0.3 V to +3.9 V
AGND DRGND –0.3 V to +0.3 V
AVDD DRVDD –3.9 V to +3.9 V
Digital Outputs (D+, D–,
DCO+, DCO–, FCO+, FCO–)
DRGND –0.3 V to DRVDD
LVDSBIAS DRGND –0.3 V to DRVDD
CLK AGND –0.3 V to AVDD
VIN+, VIN– AGND –0.3 V to AVDD
PDWN, DTP AGND –0.3 V to AVDD
REFT, REFB AGND –0.3 V to AVDD
VREF, SENSE AGND –0.3 V to AVDD
ENVIRONMENTAL
Operating Temperature
Range (Ambient)
–40°C to +85°C
Maximum Junction
Temperature
150°C
Lead Temperature
(Soldering, 10 sec)
300°C
Storage Temperature Range
(Ambient)
–65°C to +150°C
Thermal Impedance1 25°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
I. 100% production tested.
II. 100% production tested at 25°C and guaranteed by design
and characterization at specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C and guaranteed by design
and characterization for industrial temperature range.
1 θJA for a 4-layer PCB with a solid ground plane in still air.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD9229
Rev. B | Page 9 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13
14
15
16
17
18
19
20
21
22
23
24
VIN–B
VIN+B
AGND
AVDD
SENSE
VREF
REFB
REFT
AVDD
AGND
VIN+C
VIN–C
48
47
46
45
44
43
42
41
40
39
38
37
DCO+
DCO–
FCO+
FCO–
D+A
D–A
D+B
D–B
D+C
D–C
D+D
D–D
1
2
3
4
5
6
7
8
9
10
11
12
DRGND
DRVDD
NC
DTP
AVDD
AGND
PDWN
AVDD
AGND
VIN+A
VIN–A
AGND
DRVDD
LVDSBIAS
AGND
AVDD
AGND
CLK
AVDD
AGND
VIN+D
VIN–D
AGND
35 DRGND36
34
33
32
31
30
29
28
27
26
25
AD9229
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
EXPOSED PADDLE, PIN 0
(Bottom of Package)
04418-003
NC = NO CONNECT
Figure 3. LFCSP Top View
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
5, 8, 16, 21,
29, 32
AVDD Analog Supply
6, 9, 12, 15, 22,
25, 28, 31, 33
AGND Analog Ground
2, 35 DRVDD Digital Output Supply
1, 36 DRGND Digital Ground
0 AGND
Exposed Paddle/Thermal Heat
Slug (Located on Bottom of
Package)
3 NC No Connect
4 DTP Digital Test Pattern Enable
7 PDWN
Power-Down Selection (AVDD =
Power Down)
10 VIN+A ADC A Analog Input—True
11 VIN–A
ADC A Analog Input—
Complement
13 VIN–B
ADC B Analog Input—
Complement
14 VIN+B ADC B Analog Input—True
17 SENSE Reference Mode Selection
18 VREF Voltage Reference Input/Output
19 REFB Differential Reference (Bottom)
20 REFT Differential Reference (Top)
23 VIN+C ADC C Analog Input—True
24 VIN–C
ADC C Analog Input—
Complement
Pin No. Mnemonic Description
26 VIN–D
ADC D Analog Input—
Complement
27 VIN+D ADC D Analog Input—True
30 CLK Input Clock
34 LVDSBIAS
LVDS Output Current Set
Resistor Pin
37 D–D
ADC D Complement Digital
Output
38 D+D ADC D True Digital Output
39 D–C
ADC C Complement Digital
Output
40 D+C ADC C True Digital Output
41 D–B
ADC B Complement Digital
Output
42 D+B ADC B True Digital Output
43 D–A
ADC A Complement Digital
Output
44 D+A ADC A True Digital Output
45 FCO–
Frame Clock Indicator—
Complement Output
46 FCO+
Frame Clock Indicator—True
Output
47 DCO–
Data Clock Output—
Complement
48 DCO+ Data Clock Output—True
AD9229
Rev. B | Page 10 of 40
EQUIVALENT CIRCUITS
AVDD
AGND
VIN+, VIN–
04418-004
Figure 4. Equivalent Analog Input Circuit
AVDD
170Ω
AGND
C
L
K
04418-005
Figure 5. Equivalent Clock Input Circuit
AVDD
375Ω
AGND
PDWN
04418-006
Figure 6. Equivalent Digital Input Circuit
DRVDD
DRGND
D– D+
V
V
04418-007
V
V
Figure 7. Equivalent Digital Output Circuit
AVDD
375Ω100kΩ
AGND
DTP
04418-051
Figure 8. Equivalent DTP Input Circuit
AD9229
Rev. B | Page 11 of 40
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0
–20
–40
–60
–80
–120
–100
0 8.14.1 12.2 16.3 20.3 24.4 28.4 32.5
04418-009
AIN = –0.5dBFS
SNR = 70.4dB
ENOB = 11.4 BITS
SFDR = 85.8dBC
Figure 9. Single-Tone 32k FFT with fIN = 2.4 MHz, fSAMPLE = 65 MSPS
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0
–20
–40
–60
–80
–120
–100
0 8.14.1 12.2 16.3 20.3 24.4 28.4 32.5
04418-010
AIN = –0.5dBFS
SNR = 69.6dB
ENOB = 11.3 BITS
SFDR = 82.4dBC
Figure 10. Single-Tone 32k FFT with fIN = 30 MHz, fSAMPLE = 65 MSPS
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0
–20
–40
–60
–80
–120
–100
0 8.14.1 12.2 16.3 20.3 24.4 28.4 32.5
04418-011
AIN = –0.5dBFS
SNR = 68.5dB
ENOB = 11.1 BITS
SFDR = 81.3dBC
Figure 11. Single-Tone 32k FFT with fIN = 70 MHz, fSAMPLE = 65 MSPS
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0
–20
–40
–60
–80
–120
–100
0 8.14.1 12.2 16.3 20.3 24.4 28.4 32.5
04418-012
AIN = –0.5dBFS
SNR = 68.1dB
ENOB = 11.0 BITS
SFDR = 77.0dBC
Figure 12. Single-Tone 32k FFT with fIN = 120 MHz, fSAMPLE = 65 MSPS
ENCODE (MSPS)
SNR/SFDR (dB)
90
85
80
75
70
60
65
10 2015 25 30 35 40 45 50
04418-013
2V p-p, SNR (dB)
1V p-p, SFDR (dBc)
1V p-p, SNR (dB)
2V p-p, SFDR (dBc)
AIN = –0.5dBFS
Figure 13. SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz, fSAMPLE = 50 MSPS
ENCODE (MSPS)
SNR/SFDR (dB)
90
85
80
75
70
60
65
10 2015 25 30 35 40 45 50
04418-014
2V p-p, SNR (dB)
1V p-p, SFDR (dBc)
1V p-p, SNR (dB)
2V p-p, SFDR (dBc)
AIN = –0.5dBFS
Figure 14. SNR/SFDR vs. fSAMPLE, fIN = 25 MHz, fSAMPLE = 50 MSPS
AD9229
Rev. B | Page 12 of 40
ENCODE (MSPS)
SNR/SFDR (dB)
95
90
85
80
75
70
60
65
10 2015 25 30 35 40 45 6550 55 60
04418-015
2V p-p, SNR (dB)
1V p-p, SFDR (dBc)
1V p-p, SNR (dB)
2V p-p, SFDR (dBc)
AIN = –0.5dBFS
Figure 15. SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz, fSAMPLE = 65 MSPS
ENCODE (MSPS)
SNR/SFDR (dB)
85
80
75
70
60
65
10 2015 25 30 35 40 45 6550 55 60
04418-016
2V p-p, SNR (dB)
1V p-p, SFDR (dBc)
1V p-p, SNR (dB)
2V p-p, SFDR (dBc)
AIN = –0.5dBFS
Figure 16. SNR/SFDR vs. fSAMPLE, fIN = 30 MHz, fSAMPLE = 65 MSPS
ANALOG INPUT LEVEL (dBFS)
SNR/SFDR (dB)
90
80
70
60
40
30
50
10
0
20
–60 –10–20–30–40–50 0
04418-017
80 dB REFERENCE
1V p-p, SFDR (dBc)
1V p-p, SNR (dB)
2V p-p, SFDR (dBc)
2V p-p, SNR (dB)
Figure 17. SNR/SFDR vs. Analog Input Level,
fIN = 10.3 MHz, fSAMPLE = 50 MSPS
ANALOG INPUT LEVEL (dBFS)
SNR/SFDR (dB)
90
80
70
60
40
30
50
10
0
20
–60 –10–20–30–40–50 0
04418-018
80 dB REFERENCE
1V p-p, SFDR (dBc)
1V p-p, SNR (dB)
2V p-p, SFDR (dBc)
2V p-p, SNR (dB)
Figure 18. SNR/SFDR vs. Analog Input Level,
fIN =25 MHz, fSAMPLE = 50 MSPS
ANALOG INPUT LEVEL (dBFS)
SNR/SFDR (dB)
90
80
70
60
40
30
50
10
0
20
–60 –10–20–30–40–50 0
04418-019
80 dB REFERENCE
1V p-p, SFDR (dBc)
1V p-p, SNR (dB)
2V p-p, SFDR (dBc)
2V p-p, SNR (dB)
Figure 19. SNR/SFDR vs. Analog Input Level,
fIN = 10.3 MHz, fSAMPLE = 65 MSPS
ANALOG INPUT LEVEL (dBFS)
SNR/SFDR (dB)
90
80
70
60
40
30
50
10
0
20
–60 –10–20–30–40–50 0
04418-020
80 dB REFERENCE
1V p-p, SFDR (dBc)
1V p-p, SNR (dB)
2V p-p, SFDR (dBc)
2V p-p, SNR (dB)
Figure 20. SNR/SFDR vs. Analog Input Level,
fIN = 30 MHz, fSAMPLE = 65 MSPS
AD9229
Rev. B | Page 13 of 40
FREQUENCY (MHz)
SNR/SFDR (dB)
90
85
80
75
65
60
70
50
45
55
1 10010 1000
04418-021
SFDR (dBc)
SNR (dB)
Figure 21. SNR/SFDR vs. fIN, fSAMPLE = 65 MHz
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0
–20
–40
–60
–80
–120
–100
0 8.14.1 12.2 16.3 20.3 24.4 28.4 32.5
04418-022
AIN1 AND AIN2= –7.0dBFS
SFDR = 73.0dBc
IMD2 = 80.5dBc
IMD3 = 73.0dBc
Figure 22. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz,
fSAMPLE = 65 MSPS
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0
–20
–40
–60
–80
–120
–100
0 8.14.1 12.2 16.3 20.3 24.4 28.4 32.5
04418-023
AIN1 AND AIN2= –7.0dBFS
SFDR = 68.5dBc
IMD2 = 77.0dBc
IMD3 = 68.5dBc
Figure 23. Two-Tone 32k FFT with fIN1 = 69 MHz and fIN2 = 70 MHz,
fSAMPLE = 65 MSPS
ANALOG INPUT LEVEL (dBFS)
SFDR (dB)
80
70
60
40
30
50
10
0
20
–60 –19 –10–28–36–44–52–56 –15–23–32–40–48 –7
04418-024
80 dB REFERENCE
2V p-p, SFDR (dBc)
1V p-p, SFDR (dBc)
Figure 24. Two-Tone SFDR vs. Analog Input Level, fIN1 = 15 MHz and
fIN2 = 16 MHz, fSAMPLE = 65 MSPS
ANALOG INPUT LEVEL (dBFS)
SFDR (dB)
80
70
60
40
30
50
10
0
20
–60 –19 –10–28–36–44–52–56 –15–23–32–40–48 –7
04418-025
80 dB REFERENCE
2V p-p, SFDR (dBc)
1V p-p, SFDR (dBc)
Figure 25. Two-Tone SFDR vs. Analog Input Level, fIN1 = 69 MHz and
fIN2 = 70 MHz, fSAMPLE = 65 MSPS
TEMPERATURE (°C)
SNR/SFDR (dB)
90
85
75
80
65
60
70
–40 60 8040200–20
04418-026
2V p-p, SFDR (dBc)
2V p-p, SINAD (dB)
1V p-p, SINAD (dB)
1V p-p, SFDR (dBc)
Figure 26. SINAD/SFDR vs. Temperature, fIN 10.3 MHz, fSAMPLE = 65 MSPS
AD9229
Rev. B | Page 14 of 40
TEMPERATURE (°C)
GAIN ERROR (ppm/°C)
15
10
0
5
–10
–15
–20
–5
–40 60 8040200–20
04418-027
Figure 27. Gain Error vs. Temperature
CODE
INL (LSB)
0.5
0
0.1
0.2
0.3
0.4
–0.1
–0.2
–0.3
–0.5
–0.4
0 1024512 1536 2048 2560 3072 3584 4095
04418-028
Figure 28. Typical INL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS
CODE
DNL (LSB)
0.5
0
0.1
0.2
0.3
0.4
–0.1
–0.2
–0.3
–0.5
–0.4
0 1024512 1536 2048 2560 3072 3584 4095
04418-030
Figure 29. Typical DNL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS
FREQUENCY (MHz)
CMRR (dB)
–40
–60
–50
–70
–80 022015105
04418-031
530
Figure 30. CMRR vs. Frequency, fSAMPLE = 65 MSPS
CODE
NUMBER OF HITS (1M)
10
9
8
7
6
4
5
0
3
2
1
N– 2N – 3 N – 1 N N + 1 N + 2 N + 3
04418-039
0.36LSB rms
Figure 31. Input Referred Noise Histogram, fSAMPLE = 65 MSPS
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0
–20
–40
–60
–80
–120
–100
0 8.14.1 12.2 16.3 20.3 24.4 28.4 32.5
04418-035
NPR = 60.8dB
NOTCH = 18MHz
NOTCH WIDTH = 3MHz
Figure 32. Noise Power Ratio (NPR), fSAMPLE = 65 MSPS
AD9229
Rev. B | Page 15 of 40
FREQUENCY (MHz)
FUNDAMENTAL LEVEL (dB)
0
–6
–5
–7
–8
–2
–1
–3
–4
0 450 500400350
300250200
15010050
04418-038
Figure 33. Full Power Bandwidth vs. Frequency, fSAMPLE = 65 MSPS
AD9229
Rev. B | Page 16 of 40
TERMINOLOGY
Analog Bandwidth
Analog bandwidth is the analog input frequency at which the
spectral power of the fundamental frequency (as determined by
the FFT analysis) is reduced by 3 dB from full scale.
Aperture Delay
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the 50% point rising
edge of the clock input to the time at which the input signal is
held for conversion.
Aperture Uncertainty (Jitter)
Aperture jitter is the variation in aperture delay for successive
samples and can be manifested as frequency-dependent noise
on the ADC input.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Common Mode Rejection Ratio (CMRR)
CMRR is defined as the amount of rejection on the differential
analog inputs when a common signal is applied. Typically
expressed as 20 log (differential gain/common-mode gain).
Crosstalk
Crosstalk is defined as the measure of any feedthrough coupling
onto the quiet channel when all other channels are driven by a
full-scale signal.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a pin and
subtracting the voltage from a second pin that is 180° out of
phase.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to an n-bit resolution indicates that all 2n
codes, respectively, must be present over all operating ranges.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the
number of bits. Using the following formula, it is possible to
obtain a measure of performance expressed as N, the effective
number of bits:
N = (SINAD – 1.76)/6.02
Full Power Bandwidth
Full power bandwidth is the measured –3 dB point at the analog
front-end input relative to the frequency measured.
Gain Error
The largest gain error is specified and is considered the
difference between the measured and ideal full-scale input
voltage range.
Gain Matching
Expressed as a percentage of FSR and computed using the
following equation:
%100
2
minmax
minmax ×
⎟
⎠
⎞
⎜
⎝
⎛+
−
=FSRFSR
FSRFSR
MatchingGain
where FSRMAX is the most positive gain error of the ADCs, and
FSRMIN is the most negative gain error of the ADCs.
Input-Referred Noise
Input-referred noise is a measure of the wideband noise
generated by the ADC core. Histograms of the output codes are
created while a dc signal is applied to the ADC input. Input-
referred noise is calculated using the standard deviation of the
histograms and presented in terms of LSB rms.
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs 0.5 LSB before the first
code transition. Positive full scale is defined as a level 1.5 LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line.
Noise Power Ratio (NPR)
NPR is the full-scale rms noise power injected into the ADC vs.
the rejected band of interest (notch depth measured).
Offset Error
The largest offset error is specified and is considered the
difference between the measured and ideal voltage at the analog
input that produces the midscale code at the outputs.
Offset Matching
Expressed in millivolts and computed using the following
equation:
Offset Matching = OFFMAX − OFFMIN
where OFFMAX is the most positive offset error, and OFFMIN is
the most negative offset error.
AD9229
Rev. B | Page 17 of 40
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.
Output Propagation Delay
The delay between the clock logic threshold and the time when
all bits are within valid logic levels.
Second and Third Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the
second or third harmonic component, reported in decibels
relative to the carrier.
Signal-to Noise and Distortion (SINAD) Ratio
SINAD is the ratio of the rms value of the measured input
signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc.
The value for SINAD is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference in decibels between the rms amplitude of
the input signal and the peak spurious signal.
Tem p er atu r e D ri f t
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at TMIN or TMAX.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. It may be reported in
decibels relative to the carrier (that is, degrades as signal levels
are lowered) or in decibels relative to full scale (always related
back to converter full scale).
AD9229
Rev. B | Page 18 of 40
THEORY OF OPERATION
The AD9229 architecture consists of a front-end switched capa-
citor sample-and-hold amplifier (SHA) followed by a pipelined
ADC. The pipelined ADC is divided into three sections: a 4-bit
first stage followed by eight 1.5-bit stages and a final 3-bit flash.
Each stage provides sufficient overlap to correct for flash errors
in the preceding stages. The quantized outputs from each stage
are combined into a final 12-bit result in the digital correction
logic. The pipelined architecture permits the first stage to
operate on a new input sample while the remaining stages
operate on preceding samples. Sampling occurs on the rising
edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be config-
ured as ac- or dc-coupled in differential or single-ended modes.
The output staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The data is
then serialized and aligned to the frame and output clock.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9229 is a differential switched-
capacitor SHA that has been designed for optimum perfor-
mance while processing a differential input signal. The SHA
input can support a wide common-mode range and maintain
excellent performance. An input common-mode voltage of
midsupply minimizes signal-dependent errors and provides
optimum performance.
04418-029
H
H
VIN+
VIN–
C
PAR
C
PAR
S
S
S
S
Figure 34. Switched-Capacitor SHA Input
The clock signal alternately switches the SHA between sample
mode and hold mode (see Figure 34). When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can
be placed across the inputs to provide dynamic charging
currents. This passive network creates a low-pass filter at the
ADC’s input; therefore, the precise values are dependent on
the application.
The analog inputs of the AD9229 are not internally dc-biased.
In ac-coupled applications, the user must provide this bias
externally. For optimum performance, set the device so that
VCM = AV D D /2; however, the device can function over a wider
range with reasonable performance (see Figure 35 and Figure 36).
ANALOG INPUT COMMON-MODE VOLTAGE (V)
SNR/SFDR (dB)
90
85
75
80
65
60
70
0 2.5 3.02.01.51.00.5
04418-053
2V p-p, SFDR (dBc)
2V p-p, SNR (dB)
1V p-p, SNR (dB)
1V p-p, SFDR (dBc)
Figure 35. SNR/SFDR vs. Common-Mode Voltage, fIN = 2.4 MHz,
fSAMPLE = 65 MSPS
ANALOG INPUT COMMON-MODE VOLTAGE (V)
SNR/SFDR (dB)
90
65
55
60
45
40
50
85
75
80
70
0 2.5 3.02.01.51.00.5
04418-054
2V p-p, SFDR (dBc)
2V p-p, SNR (dB)
1V p-p, SNR (dB)
1V p-p, SFDR (dBc)
Figure 36. SNR/SFDR vs. Common-Mode Voltage, fIN = 30 MHz,
fSAMPLE = 65 MSPS
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
AD9229
Rev. B | Page 19 of 40
An internal reference buffer creates the positive and negative
reference voltages, REFT and REFB, respectively, that defines
the span of the ADC core. The output common-mode of the
reference buffer is set to midsupply, and the REFT and REFB
voltages and span are defined as
REFT = 1/2 (AV D D + VREF)
REFB = 1/2 (AV D D − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the
VREF voltage.
The internal voltage reference can be pin-strapped to fixed
values of 0.5 V or 1.0 V or adjusted within the same range, as
discussed in the Internal Reference Connection section.
Maximum SNR performance is achieved by setting the AD9229
to the largest input span of 2 V p-p.
The SHA should be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined in Figure 35 and Figure 36.
Differential Input Configurations
Optimum performance is achieved by driving the AD9229 in a
differential input configuration. For ultrasound applications,
the AD8332 differential driver provides excellent performance
and a flexible interface to the ADC (see Figure 37).
AD8332
1.0kΩ
1.0kΩ
374Ω
187Ω
04418-032
AD9229
VIN+
VIN–
AVDD
AGND
R
R
C
0.1μF
187nH VREF
0.1μF
0.1μF0.1μF
0.1μF10μF
0.1μF
1V p-p 0.1μF
AVDD
LNA
120nH
VGA
VOH
VIP
INH
22p
LMD
VIN
LOP
LON
VOL
18nF 274Ω
Figure 37. Differential Input Configuration Using the AD8332
However, the noise performance of most amplifiers is not
adequate to achieve the true performance of the AD9229. For
applications where SNR is a key parameter, differential transfor-
mer coupling is the recommended input configuration. An
example of this is shown in Figure 38.
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and may need to be reduced
or removed.
04418-033
AD9229
VIN+
VIN–
AVDD
AGND
2
Vp-p
R
R
C
49.9Ω
0.1μF
1kΩ
1kΩ
AVDD
Figure 38. Differential Transformer—Coupled Configuration
Single-Ended Input Configuration
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input
common-mode swing. However, if the source impedances
on each input are matched, there should be little effect on
SNR performance. Figure 39 details a typical single-ended
input configuration.
04418-034
2V p-p
R
R
C
49.9Ω0.1μF
10μF
10μF 0.1μF
AD9229
VIN+
VIN–
AVDD
AGND
AVDD
1kΩ
1kΩ
1kΩ
1kΩ
Figure 39. Single-Ended Input Configuration
CLOCK INPUT CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensi-
tive to clock duty cycle. Typically, a 10% tolerance is required on
the clock duty cycle to maintain dynamic performance charac-
teristics. The AD9229 has a self-contained clock duty cycle
stabilizer that retimes the nonsampling edge, providing an
internal clock signal with a nominal 50% duty cycle. This allows
a wide range of clock input duty cycles without affecting the
performance of the AD9229.
An on-board phase-locked loop (PLL) multiplies the input
clock rate for the purpose of shifting the serial data out. The
stability criteria for the PLL limits the minimum sample clock
rate of the ADC to 10 MSPS. Assuming steady state operation of
the input clock, any sudden change in the sampling rate could
create an out-of-lock condition leading to invalid outputs at the
DCO, FCO, and data out pins.
AD9229
Rev. B | Page 20 of 40
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (fA) due only to aperture jitter (tA) can be
calculated with the following equation:
SNR degradation = 20 × log 10 [1/2 × π × fA × tA]
In the equation, the rms aperture jitter, tA, represents the root
sum square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification.
Applications that require undersampling are particularly
sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9229. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other
methods), it should be retimed by the original clock at the
last step.
Power Dissipation and Power-Down Mode
As shown in Figure 40 and Figure 41, the power dissipated by
the AD9229 is proportional to its sample rate. The digital power
dissipation does not vary much because it is determined
primarily by the DRVDD supply and bias current of the LVDS
output drivers.
ENCODE (MSPS)
POWER (mW)
1200
900
800
600
700
1000
1100
CURRENT (mA)
350
250
0
100
50
200
150
300
10 5040 4530 3520 2515
04418-056
I
AVDD
TOTAL POWER
I
DRVDD
Figure 40. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 50 MSPS
ENCODE (MSPS)
POWER (mW)
1400
1100
1000
800
900
1200
1300
CURRENT (mA)
500
300
250
200
0
50
150
100
350
400
450
10 50 60403020
04418-055
I
AVDD
TOTAL POWER
I
DRVDD
Figure 41. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 65 MSPS
By asserting the PDWN pin high, the AD9229 is placed in
power-down mode. In this state, the ADC typically dissipates
3 mW. During power-down, the LVDS output drivers are placed
in a high impedance state. Reasserting the PDWN pin low
returns the AD9229 to normal operating mode.
In power-down mode, low power dissipation is achieved by
shutting down the reference, reference buffer, PLL, and biasing
networks. The decoupling capacitors on REFT and REFB are
discharged when entering standby mode and then must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in the power-down
mode; shorter cycles result in proportionally shorter wake-up
times. With the recommended 0.1 μF and 10 μF decoupling
capacitors on REFT and REFB, it takes approximately 1 sec to
fully discharge the reference buffer decoupling capacitors and
4 ms to restore full operation.
Digital Outputs
The AD9229’s differential outputs conform to the ANSI-644
LVDS standard. To set the LVDS bias current, place a resistor
(RSET is nominally equal to 4.0 kΩ) to ground at the
LVDSBIAS pin. The RSET resistor current is derived on-chip
and sets the output current at each output equal to a nominal
3.5 mA. A 100 Ω differential termination resistor placed at the
LVDS receiver inputs results in a nominal 350 mV swing at the
receiver. To adjust the differential signal swing, simply change
the resistor to a different value, as shown in Table 7.
Table 7. LVDSBIAS Pin Configuration
RSET Differential Output Swing
3.7 kΩ 375 mV p-p
4.0 kΩ (default) 350 mV p-p
4.3 kΩ 325 mV p-p
AD9229
Rev. B | Page 21 of 40
Table 9. Digital Test Pattern Pin Settings
The AD9229’s LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capa-
bility for superior switching performance in noisy environ-
ments. Single point-to-point net topologies are recommended
with a 100 Ω termination resistor placed as close to the receiver
as possible. It is recommended to keep the trace length no
longer than 12 inches and to keep differential output traces
close together and at equal lengths.
Selected DTP DTP Voltage
Resulting
D+ and D–
Resulting
FCO and DCO
Normal
operation
AGND Normal
operation
Normal
operation
DTP1 AVDD/3 1000 0000 0000 Normal
operation
DTP2 2 × AVDD/3 1010 1010 1010 Normal
operation
Restricted AVDD N/A N/A
The format of the output data is offset binary. An example of
the output coding format can be found in Table 8.
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9229. The input range can be adjusted by varying the refer-
ence voltage applied to the AD9229, using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly.
Table 8. Digital Output Coding
Code
(VIN+) − (VIN−),
Input Span =
2 V p-p (V)
(VIN+) − (VIN−),
Input Span =
1 V p-p (V)
Digital Output
Offset Binary
(D11 ... D0)
4095 1.000 0.500 1111 1111 1111
2048 0 0 1000 0000 0000
2047 −0.000488 −0.000244 0111 1111 1111
0 −1.00 −0.5000 0000 0000 0000
When applying the decoupling capacitors to the VREF, REFT,
and REFB pins, use ceramic, low ESR capacitors. These
capacitors should be close to the ADC pins and on the same
layer of the PCB as the AD9229. The recommended capacitor
values and configurations for the AD9229 reference pin can be
found in Figure 42 and Figure 43.
Timing
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
times the sample clock rate, with a maximum of 780 bps (12 bits
× 65 MSPS = 780 bps). The lowest typical conversion rate is
10 MSPS.
Table 10. Reference Settings
Selected Mode
SENSE
Voltage
Resulting
VREF (V)
Resulting
Differential
Span (V p-p)
External Reference AVDD N/A 2 × external
reference
Internal, 1 V p-p FSR VREF 0.5 1.0
Programmable 0.2 V to
VREF
0.5 × (1 +
R2/R1)
2 × VREF
Internal, 2 V p-p FSR AGND to
0.2 V
1.0 2.0
Two output clocks are provided to assist in capturing data from
the AD9229. The DCO is used to clock the output data and is
equal to six times the sampling clock (CLK) rate. Data is
clocked out of the AD9229 and can be captured on the rising
and falling edges of the DCO that supports double-data rate
(DDR) capturing. The frame clock out (FCO) is used to signal
the start of a new output byte and is equal to the sampling clock
rate. See the timing diagram shown in Figure 2 for more
information.
Internal Reference Connection
A comparator within the AD9229 detects the potential at the
SENSE pin and configures the reference into four possible states
(summarized in Table 10). If SENSE is grounded, the reference
amplifier switch is connected to the internal resistor divider (see
Figure 42), setting VREF to 1 V. Connecting the SENSE pin to
the VREF pin switches the amplifier output to the SENSE pin,
configuring the internal op amp circuit as a voltage follower and
providing a 0.5 V reference output. If an external resistor
divider is connected as shown in Figure 43, the switch is again
set to the SENSE pin. This puts the reference amplifier in a
noninverting mode and defines the VREF output as
DTP Pin
The digital test pattern (DTP) pin can be enabled for two types
of test patterns, as summarized in Table 9. When the DTP is
tied to AVDD/3, all the ADC channel outputs shift out the
following pattern: 1000 0000 0000. When the DTP is tied to 2 ×
AVDD/3, all the ADC channel outputs shift out the following
pattern: 1010 1010 1010. The FCO and DCO outputs still work
as usual while all channels shift out the test pattern. This
pattern allows the user to perform timing alignment
adjustments between the FCO, DCO, and the output data. For
normal operation, this pin should be tied to AGND. ⎟
⎠
⎞
⎜
⎝
⎛+×= R1
R2
VREF 15.0
In all reference configurations, REFT and REFB establish their
input span of the ADC core. The analog input full-scale range
of the ADC equals twice the voltage at the reference pin for
either an internal or an external reference configuration.
AD9229
Rev. B | Page 22 of 40
10μF 0.1μF
VREF
SENSE
0.5V
REFT
0.1μF
0.1μF 10μF
0.1μF
REFB
SELECT
LOGIC
ADC
CORE +
04418-036
VIN–
VIN+
Figure 42. Internal Reference Configuration
10μF 0.1μF
VREF
0.5V
REFT
0.1μF
0.1μF 10μF
0.1μF
REFB
SELECT
LOGIC
ADC
CORE +
+
04418-037
VIN–
VIN+
SENSE
R2
R1
Figure 43. Programmable Reference Configuration
If the internal reference of the AD9229 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 44
depicts how the internal reference voltage is affected by loading.
I
LOAD
(mA)
VREF ERROR (%)
0.05
–0.20
–0.15
–0.30
–0.35
–0.25
–0.05
0
–0.10
0 1.8 2.01.61.2 1.41.00.80.60.40.2
04418-058
VREF = 0.5V
VREF = 1.0V
Figure 44. VREF Accuracy vs. Load
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 45 shows the typical drift characteristics of the
internal reference.
TEMPERATURE (°C)
VREF ERROR (%)
0.10
0
–0.04
–0.02
–0.08
–0.10
–0.06
0.08
0.04
0.06
0.02
–40 65 805035205–10–25
04418-057
VREF = 0.5V
VREF = 1.0V
Figure 45. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. The external
reference is loaded with an equivalent 7 kΩ load. An internal
reference buffer generates the positive and negative full-scale
references, REFT and REFB, for the ADC core. Therefore, the
external reference must be limited to a maximum of 1 V.
Power and Ground Recommendations
When connecting power to the AD9229, it is recommended
that two separate 3.0 V supplies be used: one for analog
(AVDD) and one for digital (DRVDD). If only one supply is
available, it should be routed to the AVDD first and tapped off
and isolated with a ferrite bead or filter choke with decoupling
capacitors proceeding. The user can employ several different
decoupling capacitors to cover both high and low frequencies.
These should be located close to the point of entry at the PC
board level and close to the parts with minimal trace length.
A single PC board ground plane should be sufficient when
using the AD9229. With proper decoupling and smart parti-
tioning of the PC board’s analog, digital, and clock sections,
optimum performance is easily achieved.
AD9229
Rev. B | Page 23 of 40
Exposed Paddle Thermal Heat Slug Recommendations
SILKSCREEN PARTITION
PIN 1 INDICATOR
04418-052
It is mandatory that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9229. A
continuous exposed copper plane on the PCB should mate to
the AD9229 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder or epoxy filled (plugged). Figure 46. Typical PCB Layout
To maximize the solder coverage and adhesion between the
ADC and PCB, overlay a silkscreen to partition the continuous
copper plane on the PCB into several uniform sections. This
provides several tie points between the two during the reflow
process. Using one continuous plane with no silkscreen
partitions only guarantees one tie point between the ADC and
PCB. See Figure 46 for a PCB layout example. For detailed
information on packaging and the PCB layout of chip scale
packages, visit www.analog.com.
AD9229
Rev. B | Page 24 of 40
EVALUATION BOARD
The AD9229 evaluation board provides all of the support cir-
cuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially
through a transformer (default) or through the AD8332 driver.
The ADC can also be driven in a single-ended fashion. Separate
power pins are provided to isolate the DUT from the AD8332
drive circuitry. Each input configuration can be selected by
proper connection of various jumpers (see Figure 48 to Figure 52).
Figure 47 shows the typical bench characterization setup used
to evaluate the ac performance of the AD9229. It is critical that
the signal sources used for the analog input and clock have very
low phase noise (<1 ps rms jitter) to realize the ultimate
performance of the converter. Proper filtering of the analog
input signal to remove harmonics and lower the integrated or
broadband noise at the input is also necessary to achieve the
specified noise performance.
See Figure 47 to Figure 57 for complete schematics and layout
plots that demonstrate the routing and grounding techniques
that should be applied at the system level.
POWER SUPPLIES
This evaluation board comes with a wall mountable switching
power supply that provides a 6 V, 2 A maximum output. Simply
connect the supply to the rated 100 V to 240 V ac wall outlet at
47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack
that connects to the PCB at P503. Once on the PC board, the
6 V supply is fused and conditioned before connecting to three
low dropout linear regulators that supply the proper bias to each
of the various sections on the board.
When operating the evaluation board in a nondefault condition,
L504 to L506 can be removed to disconnect the switching
power supply. This enables the user to individually bias each
section of the board. Use P501 to connect a different supply for
each section. At least one 3.0 V supply is needed with a 1 A
current capability for AVDD_DUT and DRVDD_DUT;
however, it is recommended that separate supplies be used for
both analog and digital. To operate the evaluation board using
the VGA option, a separate 5.0 V analog supply is needed in
addition to the other 3.0 V supplies. The 5.0 V supply, or
AVDD_VGA, should have a 1 A current capability as well.
INPUT SIGNALS
When connecting the clock and analog source, use clean signal
generators with low phase noise, such as Rohde & Schwarz SMHU
or HP8644 signal generators or the equivalent. Use 1 m long,
shielded, RG-58, 50 Ω coaxial cable for making connections to
the evaluation board. Dial in the desired frequency and amplitude
within the ADC’s specifications tables. Typically, most ADI
evaluation boards can accept a ~2.8 V p-p or 13 dBm sine wave
input for the clock. When connecting the analog input source, it
is recommended to use a multipole, narrow-band band-pass
filter with 50 Ω terminations. ADI uses TTE, Allen Avionics,
and K&L types of band-pass filters. The filter should be
connected directly to the evaluation board if possible.
OUTPUT SIGNALS
The default setup uses the HSC-ADC-FPGA high speed
deserialization board, which deserializes the digital output data
and converts it to parallel CMOS. These two channels interface
directly with ADI’s standard dual-channel FIFO data capture
board (HSC-ADC-EVALA-DC). Two of the four channels can
then be evaluated at the same time. For more information on
channel settings on these boards and their optional settings,
visit www.analog.com/FIFO.
ROHDE & SCHWARZ,
SMHU,
2V p-p SIGNAL
SYNTHESIZER
ROHDE & SCHWARZ,
SMHU,
2V p-p SIGNAL
SYNTHESIZER
BAND-PASS
FILTER XFMR
INPUT
CLK
CHA–CHD
12-BIT
SERIAL
LVDS
2 CH
12-BIT
PARALLEL
CMOS
USB
CONNECTION
AD9229
EVALUATION BOARD
HSC-ADC-FPGA
HIGH SPEED
DESERIALIZATION
BOARD
04418-040
HSC-ADC-EVALA-DC
FIFO DATA
CAPTURE
BOARD
PC
RUNNING
ADC
ANALYZER
3.0V –+–+
AVDD_DUT
DRVDD_DUT
GND
GND
–+
5.0V
GND
AVDD_VGA
3.0V
6V DC
2Amax
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
SWITCHING
POWER
SUPPLY
Figure 47. Evaluation Board Connections
AD9229
Rev. B | Page 25 of 40
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
The following is a list of the default and optional settings or
modes allowed on the AD9229 Rev C evaluation board.
• POWER: Connect the switching power supply that is
supplied in the evaluation kit between a rated 100 V to
240 V ac wall outlet at 47 Hz to 63 Hz and P503.
• AIN: The evaluation board is set up for a transformer
coupled analog input with optimum 50 Ω impedance
matching out to 400 MHz. For more bandwidth response,
the 2.2 pF differential capacitor across the analog inputs
could be changed or removed. The common mode of the
analog inputs is developed from the center tap of the
transformer or AVDD_DUT/2.
• VREF: VREF is set to 1.0 V by tying the SENSE pin to
ground, R224. This causes the ADC to operate in 2.0 V p-p
full-scale range. A number of other VREF options are
available on the evaluation board, including 1.0 V p-p full-
scale range, a variable range that the user can set by
choosing R219 and R220 as well as a separate external
reference option using the ADR510 or ADR520. Simply
populate R218 and R222 and remove C208. To use these
optional VREF modes, switch the jumper setting on R221
to R224. Proper use of the VREF options is noted in the
Voltage Reference section.
• CLOCK: The clock input circuitry is derived from a simple
logic circuit using a high speed inverter that adds a very
low amount of jitter to the clock path. The clock input is
50 Ω terminated and ac-coupled to handle sine wave
type inputs. If using an oscillator, two oscillator footprint
options are also available (OSC200-201) to check the
ADC’s performance. J203 and J204 give the user flexibility
in using the enable pin, which is common on most
oscillators.
• PWDN: To enable the power-down feature, simply short
JP201 to AVDD on the PWDN pin.
• DTP: To enable one of the two digital test patterns on
digital outputs of the ADC, use JP202. If Pins 2 and 3 on
JP202 are tied together (1.0 V source), this enables test
pattern 1000 0000 0000. If Pins 1 and 2 on JP202 are tied
together (2.0 V source), this enables test pattern 1010 1010
1010. See the DTP Pin section for more details.
• LVDSBIAS: To change the level of the LVDS output level
swing, simply change the value of R204. Other recom-
mended values can be found in the Digital Outputs
section.
• D+, D–: If an alternate data capture method to the setup
described in Figure 47 is used, optional receiver
terminations, R205 to R210, can be installed next to the
high speed backplane connector.
ALTERNATE ANALOG INPUT DRIVE
CONFIGURATION
The following is a brief description of the alternate analog input
drive configuration using the AD8332 dual VGA. This parti-
cular drive option may need to be populated, in which case all
the necessary components are listed in Table 11. This table lists
the necessary settings to properly configure the evaluation
board for this option. For more details on the AD8332 dual
VGA, how it works, and its optional pin settings, consult the
AD8332 data sheet.
To configure the analog input to drive the VGA instead of the
default transformer option, the following components need to
be removed and/or changed.
1. Remove R102, R115, R128, R141, T101, T102, T103, and
T1044 in the default analog input path.
2. Populate R101, R114, R127, and R140 with 0 Ω resistors in
the analog input path.
3. Populate R106, R107, R119, R120, R132, R133, R144, and
R145 with 10 kΩ resistors to provide an input common-
mode level to the analog input.
4. Populate R105, R113, R118, R124, R131, R137, R151, and
R43 with 0 Ω resistors in the analog input path.
5. Currently L305 to L312 and L405 to L412 are populated
with 0 Ω resistors to allow signal connection. This area
allows the user to design a filter if additional requirements
are necessary.
AD9229
Rev. B | Page 26 of 40
VIN_C
VIN_C
R154
DNP
R134
33Ω
FB108
10
FB109
10 R136
33Ω
R130
0Ω
R129
0Ω
FB107
10 R135
1kΩ
R162
499Ω
R132
1kΩ
DNP
R133
1kΩ
DNP
R137
0Ω
DNP
C118
2.2pF
R158
DNP
C117
DNP
CM3 CM3
1
2
34
5
6
CH_C
CH_C
C115
0.1μF
C116
0.1μF
A
IN
P106
DNP
R127
0Ω
DNP
R128
65Ω
A
IN
P105
CHANNEL C
INH3
VGA INPUT
CONNECTION
T103
C121
0.1μF
R139
1kΩ
R138
1kΩC120
DNP
CM3
AVDD_DUT
AVDD_DUT
AVDD_DUT
R131
0Ω
DNP
C119
DNP
VIN_D
VIN_D
R155
DNP
R146
33Ω
FB111
10
FB112
10 R147
33Ω
R142
0Ω
R148
1kΩ
R163
499Ω
R144
1kΩ
DNP
R151
0Ω
DNP
R145
1kΩ
DNP
R43
0Ω
DNP
C125
2.2pF
C126
DNP R159
DNP
C124
DNP
R143
0Ω
FB110
10
CM4 CM4
1
2
34
5
6
CH_D
CH_D
C122
0.1μF
C123
0.1μF
A
IN
P108
DNP
R140
0Ω
DNP
R141
65Ω
A
IN
P107
CHANNEL D
INH4
VGA INPUT
CONNECTION
T104
C128
0.1μF
R150
1kΩ
R149
1kΩC127
DNP
CM4
AVDD_DUT
AVDD_DUT
AVDD_DUT
ANALOG INPUTS
04418-041
VIN_A
VIN_A
R152
DNP
R108
33Ω
FB102
10
FB103
10 R110
33Ω
R104
0Ω
R103
0Ω
FB101
10 R109
1kΩ
R160
499Ω
R106
1kΩ
DNP
R107
1kΩ
DNP
R113
0Ω
DNP
C104
2.2pF
R156
DNP
C103
DNP
CM1 CM1
1
2
34
5
6
CH_A
CH_A
C101
0.1μF
C102
0.1μF
A
IN
P102
DNP
R101
0Ω
DNP
R102
65Ω
A
IN
P101
CHANNEL A
INH1
VGA INPUT
CONNECTION
T101
C107
0.1μF
R112
1kΩ
R111
1kΩC106
DNP
CM1
AVDD_DUT
AVDD_DUT
AVDD_DUT
R105
0Ω
DNP
C105
DNP
VIN_B
VIN_B
R153
DNP
R121
33Ω
FB105
10
FB106
10 R122
33Ω
R117
0Ω
R123
1kΩ
R161
499Ω
R119
1kΩ
DNP
R118
0Ω
DNP
R120
1kΩ
DNP
R124
0Ω
DNP
C111
2.2pF
C112
DNP R157
DNP
C110
DNP
R116
0Ω
FB104
10
CM2 CM2
1
2
34
5
6
CH_B
CH_B
C108
0.1μF
C109
0.1μF
A
IN
P104
DNP
R114
0Ω
DNP
R115
65Ω
A
IN
P103
CHANNEL B
INH2
VGA INPUT
CONNECTION
T102
C114
0.1μF
R126
1kΩ
R125
1kΩC113
DNP
CM2
AVDD_DUT
AVDD_DUT
AVDD_DUT
DNP : DO NOT POPULATE
Figure 48. Evaluation Board Schematic, DUT Analog Inputs
AD9229
Rev. B | Page 27 of 40
1
2
3
4
6
8
5
7
9
10
11
12
DRGND
DRVDD
DNC
DTP
AGND
AVDD
AVDD
PDWN
AGND
VIN +A
VIN –A
AGND
GND
DRVDD_DUT
GND
GND
AVDD_DUT
AVDD_DUT
DUTCLK
GND
VIN_D
GND
36
35
34
33
31
29
32
30
28
27
26
25
AGND
DRGND
DRVDD
LVDSBIAS
AGND
AVDD
AVDD
CLK
AGND
VIN +D
VIN –D
AGND
13
14
15
16
18
20
17
19
21
22
23
24
VIN –B
VIN +B
AGND
AVDD
VREF
REFT
SENSE
REFB
AVDD
AGND
VIN +C
VIN –C
VIN _B
VIN_B
GND
AVDD_DUT
VREF_DUT
VSENSE_DUT
AVDD_DUT
GND
VIN _C
VIN_C
48
47
46
45
43
41
44
42
40
39
38
37
DCO+
DCO–
FCO+
FCO–
A–D
D–B
D+A
D+B
D+C
D–C
D+D
D–D
AD9229
VIN_D
GND
DRVDD_DUT
AVDD_DUT
AVDD_DUT
AVDD_DUT
GND
GND
VIN_A
GND
GND
R204
4.0kΩ
DCO
DCO
FCO
FCO
CHA
CHB
CHA
CHB
CHC
CHC
CHD
CHD
C203
0.1μF
C202
10μF
C201
0.1μF
C204
0.1μF
VIN_A
R203
10kΩ
PWDN ENABLE
JP201
AVDD_DUT
JP202
R202
10kΩ
R228
10kΩ
R201
10kΩ
1
2
3
DIGITAL TEST
PATTERN
ENABLE
PIN 1 TO PIN 2 = 1010 1010 1010
PIN 2 TO PIN 3 = 1000 0000 0000
OPTIONAL CLOCK OSCILLATOR
AVDD_VGA
AVDD_DUT
AVDD_DUT
JP204 JP203
1
4
2
3
EOH
VCC
GND
OUTPUT
CBELV3I66MT
OSC200
1
14
7
8
NC/ENB
VCC
GND
OUTPUT
CX3600C-65
DNP
OSC201
C209
0.1μF
C210
0.1μF
C205
0.1μF
R225
0Ω
DNP
R212
1kΩ
R211
1kΩR231
0Ω
DNP
R229
0Ω
R230
0Ω
DNP
R214
22Ω
R213
49.9Ω
ENCODE
INPUT
P201 12
U202
AVDD_DUT:14
GND:7
34
U202
AVDD_DUT:14
GND:7
DUTCLK
GNDCD10
60
GNDCD9
59
GNDCD6
56
GNDCD5
55
GNDCD8
58
GNDCD7
C10
C9
C6
C5
C8
D10
D9
D6
D5
D8
D7C7
50
49
46
45
48
47
40
39
36
35 GNDCD4
C4 D4
GNDCD3
C3 D3
GNDCD2
C2 D2
GNDCD1
C1 D1
GNDAB10
A10 B10
GNDAB9
A9 B9
GNDAB8
A8 B8
GNDAB7
A7 B7
GNDAB6
A6 B6
GNDAB5
A5 B5
GNDAB4
A4 B4
GNDAB3
A3 B3
GNDAB2
A2 B2
GNDAB1
54
53
52
51
30
29
28
27
26
25
24
23
22
21 A1 B1
4434
4333
4232
4131
2010
199
188
177
166
155
144
133
122
111
38
37
57
DCO
FCO
CHC
CHD
CHA
CHB
DCO
FCO
CHC
CHD
CHA
CHB
1469169-1
R205-R210
OPTIONAL OUTPUT
TERMINATIONS
R221
0Ω
R222
0Ω
R223
0Ω
R224
0Ω
AVDD_DUT
AVDD_DUT
VREF_DUT
VSENSE_DUT
VREF SELECT VREF = 1V = DEFAULT
R219
DNP
C208
10μF
C207
0.1μF
R217
470kΩ
R218
0Ω
DNP
R215
2kΩ
R220
DNP
R216
10kΩ
CW
C206
0.1μF
GND
ADR510/ADR520
1NV VOUTTRIM/NC
U203
EXTERNAL REFERENCE CIRCUIT
VREF = 0.5V
VREF = EXTERNAL
VREF = 0.5V (1 + R219/R220)
VREF = 1V
REMOVE C208 WHEN
USING EXTERNAL VREF
DNP : DO NOT POPULATE
04418-042
DIGITAL OUTPUTS
P202
REFERENCE
DECOUPLING
CLOCK CIRCUIT
REFERENCE CIRCUIT
U201
R205
DNP
R206
DNP
R207
DNP
R208
DNP
R209
DNP
R210
DNP
Figure 49. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface
AD9229
Rev. B | Page 28 of 40
HILO PIN
HI GAIN RANGE = 2.25V TO 5.0V
LO GAIN RANGE = 0V TO 1.0V
AD8332
ENBV
ENBL
HILO
VCM1
VIN1
VIP1
COM1
LOP1
25
26
27
28
29
30
31
32
LON1
VPS1
INH1
LMD1
LMD2
INH2
VPS2
LON2
1
2
3
4
5
6
7
8
RCLMP
GAIN
MODE
VCM2
VIN2
VIP2
COM2
LOP2
16
15
14
13
12
11
10
9
COMM
VOH1
VOL1
VPSV
NC
VOL2
VOH2
COMM
24
23
22
21
20
19
18
17
R304
187Ω
R311
10kΩ
DNP
R314
10kΩR315
274Ω
C317
10μFC318
0.1μF
C325
0.1μFC326
0.1μF
C321
18nF
R312
10Ω
R307
187Ω
R306
187ΩR309
187Ω
R305
374ΩR308
374Ω
R318
DNP
R320
DNP R321
DNP
C305
DNP C306
DNP
R319
DNP
C303
DNP C304
DNP
L305
DNP
L306
DNP L307
DNP
L308
DNP
L309
DNP
L310
DNP L311
DNP
L312
DNP
C313
0.1μF
C315
0.1μF
C307
0.1μF
C308
0.1μF
C309
0.1μF
C310
0.1μF
CH_CCH_D CH_D CH_C
C314
0.1μF
AVDD_VGA
AVDD_VGA
AVDD_VGA
R316
274Ω
C322
18nF
C323
22pF C324
22pF
L313
120nH L314
120nH
C327
0.1μFC328
0.1μF
INH4 INH3
R311
10kΩ
DNP
R317
10kΩ
DNP
C320
10μF
C319
0.1μF
C316
0.1μF
AVDD_VGA
VG
R310
100kΩ
DNP
C312
0.1μF
C311
1nF
DNP : DO NOT POPULATE
MODE PIN
POSITIVE GAIN SLOPE = 0V TO 1.0V
NEGATIVE GAIN SLOPE = 2.25V TO 5.0V
RCLAMP PIN
HILO PIN = LO = ± 50mV
HILO PIN = HI = ± 75mV
EXT VG
JP301
12
VG GND
AVDD_VGA
R302
10kΩ
R303
39kΩ
CW
VG
EXTERNAL
VARIABLE GAIN DRIVE
VARIABLE GAIN CIRCUIT
(0V TO 1.0V DC)
OPTIONAL VGA DRIVE CIRCUIT FOR CHANNELS C AND D
POWER-DOWN ENABLE
(0V TO 1V = DISABLE POWER)
044181-003
U301
AVDD_VGA
POPULATE L305 TO L312
WITH 0ΩRESISTORS OR
DESIGN YOUR OWN FILTER
Figure 50. Evaluation Board Schematic, Optional DUT Analog Input Drive
AD9229
Rev. B | Page 29 of 40
RCLAMP PIN
HILO PIN = LO = ± 50mV
HILO PIN = HI = ± 75mV
HILO PIN
HI GAIN RANGE = 2.25V TO 5.0V
LO GAIN RANGE = 0V TO 1.0V
AD8332
ENBV
ENBL
HILO
VCM1
VIN1
VIP1
COM1
LOP1
25
26
27
28
29
30
31
32
LON1
VPS1
INH1
LMD1
LMD2
INH2
VPS2
LON2
1
2
3
4
5
6
7
8
RCLMP
GAIN
MODE
VCM2
VIN2
VIP2
COM2
LOP2
16
15
14
13
12
11
10
9
COMM
VOH1
VOL1
VPSV
NC
VOL2
VOH2
COMM
24
23
22
21
20
19
18
17
R403
187Ω
R401
10kΩ
DNP
R411
10kΩR412
274Ω
C417
10μFC418
0.1μF
C421
0.1μFC422
0.1μF
C423
18nF
R402
10kΩ
R406
187Ω
R405
187ΩR408
187Ω
R404
374ΩR407
374Ω
R415
DNP
R417
DNP R418
DNP
C405
DNP C406
DNP
R416
DNP
C403
DNP C404
DNP
L405
DNP
L406
DNP L407
DNP
L408
DNP
L409
DNP
L410
DNP L411
DNP
L412
DNP
C413
0.1μF
C415
0.1μF
C407
0.1μFC408
0.1μF
C409
0.1μF
C410
0.1μF
CH_ACH_B CH_B CH_A
C414
0.1μF
AVDD_VGA
AVDD_VGA
AVDD_VGA
R413
274Ω
C424
18nF
C425
22pF C426
22pF
L413
120pH L414
120nH
C427
0.1μFC428
0.1μF
INH2 INH1
R409
10kΩ
DNP
R414
10kΩ
DNP
C420
10μF
C419
0.1μF
C416
0.1μF
AVDD_VGA
VG
R409
100kΩ
DNP
C412
0.1μF
C411
1nF
DNP : DO NOT POPULATE
MODE PIN
POSITIVE GAIN SLOPE = 0V TO 1.0V
NEGATIVE GAIN SLOPE = 2.25V TO 5.0V
OPTIONAL VGA DRIVE CIRCUIT FOR CHANNELS A AND B
POPULATE L405 TO L412
WITH 0ΩRESISTORS OR
DESIGN YOUR OWN FILTER
POWER-DOWN ENABLE
(0V TO 1V = DISABLE POWER)
044181-044
U401
Figure 51. Evaluation Board Schematic, Optional DUT Analog Input Drive Continued
AD9229
Rev. B | Page 30 of 40
POWER SUPPLY INPUT
6V
2A MAX
04418-045
U502
C514
1μFC515
1μF
32
1
PWR_IN
4
ADP33339AKC-5
OUTPUT1
OUTPUT4
INPUT
GND
VGA_AVDD
L506
10μH
U501
C502
1μFC503
1μF
32
1
PWR_IN
4
ADP33339AKC-3
OUTPUT1
OUTPUT4
INPUT
GND
DUT_AVDD
L504
10μH
U503
C506
1μFC507
1μF
32
1
PWR_IN
4
ADP33339AKC-3
OUTPUT1
OUTPUT4
INPUT
GND
DUT_DRVDD
L505
10μH
P503
C501
10μF
1
2
3
SMDC110F
F501
D501
S2A_RECT
2A
DO-214AA
D502
SHOT_RECT
3A
DO-214AB
1
42
3
FER501
CHOKE_COIL
R500
374Ω
CR500
PWR_IN
OPTIONAL POWER INPUT
C516
10μFC517
0.1μF
AVDD_VGA 5.0V
L503
10μH
P1
P2
P3
P4
P5
P6
1
2
3
4
5
6
P501
DNP
DUT_AVDD
DUT_DRVDD
VGA_AVDD
C508
10μFC509
0.1μF
AVDD_DUT 3.0V
L502
10μH
C504
10μFC505
0.1μF
DRVDD_DUT 3.0V
L501
10μH
DNP : DO NOT POPULATE
Figure 52. Evaluation Board Schematic, Power Supply Inputs
AD9229
Rev. B | Page 31 of 40
04418-046
DNP : DO NOT POPULATE
C621
0.1μF
C619
0.1μFC620
0.1μF
C627
0.1μFC630
0.1μFC631
0.1μF
C613
0.1μFC614
0.1μF
C617
0.1μFC618
0.1μF
C632
0.1μF
C625
0.1μFC628
0.1μF
DECOUPLING CAPACITORS
DRVDD_DUT
AVDD_VGA
AVDD_DUT
H1 H2
H3 H4
MOUNTING HOLES
CONNECTED TO GROUND
56
U202
AVDD_DUT : 14
GND : 7
98
U202
AVDD_DUT : 14
GND : 7
11 10
U202
AVDD_DUT : 14
GND : 7
13 12
U202
AVDD_DUT : 14
GND : 7
GND
UNUSED GATES
Figure 53. Evaluation Board Schematic, Decoupling and Miscellaneous
AD9229
Rev. B | Page 32 of 40
04418-047
Figure 54. Evaluation Board Layout, Primary Side
AD9229
Rev. B | Page 33 of 40
04418-048
Figure 55. Evaluation Board Layout, Ground Plane
AD9229
Rev. B | Page 34 of 40
04418-049
Figure 56. Evaluation Board Layout, Power Plane
AD9229
Rev. B | Page 35 of 40
04418-050
Figure 57. Evaluation Board Layout, Secondary Side (Mirrored Image)
AD9229
Rev. B | Page 36 of 40
Table 11. Evaluation Board Bill of Materials (BOM)
Item
Qnty.
per
Board REFDES Device Pkg. Value Mfg. Mfg. Part Number
1 1 AD9229LFCSP_REVC PCB PCB PCB
2 59 C327, C328, C630, C628,
C629, C631, C632, C101,
C102, C107, C108, C109,
C114, C115, C116, C121,
C122, C123, C128, C201,
C203, C204, C205, C206,
C207, C313, C314, C315,
C312, C318, C319, C412,
C316, C325,C326, C413,
C414, C415, C418, C419,
C416, C421, C422, C427,
C428, C505, C509, C517,
C613, C614, C617, C618,
C619, C620, C621, C625,
C209, C210, C627
Capacitor 402 0.1 F, ceramic,
X5R, 10 V, 10% tol
Panasonic ECJ-0EB1A104K
3 4 C104, C111, C118, C125 Capacitor 402 2.2 pF, ceramic,
COG, 0.25 pF tol,
50 V
Murata GRM1555C1H2R2GZ01B
4 9 C202, C208, C317, C320,
C417, C420, C504, C508,
C516
Capacitor 805 10 F, 6.3 V ±10%
ceramic X5R
AVX 08056D106KAT2A
5 8 C307, C308, C309, C310,
C407, C408, C409, C410
Capacitor 603 0.1 F, ceramic,
X7R, 16 V, 10% tol
Kemet C0603C104K4RACTU
6 2 C311, C411 Capacitor 402 1000 pF, ceramic,
X7R, 25 V, 10% tol
Kemet C0402C102K3RACTU
7 4 C321, C322, C423, C424 Capacitor 402 0.018 F, ceramic,
X7R, 16 V, 10% tol
AVX 0402YC183KAT2A
8 4 C323, C324, C425, C426 Capacitor 402 22 pF, ceramic,
NPO, 5% tol, 50 V
Kemet C0402C220J5GACTU
9 1 C501 Capacitor 1206 10 F, tantalum,
16 V, 10% tol
Kemet T491B106K016AS
10 6 C502, C503, C506, C507,
C514, C515
Capacitor 603 1 F, ceramic, X5R,
6.3 V, 10% tol
Panasonic ECJ-1VB0J105K
11 1 CR500 LED 603 Green, 4 V, 5 m
candela
Panasonic LNJ314G8TRA
12 1 D502 Diode DO-214AB 3 A, 30 V, SMC Micro
Commercial
Co.
SK33MSCT
13 1 D501 Diode DO-214AA 2 A, 50 V, SMC Micro
Commercial
Co.
S2A
14 1 F501 Fuse 1210 6.0 V, 2.2 A trip
current resettable
fuse
Tyco/Raychem NANOSMDC110F-2
15 1 FER501 Ferrite
bead
2020 10 H, 5 A, 50 V,
190 Ω @ 100 MHz
Murata DLW5BSN191SQ2L
16 12 FB101, FB102, FB103,
FB104, FB105, FB106,
FB107, FB108, FB109,
FB110, FB111, FB112
Ferrite
bead
603 10 Ω, test freq
100 MHz, 25% tol,
500 mA
Murata BLM18BA100SN1
17 2 JP201, JP301 Connector 2-pin 100 mil header
jumper, 2-pin
Samtec TSW-102-07-G-S
18 3 JP204, JP203, JP202 Connector 3-pin 100 mil header
jumper, 3-pin
Samtec TSW-103-07-G-S
AD9229
Rev. B | Page 37 of 40
Item
Qnty.
per
Board REFDES Device Pkg. Value Mfg. Mfg. Part Number
19 6 L501, L502, L503, L504,
L505, L506
Ferrite
bead
1210 10 H, bead core
3.2 × 2.5 × 1.6 SMD,
2 A
Panasonic -
ECG
EXC-CL3225U1
20 4 L313, L314, L413, L414 Inductor 402 120 nH, test freq
100 MHz, 5% tol,
150 mA
Murata LQG15HNR12J02B
21 12 L305, L306, L307, L308,
L309, L310, L405, L406,
L407, L408, L409, L410,
L311, L312, L411, L412
Resistor 805 0 Ω, 1/8 W, 5% tol Panasonic ERJ-6GEY0R00V
22 1 OSC200 Oscillator SMT Clock oscillator,
66.66 MHz, 3.3 V
CTS REEVES CB3LV-3C-66M6666-T
23 5 P201, P101, P103, P105,
P107
Connector SMA Sidemount SMA
for 0.063" board
thickness
Johnson
Components
142-0711-821
24 1 P202 Connector HEADER
1469169-1, right
angle 2-pair,
25 mm, header
assembly
Tyco 1469169-1
25 1 P503 Connector 0.1", PCMT
RAPC722, power
supply connector
Switchcraft SC1153
26 10 R201, R202, R228, R203,
R312, R314, R317, R402,
R411, R414
Resistor 402 10 kΩ, 1/16 W, 5%
tol
Yageo
America
9C04021A1002JLHF3
27 7 R225, R129, R142, R224 Resistor 402 0 Ω, 1/16 W, 5% tol Yageo
America
9C04021A0R00JLHF3
28 4 R102, R115, R128, R141 Resistor 402 64.9 Ω, 1/16 W,
1% tol
Panasonic ERJ-2RKF64R9X
29 4 R104, R116, R130, R143 Resistor 603 0 Ω, 1/10 W, 5% tol Panasonic ERJ-3GEY0R00V
30 14 R111, R112, R125, R126,
R138, R139, R149, R150,
R211, R212, R109, R123,
R135, R148
Resistor 402 1 kΩ, 1/16 W, 1% tol Panasonic ERJ-2RKF1001X
31 8 R108, R110, R121, R122,
R134, R136, R146, R147
Resistor 402 33 Ω, 1/16 W, 5%
tol
Yageo
America
9C04021A33R0JLHF3
32 4 R160, R161, R162, R163 Resistor 402 499 Ω, 1/16 W,
1% tol
Panasonic ERJ-2RKF4990X
33 1 R215 Resistor 402 2 kΩ, 1/16 W, 5% tol Yageo
America
9C04021A2001JLHF3
34 1 R204 Resistor 402 4.02 kΩ, 1/16 W,
1% tol
Panasonic ERJ-2RKF4021X
35 1 R213 Resistor 402 49.9 Ω, 1/16 W,
0.5% tol
Susumu RR0510R-49R9-D
36 1 R214 Resistor 402 22 Ω, 1/16 W,
5% tol
Yageo
America
9C04021A22R0JLHF3
37 2 R216,R302 Potentiom
eter
3-lead 10 kΩ, Cermet
trimmer
potentiometer,
18 turn top adjust,
10%, ½ W
BC
Components
CT-94W-103
38 1 R217 Resistor 402 470 kΩ, 1/16 W,
5% tol
Yageo
America
9C04021A4703JLHF3
39 1 R303 Resistor 402 39 kΩ, 1/16 W,
5% tol
Susumu RR0510P-393-D
40 8 R304, R306, R307, R309,
R403, R405, R406, R408,
Resistor 402 187 Ω, 1/16 W,
1% tol
Panasonic ERJ-2RKF1870X
AD9229
Rev. B | Page 38 of 40
Item
Qnty.
per
Board REFDES Device Pkg. Value Mfg. Mfg. Part Number
41 4 R305, R308, R404, R407,
R500
Resistor 402 374 Ω, 1/16 W,
1% tol
Panasonic ERJ-2RKF3740X
42 4 R315, R316, R412, R413 Resistor 402 274 Ω, 1/16 W,
1% tol
Panasonic ERJ-2RKF2740X
43 4 T101, T102, T103, T104 Transforme
r
CD542 ADT1-1WT, 1:1
impedance ratio
transformer
Mini-Circuits ADT1-1WT
44 2 U501, U503 IC SOT-223
ADP33339AKC-3,
1.5 A, 3.0 V LDO
regulator
ADI ADP33339AKC-3
45 2 U301, U401 IC LFCSP, CP-
32
AD8332ACP,
ultralow noise
precision dual VGA
ADI AD8332ACP
46 1 U502 IC SOT-223 ADP33339AKC-5 ADI ADP33339AKC-5
47 1 U201 IC LFCSP, CP-
48-1
AD9229-65, quad
12-bit, 65 MSPS
serial LVDS 3 V ADC
ADI AD9229ABCPZ-65
48 1 U203 IC SOT-23 ADR510AR, 1.0 V,
precision low noise
shunt voltage
reference
ADI ADR510AR
49 1 U202 IC TSSOP 74VHC04MTC, hex
inverter
Fairchild 74VHC04MTC
50 4 MP101-104 Part of
assembly
CBSB-14-01A-RT,
7/8" height,
standoffs for circuit
board support
Richco CBSB-14-01A-RT
51 4 MP105-108 Part of
assembly
SNT-100-BK-G-H,
100 mil jumpers
Samtec SNT-100-BK-G-H
52 4 MP109-112 Part of
assembly
5-330808-3, pin
sockets, closed end
for OSC200
AMP 5-330808-3
AD9229
Rev. B | Page 39 of 40
OUTLINE DIMENSIONS
*COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
FORPROPERCONNECTIONOF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
1
48
12
13
37
36
24
25
*5.55
5.50 SQ
5.45
0.50
0.40
0.30
0.30
0.23
0.18
0.80 MAX
0.65 TYP
5.50 REF
COPLANARITY
0.08
EXPOSED
PAD
(BOTTOM VIEW)
0.20 REF
1.00
0.85
0.80 0.05 MAX
0.02 NOM
SEATING
PLANE
12° MAX
TOP VIEW
0.60 MAX
0.60 MAX
PIN 1
INDICATOR 0.50
REF
PIN 1
INDICATOR
0.22 MIN
7.10
7.00 SQ
6.90
6.85
6.75 SQ
6.65
02-23-2010-C
Figure 58. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9229ABCPZ-65 –40°C to +85°C 48-Lead LFCSP_VQ CP-48-8
AD9229ABCPZRL7-65 –40°C to +85°C 48-Lead LFCSP_VQ CP-48-8
AD9229ABCPZ-50 –40°C to +85°C 48-Lead LFCSP_VQ CP-48-8
AD9229ABCPZRL7-50 –40°C to +85°C 48-Lead LFCSP_VQ CP-48-8
1 Z = RoHS Compliant Part.
AD9229
Rev. B | Page 40 of 40
NOTES
© 2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04418–0–5/10(B)
