CY7C343B-25HC/HI - Cypress Semiconductor

64-Macrocell MAX® EPLD

CY7C343B

Cypress Semiconductor Corporation •3901 North First Street •San Jose •CA 95134 •408-943-2600

Document #: 38-03038 Rev. ** Revised December 8, 1999

43B

Features

• 64 MAX macrocells in 4 LABs

• 8 dedicated inputs, 24 bidirectional I/O pins

• Programmable interconnect array

• Advanced 0.65-micron CMOS technology to increase

performance

• Available in 44-pin HLCC, PLCC

• Lowest power MAX device

Functional Description

The CY7C343B is a high-performance, high-density erasable

programmable logic device, available in 44-pin PLCC and

HLCC pac ka ges .

The CY7C343B contains 64 highly flexible macrocells and 128

expander product terms. These resources are divided into four

Logic Array Blocks (LABs) connected through the Program-

mable Inter-connect Array (PIA). There are 8 input pins, one

that doubles as a clock pin when needed. The CY7C343B also

has 28 I/O pins , each connected to a macr oce ll (6 for LABs A

and C, an d 8 for LABs B and D) . The remain ing 36 macr ocells

are used for embedded logic.

The CY7C343B is exce lle nt for a wide rang e of b oth s yn ch ro-

nous and asynchronous applications.

MAX is a registered trademark of Altera Corporation.

MACROCELL17

MACROCELL18

MACROCELL19

MACROCELL20

MACROCELL21

MACROCELL22

MACROCELL23

MACROCELL24

MACROCELL38

MACROCELL37

MACROCELL36

MACROCELL35

MACROCELL34

MACROCELL33

9INPUT

11 INPUT

12 INPUT

13 INPUT

MACROCELL1

MACROCELL2

MACROCELL3

MACROCELL4

MACROCELL5

MACROCELL6

MACROCELL56

MACROCELL55

MACROCELL54

MACROCELL53

MACROCELL52

MACROCELL51

MACROCELL50

MACROCELL49

MACROCELLS 7 - 16 MACROCELLS57 - 64

MACROCELLS 25 - 32 MACROCELLS39 - 48

INPUT35

INPUT/CLK34

INPUT33

INPUT31

SYSTEM CLOCK

(3, 14, 25, 36)

(10, 21, 32, 43) VCC

GND

LAB A

LAB B

LAB D

LAB C

C343B-1

Logic Block Diagram

DEDICATED INPUTS

I/O PINS

CY7C343B

Document #: 38-03038 Rev. ** Page 2 of 12

Maximum Ratings

(Above w hi ch the useful life may be impaired. For user g uid e-

lines, not tes ted .)

Storage Temperature ..................................–65°C to+135°C

Ambient Temperature with

Power Applied..............................................–65°C to+135°C

Maximum Junction Temperature

(Under Bias).......... ...... ................. ..... ...... ...... ..... ..........150°C

Supply Voltage to Ground Potential[1].............–2.0V to+7.0V

DC Output Current, per Pin[1]...................–25 mA to +25 mA

DC Input Voltage[1].........................................–2.0V to +7.0V

Note:

1. Mini mum DC input is –0.3V. During transactions, the inputs may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods

shorter than 20 ns.

Pin Configuration

Selection Guide

7C343B-25 7C343B-30 7C343B-35

Maximum Access Time (ns) 25 30 35

I/O

453

1918 20

21 22

HLCC, PLCC

Top View

23 24 2625 27 28

44 43 4142 40

GND

I/O

VCC

INPUT

INPUT/CLK

INPUT

GND

INPUT

I/O

GND

I/O

C343B-2

7C343

I/O

INPUT

GND

VCC

INPUT

I/O

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to +70°C 5V ±5%

Industrial –40°C to +85°C 5V ±10%

Military –55°C to +125°C (Case) 5V ±10%

CY7C343B

Document #: 38-03038 Rev. ** Page 3 of 12

Electrical Characteristics Ov er the Op erating Range

Parameter Description Test Conditions Min. Max. Unit

VCC Supply Voltage Maximum VCC rise time is 10 ms 4.75(4.5) 5.25(5.5) V

VOH Output H IGH Voltage IOH = –4.0 mA DC[2] 2.4 V

VOL Output LO W Vo lta ge IOL = 8 mA DC[2] 0.45 V

VIH Input HIGH Level 2.0 VCC+0.3 V

VIL Input LOW Level –0.3 0.8 V

IIX Input Current VI = VCC or ground –10 +10 µA

IOZ Output Lea ka ge Cu rren t VO = VCC or ground –40 +40 µA

tRRecom m end ed Inp ut Rise Time 100 ns

tFRecommended Input Fall Time 100 ns

Capacitance

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance VIN = 0V, f = 1.0 MHz 10 pF

COUT Output Capacitance VOUT = 0V, f = 1.0 MHz 20 pF

Note:

2. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current.

AC Test Loads and W aveforms

3.0V

OUTPUT

R1 464Ω

250Ω

50 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10% 90%

10%

<6 ns

OUTPUT

R1 464Ω

250Ω

5pF

INCLUDING

JIG AN D

SCOPE

(a) (b)

OUTPUT 1.75V

Equivalent to: THÉ VENIN EQUIVALENT (commercial/military)

ALL INPUT PULSES

C343B-4 C343B-5

163 Ω

<6 ns

CY7C343B

Document #: 38-03038 Rev. ** Page 4 of 12

Programmable Interconnect Array

The Programmable Interconnect Array (PIA) solves intercon-

nect limitations by routing only the signals needed by each

logic array block. The inputs to the PIA are the outputs of every

macrocell within the device and the I/O pin feedback of every

pin on the device.

Unlike masked or programmable gate arrays, which induce

variable delay dependent on rou ting, the PIA has a fixed delay.

This eliminates undesired skews among logic signals, which

may cause glitches in internal or external logic. The fixed de-

lay , regardless of programmable interconnect array configura-

tion, s implifies design by ensuring tha t internal signal ske ws or

races are avoided. The result is simpler design implementa-

tion, often in a single pass, without the multiple internal logic

placem ent and ro uting ite rations require d for a programm able

gate array to achieve design timing objectives.

Design Recommendations

Operation of the devices described herein with conditions

above those listed under “Absolute Maximum Ratings” may

cause permanent dam age to the de vice. This is a stress ratin g

only and functional operation of the device at these or any

other c ond iti ons a bov e those indi cated in th e ope rati ona l sec-

tions of this data sheet is not implied. Exposure to absolute

maxim um ratings cond itions for exte nded p eriods of time may

affect device reliability. The CY7C343B contains circuitry to

protect device pins from high static voltages or electric fields;

however, normal precautions should be taken to avoid apply-

ing any voltage higher than maximum rated voltages.

For proper operation, input and output pins must be con-

strained to the range GND < (VIN or VOUT) < VCC. Unused

inputs mu st alway s be tied to an approp riate logic le vel (either

VCC or GND). Each set of VCC and GND pins must be con-

nected together directly at the device. Power supply decou-

pling c apacitors of a t least 0.2 µF mu st be conn ected betwee n

VCC and GND. For the most effective decoupling, each VCC

pin should be separately decoupled to GND, directly at the

device. Decoupling capacitors should have good frequency

respons e, suc h as mo nol ith ic ce ram ic types .

Timing Considerations

Unless otherwise stated, propagation delays do not include

expanders. When using expanders, add the maximum ex-

pander delay tEXP to the overall delay. Similarly, there is an

additional tPIA delay for an input from an I/O pin when com-

pared to a signal from a straight input pin.

When calculating synchronous frequencies, use tS1 if all inputs

are o n the input pins . When expa nder l ogic is u sed i n the data

path, add the appropriate maximum expander delay, tEXP to

tS1. Determ in e wh ich of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + t S1)

is the l owest f requency. The l owest of th ese freque ncies i s the

maxim um data path freque ncy f or the sy nchron ous c onfigu ra-

tion.

Typical ICC vs. fMAX

Output Drive Current

When calculating external asynchronous frequencies, use

tAS1 if all inputs are on dedicated input pins.

When expander logic is used in the data path, add the appro-

priate maximum expander delay, tEXP to tAS1. Determine

which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the low-

est frequency. The lowest of these frequencies is the maxi-

mum data path frequency for the as ynchronou s configura tion.

The parameter tOH indicates the system compatibility of this

device when driving other synchronous logic with positive in-

put hold times, which is controlled by the same synchronous

clock. If tOH is greater than the minimum required input hold

time of the subsequent synchronous logic, then the devices

are guaranteed to function properly with a common synchro-

nous clock under worst-case environmental and supply volt-

age conditions.

200

150

100

1 kHz 10 kHz 100 kHz 1 MHz

MAXIMUM FREQUENCY

10 MHz

050 MHz100 Hz

ACTIVE (mA) Ty p.

VCC = 5.0V

Room Temp.

C343B–7

01 2 3 4

I OUTPUT CURRENT (mA) TYPICAL

VOOUTPUTVOLT AG E (V)

250

200

150

100

IOH

IOL

VCC = 5.0V

Room Temp.

C343B–8

CY7C343B

Document #: 38-03038 Rev. ** Page 5 of 12

Figure 1. CY7C343B Internal Timing Model

External Synchronous Switching Characteristics Over Operating Range

Parameter Description

7C343B-25 7C343B-30 7C343B-35

UnitMin. Max. Min. Max. Min. Max.

tPD1 De dicated Input to Combinatorial Output

Delay[3] Com’l/Ind 25 30 35 ns

tPD2 I/O Input to Combinatorial Output Delay[3] Com’l/Ind 40 45 55 ns

tSU Global clock setup time Com’l/ Ind 15 20 25 ns

tCO1 Synchro nous Clock In put to Output

Delay[3] Com’l/Ind 14 16 20 ns

tHInput Hold Time from Synchronous Clock

Input Com’l/Ind 000ns

tWH Synchronous Clock Input HIGH Time Com’l/Ind 810 12.5 ns

tWL Synchrono us Clock Input LOW Time Com’l/Ind 810 12.5 ns

fMAX Maximum Register Toggle Frequency[4] Com’l/Ind 62.5 50 40 MH

tCNT Minimum Global Clock Period Com’l/Ind 20 25 30 ns

tODH Output Data Hold Time After Clock Com’l/Ind 222ns

fCNT Maximu m Inte rnal Glob al Cloc k

Frequency[5] Com’l/Ind 50 40 33.3 MH

Notes:

3. C 1 = 35 pF.

4. The fMAX values represent the highest frequency for pipeline data.

5. This parameter is measured with a 16-bit counter programmed into each LAB.

LOGIC ARRAY

CONTROL DELAY

tLAC

EXPANDER

DELAY

tEXP

CLOCK

DELAY

tIC

tRD

tCOMB

tLATCH

INPUT

DELAY

tIN

PIA

DELAY

tPIA

OUTPUT

DELAY

tOD

tXZ

tZX

LOGIC ARRAY

DELAY

tLAD

FEEDBACK

DELAY

tFD

I/O DELAY

tIO

INPUT/

OUTPUT

INPUT

C343B-9

SYSTEM CLOCK DELAY tICS

tRH

tRSU

tPRE

tCLR

CY7C343B

Document #: 38-03038 Rev. ** Page 6 of 12

External Asynchronous Switching Characteristics Ove r Operat ing Ra nge

Parameter Description 7C343B-25 7C343B-30 7C343B-35 Unit

Min. Max. Min. Max. Min. Max.

tACO1 Asynchronous Clock Input to Output

Delay[3] Com’l/Ind 25 30 35 ns

tAS1 Dedicated Input or Feedback Set-Up

Time to Asynchr onous Cl ock Input Com’l/Ind 5 6 8ns

tAH Input Hold Time from Asynchronous

Clock Input Com’l/Ind 6 8 10 ns

tAWH Asynchronous Clock Input HIGH

Time[6] Com’l/Ind 11 14 16 ns

tAWL Asynchronous Clock Input LOW

Time[6] Com’l/Ind 911 14 ns

tACNT Minimum Internal Array Clock

Frequency Com’l/Ind 20 25 30 ns

fACNT Maximum Internal Array Clock

Frequency[5] Com’l/Ind 50 40 33.3 MHz

Internal Switching Characteristics Over Operating Range

Parameter Description 7C343B-25 7C343B-30 7C343B-35

Min. Max. Min. Max. Min. Max. Unit

tIN Dedicat ed In put Pa d and Buf fe r Dela y Com’l/Ind 5 7 11 ns

tIO I/O Input Pad and Buffer Delay Com’l/Ind 6 6 11 ns

tEXP Expander Array Delay Com’l/Ind 12 14 20 ns

tLAD Logic Array Data Delay Com’l/Ind 12 14 14 ns

tLAC Logic Array Control Delay Com’l/Ind 10 12 13 ns

tOD Output Buffer and Pad Delay[3] Com’l/Ind 556ns

tZX Output Buffer Enable Dela y[3] Com’l/Ind 10 11 13 ns

tXZ Output Buffer Disable Delay[7] Com’l/Ind 10 11 13 ns

tRSU Register Set-Up Time Relative to

Clock Signal at Register Com’l/Ind 6 8 12 ns

tRH Register Hold Time Relative to Clock

Signal at Regis ter Com’l/Ind 468ns

tLATCH Flow-Through Latch Delay Com’l/Ind 344ns

tRD Register Delay Com’l/Ind 122ns

tCOMB Transparent Mode Delay Com’l/Ind 344ns

tIC Asynchronous Clock Logic Delay Com’l/Ind 14 16 18 ns

tICS Synchro no us C loc k Delay Com’l/Ind 321ns

tFD Feedback Delay Com’l/Ind 112ns

tPRE Asynchronous Register Preset Time Com’l/Ind 567ns

tCLR Asynchronous Register Clear Time Com’l/Ind 567ns

tPIA Programmable Inte rco nne ct Array

Delay Time Com’l/Ind141620ns

Notes:

6. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the tACH and tACL parameter must be swapped.

7. C1 = 5 pF.

CY7C343B

Document #: 38-03038 Rev. ** Page 7 of 12

Switching Waveforms

C343B-10

tXZ tZX

tOD

HIGH IMPEDANCE

STATE

CLOCK FROM

LOGIC ARRAY

DATA FROM

OUTPUT PIN

tRD

Internal Synchronous

Internal Asynchronous

tIO tAWH tAWL tF

tIN

tIC

tSU tRH

tRD,tLATCH tFD tCLR,tPRE tFD

CLOC K PIN

LOGIC ARRAY

CLOCK FROM

DATA FROM

CLOCK INTO

LOGIC ARRAY

TO ANOTHER LAB

tPIA

TO LOCAL LAB

LOGIC ARRAY

C343B-11

tIN tICS

tRSU tRH

C343B-12

Internal Synchronous

SYSTEM CLOCK PIN

SYSTEM CLOCK

AT REGIS T ER

DATA FROM

LOGIC ARRAY

CY7C343B

Document #: 38-03038 Rev. ** Page 8 of 12

Switching Waveforms (continued)

Internal Combinatorial tIN

tEXP

tLAC,t

LAD

C343B-13

tCOMB tOD

INPU T PIN

I/O PI N

LOGIC ARRAY

OUTPUT

INPUT

ARRAY DELAY

EXPANDER

OUTPUT

tIO

External Combinatorial

DEDICATED INPUT/

I/O INPUT

COMBINATORIAL

OUTPUT

C343B-14

tPD1/tPD2

C343B-15

tWL

tSU tH

LOGIC ARRAY

tWH

External Synchronous

CLOCK AT REGISTE R

SYNCHRONOUS

LOGIC ARRAY

DATA FROM

REGISTERED

CLOCK PIN

OUTPUTS

tCO1

CY7C343B

Document #: 38-03038 Rev. ** Page 9 of 12

Ordering Information

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

25 CY7C343B-25HC/HI H67 44-Pin Win dowed Leaded Chip Carrier Commercial/Industrial

CY7C343B-25JC/JI J67 44-Lead Plastic Leaded Chip Carrier

30 CY7C343B-30JC/JI J67 44-Lead Plastic Leaded Chip Carrier Commercial/Industrial

35 CY7C343B-35HC/HI H67 44-Pin Win dowed Leaded Chip Carrier Commercial/Industrial

CY7C343B-35JC/JI J67 44-Lead Plastic Leaded Chip Carrier

Switching Waveforms (continued)

External Async hrono us

tAH

tAS1 tAWH tAWL

DEDICATED INPUTS OR

REGISTERED FEED BACK

C343B-16

ASYNCHRONOUS

CLOCK INPUT

CY7C343B

Document #: 38-03038 Rev. ** Page 10 of 12

Package Diagrams

44-Pin Windowed Leaded Chip Carrier H67

51-80079

CY7C343B

Document #: 38-03038 Rev. ** Page 11 of 12

of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cy press Semi conductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi

ng so indemnifies Cypress Semiconductor against all charges.

Package Diagrams (continued)

44-Lead Plastic Leaded Chip Carrier J67

51-85003-A

CY7C343B

Document #: 38-03038 Rev. ** Page 12 of 12

Document Title: CY7C343B 64-Macrocell Max ® EPLD

Document Number: 38-03038

REV. ECN NO. Issue

Date Orig. of

Change Description of Change

** 106461 07/11/01 SZV Change from Spec Number: 38-00862 to 38-03038