HIP6006CBZ-TS2662 - Intersil Corporation

TM HIP6006

Buc k and Synchronous-Re ctifier

Pulse-W i dth Modulator (PWM ) Co ntroller

The HIP6006 provides complete control and protection for a

DC-DC converter optimized for high-performance

microprocessor applications. It is designed to drive two

N Channel MOSFETs in a synchronous-rectified buck

topology. The HIP6006 integrates all of the control, output

adjus tment, monit oring and prote ction f uncti ons into a sin gle

package.

The output voltage of the converter can be precisely

regulated to as low as 1 .27V, with a maximum tolerance of

±1% over temperature and line voltage variations.

The HIP6006 provides simple, single feedback loop,

volt age-mode contr ol with fast transient response. It includes

a 200kHz free-running triangle-wave oscillator that is

adj u stab le fr o m be lo w 5 0 k H z to ove r 1 M H z . Th e e rror

amp l ifi er features a 15M H z gain-b andw idth p roduct and

6V/µs slew rate w hich enables h igh converter bandwidth for

fast transient performance. The resulting PWM duty ratio

ranges from 0% to 100%.

The HIP6006 protects against over-current conditions by

inhi biting P WM ope rati on. The HI P6006 monit ors the cur rent

by using the rDS(ON) of the upper MOSFET which eliminates

the need for a current sensing resistor.

Pinout

HIP6006

(SOIC, TSSOP)

T OP VIEW

Features

• Drives Two N-Channel MOSFETs

• Operates From +5V or +12V Input

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

• Fast Transient Response

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Ratio

• Excellent Output Voltage Regulati on

- 1.27V Internal Reference

-±1% Over Line Voltage and Temperature

• Over-Current Fault Monitor

- Does Not Require Extra Current Sensing Element

- Uses MOSFETs rDS(ON)

• Small Converter Size

- Constant Frequency Operation

- 200kHz Free-Running Oscillator Programmable from

50kHz to Over 1MHz

• 14 Pin, SOIC and TSSOP Package

Applications

• Power Supply for Pentium®, Pentium Pro, PowerPC™

and Alpha™ Microprocessors

• High-Power 5V to 3.xV DC-DC Regulators

• Low-Voltage Distributed Power Supplies

OCSET

COMP

RT VCC

LGATE

PGND

BOOT

UGATE

PHASE

GND

PVCC

Ordering Information

PART NUMBER TEMP.

RANGE (oC) PACKAGE PKG.

NO.

HIP6006 C B 0 to 70 14 Ld SOI C M14.15

HIP6006CV 0 to 70 14 Ld TSSOP M14.173

HIP6006CB-T 0 to 70 14 Ld SOIC) (T&R) M14.15

HIP 6006 CV-T 0 to 70 14 Ld TSSO P

(T&R) M14.173

Data S heet April 200 1 File Num ber 4306.2

CAU T I ON : Th es e de v i c es a re s ens i ti v e t o el ec tr os tat i c d i s charge; f ol l ow p rope r I C Handling Proced ur e s .

1-888-INTERSIL or 321-724-7143 |Intersil and Design is a trademark of Intersil Americas Inc.

Copy r ight © Intersil Americas Inc. 2001, All R ights Reserved

PowerPC™ is a trademark of IBM.

Alpha™ is a trademark of Digital Equipment Corporation.

Pentium® is a registered trademark of Intel Corporation.

Typ ical Application

Block Diagram

12V

+VO

PGND

HIP6006

COMP

GND

OSC

LGATE

UGATE

OCSET

PHASE

BOOT

VCC +5V OR +12V

PVCC +12V

MONITOR AND

PROTECTION

REF

OSCILLATOR

SOFT-

START

POWER-ON

RESET (POR)

INHIBIT

PWM

COMPARATOR

ERROR

AMP

VCC

PWM

GND

OCSET

COMP

1.27 VREF

OVER-

CURRENT

GATE

CONTROL

LOGIC

BOOT

UGATE

LGATE

PHASE

PGND

200µA

PVCC

10µA

REFERENCE +

HIP6006

Absolute Maximu m Rating s Thermal Informat ion

Su pply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15.0V

Boot Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . . +15.0V

Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.3V to VCC +0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 2

Operating Conditions

Su pply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0oC to 70oC

Junction Temperature Range. . . . . . . . . . . . . . . . . . . .0oC to 125oC

Th ermal Re si stance ( Typic al, Note 1 ) θJA (oC/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC

Max imum S t or age Te mp eratur e Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

(L ea d tips on ly )

CAUTIO N: S tresses above those listed in “Abso lute Max im um Ra tings” ma y cause per manent damage to the devi ce. This is a stress only r ating and operat ion of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Speci fications Recommended Operating Conditions, Unless Otherwise Noted

PARAMETER SYMBOL TEST CONDITIONS MIN TYP M AX UNITS

VCC SUPPLY CURRENT

Nominal Supply ICC EN = VCC; UGATE and LGATE Open - 5 - mA

Shutdown Supply EN = 0V - 50 100 µA

POW ER - O N RESET

Rising VCC Threshold VOCSET = 4.5VDC - - 10.4 V

F al lin g VCC Threshold VOCSET = 4.5VDC 8.2 - - V

Enable - Input threshold Voltage VOCSET = 4.5VDC 0.8 - 2.0 V

Rising VOCSET Threshold -1.27- V

OSCILLATOR

F ree R u nning Fr eq uenc y RT = OPEN, VCC = 12 185 200 215 kHz

T ota l Variat ion 6kΩ < RT to GND < 200kΩ-15 - +15 %

Ramp Amplitude ∆VOSC RT = OPEN - 1.9 - VP-P

REFERENCE

Reference Voltage 1.258 1.270 1.282 V

ERROR AMPLIFIER

DC Gain -88- dB

Ga in - Ban dw idt h P rod uc t GBW - 15 - MH z

Slew Rate SR COMP = 1 0pF - 6 - V/µs

GATE DRIVERS

Upper Gate Source IUGATE VBOOT - VPHASE = 12V, VUGATE = 6V 350 500 - mA

Upper Gate Sink RUGATE ILGATE = 0.3A - 5.5 10 Ω

Lower Gate Source ILGATE VCC = 12V, VLGATE = 6V 300 450 - mA

Lower Gate Sink RLGATE ILGATE = 0.3A - 3.5 6.5 Ω

PROTECTION

OCSET Current Source IOCSET VOCSET = 4.5VDC 170 200 230 µA

Soft Sta rt Curre nt ISS -10- µA

HIP6006

Functional Pin Description

RT (Pin 1)

This pin provides oscillator switching frequency adjustment.

By placing a resistor (RT) from this pin to GND, the nominal

200kH z s w itchi n g fr equency is incre ased according to the

following equation:

Conversely, connecting a pull-up resistor (RT) from this pin

to VCC reduces the switching frequency according to the

following equation.:

OCSET (P in 2)

Connect a resistor (ROCSET) from this pin to the dr ain of the

upper MOSFET. ROCSET, an internal 200µA current source

(IOCS), and the upper M O SFET on-resistance (rDS(ON)) set

the converter over-current (OC) trip point according to the

following equation:

An over-current trip cycles the soft-start function.

SS (Pin 3)

Co nn e ct a cap a cit or fro m th is p in to g ro und. Th is ca pa citor,

along with an internal 10µA current source, sets the soft-

start inte rval of the converter.

COMP (Pin 4) and FB (Pin 5)

COM P and FB a r e the av a ilable external pins of the error

am plif ier. Th e FB p i n is th e in ve rting in pu t of the error

amplifier and the COMP pin is the error amplifier output.

These pins are used to compensate the voltage-control

feedback loop of the converter.

E N (Pin 6)

Th is p in is th e open-collector enable pin. Pull this pin below

1V to disable the converter. In shutdown, the sof t start pin is

discharged and the UGATE and LGATE pins are held low.

GND (Pin 7)

Signal ground for the IC. All voltage levels are measured

with respect to this pin.

PHASE (Pin 8)

Connect the PHASE pin to the upper MOSFET sourc e. This

pin is used to monitor the voltage drop across the MOSFET

for over-current protection. This pin also provides the return

path for the upper gate drive.

UGATE (Pin 9)

Co nn ec t UG ATE to th e upper MOSFET gate. Thi s pin

provides the gate drive for the upper MOSFET.

BOOT (Pin 10)

This pin provides bias voltage to the upper MOSFET driver.

A bootstrap circuit may be used to create a BOOT voltage

suitable to drive a standard N-Channel MOSFET.

PGND (Pin 11)

This i s the power ground conn ect ion. T ie the lower MOSFET

source to this pin.

Typical Performance Curves

FIGURE 1. RT RESISTANCE vs FREQUENCY FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY

10 100 1000

SWITCHING F REQUENCY ( kHz)

RESISTANCE (kΩ

ΩΩ

Ω)

100

1000 RT PULLUP

TO +12V

RT PULLDOWN

TO VSS

100 200 300 400 500 600 700 800 900 1000

IVCC (mA)

SWITCHING FREQUENCY (kHz)

CGATE = 1000pF

CGATE = 3300pF

CGATE = 10pF

OCSET

COMP

RT VCC

LGATE

PGND

BOOT

UGATE

PHASE

GND

PVCC

Fs 200kHz 510

•

RTkΩ()

---------------------+≈(RT to GND)

Fs 200kHz 410

•

RTkΩ()

---------------------–≈(RT to 12V)

IPEAK IOCS ROCSET

•

rDS ON()

--------------------------------------------=

HIP6006

LGATE (Pin 12)

Connect LGATE to the lower MOSFET gate. This pin

provides the gate drive for the lowe r MOSFE T.

PVCC (Pin 13)

Provide a bias supply for the lower gate drive to this pin.

VCC (Pin 14)

Provide a 12V bias supply for the chip to this pin.

Fun ctio nal Descr ipt ion

Initialization

The HIP6006 autom atically initializes upon receipt of power.

Special sequenci ng of the input supplies is not necessary.

The Power-On Reset (POR ) function continually monitors

the input supply voltages and the enable (EN) pin. The POR

monitors the bias voltage at the VCC pin and the input

voltage (V IN) on the O CSET pin. The level on OCSET is

equal to VIN Less a fix ed voltag e d rop (se e ov er- curr ent

protection). With the EN pin held to VCC, the POR function

initia te s s oft start operation after both input supply voltages

exceed their POR thresholds. For operation with a single

+12V pow er source, VIN and VCC are equivalent and the

+12V power source must exceed the rising VCC threshold

before POR initiates operation.

The Power-On Reset (POR) function inhibits operation with

the chip disabled (EN pin low). With both input supplies

abo ve their POR thre shol ds, tr an sition ing t he EN pin high

initia te s a so ft s tar t i n terv al.

Soft Start

The POR function initiates the s oft start sequence. An internal

10µA cu r ren t so ur ce ch ar ges an extern a l ca pac i t or (CSS) on

the SS pin to 4V. Soft start clamps the error amplifier output

(COMP pin) and reference input (+ terminal of error amp) to

the SS pin volt age. F ig ure 3 shows the soft start interval wi t h

CSS = 0.1µF. Initially the cla mp on the erro r amplifier (CO MP

pin) controls the converter’s output voltage. At t1 in Figure 3,

the SS voltag e reaches the valley of the oscillator’s triangle

wave. The oscillator’s triangular waveform is compared to the

ramping error amplifier voltage. This generates PHASE

pulses of increasing width that charge the output capacitor(s).

This i nt er val o f i ncreasing pulse width continues t o t2 . Wit h

sufficient output voltage, the clamp on the reference input

controls the output voltage. This is the interval between t2 and

t3 in Figure 3. At t3 the SS voltage exceeds the reference

voltage and the output voltage is in regulation. This method

prov i d es a ra pi d and contro l l ed ou t put v oltage rise.

Over-Current Protection

The over-current function protects the converter from a

sho rte d output by using the upper MOSFETs on-resistance,

rDS(ON) to monitor the current. This method enhances the

converter’s efficiency and reduces cost by eliminating a

current sensing resis tor.

The over-current function cycles the soft-start function in a

hicc up mode t o provid e fault protect ion. A resi stor (R OCSET)

programs the over-current trip level. An internal 200µA

(ty pical ) curr ent sink develop s a vol tage ac ros s R OCSET that

is re fe ren ce to V IN. When the voltage across the upper

MOSFET (also referenced to VIN) exceeds the voltage

across ROCSET, the over-current function initiates a soft-

start sequence. The soft-start function discharges CSS with

a 10µA current sink and inhibits PW M operation. The soft-

start function recharges CSS, and PW M operation resumes

with the error ampli fier clamped to the SS voltage. Should an

overload occur while recharging CSS, the soft start function

inhibits PWM operation while fully charging CSS to 4V to

TIME (5m s/DIV )

SOFT-START

(1V/DIV)

t1 t2 t3

OUTPUT

(1V/DIV)

VOLTAGE

FIGURE 3. SOFT-START I NTERVAL

OUTPUT INDUCTOR SOFT-START

TIME ( 20ms/DIV)

10A

15A

FIGURE 4. OVER-CURRENT OPERATION

HIP6006

complete its cycle. Figure 4 shows this operation with an

overload co ndition. Note that the inductor c urrent inc reases

to over 15A during the CSS charging interval and causes an

over-current trip. The converter dissipates very little power

with this m ethod. The measured input power for the

conditions of Figure 4 is 2.5W.

The over-current function will trip at a peak inductor current

(IPEAK) determined by:

where IOCSET is the internal OCSET current source (200µA

- typical). The OC trip point varies mainly due to the

MOSFETs rDS(ON) variations. To avoid over-current t ri p pin g

in th e normal oper ating load range, find the ROCSET resistor

from the equation above with:

1. The maximum rDS(ON) at the highest junction

temperature.

2. The minimum I OCSET from t he sp ecificat ion t able.

3. Determine ,

where ∆I is the output inductor ripple current.

For a n equation for the ripple current see the section under

component guidelines titled ‘Output Inductor Selection’.

A sm all c erami c capacitor should be pl aced in parallel with

ROCSET to smooth the voltage across ROCSET in the

pre senc e of s witc hing noise on the input v oltage.

Application Guidelines

Layout C onsiderat ions

As in any high frequen cy s witching conver t e r, layou t is v ery

important. Switching current from one power device to

another can generate voltage transients across the

impedances of the interconnecting bond wires and circuit

traces. These interconnecting impedances should be

minimized by using wide, short printed circuit traces. The

critical components should be located as close together as

possible using ground plane construction or single point

grounding.

Figure 5 shows the critical power components of the

converter. To minimize the voltage overshoot the

int erconnec ting wires indicated by heav y lines sho uld be part

of ground or power plane in a printed circuit board. The

components shown in Figure 6 should be located as close

together as possible. Please note that the capacitors CIN

and CO each represent numerous physica l capacitor s.

Locate the HIP6006 within 3 inches of the MOSFETs, Q1

and Q2. The circuit traces for the MOSFETs’ gate and

source connections from the HIP6006 must be sized to

handle up to 1A peak current.

Figure 6 shows the circuit traces that require additional

layout consideration. Use single point and ground plane

construction for the circuits shown. Minimize any leakage

current paths on the SS PIN and locate the capacitor, Css

close to the SS pin because the internal current source is

only 10µA. Provide local VCC decoupling between VCC and

GND pins. Loc ate the capacitor , CBOOT as close as pract ical

to the BOOT and PHASE pins.

Feedba ck Compensation

Figure 7 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

(Vout) is regulated to the Reference voltage level. The error

amplifier (Error Amp) output (VE/A) is compared with the

oscillator (O SC) triangular wave to provide a pulse-width

modulated (PWM) wave with an amplitude of VIN at the

PHASE node. The PWM wave is smoothed by the output filter

(LO and CO).

The modulator transfer function is the small-signal transfer

function of Vout/V E/A. This function is dominated by a DC

Gain and the output filter (LO and CO), with a double pole

break frequ ency at FLC and a zero at FESR. The DC Gain of

the modul at or is sim ply t he input vol tag e (VIN) divided by t he

peak-to-peak oscillator voltage ∆VOSC.

IPEAK IOCSET ROCSET

•

rDS ON()

---------------------------------------------------=

IPEAK for IPEAK IOUT MAX()

∆I()2⁄+>

PGND

LGATE

UGATE

PHASE

Q2 D2

FIGURE 5. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

VIN

VOUT

RETURN

HIP6006

CIN

LOAD

FIGURE 6. PRINTED CIRCUIT BOARD SM ALL SIGN AL

LAYOUT GUIDELINES

+12V

HIP6006

GND

VCC

BOOT D1 LO

VOUT

LOAD

PHASE

+VIN

CBOOT

CVCC

CSS

HIP6006

Modulator Break Frequ ency Equatio ns

The compensation network consists of the error amplifier

(internal to the HIP6006) and the impedance networks ZIN

and ZFB. The goal of the compensat ion network is to pr ovi de

a closed loop tr ansfer fu nction with the highes t 0dB crossi ng

fre quenc y (f0dB) and adequate phas e margi n. Phase m argin

is the difference between the closed loop phase at f0dB and

180o. The equations below relate the compensation

network’s poles, zeros and gain to the components (R1, R2,

R3, C1, C2, and C3) in Figure 8. Use these guidelines for

lo cati ng the poles and zeros of the compensation network:

Compensation Break Frequency Equations

1. Pi ck Gain (R2/R1) for desired converter bandwidth

2. Pl ace 1ST Zero Below Filter’s Doubl e Pole

(~75% F LC)

3. Pl ace 2ND Zero at Filter ’s Double Pole

4. Pl ace 1ST Pole at the ESR Zero

5. Pl ace 2ND Pole at Half the Switc hing Frequency

6. Check Gain against Error Amp lifier’s Open-Loop Gain

7. Est imate Phase Margin - Repeat if Necessary

Figure 8 shows an asymptotic plot of the DC-DC converter’s

gain vs frequency. The actual Modulator Gain has a high

gain peak do to the high Q factor of the output filter and is

not shown in Figure 8. Using the above guidelines should

give a Compensation Gain similar to the curve plotted. The

open loop error amplifier gain bounds the compensation

gain. Check the compensation gain at FP2 with the

c apa bi l it i es o f t he error am pl i fi er. The Closed Loop Gain is

constructed on the log-log graph of Figure 8 by adding the

Modulator Gain (in dB) to the Compensation Gain (in dB).

This is equivalent to multiplying the modulator transfer

function to the compensation transfer f unction and plotting

the gain.

The compensation gain uses external impedance networks

ZFB and ZIN to prov i de a stable, hi gh band width (B W)

overall loop. A stable control loop has a gain crossing with -

20dB/decade slope and a phase margin greater than 45o.

Include worst case component variations when determining

phase margin.

Compon ent Selection Guid elin es

Output Capacito r Selection

An output capacit or is requi red to filter the output and sup ply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current.

The load transient requirements are a function of the slew

rate (di/dt) and the magnitude of the transient load current.

These requirements are generally met with a mix of

capacitors and careful layout.

FIGURE 7. VOLTAGE - MODE BUCK CONVERTER

COMPENSATION DESIGN

VOUT

OSC

REFERENCE

ESR

VIN

∆VOSC

ERROR

AMP

PWM DRIVER

(PARASITIC)

REF

R2 C3

COMP

VOUT

ZFB

HIP6006

ZIN

COMPARATOR

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

VE/A

-ZIN

ZFB

FLC 1

2πLOCO

••

---------------------------------------= FESR 1

2πESR CO

•()•

---------------------------------------------=

FZ1 1

2πR•2C1•

----------------------------------=

FZ2 1

2πR1 R3+()C3••

------------------------------------------------------=

FP1 1

2πR2•C1 C2•

C1 C2+

----------------------





•

-------------------------------------------------------=

FP2 = 1

2πR3 C3••

----------------------------------

100

-20

-40

-60

FP1

FZ2

10M1M100K10K1K10010

OPEN LOOP

ERROR AMP GAIN

FZ1 FP2

FLC FESR

COMPENSATION

GAIN (dB)

FREQUENCY (Hz)

GAIN

20LOG

(VIN/∆VOSC)

MODULATOR

GAIN

20LOG

(R2/R1)

CLOSED LOOP

GAIN

FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

HIP6006

Mode rn micr oprocess ors produce tran sient load rates ab ove

1A/ns. High frequency capacitors initially supply the

transient and slow the current load rate seen by the bulk

capacitors. The bulk filter capac itor values are generally

determ ined by the E SR (effective series resist ance) and

voltage rating requirements rather than actual capacitance

requirements.

High frequency decoupling capacitors should be placed as

clos e to the po wer pi ns of t he load as p hysical ly pos si ble. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requ ir em ents. For example, Intel

recommends that the hig h frequency decoupling for the

Pentium Pro be composed of at least forty (40) 1.0µF

ceramic capacitors in the 1206 surface-mount package.

Use only specialized l ow-ESR capacitors intended for

switching- regul ator appli cati ons for the bulk capaci tor s.

The bulk c apa ci tor’s ESR will det ermine the o u tput ripple

voltage and the i n itial vo ltage drop aft er a hi gh sl ew-rate

transient. An aluminum electrolytic capacitor's ESR value is

related to the ca se si ze wi th l ower ESR avai la ble in lar ger

case sizes. However, the equivalent series inductance

(ESL ) of these capacitors inc reases with case size and can

reduce the usefulness o f the capacitor to high slew-rate

transient loadi ng. U nf ortunat ely, ESL is not a spe cified

paramet er. Work with your capacitor supplier and measure

the capac itor’s im pedance wi th freq uency t o sel ect a

suitable component. In most cases, multiple electrolytic

capac itors of small case size pe rfo rm better th an a s ingle

large case cap aci to r.

Outp ut Indu ct or S e lection

The out pu t in du ct or is se le c ted to meet the out pu t v o lt a ge

ripple requirements and minimize the converter’s response

ti me to t he load tr ans ient. The i nduct or value det ermi nes the

converter’s ripple current and the ripple voltage is a function

of the ripple current. The ripple voltage and current are

approximated by the following equations:

Incr easing the value of induc tance r educe s the r ipple current

and voltage. However, the large inductance values reduce

the converter’s response time to a load transient.

One of the paramete rs limit ing the convert er’s respons e to a

load transient is the time required to change the inductor

current. Given a suffic iently fast control loop design, the

HIP6006 will provi de eith e r 0% or 100% duty cycle in

response to a load transient. The response time is the time

required to slew the inductor current from an initial current

value to the transi ent current l evel. During this interva l the

difference between the inductor current and the transient

current l evel must be supplied by the output capacitor.

Minimizing the response time can minimize the output

capacitance required.

The response time to a transient is different for the

application of load and the removal of load. The following

equations give the approximate response time interval for

appli cati on and removal of a transient load:

where: ITRAN is the transient load current step, tRISE is the

respon se tim e to th e ap plicatio n of load, and tFALL is the

response time to the removal of load. With a +5V input

source, the worst case response time can be either at the

application or removal of load and dependent upon the

output voltage setting. Be sure to check both of these

equations at the minimum and maximum output leve ls for

the worst case response time.

Input Capaci tor Selection

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic

capaci tors for high freque ncy decoupling and bulk capacitor s

to supply the current needed each time Q1 turns on. Place

the small ceramic capacitors physically close to the

MOSFETs and between the drain of Q1 and the source of

Q2.

The im portant paramet er s for the bulk input capaci tor are th e

voltage rating and the R MS curren t rating. For reliable

operation, select the bulk capacitor with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum

input voltage and a voltage rating of 1.5 times is a

conservative guideline. The RMS current rating requirement

for the input capacitor of a buck regulator is approximately

1/2 the DC l oad current.

For a through hole design, several electrolytic capacitors

(Panasonic HFQ series or Nichicon PL series or Sanyo MV-

GX or equivalent) may be needed. For surface mount

designs, solid tantalum capacitors can be used, but caution

must be exercised with regard to the capacitor surge cu rrent

rating. These capacitors must be capable of handling the

surge-curr ent at power-up. The TPS series avail able from

AVX, and the 593D series from Sprague are bo th sur ge

current tested.

MOSFET Selecti on/Considerations

The HIP6006 requi res 2 N-Channel power MOSFETs. These

should be selected based upon rDS(ON), gate supply

requirements, and thermal management requirements.

In hi gh- cur ren t a pp li cat io ns, the MOSFET power dissipation,

package selection and heatsink are the dominant design

fac tors . T he p o wer dissi patio n in cludes two loss

components; conduction loss and switching loss. The

∆VOUT=∆I x ESR

∆I = VIN - VOUT

Fs x L

--------------------------------VOUT

VIN

----------------

•

tFALL LOITRAN

VOUT

-------------------------------=tRISE LOITRAN

VIN VOUT

–

--------------------------------=

HIP6006

conduction losses are the largest component of power

dissipation for both the upper and the lower MOSFETs.

These losses are distributed between the two MOSFETs

according to duty factor (see the equations below). Only the

upper MOSFET has switching losses, since the Schottky

rectifier clamps the switching node before the synchronous

rec tifie r tu r ns on .

The s e equati ons assume linear voltage-current transitions

and do not adequately model power loss due the reverse-

recovery of the lower MOSFETs body diode. The

gat e-c h ar ge lo sses a re dissipated by th e HIP6006 and don't

heat the MOSFETs. However, large gate-charge increases

the switching interval, tSW which increases the upper

MOSFET switching losses. Ensure that both MOSFETs are

within their maximum junction temperature at high ambient

temperature by calculating the temperature rise according to

package thermal-resistance specifications. A separate

heatsink may be necessary depending upon MO SFET

power, packa ge type, ambient temperature and air flow.

Standard-gate M OSFETs are normally recommended for

use with the HIP6006. However, logic-level gate MOSFETs

can be used und er spec ial c ircumst ances. The input volt age,

upper gate drive level, and the MOSFETs absolute gate-to-

source voltage rating determine whether logic-level

MO S F E Ts a re appropr ia t e .

Figur e 9 shows the uppe r gate drive (BOOT pin) supplied by

a bootst rap ci rcuit from VCC. T h e boot capacit or , CBOOT

develops a floating supply voltage referenced to the PHASE

pin. This supply is refreshed each cycle to a voltage of VCC

less the boot diode drop (V D) when the lower MOSFET, Q2

turns on. A logic-leve l MO SFET c an only b e used f or Q1 if

the MOSFETs absolute gate-to-source voltage rating

exceeds the maximum voltage applied to VCC. For Q2, a

logic-level MOSFET can be used i f its absolute ga te-to-

source voltage rating exceeds the maximum voltage applied

to PVCC.

Figure 10 shows the upper gate drive supplied by a direct

connection to VCC. This option should only be used in

converter systems where the main input voltage is +5 VDC

or less. The peak upper gate-to-source voltage is

approximately VCC less the input supply. For +5V main

power and +12 VDC for the bias, the gate-to-source voltage

of Q1 is 7V. A logic-level MOSFET is a good choice for Q1

and a logi c-level MOSFET can be used for Q2 if its absolute

gate-to-source voltage rating exceeds the maximum voltage

applied to PVCC.

Schottky Selection

Rectifier D2 is a clamp that catches the negative inductor

swi ng duri ng the dead time between turni ng off the lo wer

MOSFET and turning on the upper MOSFET. The diode must

be a Schottky type to prevent the lossy parasitic MOS FET

body diode from conducting. It is acceptable to omit the diode

and let the body diode of the lower MOSFET clamp the

negative inductor swing, but efficiency will drop one or two

perc ent as a result. The diode's r ated reverse breakd own

vol t age m ust be gr eater t han the maximum input vo l tage.

PUPPER = IO2 x rDS(ON) x D + 1

2Io x VIN x tSW x Fs

PLOWER = IO2 x rDS(ON) x (1 - D)

Wher e: D is the duty cycle = VO / VIN,

tSW is the switching interval, and

Fs is the switching frequency.

+12V

PGND

HIP6006

GND

LGATE

UGATE

PHASE

BOOT

VCC

+5V OR +12V

FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION

NOTE:

VG-S ≈

≈≈

≈ VCC - VD

NOTE:

VG-S ≈

≈≈

≈ PVCC

CBOOT

DBOOT

PVCC +5V

OR +12V

+12V

PGND

LGATE

UGATE

PHASE

BOOT

VCC

+5V OR LESS

FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION

NOTE:

VG-S ≈

≈≈

≈ VCC - 5V

NOTE:

VG-S ≈

≈≈

≈ PVCC

PVCC

+5V

OR +12V

HIP6006

GND

HIP6006

HIP 6006 DC-DC Conv erter Applic ation Circuit

The figure below shows an application circuit of a DC-DC

Converter for a microprocessor application. Detailed

in f orm ati on on the ci rcuit , in cluding a complete Bill-of-

Materials and circuit board description, can be found in

application note AN9722. Se e Intersil’s home pag e on the

web: www. intersil.com.

HIP6006

COMP

REF

GND

OSC

VCC

VIN

C1-3

C6-9

0.1µ

µµ

µF

2x 1µ

µµ

µF

0.1µ

µµ

µF

1µ

µµ

µF

15k

3x 680µ

µµ

µF

4x 1000µ

µµ

µF

UGATE

OCSET

PHASE

BOOT

SPARE

CR1

3.01k

1000pF

CR2

C13 R1

R3 R4

C15 R5

C14

C12

C17-18

C19

C20

4148

RTN

12VCC

14 2

SPARE

PGND

LGATE

PVCC

JP1

1206

MBR

340

VOUT

RTN

ENABLE

COMP

TP1

PHASE

TP2

10k

MONITOR AND

PROTECTION

C16

0.01µ

µµ

µF

33pF

SPARE

Compo nent Selection Notes:

C1-C3 - 3 each 680µF 25W VDC, Sanyo MV-GX or equi valent

C6-C9 - 4 each 1000µF 6. 3W VDC, Sanyo MV-GX or equivalent

L1 - Co re: Mic r om e tal s T 5 0-52B ; Wind ing: 10 Tu rns o f 17AW G

CR1 - 1N4148 or equivalent

CR2 - 3A, 40V Schottky, Motorola MBR340 or equivalent

Q1, Q2 - Intersil MOSFET; RFP25N05 FIGURE 11. DC-DC CONVERTER APPLICATION CIRCUIT

HIP6006

Thin Shrink Small Outline Plastic Packages (TSSOP)

INDEX

AREA E1

123

-B-

0.10(0.004) C AMBS

-A-

-C-

SEATIN G PL A N E

0.10(0.004) c

E0.25(0.010) BM M

0.25

0.010

GAUGE

PLANE

NOTES:

1. Thes e pack ag e di me ns io ns ar e wi th in al low ab le dime nsi o ns o f

JEDEC MO-153-AC, Issue E.

2. Dimensio ning and tolerancing per ANSI Y14 .5M-1982.

3. Dimens ion “D” do es not in clud e mold fl ash, protr usi ons or ga te burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per

side.

5. The chamf er on the b ody is op tiona l. If it is not pr esen t, a vi sual inde x

feature must be located within the crosshatched area.

6. “L ” i s t he length of te rmi nal f or soldering to a s ubst r a te.

7. “N” is th e num be r of ter m in al po sition s.

8. Terminal numb ers are shown for refe rence onl y.

9. Dimension “b” does not include dambar protrusion. Allowable dambar

protr usion shal l be 0.08mm (0.003 inch) t otal in excess o f “b” dimen-

sion at maximum material condition. Minimum space between protru-

sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controll ing dimens ion: M ILLIMET ER. Con vert ed inch dime nsio ns

ar e not ne c es sa r il y ex ac t. ( An gles i n deg rees )

0.05(0.002)

M14.173

14 LEAD THI N SHRINK SMALL OUTLINE PLASTIC

PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.047 - 1.20 -

A1 0.002 0.006 0.05 0.15 -

A2 0.031 0.051 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.195 0.199 4.95 5.05 3

E1 0.169 0.177 4.30 4.50 4

e 0 .026 BS C 0.65 BS C -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N14 147

α0o8o0o8o-

Rev. 1 6/00

All Intersil products are manufactured, assembled and tested utilizing ISO9000 q ua lity systems.

Int ers il Co rp oratio n’s qu alit y certific ation s c a n b e v i ewed at website ww w.inter si l.co m /d e sig n /quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.

Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Infor mation furnished by Inter sil is beli eved to be accurate and reliable. How-

ever, no responsibility is a ssume d by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties whi ch may resul t from its use.

No l icens e is granted by implication or otherwise under any pa tent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web sit ewww.intersil.com

Sales Of f i ce Headqu ar ters

NORTH AMERICA

Intersil Corporation

2401 Palm Bay Rd., Mail Stop 53-204

Palm Bay, FL 329 05

TEL: (3 21) 724-7000

FAX: (321) 724-7240

EUROPE

Intersil SA

Mercure Center

100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111

FAX: (32) 2.724.22.05

ASIA

Intersil Ltd.

8F-2, 96, Sec. 1, Chien-kuo North,

Taipei , Taiwan 104

Re public of China

TEL: 886-2-2515-8508

FAX: 886-2-2515-8369

HIP6006

Small Outline Plastic Packages (SOIC)

NOTES:

1 . Sy mb o l s a re de f in ed i n t he “ MO S er i es S ym b ol Li s t ” i n Se ct i o n 2.2 of

Pu blic ation N u mber 95 .

2. Dimensio ning and tolerancing per ANSI Y14 .5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead

fl as h and p ro t ru sions shall not ex ceed 0.25 m m (0.0 10 inch) per side.

5. The chamfer on the body is optional. If it is not prese nt, a visual index

feature must be located within the crosshatched area.

6. “L ” i s t he length of te rmi nal f or soldering to a s ubst r a te.

7. “N” is th e num be r of ter m in al po sition s.

8. Terminal numb ers are shown for refe rence onl y.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0. 61 m m (0.024 i nc h) .

10. Controll ing dimens ion: M ILLIMET ER. Con vert ed inch dime nsio ns

are not necessarily exact.

INDEX

AREA E

123

-B-

0.25(0.010) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45o

0.25(0.010) BM M

M14.15 (JED EC MS-012-AB ISSUE C)

14 LEAD NARROW BODY SMALL OUTLINE PLASTIC

PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMINMAXMINMAX

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.3367 0.3444 8.55 8.75 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N14 147

α0o8o0o8o-

Rev. 0 12/ 93