T UCT ROD ACEMEN at P E r T L e E P t L n E e O R OBS ENDED upport C om/tsc c . M S l l M si ECO Technica ww.inter Sheet NO RData r w u r o o IL act cont -INTERS 8 8 8 1 (R) EL7560 August 21, 1998 FN7294 Programmable CPU Power Supply Unit Features The EL7560 is the simplest, most cost effective method for powering modern high power CPUs which require a user adjustable output voltage. Although it is particularly designed to function with next generation CPUs, its simple design can provide low cost solutions for any 5V to 3V application. * 3.3V @ 12.4amps continuous * Internal FETs * >90% efficiency * Synchronous switching * 4-bit digitally adjustable output voltage The circuit uses on chip resistorless current sensing for high efficiency, stable current mode control. An on chip temperature sensor resets the OT pin. The OT pin can be tied directly to the OUTEN pin for automatic overtemperature shutdown. The user can adjust the oscillator frequency as well as the slope compensation. * User adjustable slope compensation * Internal soft start * Over temperature indicator * Low current sleep mode The output voltage is adjustable using a 4-bit parallel interface. A power OK signal "PWRGD' pulls high when the FB pin is within -7% of the programmed value. * Low parts count Pinout * Operates up to 1MHz * Pulse by pulse current limiting * High efficiency at light load EL7560 (28-PIN SOIC) TOP VIEW * 1% output accuracy * Sync function * Power good signal 5V Applications D2 1F C5 1 CP- FB 28 2 CP+ CREF 27 3 C2V CSLOPE 26 4 VSS COSC 25 100 +10V D1 R3 1K C4 D3 C8 10 5 VHI .1F C6 VOUT +2V - 3.5V VDD 24 .1F 30 6 LX 2.5H L1 4mF C10 +5V R2 10K VIN 23 7 LX VSSP 22 8 LX VIN 21 9 LX VSSP 20 10 LX VSSP 19 11 TEST VID0 18 12 PWRGD VID1 17 13 OT VID2 16 14 OUTEN VID3 15 * Local high power CPU supplies 68p C7 220p R1 1F C11 * PC motherboards 4.7F Ordering Information ACND L2 1.5H C1 C9 .1F 2mF 5V PART NUMBER TEMP. RANGE PACKAGE PKG. NO. EL7560CM -40C to +85C 28-Pin SOIC MDP0027 PGND OUTPUT VOLTAGE* SELECT * See VID Table on page 3 Note: * AGND and PGND should be connected at C10 * D3 is 1.235V reference. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. EL7560 Absolute Maximum Ratings (TA = 25C) Supply (VIN, VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Output Pins . . . . . . . . . . . . . . . -0.3V below GND, +0.3V above VDD Instantaneous Peak Output Current . . . . . . . . . . . . . . . . . . . . . .16A Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 135C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3W CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications PARAMETER VDD = VIN = 5V, COSC = 1nF, CSLOPE = 68pF, TA = 25C, unless otherwise specified (Note 1) DESCRIPTION CONDITION MIN TYP MAX UNITS 8.0 9 9.5 V 0.105 V 135 kHz V2X Voltage Doubler Output DACLSB DAC Resolution FOSC Oscillator Initial Accuracy FOSCTC Oscillator Tempco VRAMP Oscillator Ramp Amplitude MSS Soft Start Slope FOSC=500kHz IVID VID Pull Up Current VID = 0V ICSLOPE CSLOPE Charging Current IDD Supply Current IDDOFF Stdby Current RDSON Composite FET Resistance RDSONTC RDSON Tempco VOUT Output Initial Acurracy VID=0111 2.765 VRANGE Output Voltage Range VID=1110 to 0000 2.065 ILMAX Maximum current VOUT=0 VOUT-TC Output Tempco 0C<TA<70C VOUT-LINE Output Line Regulation VOUT=2.8, 4.5VDD<5.5, VDD=VIN -1 1 % VOUT-LOAD Output Load Regulation 0.3A<ILOAD<12.4A -1 1 % VOUT-TOT Output Total Variation -2 2 % OTOFF Over Temperature Threshold 135 C OTHYS Over Temperature Hysteresis 50 C VPWRGD Power Good Threshold with Respect to Desired OutputVoltage VDD-ON Minimum VDD form Startup VDD-OFF Maximum VDD for Shutdown VDD=5V, ILOAD=20mA 0.095 105 0C<TA<125C 120 0.1 %/C 1.2 V 0.3 V/msec 9 13 18 A 32 40 48 A OUTEN=4V FOSC=120kHz 25 35 mA OUTEN=0V 3 5 mA 25 m 18 0.1 VID=0111 -9 2.8 m/C 2.835 V 3.535 V 14.0 amps 1 % -7 -5 % 4 V 3.75 NOTE: 1. The oscillator and voltage doubler operate normally when VDD exceeds VDD-ON threshold, independent of the OUTEN logic level. 2 V EL7560 Voltage Identification Codes P6 PINS VID3 VID2 VID1 VID0 VDC 1 1 1 1 0, No CPU 1 1 1 0 2.1 1 1 0 1 2.2 1 1 0 0 2.3 1 0 1 1 2.4 1 0 1 0 2.5 1 0 0 1 2.6 1 0 0 0 2.7 0 1 1 1 2.8 0 1 1 0 2.9 0 1 0 1 3.0 0 1 0 0 3.1 0 0 1 1 3.2 0 0 1 0 3.3 0 0 0 1 3.4 0 0 0 0 3.5 3 EL7560 EL7560 Pin Descriptions PIN NUMBER NAME 1 CP- Negative input for the charge pump bootstrap capacitor. (Note 1) 2 CP+ Positive input for the charge pump bootstrap capacitor. (Note 1) 3 C2V Voltage doubler output. Pin requires at least a 1F capacitor to GND. (Note 1) 4 VSS Ground return for the control circuitry. 5 VHI Positive supply for the high side driver. This pin is bootstrapped from the LX pin with a 0.1F capacitor. 6 LX Common connection between the two large internal FETs. External inductor connection. 7 LX Same as pin 6. 8 LX Same as pin 6. 9 LX Same as pin 6. 10 LX Same as pin 6. 11 TEST 12 PWRGD 13 OT Overtemperature indicator. Pulls low when the die temperature exceeds 135C. Pin has 10mA pull-up. 14 OT A logic high on OUTEN enables the regulator (Note 1) 15 VID3 Bit 3(MSB) of the output voltage select DAC. 16 VID2 Bit 2 of the output voltage select DAC. 17 VID1 Bit 1 of the output voltage select DAC. 18 VID0 Bit 0(LSB) of the output voltage select DAC. 19 VSSP Ground return to the buck regulator. 20 VSSP Same as pin 19. 21 VIN 22 VSSP Same as pin 19. 23 VIN Same as pin 21. 24 VDD Pin supplies power to the internal control circuitry. 25 COSC 26 CSLOPE 27 CREF 28 FB DESCRIPTION This is test pin and must remain grounded at all times Pin pulls high when the FB pin is within - 7%(typ) of its programmed value. Positive power supply input to the buck regulator. Oscillator timing capacitor. Oscillator Frequency is approximately: FOSC(Hz)=0.0001/COSC(F). The duty cycle is approximately 5%. (Note 1) Slope compensation capacitor. External reference input pin. Voltage feedback pin for the buck regulator. NOTE: 1. The oscillator and voltage doubler operate normally when VDD exceeds VDD-ON threshold, independent of the OUTEN logic level. 4 EL7560 Typical Performance Curves IDD vs VDD Oscillator Frequency vs COSC 35 10000 30 Frequency (kHz) IDD (mA) 25 20 15 10 1000 100 5 0 1 2 3 4 5 10 10 6 100 VDD (V) 2.23 TA=25C TA=25C 3.535 IOUT = 0.3A 2.22 IOUT = 0.3A 3.525 2.21 3.515 VOUT (V) VOUT (V) 10000 Line Regulation (VID3:0=1101) ILine Regulation (VID3:0=0000) 3.545 IOUT = 4A 3.505 3.495 IOUT = 8A IOUT = 11A 3.475 3.465 4.4 4.6 4.8 5.0 5.2 5.4 IOUT = 4A 2.20 2.19 IOUT = 8A 2.18 3.485 IOUT = 11A 2.17 2.16 4.4 5.6 4.6 4.8 5.0 5.2 5.4 5.6 VIN (V) VIN (V) Load Regulation (VID3:0=1101) Load Regulation (VID3:0=0000) 3.54 2.25 VIN=5V VIN=5V 3.53 TA=25C 3.52 TA=25C 2.23 3.51 VOUT (V) VOUT (V) 1000 COSC (pF) 3.50 3.49 2.21 2.19 3.48 2.17 3.47 3.46 2.15 0 2 4 6 IOUT (A) 5 8 10 12 0 2 4 6 IOUT (A) 8 10 12 EL7560 Typical Performance Curves (Continued) VOUT vs CSLOPE 6 5 5 Load Reg (%) 4 4 Line Reg (%) Load Reg (%) VOUT (%) VOUT (%) VOUT vs CSLOPE 6 3 DVOUT (%) 2 DVOUT (%) Line Reg (%) 3 Load Reg (%) 2 1 1 DVOUT (%) 0 0 -1 -1 Line Reg (%) 0 50 100 150 200 0 250 50 100 150 200 RDSON vs Temp Efficiency vs Output Current 39 95 3.5V 90 35 85 Eficiency (%) RDSON (m) y = 0.1006x + 23.766 37 33 31 3.1V 80 2.1V 75 29 70 27 65 25 20 250 CSLOPE (pF) CSLOPE (pF) 40 60 80 60 0.3 100 120 140 160 Temperature(C) 1 2 3 4 5 8 11.2 12.4 IOUT Transient Load Step 0.3Amp to 12.4Amp Switching Waveforms ILOAD = 2A 2V/div V(LX) VOUT 20mV/div VOUT 20mV/div 6 EL7560 EL7560 Functional Block Diagram PWRGD, Pin 12 VID [0:3], Pin 15,16,17,18 Cp+, Pin 2 Cp-, Pin 1 To VOUT FB, Pin 28 C2V, Pin 3 V2X DAC - + VDD and VIN, Pin 21,23,24 + CREF, Pin 27 VDD + ISLOPE + - CSLOPE, Pin 26 VHI, Pin 5 LEB TDELAY Q + 4V LX, Pin 6,7,8,9,10 R Q S VDD UVLO RSS VSSP, Pin 19,20,21 OUTEN, Pin 14 R S - VDD FF + CSS Zero Cross Detect - S + COSC, Pin 25 - R + OT, Pin 13 Over Temp Sensor VSS, Pin 4 Thermal considerations and power dissipation: To achieve the maximum 12.4A continuous output current, the EL7560 is packaged in a 28 pin HSOP (Heat-Slug SO Package). Within the package, the EL7560 die is attached to one side of a copper slug. The other side of the slug is coincident with the package top surface, and is therefore exposed to the ambient environment. The copper slug provides an exceptionally low thermal resistance (JC) of typically 7C/W. To obtain low junction to ambient thermal resistance (JA), a heatsink is required to provide heat transfer path from the die to the ambient. The EL7560 power dissipation is a direct function of the "on" resistance of the internal power FETs (Rds-on) and the output current. For the maximum 12.4A output current and the worse case Rds-on at 125C (35m), the power dissipation is Iout2*R = 5.38W. To maintain 12.4A continuous output current operation at the maximum 70C ambient temperature, the die temperature must be kept below the 135C thermal shut down temperature. This requires a JA of 12C/W. To help achieve such a low JA with practical size heatsink, airflow is also required. Application note #13 shows the 11C/W thermal resistance can be achieved with the Wakefield heatsink #8052-60 and minimum 200LFM airflow. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7