Next Generation OP07 Ultralow
Offset Voltage Operational Amplifier
OP77
Rev. E
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113 ©2002–2010 Analog Devices, Inc. All rights reserved.
FEATURES
Outstanding gain linearity
Ultrahigh gain, 5000 V/mV min
Low VOS over temperature, 55 μV max
Excellent TCVOS, 0.3 μV/°C max
High PSRR, 3 μV/V max
Low power consumption, 60 mW max
Fits OP07, 725,108A/308A, 741 sockets
Available in die form
PIN CONNECTIONS
V
OS
TRIM
1
–IN
2
+IN
3
V–
4
V
OS
TRIM
8
V+
7
OUT
6
NC
5
NC = NO CO NNE CT
OP77
TOP VIEW
(No t to Scale)
00320-001
Figure 1. 8-Pin Hermetic
DIP_Q-8 (Z Suffix)
V
OS
TRIM
V
OS
TRIM V+
4V– (CAS E)
+IN NC
NC = NO CONNECT
–IN OUT
00320-002
OP77
TOP VIEW
(Not to Scal e)
7
3
1
5
62
8
4
Figure 2. TO-99
(J Suffix)
GENERAL DESCRIPTION
The OP77 significantly advances the state-of-the-art in
precision op amps. The outstanding gain of 10,000,000 or more
for the OP77 is maintained over the full 10 V output range. This
exceptional gain-linearity eliminates incorrectable system
nonlinearities common in previous monolithic op amps and
provides superior performance in high closed-loop gain
applications. Low initial VOS drift and rapid stabilization time,
combined with only 50 mW of power consumption, are
significant improvements over previous designs. These
characteristics, plus the exceptional TCVOS of 0.3 μV/°C
maximum and the low VOS of 25 μV maximum, eliminates the
need for VOS adjustment and increases system accuracy over
temperature.
A PSRR of 3 μV/V (110 dB) and CMRR of 1.0 μV/V maximum
virtually eliminate errors caused by power supply drifts and
common-mode signals. This combination of outstanding
characteristics makes the OP77 ideally suited for high resolution
instrumentation and other tight error budget systems.
OP77
Rev. E | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Connections ............................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Electrical Specifications ............................................................... 3
Wafer Test Limits .......................................................................... 4
Typical Electrical Characteristics ............................................... 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance .......................................................................6
ESD Caution...................................................................................6
Typical Performance Characteristics ..............................................7
Test Circuits ..................................................................................... 10
Applications ..................................................................................... 11
Precision Current Sinks ............................................................. 12
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 16
REVISION HISTORY
4/10—Rev. D to Rev. E
Removed Figure 33 and Two Subsequent Paragraphs ............... 12
6/09—Rev. C to Rev. D
Changes to Figure 1 and Figure 2 ................................................... 1
Changes to Table 1 ............................................................................ 3
Removed Endnote 1 and Endnote 2 in Table 3 ............................ 4
Changes to Figure 16 ........................................................................ 9
Changes to Figure 31 and Figure 32 ............................................. 12
Changes to Figure 38 ...................................................................... 14
Moved Figure 39 ............................................................................. 14
10/02—Rev. B to Rev. C
Edits to Specifications ...................................................................... 2
Figure 2 Caption Changed ............................................................ 10
Figure 3 Caption Changed ............................................................ 10
Edits to Figure 10 ............................................................................ 11
Updated Outline Dimensions ....................................................... 15
2/02—Rev. A to Rev. B
Remove 8-Lead SO PIN Connection Diagrams ........................... 1
Changes to Absolute Maximum Rating ......................................... 2
Remove OP77B column from Specifications ................................ 2
Remove OP77B column from Electrical Characteristics ........ 3, 5
Remove OP77G column from Wafer Test Limits ......................... 6
Remove OP77G column from Typical Electrical Characteristics6
OP77
Rev. E | Page 3 of 16
ELECTRICAL SPECIFICATIONS
@ VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 1.
OP77E OP77F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
INPUT OFFSET VOLTAGE VOS 10 25 20 60 μV
LONG-TERM STABILITY1 V
OS/time 0.3 0.4 μV/Mo
INPUT OFFSET CURRENT IOS 0.3 1.5 0.3 2.8 nA
INPUT BIAS CURRENT IB −0.2 +1.2 +2.0 −0.2 +1.2 +2.8 nA
INPUT NOISE VOLTAGE2 e
np-p 0.1 Hz to 10 Hz 0.35 0.6 0.38 0.65 μVp-p
INPUT NOISE VOLTAGE DENSITY en fO = 10 Hz 10.3 18.0 10.5 20.0 nV/√Hz
f
O = 100 Hz2 10.0 13.0 10.2 13.5
f
O = 1000 Hz 9.6 11.0 9.8 11.5
INPUT NOISE CURRENT2 inp-p 0.1 Hz to 10 Hz 14 30 15 35 pAp-p
INPUT NOISE CURRENT DENSITY in fO = 10 Hz 0.32 0.80 0.35 0.90 pA√Hz
f
O = 100 Hz2 0.14 0.23 0.15 0.27
f
O = 1000 Hz 0.12 0.17 0.13 0.18
INPUT RESISTANCE
Differential Mode3 R
IN 26 45 18.5 45 MΩ
Common Mode RINCM 200 200 GΩ
INPUT VOLTAGE RANGE IVR ±13 ±14 ±13 ±14 V
COMMON-MODE REJECTION RATIO CMRR VCM = ±13 V 0.1 1.0 0.1 1.6 μV/V
POWER SUPPLY REJECTION RATIO PSRR VS = ±3 V to ±18 V 0.7 3.0 0.7 3.0 μV/V
LARGE-SIGNAL VOLTAGE GAIN AVO RL ≥ 2 kΩ 5000 12,000 2000 6000 V/mV
V
O = ±10 V
OUTPUT VOLTAGE SWING VO RL ≥ 10 kΩ ±13.5 ±14.0 ±13.5 ±14.0 V
R
L ≥ 2 kΩ ±12.5 ±13.0 ±12.5 ±13.0
R
L ≥ 1 kΩ ±12.0 ±12.5 ±12.0 ±12.5
SLEW RATE2 SR RL ≥ 2 kΩ 0.1 0.3 0.1 0.3 V/μs
CLOSED-LOOP BANDWIDTH2 BW AVCL + 1 0.4 0.6 0.4 0.6 MHz
OPEN-LOOP OUTPUT RESISTANCE RO 60 60 Ω
POWER CONSUMPTION Pd VS = ±15 V, no load 50 60 50 60 mW
V
S = ±3 V, no load 3.5 4.5 3.5 4.5
OFFSET ADJUSTMENT RANGE Rp = 20 kn ±3 ±3 mV
1 Long-term input offset voltage stability refers to the averaged trend line of VOS vs. time over extended periods after the first 30 days of operation. Excluding the initial
hour of operation, changes in VOS during the first 30 operating days are typically 2.5 μV.
2 Sample tested.
3 Guaranteed by design.
OP77
Rev. E | Page 4 of 16
@ VS = ±15 V, −25°C ≤ TA ≤ +85°C for OP77FJ and OP77E/OP77F, unless otherwise noted.
Table 2.
OP77E OP77F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
INPUT OFFSET VOLTAGE VOS 10 45 20 100 μV
AVERAGE INPUT OFFSET VOLTAGE DRIFT1 TCVOS 0.1 0.3 0.2 0.6 μV/°C
INPUT OFFSET CURRENT IOS 0.5 2.2 0.5 4.5 nA
AVERAGE INPUT OFFSET CURRENT DRIFT2 TCIOS 1.5 4.0 1.5 85 pA/°C
INPUT BIAS CURRENT IB −0.2 +2.4 +4.0 −0.2 +2.4 +6.0 nA
AVERAGE INPUT BIAS CURRENT DRIFT2 TCIB 8 40 15 60 pA/°C
INPUT VOLTAGE RANGE IVR ±13.0 ±13.5 ±13.0 ±13.5 V
COMMON-MODE REJECTION RATIO CMRR VCM = ±13 V 0.1 1.0 0.1 3.0 pV/V
POWER SUPPLY REJECTION RATIO PSRR VS = ±3 V to ±18 V 1.0 3.0 1.0 5.0 μV/V
LARGE-SIGNAL VOLTAGE GAIN AVO R
L ≥ 2 kΩ 2000 6000 1000 4000 V/mV
V
O = ±10 V
OUTPUT VOLTAGE SWING VO RL ≥ 2 kΩ ±12 ±13.0 ±12 ±13.0 V
POWER CONSUMPTION Pd VS = ±15 V, no load 60 75 60 75 mW
1 OP77E: TCVOS is 100% tested on J and Z packages.
2 Guaranteed by end-point limits.
WAFER TEST LIMITS
@ VS = ±15 V, TA = 25°C, for OP77NBC devices, unless otherwise noted.
Table 3.
Parameter Symbol Conditions OP77NBC Limit Unit
INPUT OFFSET VOLTAGE VOS 40 μV max
INPUT OFFSET CURRENT IOS 2.0 nA max
INPUT BIAS CURRENT IB ±2 nA max
INPUT RESISTANCE
Differential Mode RIN 26 MΩ min
INPUT VOLTAGE RANGE IVR ±13 V min
COMMON-MODE REJECTION RATIO CMRR VCM = ±13 V 1 μV/V max
POWER SUPPLY REJECTION RATIO PSRR VS = ±3 V to ±18 V 3 μV/V max
OUTPUT VOLTAGE SWING VO RL = 10 kΩ ±13.5 V min
R
L = 2 kΩ ±12.5
R
L = 1 kΩ ±12.0
LARGE-SIGNAL VOLTAGE GAIN AVO RL = 2 kΩ 2000 V/mV min
V
O = ±10 V
DIFFERENTIAL INPUT VOLTAGE ±30 V max
POWER CONSUMPTION Pd VO = 0 V 60 mW max
OP77
Rev. E | Page 5 of 16
TYPICAL ELECTRICAL CHARACTERISTICS
@ VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter Symbol Conditions OP77NBC Limit Unit
AVERAGE INPUT OFFSET VOLTAGE DRIFT TCVOS RS = 50 Ω 0.1 μV/°C
NULLED INPUT OFFSET VOLTAGE DRIFT TCVOSn RS = 50 Ω, RP = 20 kΩ 0.1 μV/°C
AVERAGE INPUT OFFSET CURRENT DRIFT TCIOS 0.5 pA/°C
SLEW RATE SR RL ≥ 2 kΩ 0.3 V/μs
BANDWIDTH BW AVCL + 1 0.6 MHz
OP77
Rev. E | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter1 Rating
Supply Voltage ±22 V
Differential Input Voltage ±30 V
Input Voltage2 ±22 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −25°C to +85°C
Junction Temperature (TJ) −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 6.
Package Type θJA1 θ
JC Unit
8-Pin TO-99 H-08 (J Suffix) 150 18 °C/W
8-Lead Hermetic CERDIP Q-8 (Z Suffix) 148 16 °C/W
1Absolute Maximum Ratings apply to both dice and packaged parts, unless
otherwise noted.
2For supply voltages less than ±22 V, the absolute maximum input voltage is
equal to the supply voltage.
1θJA is specified for worst-case mounting conditions, i.e., θJA is specified for a
device in socket for the TO-99 and CERDIP packages.
ESD CAUTION
OP77
Rev. E | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
2
1
0
–1
–2
–10 –5 0 5 10
OUTPUT VOLTAGE (V)
INPUT VOLT AG E ( µ V)
(NULLED TO 0µV @ V
OUT
= 0V)
00320-004
V
S
= ±15V
T
A
= 25°C
R
L
= 10kΩ
Figure 3. Gain Linearity (Input Voltage vs. Output Voltage)
25
20
15
10
5
0
–55 –35 –15 5 25 45 65 85 105 125
TEM P ERATURE (°C)
OPEN-LOOP GAIN (V/µV)
00320-005
V
S
= ±15V
Figure 4. Open-Loop Gain vs. Temperature
16
12
8
4
00 ±5 ±10 ±15 ±20
POW ER SUPP L Y VOLTAGE ( V)
OPEN-LOOP GAIN (V/µV)
00320-006
T
A
= 25°C
R
L
= 2kΩ
Figure 5. Open-Loop Gain vs. Power Supply Voltage
30
20
10
0
–10
–20
–30
–55 –35 –15 5 25 45 65 85 105 125
TEM P ERATURE (°C)
CHANGE I N OF FSET VO LT AGE (µ V )
00320-007
J, Z PACKAGES
+0.3µV/°C
MEAN
S.D.
–0.3µV/°C
Figure 6. Untrimmed Offset Voltage vs. Temperature
4
3
2
1
0
–1
–2
–3
–40 0.5 1.0 1.5 2.0 2.5 3.0 3.5
TIME AFT ER P OW E R S UP P LY T URN- ON (Min utes)
CHANGE IN INP UT OF FSET VO LT AGE (µV)
00320-008
V
S
= ±15V
T
A
= 25°C
Figure 7. Warm-Up Drift
30
25
20
15
10
5
0
–10 0 10203040506070
TIME ( Seco nd s)
ABSOLUTE CHANG E IN INP UT
OFFSET VOLTAGE (µV)
00320-009
V
S
= ±15V
DEVICE I M MERSED I N
70°C OIL BATH (20 UNITS)
MAXIMUM
MIMIMUM
AVERAGE
Figure 8. Offset Voltage Change Due to Thermal Shock
OP77
Rev. E | Page 8 of 16
100
80
60
40
20
0
–2010 100 1k 10k 100k 1M 10M
FREQUENCY ( Hz )
CLOSED-LOOP GAIN (dB)
00320-010
V
S
= ±15V
T
A
= 25°C
Figure 9. Closed-Loop Response for Various Gain Configurations
160
140
120
100
80
60
40
20
0
0
45
90
135
180
0.01 0.1 1 10 100 1k 10k 100k 1M
FREQUENCY ( Hz )
OPEN-LOOP GAIN (dB)
PHASE (Degrees)
00320-011
V
S
= ±15V
T
A
= 25°C
Figure 10. Open-Loop Gain/Phase Response
150
140
130
120
110
100
90
801 10 100 1k 10k 100k
FREQUENCY (Hz)
CMMR (d B)
00320-012
TA = 25° C
Figure 11. CMRR vs. Frequency
130
120
110
100
90
80
70
60
0.1 1 10 100 1k 10k
FREQUENCY ( Hz )
PSRR (dB)
00320-013
T
A
= 25°C
Figure 12. PSRR vs. Frequency
4
3
2
1
0
–75 –50 –25 0 25 50 75 100 125
TEMPERAT URE (°C)
INPUT BIAS CURRE NT ( nA)
00320-014
V
S
= ±15V
Figure 13. Input Bias Current vs. Temperature
2.0
1.5
1.0
0.5
0
–75 –50 –25 0 25 50 75 100 125
TE M P ERATURE (°C)
INPUT O F F S ET CURRENT (nA)
00320-015
V
S
= ±15V
Figure 14. Input Offset Current vs. Temperature
OP77
Rev. E | Page 9 of 16
10
1
0.1
100 1k 10k 100k
FREQUENCY ( Hz )
RMS NOISE (mV)
00320-016
V
S
= ±15V
T
A
= 25°C
Figure 15. Input Wideband Noise vs. Bandwidth (0.1 Hz to Frequency
Indicated)
1k
100
10
11 10 100 1k
FREQUENCY ( Hz )
INPUT NOISE VOLTAGE (nV/ Hz)
00320-017
VS = ±15V
TA = 25°C
RESISTORS
INCLUDED
EXCLUDED
RS = 0
RS1 = RS 2 = 20 0kΩ
THERM A L NOISE O F SO URCE
Figure 16. Total Input Noise Voltage vs. Frequency
32
28
24
20
16
12
8
4
01k 10k 100k 1M
FREQUENCY (Hz)
PEAK-TO- P E AK AMP LI TUDE (V)
00320-018
V
S
= ±15V
T
A
= 25°C
Figure 17. Maximum Output Swing vs. Frequency
100
10
1010203040
TOTAL SUPPLY VOLTAGE V+ TO V– (V)
POW ER CONS U M PT ION ( mW)
00320-019
T
A
= 25°C
Figure 18. Power Consumption vs. Power Supply
20
15
10
5
0
100 1k 10k
LOAD RESI STANCE TO GROUND ( Ω)
MAXIMUM OUTPUT (V )
00320-020
VS = ±15V
TA = 25°C
VIN = ±10mV
POSITIVE SWI NG
NEGATI VE SWI NG
Figure 19. Maximum Output Voltage vs. Load Resistance
40
35
30
25
20
150123
TIME FROM OUTPUT BEING SHORTENED (Minutes)
OUT P UT SHO RT-CI RCUIT CURRE NT ( mA)
00320-021
4
V
S
= ±15V
T
A
= 25°C
Figure 20. Output Short-Circuit Current vs. Time
OP77
Rev. E | Page 10 of 16
TEST CIRCUITS
OP77
200k
Ω
V
O
50Ω
V
OS
= V
O
4000
00320-022
Figure 21. Typical Offset Voltage Test Circuit
INPUT REFERRED NOISE = V
O
25,000
00320-023
OP77
2.5M
Ω
V+
V–
OUTPUT
100Ω
100Ω
3.3kΩ
4.7µF
(≈10Hz FILTER)
76
4
2
3
Figure 22. Typical Low-Frequency Noise Test Circuit
00320-024
OP77
V+
OUTPUT
V–
20kΩ
INPUT
+
–1876
4
2
3
Figure 23. Optional Offset Nulling Circuit
00320-025
OP77
100kΩ
+18V
–18V
76
4
2
3
+10µF
+10µF
0.1µF
0.1µF
*
*
10Ω
10Ω
10kΩ10kΩ
NOTES
*
1 PER BO ARD
Figure 24. Burn-In Circuit
1MΩ
R
L
V
X
10Ω
10kΩ100kΩ
V
IN
= ±10V
TYPIC
A
LPRECISION
OP AMP
V
Y
V
X
–10V 0V +10V
NOTES
1. GAIN NOT CONSI STANT. CAUS ES NONL INEAR ERRO RS .
2
.A
VO
SPEC IS ONLY PART OF THE SOLUTION.
3
. CHECK S PE CIFI
C
ATI ON TABLE 1 AND TABLE 2 FOR PERFORM ANCE.
00320-026
A
VO
650V/mV
R
L
= 2kΩ
Figure 25. Open-Loop Gain Linearity
Actual open-loop voltage gain can vary greatly at various output
voltages. All automated testers use endpoint testing and therefore
only show the average gain. This causes errors in high closed-
loop gain circuits. Because this is difficult for manufacturers to
test, users should make their own evaluations. This simple test
circuit makes it easy. An ideal op amp would show a horizontal
scope trace.
VY
VX
–10V 0V +10V
00320-027
Figure 26. Output Gain Linearity Trace
This is the output gain linearity trace for the new OP77. The
output trace is virtually horizontal at all points, assuring
extremely high gain accuracy. The average open-loop gain is
truly impressive—approximately 10,000,000.
OP77
Rev. E | Page 11 of 16
APPLICATIONS
00320-028
OP77E
R2
1MΩ
R4
1MΩ
+15V
–15V
R1
1kΩ
R3
1kΩ
76
4
2
3
0.1µF
0.1µF
Figure 27. Precision High-Gain Differential Amplifier
The high gain, gain linearity, CMRR, and low TCVOS of the
OP77 make it possible to obtain performance not previously
available in single-stage, very high-gain amplifier applications.
For best CMR, 2R
1R must equal 4R
3R . In this example, with a
10 mV differential signal, the maximum errors are as listed in
Table 7.
Table 7. Maximum Errors
Type Amount
Common-Mode Voltage 0.01%/V
Gain Linearity, Worst Case 0.02%
TCVOS 0.003%/°C
TCIOS 0.008%/°C
00320-029
+15V
–15V
R
S
R
F
100Ω
76
4
2
3
0.1µF
0.1µF
10µF
OUTPUT
INPUT
C
LOAD
OP77
Figure 28. Isolating Large Capacitive Loads
This circuit reduces maximum slew rate but allows driving
capacitive loads of any size without instability. Because the boon
resistor is inside the feedback loop, its effect on output
impedance is reduced to insignificance by the high open-loop
gain of the OP77.
00320-030
R1
100kΩ
R3
1kΩ
R4
990Ω
R5
10Ω
6
2
3
V
IN
I
OUT
< 15mA
R2
100kΩ
OP77
Figure 29. Basic Current Source
00320-031
R1
R3
+15V
–15V
R4
R5
62N2222
2N2907
2
3
V
IN
R2
OP77
I
OUT
= V
IN
( )
GI VEN R3 = R4 + R5, R1 = R2
R3
R1 – R5
I
OUT
< 100mA
Figure 30. 100 mA Current Source
These current sources can supply both positive and negative
current into a grounded load.
Note that
1R
3R
2R
4R5R
2R
4R
5R
ZO+
⎟
⎠
⎞
⎜
⎝
⎛+
=
1
And that for ZO to be infinite 2R
4R5R + must = 1R
3R
OP77
Rev. E | Page 12 of 16
PRECISION CURRENT SINKS
0
0320-032
V
+
200Ω
R1
1Ω
1W
R
L
IRF520
I
O
V
IN
OP77
I
O
=
V
IN
> 0V
FULL SCALE OF 1V.
I
O
= 1A/V
V
IN
R1
Figure 31. Positive Current Sink
00320-033
200Ω
R
L
R1
IRF520
I
O
V
IN
V–
OP77 I
O
=
V
IN
> 0V
V
IN
R1
Figure 32. Positive Current Source
The simple high-current sinks, shown Figure 31 and Figure 32,
require the load to float between the power supply and the sink.
In these circuits, the high gain, high CMRR, and low TCVOS of
the OP77 ensure high accuracy.
The high gain and low TCVOS ensure accurate operation with
inputs from microvolts to volts. In Figure 33, the signal always
appears as a common-mode signal to the op amps. The
OP77EZ CMRR of 1 μV/V ensures errors of less than 2 ppm.
00320-035
+15V
–15V
1kΩ1kΩ
R3
2kΩ
C1
30pF D1
1N4148
76
4
2
3
0.1µF
0.1µF
2N4393
VIN
+15V
VOUT
0 < VOUT < 10V
D2
–15V
76
4
2
3
0.1µF
0.1µF
OP77E
OP77E
Figure 33. Precision Absolute Value Amplifier
00320-036
100ΩV
OUT
15
V
0.1µF
OP77
100Ω
100Ω
10µF
6
4
REF-01
V
O
2
6
4
REF-01
V
O
2
6
4
REF-01
V
O
2
+
Figure 34. Low Noise Precision Reference
OP77
Rev. E | Page 13 of 16
Figure 34 relies upon low TCVOS of the OP77 and noise
combined with very high CMRR to provide precision buffering
of the averaged REF-01 voltage outputs.
In Figure 35, CH must be of polystyrene, Teflon*, or
polyethylene to minimize dielectric absorption and leakage.
The droop rate is determined by the size of CH and the bias
current of the AD820.
*Teflon is a registered trademark of the Dupont Company
00320-037
+15V
–15V
1k
Ω
1kΩ1kΩ
1N4148
76
4
2
3
0.1µF
0.1µF
2N930
C
H
V
IN
RESET
+15V
V
OUT
–15V
76
4
2
3
0.1µF
0.1µF
AD820
OP77
Figure 35. Precision Positive Peak Detector
OP77
Rev. E | Page 14 of 16
00320-038
+15V
–15V
RS
1kΩ
R1
2kΩ
CC
RF
100kΩ
D1
1N4148
76
4
2
3
0.1µF
0.1µF
VOUT
V
TH
VIN
OP77
Figure 36. Precision Threshold Detector/Amplifier
When VIN < VTH, amplifier output swings negative, reversing the
biasing diode D1. VO = VTH if RL= ∞ when VIN > VTH, the loop
closes,
()
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛+−+=
S
F
TH
IN
TH
OR
R
VVVV 1
C
00320-039
+15
V
–15V
R
a
R
b1
2
V
IN
GND
V
O
TRIM
TEMP
6
5
3
4R
bp
1.5kΩ
50kΩ
R
c
0.1µF
0.1µF
V
OUT
OP77
REF-02
Figure 37. Precision Temperature Sensor
Table 8. Resistor Values
TCVOUT Slope (S) 10 mV/°C 100 mV/°C 10 mV/°F
Temperature Range −55°C to
+125°C
−55°C to
+125°C
−67°F to
+257°C
Output Voltage
Range
−0.55 V to
+1.25 V
−5.5 V to
+12.5V
−0.67 V to
+2.57V
Zero-Scale 0 V @ 0°C 0 V @ 0°C 0 V @ 0°F
Ra (±1% Resistor) 9.09 kΩ 15 kΩ 7.5 kΩ
Rb1 (±1% Resistor) 1.5 kΩ 1.82 kΩ 1.21 kΩ
Rbp (Potentiometer) 200 Ω 500 Ω 200 Ω
Rc (±1% Resistor) 5.11 kΩ 84.5 kΩ 8.25 kΩ
C is selected to smooth the response of the loop.
00320-003
7
18
3
2
4
OUTPUT
6
R9
R5
C3
C1
C2
R7
R8R6
Q19
Q18
Q20
Q16
Q17
Q11 Q12
Q10Q9
Q13
Q27
Q4Q3 Q8
Q5
R3
R2A
1
R1A
R2B
1
R1B
R4
Q1
Q23
Q7
Q24
Q21
Q22
Q6
Q2
Q26
Q25
Q14
Q15
R10
V+
V–
NONINVERTING
INPUT
INVERTING
INPUT
1
R2A AND R2B ARE E LECT RONICALLY ADJUSTE D ON CHIP AT FACTORY.
(OPTIONAL
NULL)
Figure 38. Simplified Schematic
OP77
Rev. E | Page 15 of 16
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.310 (7.87)
0.220 (5.59)
0.005 (0.13)
MIN 0.055 (1.40)
MAX
0.100 (2.54) BSC
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.405 (10.29) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36) 0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
14
58
Figure 39. 8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
CONT ROLLING DI M E NSIONS ARE IN INCHE S ; M IL L IME TER DI M E NS IONS
(IN PARENTHESES) ARE ROUNDED-O FF INCH EQUIVALENT S FOR
REFE RE NCE ONLY AND ARE NO T AP P ROPRIAT E FO R US E IN DES IGN.
COMP LIANT TO JE DEC STANDARDS MO -002-AK
0.2500 (6.35) MIN
0.5000 ( 1 2.70)
MIN
0.1850 (4.70)
0.1650 (4.19)
REFE RE NCE P LANE
0.0500 (1.27) MAX
0.0190 ( 0.48)
0.0160 ( 0.41)
0.0210 ( 0. 53 )
0.0160 ( 0. 41 )
0.0400 ( 1. 02 )
0.0100 ( 0. 25 )
0.0400 ( 1.02) M A X 0.0340 ( 0.86)
0.0280 ( 0.71)
0.0450 ( 1.14)
0.0270 ( 0.69)
0.1600 ( 4.06)
0.1400 ( 3.56)
0.1000 (2.54)
BSC
6
28
7
5
4
3
1
0.2000
(5.08)
BSC
0.1000
(2.54)
BSC
0.3700 ( 9.40)
0.3350 ( 8.51)
0.3350 (8.51)
0.3050 (7.75)
45° BSC
BASE & SEATING PLANE
022306-A
Figure 40. 8-Pin Metal Header [TO-99]
(H-08)
Dimensions shown in inches and (millimeters)
OP77
Rev. E | Page 16 of 16
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
OP77FJ −25°C to +85°C 8-Pin Metal Header [TO-99] H-08 (J Suffix)
OP77FJZ −25°C to +85°C 8-Pin Metal Header [TO-99] H-08 (J Suffix)
OP77EZ −25°C to +85°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8 (Z Suffix)
OP77FZ −25°C to +85°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8 (Z Suffix)
OP77NBC Die
1 Z = RoHS Compliant Part.
©2002–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00320-0-4/10(E)
