UC3842A - Unitrode Semiconductor - Datasheet.Directory

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•Optimized for Off -line and DC to DC

Converters

•Low Start Up Current (<0.5mA)

•Trimm ed Oscillator Discharge Current

•Automatic Feed Forward Compensation

•Pulse-by-Pulse Current Limiting

•Enhanced Load Response Characteristics

•Under-Voltage Lockout With Hysteresis

•Double Pulse Suppression

•High Current Totem Pole Out put

•Internally T rimmed Bandgap Reference

•500kHz Operation

•Low RO Error Amp

Current Mode PWM Controller

The UC1842 A/3A/4A/5A famil y of control ICs is a pin for pin compat-

ibl e improved version o f th e UC 3842/3 /4/5 family. Providing the nec-

essary features to control current mode switched mode power

supplies, this family has the following improved features. Start up cur-

rent is guaranteed to be less than 0.5mA. Oscillator discharge is

trimmed to 8.3mA. During under voltage lockout, the output stage can

sink at least 10mA at less than 1.2V for V CC over 5 V.

Th e difference between members of th is family are shown in the table

below.

UC1842A/3A/4A/5A

UC2842A/3A/4A/5A

UC3842A/3A/4A/5A

BLOCK DIAGRAM

FEATURES DESCRIPTION

Part # UVLO O n UVLO O ff Maximum Duty

Cycle

UC1842A 16.0V 10.0V <100%

UC1843A 8.5V 7.9V <100%

UC1844A 16.0V 10.0V <50%

UC1845A 8.5V 7.9V <50%

No te 1: A = DI L-8 P in Num ber. B = SO- 14 Pin Num be r .

No te 2: Toggle f lip flop use d only in 1844A and 1845A.

A/ B

PACKAGE PIN FUNCTION

FUNCTION PIN

N/C 1

Comp 2

N/C 3-4

VFB 5

N/C 6

ISENSE 7

N/C 8-9

RT/CT10

N/C 11

Pwr Gnd 12

Gnd 13

N/C 14

Output 15

N/C 16

VC17

VCC 18

N/C 19

VREF 20

DIL- 8, SO IC-8 (TOP VIEW )

J or N, D8 Package

CONNECTI ON DIAGRAMS

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for -55°C ≤ TA ≤ 125°C f or t h e

UC184xA; -40°C ≤ TA ≤ 85°C for the UC284xA; 0 ≤ TA ≤ 70 °C for the UC384xA; VCC = 15V (Note 5); R T = 10k; CT = 3.3nF; TA = T J; Pin

numbers refer to DIL-8.

PARAMETER TEST CONDI TION S UC184xA\UC284xA UC384xA UNITS

MIN. TYP. MAX. MIN. TYP. MAX.

Re ferenc e Sect ion

Output Voltage TJ = 25°C, IO = 1mA 4 .95 5 .00 5 .05 4 .90 5 .00 5 .10 V

Lin e Regulation 12 ≤≤ VIN ≤≤ 25V 6 20 6 20 mV

L oad Reg ulat io n 1 ≤≤ IO ≤≤ 20mA 6 25 6 25 mV

T emp. Stabilit y (Note 2, Note 7) 0.2 0.4 0.2 0.4 mV/°C

Total Output Variation Line, Load, Temp. 4.9 5.1 4.82 5.18 V

Output Noise Voltage 10Hz ≤≤ f ≤≤ 10kHz

TJ = 25°C (Note 2) 50 50 µV

L ong Te rm Sta bi lity TA = 125°C, 1000Hrs. (No te 2) 525 525mV

Output Short Circuit -30 -100 -180 -30 -100 -180 mA

Oscillator Section

Initial Accur acy TJ = 25°C (Note 6) 47 52 57 47 52 57 kHz

Vo ltag e Sta b ility 12 ≤≤ VCC ≤≤ 25V 0.2 1 0.2 1 %

Temp. Stabili ty TMIN ≤≤ TA ≤≤ TMAX (Note 2) 5 5 %

Amplitude VPIN 4 peak to peak (Not e 2) 1. 7 1.7 V

Dischar ge Curren t TJ = 25 °C, V PIN 4 = 2V (Note 8) 7.8 8.3 8.8 7.8 8.3 8.8 mA

VPIN 4 = 2V ( Note 8) 7.5 8. 8 7.6 8. 8 m A

ABSOLUTE MAXIMUM RATINGS (Not e 1)

Note 1. All voltage s are with respe ct to Grou nd, Pin 5. Curren ts

are posit ive int o, negative o u t of the spe cified ter min al. Co n sult

Packaging Sec tion of Datab ook for th e rmal limitations and con-

siderat ions of packages. Pin numb ers ref er to DI L packa ge only.

PLCC-20, LCC-20

(TOP VIEW)

Q, L Package s

UC1842A/3A/4A/5A

UC2842A/3A/4A/5A

UC3842A/3A/4A/5A

Supply Voltage (Lo w Imped ance Source) . . . . . . . . . . . . . . 30V

Supply Voltage (ICC mA). . . . . . . . . . . . . . . . . . . . . Self Lim iting

Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1A

Out put Energy ( Capac itive Lo ad). . . . . . . . . . . . . . . . . . . . . 5µJ

Analog Input s (Pins 2, 3) . . . . . . . . . . . . . . . . . . -0.3V to +6.3V

Error Amp Out pu t Sink Curre nt . . . . . . . . . . . . . . . . . . . . 1 0mA

Power Dissipation at TA ≤ 25°C (DI L- 8) . . . . . . . . . . . . . . . . 1W

Stora ge Tem pe rature Rang e . . . . . . . . . . . . . -65°C to +150 ° C

Lead Tem per at ure (Solde ring, 10 Sec onds ) . . . . . . . . . . 300° C

SOIC-14 (TOP VIEW)

D Package

PARAMETER TEST CONDI TION S UC184xA\UC284xA UC384xA UNITS

MIN. TYP. MAX. MIN. TYP. MAX.

Erro r Am p Sectio n

Input Voltage VPIN 1 = 2. 5 V 2. 4 5 2.5 0 2.5 5 2. 4 2 2. 5 0 2.58 V

Input Bias Current -0.3 -1 -0.3 -2 µA

AVOL 2 ≤ VO ≤ 4V 65 90 65 90 dB

Un ity Gain Bandwidt h TJ = 25°C (Note 2) 0.7 1 0.7 1 MHz

PSRR 12 ≤ VCC ≤ 25V 6070 6070 dB

Output Sink Current VPIN 2 = 2. 7V, VPIN 1 = 1.1V 2 6 2 6 m A

Output Source Current VPIN 2 = 2.3V, VPIN 1 = 5V -0.5 -0.8 -0.5 -0.8 mA

VOUT High VPIN 2 = 2.3V, RL = 15k to gr ound 5 6 5 6 V

VOUT Low VPIN 2 = 2.7V, RL = 15k to Pin 8 0.7 1.1 0.7 1.1 V

Current Sense Section

Ga in (Note 3, Not e 4) 2.8 5 3 3.15 2.8 5 3 3.15 V/V

Max imum Input Signal V PIN 1 = 5V ( No t e 3) 0.9 1 1. 1 0. 9 1 1. 1 V

PSRR 12 ≤ VCC ≤ 25V (Note 3) 70 70 dB

Input Bias Current -2 -10 -2 -10 µA

Delay to O u tput V PIN 3 = 0 to 2V (Note 2) 150 300 150 300 ns

Ou tpu t Secti on

Output Low Level ISINK = 20mA 0.1 0.4 0.1 0.4 V

ISINK = 200m A 1 5 2.2 15 2.2 V

Output High Level ISOURCE = 20 mA 1 3 13. 5 13 13.5 V

ISOURCE = 200mA 1 2 13. 5 12 13. 5 V

Rise Ti me TJ = 25 °C, C L = 1nF (Not e 2) 50 150 50 150 ns

Fall Time TJ = 25 °C, CL = 1nF (Note 2) 5 0 150 50 150 n s

UVLO Saturation VCC = 5V, ISINK = 10 mA 0. 7 1. 2 0. 7 1. 2 V

Un der -Vol t age Lo ckou t Secti on

Start Threshold x842A/4A 15 16 17 14.5 16 17.5 V

x843A/5A 7.8 8.4 9.0 7.8 8.4 9.0 V

Min. Oper at io n Voltage Af te r x842A/4 A 9 1 0 1 1 8.5 10 11.5 V

Turn On x843A/5A 7.0 7.6 8.2 7.0 7.6 8.2 V

PWM Section

Max imum Duty Cycle x842A/3A 94 96 100 94 96 100 %

x844A/5A 47 48 50 47 48 50 %

Minimum Duty Cycle 0 0 %

T ota l Standb y Current

Start-Up Current 0.3 0. 5 0.3 0.5 mA

Operating Supply Current VPIN 2 = V PIN 3 = 0V 11 17 11 17 mA

VCC Zener Voltage ICC = 25mA 30 34 30 34 V

UC1842A/3A/4A/5A

UC2842A/3A/4A/5A

UC3842A/3A/4A/5A

Note 2: These par am et ers, alt hou gh gua ran teed, are not 100%

te st ed in production.

Note 3: Parame te r measu red at trip poin t of latch with V

PIN2

= 0.

Note 4: Gain def ined as : A

= ∆

∆

; 0

≤

PIN 3

≤

0. 8 V.

Note 5 : Adjust V

above the st ar t thresho ld before setting at

15V.

Note 6: O ut put frequ ency equals oscillator frequ ency for the

UC1842A and UC1843 A. Outpu t frequen cy is one half

osc illat or frequency for the UC1 844A and UC1845A.

Not e 7: "Tem pe r at u re sta b i lit y, sometim es re fe rr ed to as a ve r ag e

tem per ature coef f icie nt, is describe d by t he equ atio n:

Temp

Stability

REF

(

max

) −

REF

(

min

)

(

max

) −

(

min

)

REF

(m ax) and V

REF

(min) ar e the m axim um & mini-

mum refere nce voltag e me asur ed ov er t he ap pro priat e

temp era tu re range . Note that the ext r emes in volt age

do not necessa rily occur at th e extremes in tem pera-

ture."

Note 8: This param et er is measure d w ith R

= 10k

Ω

to V

REF

This contributes appr oximately 300

A of current to t h e

measuremen t. The total cur re nt flowing into the R

pin will be approximately 300

A higher than the meas-

ured value.

ELECTRICAL CHARACTERISTICS (cont.) U nless otherwise stated, these specifications apply for -55°C ≤ TA ≤ 125°C fo r

the UC184xA; -40°C ≤ TA ≤ 85 °C for the UC284xA; 0 ≤ TA ≤ 70 °C for the UC384xA; VCC = 15V (Note 5); RT = 10k; CT = 3.3nF; TA = TJ;

Pin numbers re fe r to DIL-8.

Error Amp Con fi g urati on

UC1842A/3A/4A/5A

UC2842A/3A/4A/5A

UC3842A/3A/4A/5A

Under-Vo ltage L ocko u t

During UVLO , the Out put is low.

Current Sense Circuit

A sma ll RC filter may be req uired to suppress switch tra nsient s.

Peak Curre nt (IS) is Dete rm ined By The Form u la

ISMAX ≈ 1.0V

Error Amp can Source and Sink up to 0.5m A, and S ink up to 2mA.

APPLI CATIO NS DATA (cont. )

Open -Lo op Labo rato ry Test Fixt ure

UC1842A/3A/4A/5A

UC2842A/3A/4A/5A

UC3842A/3A/4A/5A

Ou tpu t Satura ti on Cha rac ter i stics Err or Amp lifie r Ope n-L oop Fre quen cy Re spon se

Oscillator Section

Osc illat or Frequ ency vs Timi ng Resis tan ce

Maximum Duty Cycle vs Timing Resistor

High peak cur ren ts associa te d with capacit ive loads necess i-

tat e caref ul grou nding tech niques . Timing and bypas s cap aci-

tors should be connect ed close to pin 5 in a single point

ground . Th e transis to r and 5k potent iom et er are used to s am -

ple the osc illator wavef orm and apply an adjust able ram p to

pin 3.

Off-l ine Fl yb ack Regu lato r

Slope Comp ensation

APPLI CATIO NS DATA (cont. )

UC1842A/3A/4A/5A

UC2842A/3A/4A/5A

UC3842A/3A/4A/5A

Power Supply Speci fications

1. Input Volt age 95VAC to 130 VA

(50 Hz/60Hz)

2. Line I solation 3750V

3. S w itch ing Frequency 40kHz

4. Ef ficiency @ Full Load 70%

5. O ut put V oltage:

A. +5V, ±5%; 1A to 4A load

Ripple voltage : 50mV P-P M ax

B. +12V, ±3%; 0.1A to 0.3A load

Ripple voltage : 100m V P-P Max

C. -12V ,±3%; 0.1A t o 0.3A load

Ripple voltage : 100m V P-P Max

A fraction of the os cillator ramp ca n be resist iv ely

summ ed wit h the cur ren t sense sign al to pr ovide slope

comp e nsat ion for conve rter s requiring d u ty cycles ov er

50%.

Note t hat capacito r, C, form s a filter with R2 to suppress

the leading edge switch sp ikes.

UNITRODE INTEGRATED CIRCUITS

7 CONTINENTAL BLVD. • MERRIMACK, NH 03054

TEL. (603) 424-2410 • FAX (603)4 24-346 0

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