MC6840S - Motorola / Freescale Semiconductor

MOTOROLA

■SEMICONDUCTOR

TECHNICAL DATA

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MC6840

Programmable Timer Module (PTM)

The MC6840 is aprogrammable subsystem component of the M6800 Family designed to provide .!,.

A),,),,

l.~:~:.*L~\,\.,,.l.,.,$..,

variable system time intervals. t,.,~,1..

~*:~\ .

,:::’~”,<$,+

The MC6840 has three 16-bit binary counters, three corresponding control registers, and astatus ){t t,$.~t.+

\“:tt+.:?.,:t:’i’

\.:?,\\,+,

.’\’ :,~>.,,,.~...~.

andlor generate output signals. The MC6840 may be utilized for such tasks as frequency measure- ~:,~:;,~<~r.......+

,.,,. .+

~L.4!:s+”

ments, event counting, interval measuring, and similar tasks. The device may be used for square .<\;:

\*Y>:”*.

~.\\,\.*;L*

wave generation, gated delay signals, single pulses of controlled duration, and pulse width modul~?~’’’*,., ~

“--’. ~.t.:~,,,

tion as well as system interrupts. .$

‘$tt<v

,>~+

Three

@MOTOROLA =

MOTOROLA INC ,1988 DS9802R3

BLOCK DIAGRAM

&IRea,ster I

E(Enable)

AClock

J!{ ‘,~t..

The average chip-juncti~wt~~$eratu re, TJ, in ‘C can be obtained from:

.,>

,$>5, -*, $:

.,d:P:.. 3... ~TJ =TA+ (PD*OJA)

;.,

~.s>>,,

$i<

where: :<:*,

‘.~~..$.’

TA =Arn~~~m\,fem peratu re, ‘C

OJA =+P@k~d’’Thermal Resistance, Junction-to-Ambient, ‘Cm

pD ,~~~~~+ PpORT

PINT ,!kd~~ xVcc, Watts —Chip Internal Power

Pp~T3W$=’*~ort Power Dissipation, Watts —User Determined

.,4 ~

~*;’.?,,*

~~$@~~#appliCatiOnS ppORT<plNTand can be neglected. ppORTmay become significant if the device is configured

.AQ&+$ve Darlington bases or sink LED loads.

~~~~%approximate relationship between PD and TJ (if PpORT is neglected) is:

,, PD= K: (TJ +273°C) (2)

Solving equations (1) and (2) for Kgives:

K=PD ●(TA+2730C) +0JNPD2 (3)

where Kis aconstant pertaining to the particular part. Kcan be determined from equation (3) by measuring PD (at

equilibrium) for aknown TA, Using this value of K, the values of PD and TJ can be obtained by solving equations

(1) and (2) iteratively for any value of TA

—.

(1)

MOTOROLA MC6840

2DS9802R3

MAXIMUM RATINGS

Rating Symbol Value Unit

Supply Voltage Vcc –0.3 to +7.0 v

Input Voltage V,n –0.3 to +7.0 v

Operating Temperature Range –TL to TH

MC~, MC~A40, MC~B40 TA Oto +70

MCWOC, MC6BA40C –40to +85 ‘c

Storage Temperature Range Tstg –55to +150 ‘c

THERMAL CHARACTERISTICS

Characteristic Symbol Value Unit

Thermal Resistance 9JA ‘cm

Cerdip 65

Plastic 100

This devtce contains circuitry to protect the

Inputs agatnst damage due to high static

voltages or electric fields, however, it IS ad-

vised that normal precautions be taken to

avoid application of any voltage higher than

max!mum rated voltages to this htgh-

tmpedance clrcult. For proper operation It IS

recommended that V,n and Vout be con-

strained to the range VSSS(Vln or Vout)

SVCC. Rellabllity of operation ISenhanced~,

unused Inputs are tied to an appropr!atewt$~$.

voltage level (e g., eltner VSS or V@&$ ,“’$.~

~, f?.’:),:,

DC ELECTRICAL CHARACTERISTICS (VCC =5.o Vdc +5%, VSS =0, TA= TL to TH unless otherwise noted) .,ih ~+.,

,’!>$:.,.:?.

‘\*,i

Characteristic Symbol Min IT~,?.. ~~ Max Unit

Input High Voltage VIH VSS+2.O ‘;’%- ‘~ Vcc v

Input Low Voltage vlL v s s –Q,$ >?’~&:’ VSS+O.8 v

Input Leakage Current (Vin =0 to 5.25 V) , .,,. ....

Iin ..5 “**$*l .0 2.5 PA

~.,t.

HI-Z (Off State) Input Current (Vin= 0.5 to 2,4 V) DO-D7 ITS[ ..,:<.>

.!,. $$J

,.,., ..}}:, 20 10 pA

Output High Voltage t$?,:::%:,::~”}:.

(lL~ad= –205KA) DO-D7 vOH,:.,.? V~~+ 2.4 –—v

(l Load= –2~KA) Other Outputs VSS+2.4 ––

f’.$;:~$:,ii :,+

Output Low Voltage is‘i~~.-~,~.s~<

*(5. ‘*?

(l Load= 1.6 mA) m, DO-D7 .2 ‘%Q# -—VSS+O.4 v

(l Load =3.2 mA) 01-05?; :&s~’ ——VSS+0,4

Output Leakage Current (Off State) (VOH =2.4 V) .,i.~ ‘$ILOH –1.0 10 PA

Internal Power Dissipation (Measured at TA= TL) .....

-..:*<>.

+:$?1$$., PINT —470 7W mW

Input Capacitance tf\ “$

(Vln=O, TA=250C, f=l.O MHz) >,,p.,~~.D7 Ci” ——12.5

“?l$~~fl others pF

— — 75

Output Capacitance >.

,:..>.’

(V,n=O. TA=25°C, f=l.O MHz) %.

.? IRQ Cn,,t — — 5.0 pF

Characteristic

Input Rise and Fall Times

(Fiaures 4 and 5) ~. ~, and RESET

AC OPERATING CHARACTERISTICS (See Figure:Q~!%&;}$*

$+...i$

I..i: kAPcaAn MC6BA40 MC6BB40

1Max Min Max Min Max

I.:cr-~ ~~I-1.0” —0.666. —O.w”

Inuut Pulse Width Low (Figure 2) if “’.?:.:

!’+> I

‘~As~nchronous Input) -:’::$; ‘3:q>%WL

~,({, tcyc E+tsu +thd –tcycE+ tsu +thd –tcyc E+tsu +thd –

C, G, and RESET ~, :

IrvvH tcVcE+ tsu +thd –tcycE+ tsu +thd –tcVcE+ tsu +thd –

Input Pulse Width High (Figw&~~’s’p I-,

(Asynchronous Input) ~ii~ ~$Y 1,,1[1

thd 50 —50 —w—

ion Time (Figure 7) tsvnc 250 —2m —175 —

ln~~:pu]se Width pWL, PWH 120 80

C3’( – 8 Prescaler Mode On Iv) ——60 —

Output Delay, 01-03 (Figure 5)

(VOH =2.4 V, Load B) TTL tco —700 —460 —Mo

(V0H=2.4V, Load D) MOS tcm —450 —450 —MO

(VOH=O.7 VDD, Load D) CMOS tcmos —2.0 —1.35 —1,0

Interrupt Release Time (Figure 6) tlR —1.2 —0.9 —07

tr and tfs tcvcE

—

Unit

—

MC6840 MOTOROLA

DS9802R3 3

BUS TIMING CHARACTERISTICS (COO~1-+=. I~--~ Q)

,UUG I“” LGa 1, z, a,, ”d,

IIdent.

Numbr Characteristic MC6840 MC68A40 MC68840

..lin Max Min Max Min Max ‘nit

1Cycle Time tcvc 1.0 10 0.67 10 0.5 10 #s

2Pulse Width, ELow PWEL 430 9W 280 9500 210 9m ns

3Pulse Width, EHigh PWEH 4W 9W 280 9m 220 9m ns

4Clock Rise and Fall Time tr, tf —25 – 25 – 20 ns

Q4..

Address Hold Time tAH 10 – 10 – 10 – ns

;s Setup Time Before EtAS 80 – 60 – 40 – ns

Jp Time Before Etcs 80 – 60 – 40 – Q:.ns

elect Hold Time tCH 10 – 10 – 10 ~

,., ,-

14 Chip Select Setu

15 Chip Sf’ ‘“”

18 Read Data Hold IIme ItDHR1201W01201~. I20 I~Qs$f” ns

21 !Write Data Hold Time tDHW 10 – 10 – I ,~,Q,$J*,p~;@Ins

:ral Output Data Delay Time tDDR – 290 – I180 .~~.~,’”~j $~ ] ns

sral Input Data Setup Time tDSW ~~~ —80

~!, FI$URE2 –INPUT PULSE WIDTH LOW FIGURE3 –INPUT PULSE WIDTH HIGH

..,\:.;?:,‘*T:*.*}

—.

MOTOROLA MC6840

4DS9802R3

FIGURE4 –INPUT SETUP AND HOLD TIMES FIGURE 5 – OUTPUT DELAY

‘esrpO’”’T

I300F

—

NOT E: Timing measurements are referenced to and from alow voltage of 0.8 volts and ahigh voltage of 2.0 volts, unless otherwise noted.

MC6840 MOTOROLA

DS9802R3 5

DEVICE OPERATION

The MCW is part of the Mm microprocessor family

and is fully bus compatible with MWOO systems. The three

timers in the MC~ operate independently and in several

distinct modes to fit awide variety of measurement and syn-

thesis applications.

The MCWO is an integrated, set of three distinct

counter/timers. It consists of thre’e’ 16-bit data latches,

three 16-bit counters (clocked independently), and the

comparison and enable circuitry necessary to implement

various measurement and synthesis functions. In addition, it

contains interrupt drivers to alert the processor that apar-

ticular function has been completed.

In atypical application, atimer will be loaded by first stor-

ing two bytes of data into an associated Counter Latch. This

data is then transferred into the counter via aCounter in-

itialization cycle. If the counter is enabled, the counter

decrements on each subsequent clock period which may be

an external clock, or Enable (E) until one of several predeter-

mined conditions causes it to halt or recycle. The timers are

thus programmable, cyclic in nature, controllable by external

inputs or the MPU program, and accessible by the MPU at

anv time.

BUS INTERFACE

The Programmable Timer Module (PTM) interfaces to the

M6BO0 Bus with an 8-bit bidirectional data bus, two Chip

Select lines, aRead/Write line, aclock (Enable) line, and in-

terrupt Request line, an external Reset line, and three

with an MPU address line into aChip Select of the PTM

when using the MC6800/6802/680B.

“open drain” output (no load device on the chip) which per-

mits other similar interrupt request lines to be tied together in

awire-OR configuration.

Them line is activated if, and onlv if, the Composite in-

terrupt Flag (Bit 7of the Internal Status Register) is asserted.

The conditions under which the ~Q line is activated are

discussed in conjunction with the Status Register.

RESET –Alow level at this input is clocked lnt~ !fi@ PTM

by the E(Enable) input. Two Enable pulses a~~.r~~~~d to

synchronize and process the signal. Th~ ~$~ then

recognizes the active “low” or inactive ~~l~t~~~&ti the third

Enable pulse. If the RESET signal is a~yw~~bus, an addi-

tional Enable period is required if SQ$U9 ttw$s are not met.

The RESET input must be stable ,&@$~P~$$~for the minimum

time stated in the AC Operating’;:$~,a]ecteristics.

Recognition of alow level ~~~hlsh!~put by the PTM causes

the following action to o~c~s$~~

a. All counter latch@’ ~r~;$reset to their maximum COUnt

.JtQ,ff>

values. .,.,.&...,>,,?

,’i>:,,~:-....”.,$.,

b. All Control %${~~bits are cleared with the exception

of CRIOJi~~ter~l reset bit) which is set.

c. All cofi’~$~<=.are preset to the contents of the latches.

~:,$..,:~.~;j,,,.s.,<.,,>

d. All@ou~$er outputs are reset and all counter clocks are

.~;~$w.

.’:!..:?~

e. ~$~ Status Register bits (interrupt flags) are cleared.

,>..:‘

:~”~:,~:.

+’r~it,?RwlSTER SELECT LINES (RSO, RSl~RS2) –These in-

:,.,,

,!.i%:~~ts are used in conjunction with the R/W line to select the

““* “Internal registers, counters and latches as shown in Table 1.

~t!~i.>.${\+i

~*~:\,, ,

.,,.

~t?

BIDIRECTIONAL DATA (DGD7) –The bidirectional .data N

lines (DO-D7) allow the transfer of data between t~@skU

and PTM. The data bus output drivers are t~~$,~$ta$e

devices which remain in the high-impedance (Q@),%t$~~ ex-

cept when the MPU performs aPTM ~$~~~’~eration

(Read/Write and Enable lines high and PT~~$~~~~;Welects ac-

tivated). :*.. i:;?:+

?,$ ?~ .

.,,.,

CHIP SELECT (CSO, CS1 )–T@?e~?W7signals are used

to activate the Data Bus interfa~{%k~llow transfer of data

from the PTM. With C~O =@~an$ CSI =1, the device is

selected and data transfer,,$~’R~,~% fir.

‘yi !$

READ/WRITE (R/~$+– “$%is signal is generated by the

MPU to control thaj-~%i~~ion of data transfer on the Data

Bus. With the Pl~~$&lected, alow state on the PTM R/~

line enables the{~~t buffers and data is transferred from the

MPU to the ~~~%nthe trailing edge of the E(Enable) clock.

Alternat~~T ,J:&fider the same conditions) R/~= 1 and

Enabl@~$~#!lows data in the PTM to be read by the MPU.

>.:.+

.,, ~

*,,,.::>.i,,,.>.<,r

!~%~LE (E CLOCK) –The Eclock signal synchronizes

da’~’;ansfer between the MPU and the PTM. It also per-

forms an equivalent synchronization function on the external

clock, reset, and gate inputs of the PTM.

INTERRUPT REQUEST (~Q) –The active low Interrupt

Request signal is normallv tied directly (or through priority in-

terrupt circuitry) to the ~input of the MPU. This is an

NOTE

The PTM is accessed via MPU Load and Store operations

in much the same manner as a memory device. The instruc-

tions available with the M6800 family of MPUS which per-

form read-modify-write operations on memory should not be

used when the PTM is accessed. These instructions actually

fetch abyte from memory, perform an operation, then

restore it to the same address location. Since the PTM uses

the R/~ line as an additional register select input, the

modified data will not be restored to the same register if

these instructions are used.

CONTROL REGISTER

Each timer in the MC6B40 has acorresponding write-only

Control Register. Control Register #2 has aunique address

space (RSO= 1, RS=O, RS2=O) and therefore may be writ-

ten into at any time. The remaining Control Registers (#1 and

#3) share the Address Space selected by alogic zero on all

CR20 –The least significant bit of Control Register #2

(CR20) is used as an additional addressing bit for Control

Registers #1 and #3. Thus, with all Register selects and R/~

inputs at logic zero, Control Register #1 will be written into if

CR20 is alogic one. Under the same conditions, Control

tion has occurred, since all control register bits (except

CR IO) are cleared. Therefore, one may write in the sequence

CR3, CR2, CRI,

MOTOROLA MC6840

6DS9802R3

TABLE 1 – REGISTER SELECTION

select Inputs Operations

RS2 RSI RSO Rl~ =OR/ti =1

000CR20 =OWrite Control Register #3 No Operation

CR20 =1Write Control Register #1

o 0 1Write Control Register #2 Read Status Register

o 1 0Write MSB Buffer Register Read Timer #l Counter

o 1 1 Write Timer #1 Latches Read LSB Buffer Register .\,

100‘*,\,

Write MSB Buffer Register Read Timer #2 Counter .,k.1+~,,,..,~,,,

101Write Timer #2 Latches Read LSB Buffer Register ,:), “%?

~::

1 1

.*:,J!:,: ‘~”

oWrite MSB Buffer Register Read Timer #3 Counter ‘I}*, \~,}>

‘$$.~.$,~..~,,8,

111Write Timer #3 Latches ,*f~,! t$:,:+

Read LSB Buffer Register **} ~i, ,,,

‘~,,>i!:.~~.*::

.<&@ ,,:$,,:$‘

\.* ,),$ ,.

~:<,:..... ,..

CR1O –The least significant bit of Control Register #1 is

used as an Internal Reset bit. When this bit is alogic zero, all

timers are allowed to operate in the modes prescribed by the

remaining bits of the control registers. Writing a“one” into

CRIO causes all counters to be preset with the contents of

the corresponding counter latches, all counter clocks to be

disabled, and the timer outputs and interrupt flags (Status

are undisturbed by an Internal Reset and mav be written into

regardless of the state of CR IO.

The least significant bit of Control Register #3 is used as a

selector for a-8 prescaler which is available with Timer #3

onlv. The prescaler, if selected, ISeffectively placed between

-’,li+ %$’

the clock input circuitrv and the i@%’~:$p*@ounter #3. It can

therefore be used with either the.int~,~clock (Enable) or an

s,::;:?

When initializing T~@3 $tito the divide-by-eight mode on

consecutive E-cycles “%~:@~with DMA), Control Register 3

must be initiali~~~~efore Timer Latch #3 to insure proper

timer initiali~A%~,J ‘f”’

.,<,:...

~b!:%

TABLE 2 – CONTROL q#G~$?ER BITS

rrupt Control (See Table 3) I

!.,

Timer #X Counting Mode Control

TX configured for normal (16-bit) counting mode

TX configured for dual 8-bit counting mode

CRX1 Timer #X Clock Source

oTX uses external clock source on ~input

~+:$ 1TX uses Enable clock

CR1O Internal Reset 8it CR20 Control Register Address Blt CR30 Timer #3 Clock Control

OAll ttmers allowed to operate OCR#3 mav be written OT3 Clock is not prescaled

1All timers held mpreset state 1CR#l mav be written 1T3 Clock is prescaled bv –B

X=l x=2 x=3

MC6840 MOTOROLA

DS9802R3 7

Control Register Bits CR1O, CR20, and CR30 are unique in

that each selects adifferent function. The remaining bits (1

through 7) of each Control Register select common func-

tions, with aparticular Control Register affecting only its cor-

responding timer.

CRX1 –Bit 1of Control Register #1 (CR11 )selects

whether an internal or external clock source is to be used

with Timer #l. Similarly, CR21 selects the clock source for

Timer #2, and CR31 performs this function for Timer #3. The

function of each bit of Control Register “X” can therefore be

defined as shown in the remaining section of Table 2.

CRX2 –Control Register Bit 2selects whether the binary

information contained in the Counter Latches (and subse-

quently loaded into the counter) is to be treated as asingle

16-bit word or two 8-bit bytes. In the single 16-bit Counter

Mode (CRX2= O) the counter will decrement to zero after

N+1enabled [G= O) clock periods, where Nis defined as the

16-bit number in the Counter Latches. With CRX2= 1, a

similar Time Out will occur after (L+ I)*(M +1) enabled

clock periods, where L and M, respectively, refer to the LSB

and MSB bytes in the Counter Latches.

CRX3-CRX7 –Control Register 8its 3, 4, and 5 are ex-

plained in detail in the Timer Operating Mode section. Bit 6is

an interrupt mask bit which will be explained more fully in

conjunction with the Status Register, and bit 7is used to

enable the corresponding Timer Output. Asummary of the

control register programming modes is shown in Table 3.

STATUS REGISTER/lNTERRUPT FLAGS

The MC~ has an internal Read-Only Status Register

which contains four Interrupt Flags, (The remaining four Qts

of the register are not used, and defaults to zeros whe~~~;

ing read.; Bits O, 1, and 2 are assigned to Timers 1, 20,3NQ @

respectively, as individual flag bits, while Bit 7is a,<$o<~~~$~te

Interrupt Flag. This flag bit will be asserted if{~~~$~’~<$~e in-

dividual flag bits is set while Bit 6of the cor~~sw~$~$fig Con-

trol Register is at alogic one, The condil~~~;~~r asserting

the composite Interrupt Flag bit can thwqfd~ be expressed

‘!!?;?,.Jr,...

as: ,Y,\,r

,,,. .x

),:

INT= IIo CR16+ 12. CR26&f~;$@%

*jt

where INT =Composl@~j~~$~&&pt Flag (Bit 7)

11= Timer #~Qln~~rrupt Flag (Bit O)

12= Tirq@,#2 ‘~kerrupt Flag (Bit 1)

13= ~~&~~2 Interrupt Flag (Bit 2)

*), “v+y!~

An interrupt flag is cleared by aTimer Reset con@tion,

i.e., External RESET=O or Internal Reset Bit (CR1O)= 1. It

will also be cleared by aRead Timer Counter Command pro-

vided that the Status Register has previously been read while

the interrupt flag was set. This condition on the Read Status –

to prevent missing interrupts which might occur after the

status register is read, but prior to reading the Timer

Counter.

An Individual Interrupt Flag is also cleared by aWrite

Timer Latches (W) command or aCounter Initializqtf@ie (Cl)

sequence, provided that Wor Cl affects the,,,l~’~&~cor-

responding to the individual Interrupt Flag, ~,~y$..~+

$! ,<.:

y>.<W,:+$*11:

COUNTER LATCH iNITIALl~TION ,<+i.\.*““.’]:i,..

,,.+,.\ .,.

~“t?<:?f{,,~.~~,~

Each of the three Independent tim~$~~~~~sts of a16-bit

addressable counter and a 16-bi$e~~~@sable latch. The

counters are preset to the binary n~b~rs stored in the latch-

es. Counter initialization res~+l~~kin Ne transfer of the latch

contents to the counter. ~~}~Q@s in Table 4regarding the

binary number N, L, or$@~~*d into the Latches and their

relationship to the ~,~~~,~,.waveforms and counter Time-

outs. .,.~:2,

>.b‘.3*

:..~:..<~.$,,,,\\,,,

Since the PT~,,da;~:$us is 8-bits wide and the counters are

16-bits wide, ~~~borary register (MSB Buffer Register) is

provided. iFmi$~~write only” register is for the Most-

Signific(~tt.Q~]~ of the desired latch data. Three addresses

are pr&~J~~~or the MSB Buffer Register (as indicated in

Ta&e 1), %ut they all lead to the same Buffer. Data from the

Wy&$JBuffer will automatically be transferred into the Most-

f$?$niflcant Byte of Timer #X when aWrite Timer #X Latches

‘~$.,~$~kmand is performed. So it can be seen that the MC6840

f$~~~;has been designed to allow transfer of two bytes of data into

“3 the counter latches provided that the MS Bis transferred ,-

>.!& first. The storage order must be observed to ensure proper

latch oDeration.

In many applications, the source of the data will be an

M6800 Family MPU. It should be noted that the 16-bit store

operations of the M68~ family microprocessors (STS and

STX) transfer data in the order required by the PTM. AStore

Index Register Instruction, for example, results in the MSB

of the Xregister being transferred to the selected address,

then the LSB of the Xregister being written into the next

higher location. Thus, either the index register or stack

pointer may be transferred directly into aselected counter

latch with asingle instruction,

Alogic zero at the RESET input also initializes the counter

latches. In this case, all latches will assume amaximum

count of 65,53510. It is important to note that an Internal

f:.... “* ‘

,.:. ‘~l.l.,t(;f:j)

,..:..l,

hi:.,\,,..--\\

...

~~“’~$P;Rx4 ~Rx5

~cRp7 TABLE 3 – PTM OPERATING MODE SELECTION

.:~,.\?y>.,,.’~

,.t’..~,:,:t.t

.:$ !~o0 0 Continuous Operating Mode: Gate 1or Write to Latches or Reset Causes Counter Initialization

.,.:)\:>I’~~\~.*.’’.*.

...*.,

,!!s.... ,,, 10 0 Frequency Comparison Mode: Interrupt If Gate ~is< Counter Time Out

“i....~!’,..,?.,“b.

,,,..,.L*.~..,, o1 0 Continuous Operating Mode: Gate 1or Reset Causes Counter Initialization

“!J:::

-:..- 110Pulse Width Comparison Mode: Interrupt if Gate ~#Is< Counter Time Out

o0 1 Single Shot Mode: Gate Jor Write to Latches or Reset Causes Counter Initialization

10 1 Frequency Comparison Mode: Interrupt If Gate ~Is> Counter T!me Out

o1 1 Single Shot Mode: Gate Ior Reset Causes Counter Initialization

11 1 Pulse Width Comparison Mode: Interrupt If Gate $~is> Counter Time Out —

MOTOROLA MC6840

8DS9802R3

Reset (Bit zero of Control Register 1Set) has no effect on

the counter latches.

COUNTER INITIALIZATION

YCounter Initialization is defined as the transfer of data from

the latches to the counter with subsequent clearing of the in-

dividual Interrupt Flag associated with the counter. Counter

Initialization always occurs when areset condition

(R ESET=O or CR1O= 1) is recognized. It can also occur –

depending on Timer Mode –with aWrite Timer Latches

command or recognition of anegative transition of the Gate

input.

Counter recycling or re-initialization occurs when a

negative transition of the clock input is recognized after the

counter has reached an all-zero state. In this case, data IS

transferred from the Latches to the Counter.

ASYNCHRONOUS lNPUT/OUTPUT LINES

Each of the three timers within the PTM has external clock

and gate Inputs as well as acounter output line. The inputs

are high-impedance, TTL-compatible lines and ouputs are

capable of driving two standard TTL loads.

—— ——

CLOCK INPUTS (Cl, C2, and~) –Input pins Cl, C2,

and ~will accept asynchronous TTL voltage level signals to

decrement Timers 1, 2, and 3, respectively. The high and low

levels of the external clocks must each be stable for at least

one system clock period plus the sum of the setup and hold

times for the clock inputs, The asynchronous clock rate can

vary from dc to the limit Imposed by the Enable Clock Setup,

and Hold times.

The external clock inputs are clocked In by Enable pulses.

Three Enable periods are used to synchronize and process

-, the external clock. The fourth Enable pulse decrements the

internal counter. This does not affect the input frequency,,,$f

merely creates adelay between aclock input transitioK$&~~<,

internal recognition of that transition by the PT1~~}@l~’&

references to Cinputs in this document relate t,~:lfi$$r~~l

recognition of the input transition, Note that aQ~&$~fi~~~ or

low level which does not meet setup and hol~i~,~~!~~cifica-

tions may require an additional Enable puls~:J,&~?~Wognltion.

When observing recurring events, alack{~~, ~~o~hronization

will result in “jitter” being observed+:f~ Jh&Y’output of the

PTM when using asynchronou:,,%/@$ and gate Input

-..**,

signals. There are two types of ji~er.$ System jitter” is the

result of the Input signals be~&ti~*8i~ synchronization with

Enable, permitting signal:$wlt~~ginal setup and hold time

to be recognized by eith.~~~eblt time nearest the input tran-

sition or the subseque~~’%~~+dme.

“Input jitter” ca~%$~ great as the time between input

signal negative ,gw${ansitions plus the svstem jitter, if the

first transitiq~.<?~$ecbgnized during one system cycle, and

not recogni$~d~’~next cycle, or vice versa. See Figure 9.

,k..i:~+i:l?!:!?,,.+.s,::”

,i~$:.$.,y)i~

,i~,:i:>

.$,*,,,.*,!, FIGURE 9 – INPUT JITTER

.::,.,~,.,”..~\

.%),:.

.,>?$,..t

Enable~ ~

I“p”t ~~

Recog

Input Either. ~

Here +~System

CLOCK INPUT C= (+8PRESCALER MODE) –External

clock Input ~represents aspecial case when Timer #3 is

programmed to utilize its optional -8 prescaler mode.

The divide-by-8 prescaler contains an asynchronous ripple

counter; thus, input setup (tsu) and hold times (thd) do not

apply. As long as minimum input pulse widths are maintain-

ed, the counter will recognize and process all iriput clock

(~) transitions. However, in order to guarantee that aclock

transition is processed during the current Ecycle, acertain

amount of synchronization time (tsYnc) is required bef~en

the ~3 transition and the falling edge of Enable ($$~~~&te

9). If the synchronization time requirement is n~t~~~it is

possible that the ~transition will not be pro,Ge~~&&ntil the

following Ecycle. ~;t‘~’,:.e.\\”s::,

.<*,+?**.t~~

The maximum input frequency and +[~:~ak+~ duty cycles

for the -8 prescaler mode are :w~~@under the AC

Operating Characteristics, lnternall~$.th~ ‘-8 prescaler out-

..*.,\**,

put is treated in the same manng$~s th~previouslv discussed

clock in~uts

accept asvnchronous~j~-~wrnpatlble signals which are used

as triggers or cl~~$lga%~~g functions to Timers 1, 2, and 3,

respectively, Th$~.$Y4mg inputs are clocked into the PTM bv

‘~~.’~.~:t.,

the E(enab~~’’b~b% in the same manner as the previously

discusse,~~,~~~~ffiputs. That IS, aGate transition is recogniz-

ed by,,th5~$~tTM on the fourth Enable pulse (provided setup

anq:$~ld tlrne requirements are met), and the high or low

J,%: ~~.the Gate input must be stable for at least one system

,+~oc~ period plus the sum of setup and hold times. All

$~~~~:~~?$rences to Gtransition in this document relate to Internal

**,. recognition of the Input transition.

The Gate inputs of all timers directly affect the internal

16-bit counter. The operation of ~is therefore Independent

of the -8 prescaler selection,

TIMER OUTPUTS (01, 02, 03) –Timer outputs 01, 02,

and 03 are capable of driving up to two TTL loads and pro-

duce adefined output waveform for either Continuous or

Single-Shot Timer modes. Output waveform definition ISac-

complished bv selecting either Single 16-bit or Dual 8-bit

operating modes. The Single 16-bit mode will produce a

square-wave output in the continuous mode and a single

pulse in the single-shot mode. The Dual 8-bit mode will pro-

duce avariable duty cycle pulse in both the continuous and

single-shot timer modes, One bit of each Control Register

(CRX7) is used to enable the corresponding output. If this bit

is cleared, the output will remain low (VOL) regardless of the

operating mode. If it is cleared while the output IS high the

output will go low during the first enable cycle following a

write to the Control Register.

The Continuous and Single-Shot Timer Modes are the

onlv ones for which output response is defined in this data

sheet. Refer to the Programmable Timer Fundamentals and

Applications manual for adiscussion of the output signals in

other modes. Signals appear at the outputs (unless

CRX7=O) during Frequency and Pulse Width comparison

modes, but the actual waveform is not predictable in typical

applications.

MC6840 MOTOROLA

DS9802R3 9

TIMER OPERATING MODES

The MCWO has been designed to operate effectively in a

wide variety of applications. This is accomplished by using

three bits of each control register (CRX3, CRX4, and CRX5)

to define different operating modes of the Timers. These

modes are divided into WAVE SYNTHESIS and WAVE

MEASUREMENT modes, and are outlined In Table 4.

TABLE 4 – OPERATING MODES

Control Register

CRX3 CRX4 CRX5 Timer Operating Mode

o“oCon?lnuous

o‘1Single-Shot Svntheslzer

10.Frequency Comparison

11“Measurement

Pulse Width ComDarlson

.Defines Add!tlonal Timer Function SelectIon

One cf the WAVE SYNTHESIS modes IS the Continuous

Operating mode, which is useful for cvclic wave generation.

Either symmetrical or variable dutycycle waves can be

generated in this mode. The other wave svnthesis mode, the

Single-Shot mode, is similar In use to the Continuous

operating mode, however, asingle pulse is generated, with a

programmable preset width.

The WAVE MEASUREMENT modes include the Frequen-

cy Comparison and Pulse Width Comparison modes which

are used to measure cyclic and singular pulse widths, respec-

tively.

In addition to the four timer modes in Table 4, the remain-

ing control register bit is used to modify counter initialization

and enabling or interrupt conditions, ,+*<

WAVE SYNTHESIS MODES .)P\::*

,.~~’~.,~

~*\+,,>

CONTINUOUS OPERATING MODE (TABLE 5k/f#$~\he

continuous mode will synthesize acontinuous ,&’~:ye’~itha

period proportional to the preset number im~$~~t~dtticular

timer latches. Any of the timers in the PTM ~$$&’”program-

‘$, k. ‘?’s.

med to operate in acontinuous mode ~~h~,~tr~ zeroes into

bits 3 and 5 of the corresponding co~~~o~k$$ster. Assuming

that the timer output is enabled (CR X7= 1), either asquare

wave or avariable duty cvcle waveform will be generated at

the Timer Output, OX, The type of output is selected via

Control Register Bit 2.

Either aTimer Reset (CR1O= 1or External Reset=O) con- -

dition or internal recognition of anegative transition of the

Gate input results in Counter Initialization. AWrite Timer

latches command can be selected as aCounter Initialization

signal bv clearing CR X4.

The counter IS enabled by an absence of aTimeA~~eset

condition and a logic zero at the Gate Input. 1~,’%s’’pk5-blt

mode, tke counter WIII decrement on the flr~$’~~~~ cycle

during or after the counter Initlallzatlon cvcl~~~~~%nues to

decrement on each clock signal so long as.$~~~@alns low and

no reset condition exists. ACounter Ti.@e,~&&~$the first clock

after all counter bits =O) results in~~~x~~l~dlvldual Interrupt

Flag being set and relnitlallzatlon.~~ f~’’~ounter.

In the Dual 8-bit mode (C RX2A= tk~~fer to the example n

Figure 10 and Tables 5 and 6~$%~$.MSB decrements once for

everv full countdown of t~$~~$~+ 1. When the LSB =O, the

MSB is unchanged; on~~~n$$xt clock pulse the LSB IS reset

to the count in l~~k.~s~ Latches, and the MSB IS

‘<t,~<&<,)*.+:‘

decremented by 1(oR%). *he output, If enabled, remains low

during and af~~j~itiaflzation and WIII remain low until the

counter M,$,Q~?$~~~~>eroes. The output will go high at the

beginning $f t$ ‘fiext clock pulse. The output remains high

until b@$~$~k$&SB and MSB of the counter are all zeroes. At

*..+,,,?!

thei~egmlng of the next clock pulse the defined Time Out

(~@~~wIll occur and the output WIII go low. In the Dual 8-bit

~.~~d$~~he period of the output of the example in Figure 10

,thr,~:~w,~tildspan 20 clock pulses as opposed to IW6 clock pulses

3&$~~~3ing the normal 16-bit mode

@.$<,.

“Aspecial time-out condition exists for the dual 8-bit mode

,~~

,,,,:2 (CR X2= 1) if L=O. In this case, the counter WIII revert to a –

mode similar to the single 16-bit mode, except Time Out oc-

curs after M+1‘ clock pulses. The output, if enabled, goes

low during the Counter Inltlallzatlon cycle and reverses state

at each Time Out. The counter remains cyclical (Is re-

initialized at each Time Out) and the Indlvldual Interrupt Flag

is set when Time Out occurs. If M=L=O, the Internal

counters do not change, but the output toggles at arate of

fi the clock frequency.

MOTOROLA MC6840

10 DS9802R3

—— ——

TABLE 8 – FREQUENCY COMPARISON MODE

Mode Bit 3Bit 4Control Reg. Counter Counter Enable Counter Enable Interrupt Flag

Bit 5Initiahzation Flip-Flop Set (CE) Flip-Flop Reset (CE) sat (1)

Frequencv 100~.j. ~+ TO)+ R~.~.~.r W+R+I al Before TO

Comparison 101~1 .~+ R—— —-

GI. W.R. IW+R+I TO Before ~1

Pulse Width 11 0 RI ●T+ R————

GIW. R. IW+ R+I+G Et Before TO

Comparison 1 1 1 c! .T+F —— ——

GI. W.R. IW+ R+I+G TO Before ~t

PIN ASSIGNMENT

-/ 1

02 3 26 ~

rz 425 DO

a5 24 D1

03 6 23 D2

=7 22 D3

RESET 821 D4

m9 20 D5

RSO 10 19 D6

RS1 11 18 D7

RS2 12 17 E

R/~ 13 16 CS1

vc~ 14 15 CTO

MC6840 MOTOROLA

DS9802R3 13

The three differences between Single-Shot and Continous

Timer Mode can be summarized as attributes of the Single-

Shot mode:

1, Output is enabled for only one pulse until it is reinitializ-

ed.

2. Counter Enable IS independent of Gate

3. L= M=0 or N=0 disables output.

Aside from these differences, the two modes are identical,

WAVE MEASUREMENT MODES

TIME INTERVAL MODES –The Time Interval Modes are

the FrequencV (period) Measurement and Pulse Width Corr-

parison Modes, and are provided for those applications

which require more flexibility of interrupt generation and

Counter Initialization. Individual Interrupt Flags are set In

these modes as afunction of both Counter Time Out and

transitions of the Gate Input. Counter Initialization IS also af-

fected bv Interrupt Flag status.

Atimer’s output is normally not used in aWave Measure-

ment mode, but it IS defined. If the output is enabled, [t will

operate as follows. During the period between relnitialization

of the timer and the first Time Out, the output will be a

logical zero. If the first Time Out is completed (regardless of

Its method of generation), the output will go high. If further

TO’s occur, the output will change state at each completion

of aTime-Out.

The counter does operate in either Single 16-bit or Dual

8-bit modes as programmed bv CRX2. Other features of the

Wave Measurement Modes are outlined in Table 7.

Frequency Comparison Or Petiod Measurement Mode

(CRX3= 1, CRX4=O) –The Frequency Comparison Mode

with CR X5= 1is straightforward. If Time Out occurs prior to

the first negative transition of the Gate input after aCount@r

Initialization cvcle, an Individual Interrupt Flag is set. *Q,

counter IS disabled, and a Counter Initialization cvcle ~a~~o’~’

‘i?.$\\@\,.,...?.,

begin u~il the interrupt flag is cleared and a nega$j$e~dn5~-

tion on Gis detected. ,2,,,,,+,:,,...‘+!.\.

~$l~.y,,+::

~.’l, ..,<.,,,

If CR X5= O, as shown in Tables 7 and 8,,@~{~,;,W~upt IS

generated if Gate input returns low prior tq$’$w’’Out. If a

Counter Time Out occurs first, the coukh~fi$ r~cvcled and

continues to decrement. Abit is set ~~ht$~~ti%e timer on the

initial Time Out which precludes fw.tm~+$dividual interrupt

*3),~.’‘::,,

,,,:

FIGURE 7 –

generation until anew Counter Initialization cycle has been

completed. When this internal bit is set, anegative transition

of the Gate input starts anew Counter Initialization cvcle.

(The condition of ~1 ●

~TO is satisfied, since aT[me Out

has occurred and no individual Interrupt has been

generated. )

AnV of the timers within the PTM may be programmed to

compare the period of apulse (giving the frequencv after

calculations) at the Gate input with the time period re-

quested for Counter Time Out. Anegative transition ~f the

Gate Input enables the counter and starts aCoq{]J~$,J,n-

itlallzatlon cvcle —provided that other condltlon~~+ a’9~m8Ed

in Table 8, are satisfied. The counter decreme$~s~%veach

clock signal recognized during or after Cou<~~##i\~~M’llzation

until an Interrupt is generated, aWrite Tj*”@~hes com-

mand is Issued, or aTimer Reset condl$j~’~o~;flrs. It can be

seen from Table 8that an inte(.[*@~<~@fidltion will be

generated (f CRX5=0 and the pe~~d ,~f ’the pulse (single

pulse or measured separately [d~etid-w’ pulses) at the Gate

input is less than the Count8{~~*,0ut period. If CRX5= 1,

an interrupt is generated J&~$&~verse IS true.

Assume now with Ct$,%$=~$ that aCounter Initialization

has occurred and tha$i~~fl~~te input has returned low prior

to Counter Time ,Q,ut.’’Q~nce there is no Individual Interrupt

Flag generated,,~~~]$$ ~,utomatlcally starts anew Counter in-

itialization C@~~$$~e process will continue with frequencv

comparis~o~$e~,~$ performed on each Gate input cvcle until

the mo~,~s changed, or acvcle is determined to be above

the ~~de~.mined limit.

.4:.\,.;*.,,

h.,~,~.a

&*’~ls#Width Comparison Mode (CRX3= 1, CRX4= 1) -

+&,~$~&~rnode is similar to the FrequencV Comparison Mode ex-

~.(..,.~ept for apositive, rather than negative, transition of the

.t$:\\tfw>::

““>?Gate input terminates the count. With CRX5= O, an lndivld-

f}‘~ ual Interrupt Flag will be generated if the zero level pulse

applied to the Gate input is less than the time period required

for Counter Time Out, With CRX5= 1, the interrupt is gener-

ated when the reverse condition is true.

As can be seen in Table 8, apositive transition of the Gate

input disables the counter. With CR X5= O, it IS therefore

possible to directlv obtain the width of anv pulse causing an

interrupt. Similar data for other Time Interval Modes and

conditions can be obtained, if two sections of the PTM are

dedicated to the purpose.

OUTPUT DELAY

,.,,

+:::,

~,,/+.’

?;/,,,.:$, <‘‘. cRX3 =1

cq,%~,:;:5*X5 Application Condition for Setting Individual Interrupt Flag

,,,.8’ J“

.J*, .~.s. oFrequency Comparison Interrupt Generated if Gate Input Period (l/F) is less

‘\y,.,,,.~l)+

‘\~.>;. than Counter Time Out (TO)

“,’:*+ii

.J:>!, -‘[:0 1Frequency Comparison

:k:\\ ;~j Interrupt Generated !f Gate Input Period (1 /F) is greater

\3..x/~ ~s~ij,.\$ than Counter Time Out (TO)

....s. .’.

.,,,,.s%}::,:,?

.,>,,,\toPulse Width Comparison Interrupt Generated if Gate Input “Down Time” is less

qj>~,, ;i~,

~:<$.,F

<,:.-.,,. than Counter Time Out (TO)

>,,>,,

‘t.., 11Pulse Width Comparison Interrupt Generated If Gate Input “Down Time” IS greater

than Counter Time Out (TO)

MOTOROLA MC6840

12 DS9802R3

-——— -—

.— ... ....

FIGURE 10 –TIMER OUTPUT WAVEFORM EXAMPLE

(Continuous Dual 8-Bit Mode Using Internal Enable)

“Time

Example: Contents of MSB =03 =Mout

Contens of LSB =04 =LI

~M(L+l)+l~L4

~Algebraic Expression

----

~1A ~m ‘L 1

03(04+ 1)+ 1=

I16 Enables II

I2.4 V

Counter Output 0.4 v.“*Q.

1: @kr.\:27,,

.b,;:t. .:6

l\ ~,~+s~’.

~;,?*,

II <~:;*:>~~(~

‘~$~~$

II $~’:~..

Enable \\ ,,,>:!$

>$’,i ,<~~t~

(System 02) J,,

,:. ?.,.* ‘$

Iid:

II ,,,,:.. ,5,,,,L,X

,.i:

_l+L~,+L~l +L~ ~L

‘.’’*:..{:,

,,s~?p%k&*$

5Enable

.,:-” ,,,,,iv ‘

5Enable 5Enable ,I4Enable *’.$&*J, !,:.

..$,.\\.*

Pu Ises Pulses Pulses Pu Ises $~,k ..!:,.:

.::>.,,+

Ii ~1+LV,*J:,,::’””i.

1[ II ,5Eq,~j: ~k$! ,

II II [pu+!?~~ ,*S

1, Il., +$?~..,,,f,?

II (M+l)(L+l) ~.~:: .?$>.

II ,.

:’?$}>

I~ki\\ ,k..,&’””

T.;

(M +1)(L+ 1) =Period Al& br$l&” Expression

M(L +1) +1=LOW portion of period ..$j~9f$?y\(03 +1) =20 Enable or

L=Pulse width ,+, +$&ternal Clock Pulses

.$.*\$k

*Preset LSB and MSB to Respective Latches on the negattve trans[f~o~!of the Enable

**Preset LSB to LSB Latches and Decrement MSB bv one on th~~;~~,ti;$ transition of the Enable

.. k

~~”h‘:$s~$,,$y

,*,,, .,\.,..,

.t,te

t$~,)?it$,<;,}

The tilscussion of the Continuous Mode has assumed that +U

*the counter results in the setting of an Individual Interrupt

Ythe application requires an output signal. It should be noted. *Flag and re-initialization of the counter.

,+.:.{..’

that the Timer operates in the same manner with the out~ti%$,, The second major difference between the Single-Shot and

disabled (C RX7=O). ARead Timer Counter comman&~s ‘*: Continuous modes is that the internal counter enable is not

~?$:J?.S:J:>.

valid regardless of the state of CR X7. ‘‘k’.“‘“’” dependent on the Gate input level remaining In the low state

,$.:J’?.,, !,$.

,.. \i-

.+::i~\*\$:).\,,., for the Single-Shot mode.

SINGLE-SHOT TIMER MODE –This mode~st~%’~%$’al to Another special condition is Introduced in the Single-Shot

the Continuous Mode with three exceptioq~’$~$$ first of mode. If L= M=O (Dual 8-bit) or N=O (Single 16-bit), the

these is obvious from the name –the o~~pu~it~turns to aoutput goes low on the first clock received during or after

low level after the initial Time Out a~~:r~w~ns low until Counter Initialization. The output remains low until the

another Counter Initialization cyclec,$$~~s,$ Operating Mode is changed or nonzero data IS written Into

As indicated in Table 6, the inte$~a~~ountlng mechanism the Counter Latches. Time Outs continue to occur at the end

remains cvclical in the Single-$@@~;~@de. Each Time Out of of each clock period.

.:..$.., .,

‘,*

“:’:::.:.,:,,~

>J:,i.

,,,.

$1’::,+., TABLE 6– SINGLE-SHOT OPERATING MODES

~’ ,*)

syb$h~;s’m

\“des ISINGLE-SHOT MODE

‘Q~,\

-~$>;,<>

..,, .$\ ~(CRX3 ‘0, CR X7= I, CRX5= 1)

<$~$~~~1 Register Initialization/Output Waveforms

..@ r;?*X2

$, CRX4 Counter Initialization Timer Output (OX)

Yi*,>’

‘i<**.J:$~!.l:.,

~}.:

$<,*‘<tfr:$,. 0 0 ~L+W+R

:..i$>%

kw+~s,,%.

~t,-:.

‘..~>::,

.,:,.-:.

,,\\\: ~F_y’N+l’T’lo

.,. 0 1 ~$+R

106J +W+R

1 1 5$+R

~(L+’’(q::~’L’)(M+’’(T)~

lo TO TO

Symbols are asdefined in Table 5.

MC6840 MOTOROLA

DS9802R3 11

PACWGE DIMENSIONS

NOTES:

1. POSITIONAL TOLERANCE OF LEAOS (01,

SHALL BE WITHIN 0.25rnrn(0.OID) AT

MAXIMUM MATERIAL CONOITION, IN

hnfitinfinfifi hfin AA

,8 ,,, , RELATION TO SEATING PLANE ANO PSUFFIX

EACH OTHER. PLASTIC PACKAGE

L: 2, OIMENSION LTO CENTER OF LEAOS CASE 71002

WHEN FORMEO PARALLEL.

3. OIMENSION BDOES NOT IN CLUOE

MOLO FLASH.

AL-

Ni ,

--H– -G- - - --- K

F~---

DSF*T,,Z-—~

?,l,,[

SSUFFIX

CERDIP PACKAGE

CASE 7S01

NOTES

1. OIM ~IS OAT,&~

2. POSITIONAL T~j~~O+&&,AOS:

r: ,3;:E:;”’

4DIM A&#Q$>J,N5~UOES MENISCUS.

5OIM ~k::YY&*ENTER OF LEA05

6. OIM~&lONING AN OTOLERANCING

,,~~ PER ~NSl Y14.5, 1973.

rA -)~jjF L‘1

~G~

-+y[f~k ~

F::wD*t,>+

..,.> ~M I

+:\

i, ,,

..! .“$v$>>t.$?:’

~y”’“-.::::

,)$

~,::.

.,*‘.,’!!.,.~~.:..~<..,,.,,

,.,, ..

?:i:, ,$$.

‘~,,:t,

,>, .*:,*

,,i$: ,ij”~

“%;;* “i,<,!l

~::~,,

,!t, \*t:

.<%:,i,,$,,.i,.

J’$! .“,?:*

.. ~.,,

~~.’,>.

‘$:s:,:, ,,$$

.1:$...{J:+‘\.:;$.

,:.,:$ ~.{?::\\,

:,, .~> ‘~

.,,

~>$t.

,,\i.$,$$<\.**...F?’

~,$ii,

.,ii:~:!:it:<-,:,,

kb,

“*{*,t..}

‘\\ k*i:.. ,

:,$,,;;,:..!’,

hotorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola

does not assume any Iiabilitv arising out of the application or use of anv product or circuit described herein; neither does it convev any license

under its patent rights nor the rights of others. Motorola products are not authorized for use as components in life suppofl devices or systems

intended for surgical implant into the body or intended to support or sustain life. Buver agrees to notify Motorola of anv such intended end use

whereupon Motorola shall determine availability and suitability of its product or products for the use intended. Motorola and @are registered

trademarks of Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity/Affirmative Action EmploVer.

—

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USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.

EUROPE: Motorola Ltd.; European Literature Center; 88 Tanners Drive, Blakelands Milton KeVnes, MK145BP, England.

ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; PO. Box 80300; Cheung Sha Wan Post Office; Kowloon Hong Kong.

-MMOrOROLA MC6840

.-,,,,5., ,.,.,,, 1,“,. 7-88 IWERW .=0 C578Z4 5.WO YCACM DS9802R3