IDT74ALVCF162835APF8 - Integrated Device Technology

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCF162835A

3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

1JANUARY 2004INDUSTRIAL TEMPERATURE RANGE

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• 0.5 MICRON CMOS Technology

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

•VCC = 3.3V ± 0.3V, Normal Range

•VCC = 2.7V to 3.6V, Extended Range

•VCC = 2.5V ± 0.2V

• CMOS power levels (0.4µµ

µµ

µ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• Available in TSSOP and TVSOP packages

FUNCTIONAL BLOCK DIAGRAM

DRIVE FEATURES:

• Balanced Output Drivers: ±18mA

• Low switching noise

APPLICATIONS:

• SDRAM Modules

• PC Motherboards

• Workstations

IDT74ALVCF162835A

3.3V CMOS 18-BIT

UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

DESCRIPTION:

This 18-bit universal bus driver is built using advanced dual metal CMOS

technology. Data flow from A to Y is controlled by the output-enable (OE)

input. The device operates in the transparent mode when the latch-enable

(LE) input is high. The A data is latched if the clock (CLK) input is held at

a high or low logic level. If LE is low, the A data is stored in the latch flip-flop

on the low-to-high transition of CLK. When OE is high, the outputs are in the

high-impedance state.

The ALVCF162835A has series resistors in the device output structure

which will reduce switching noise in 128MB and 256MB SDRAM modules.

Designed with a drive capability of ±18mA, the ALVCF162835A is a mid-

way drive between the ALVC162835 (±12mA) and ALVC16835 (±24mA).

The ALVCF162835A is a faster version of the ALVCF162835 or

ALVC162835. It is suitable for PC133 applications and particularly SDRAM

Modules clocked at 133 MHz.

TO 17 O THE R CHANN ELS

CLK

3Y1

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCF162835A

3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

PIN CONFIGURATION Symbol Description Max Unit

VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6 V

VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V

TSTG Storage Temperature –65 to +150 °C

IOUT DC Output Current –50 to +50 mA

IIK Continuous Clamp Current, ±50 mA

VI < 0 or VI > VCC

IOK Continuous Clamp Current, VO < 0 –50 mA

ICC Continuous Current through each ±1 0 0 mA

ISS VCC or GND

ABSOLUTE MAXIMUM RATINGS(1)

NOTES:

1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. VCC terminals.

3. All terminals except VCC.

Pin Names Description

OE 3-State Output Enable Inputs (Active LOW)

CLK Register Input Clock

LE Latch Enable (Transparent HIGH)

Ax Data Inputs

Yx 3-State Outputs

PIN DESCRIPTION

TSSOP/ TVSOP

TOP VIEW

GND

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

A10

A11

A12

A13

A14

A15

VCC

A16

A17

A18

GND

VCC

CLK

GND

VCC

GND

NOTE:

1. As applicable to the device type.

Symbol Parameter(1) Conditions Min. Typ. Max. Unit

CIN Input Capacitance VIN = 0V 4 5 6 pF

COUT Output Capacitance VOUT = 0V — 7 9 pF

COUT I/O Port Capacitance VIN = 0V — 7 9 pF

CAPACITANCE (TA = +25°C, F = 1.0MHz)

NOTES:

1 . H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Z = High-Impedance

↑ = LOW-to-HIGH Transition

2. Output level before indicated steady-state input conditions were established, pro-

vided that CLK is HIGH before LE went LOW.

3. Output level before the indicated steady-state input conditions were established.

FUNCTION TABLE(1)

Inputs Outputs

OE LE CLK Ax Yx

HXXX Z

LHXL L

LHXH H

LL↑LL

LL↑HH

LLHX Y

0(2)

LLLX Y

0(3)

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCF162835A

3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

Symbol Parameter Test Conditions Min. Typ.(1) Max. Unit

VIH Input HIGH Voltage Level VCC = 2.3V to 2.7V 1.7 — — V

VCC = 2.7V to 3.6V 2 — —

VIL Input LOW Voltage Level VCC = 2.3V to 2.7V — — 0.7 V

VCC = 2.7V to 3.6V — — 0.8

IIH Input HIGH Current VCC = 3.6V VI = VCC ——±5µA

IIL Input LOW Current VCC = 3.6V VI = GND — — ±5µA

IOZH High Impedance Output Current VCC = 3.6V VO = VCC ——±10 µA

IOZL (3-State Output pins) VO = GND — — ±10

VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V

VHInput Hysteresis VCC = 3.3V — 100 — mV

ICCL Quiescent Power Supply Current VCC = 3.6V — 0.1 40 µ A

ICCH VIN = GND or VCC

ICCZ

∆ICC Quiescent Power Supply Current One input at VCC - 0.6V, other inputs at VCC or GND — — 750 µA

Variation

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Operating Condition: TA = –40°C to +85°C

NOTE:

1. Typical values are at VCC = 3.3V, +25°C ambient.

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OUTPUT DRIVE CHARACTERISTICS

Symbol Parameter Test Conditions(1) Min. Max. Unit

VOH Output HIGH Voltage VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — V

VCC = 2.3V IOH = – 6mA 1.9 —

IOH = – 8mA 1.7 —

VCC = 2.7V IOH = – 6mA 2.2 —

IOH = – 12mA 2 —

VCC = 3V IOH = – 8mA 2.4 —

IOH = – 18mA 2 —

VOL Output LOW Voltage VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 V

VCC = 2.3V IOL = 6mA — 0.4

IOL = 8mA — 0.55

VCC = 2.7V IOL = 6mA — 0.4

IOL = 12mA — 0. 6

VCC = 3V IOL = 8mA — 0.55

IOL = 18mA — 0. 8

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCF162835A

3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

OPERATING CHARACTERISTICS, TA = 25°C

VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V

Symbol Parameter Test Conditions Typical Typical Unit

CPD Power Dissipation Capacitance Outputs enabled CL = 0pF, f = 10Mhz 30 35 pF

CPD Power Dissipation Capacitance Outputs disabled 12.5 14

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

SWITCHING CHARACTERISTICS(1)

VCC = 2.5V ± 0.2V VCC = 2.7V VCC = 3.3V ± 0.3V

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

fCLOCK 150 — 150 — 150 — MHz

tPLH Propagation Delay 1 4 —4.6 1 3.5 ns

tPHL Ax to Yx

tPLH Propagation Delay 1.3 5.5 —5.4 1.3 4.6 ns

tPHL LE to Yx

tPLH Propagation Delay 1.4 5.9 —5.6 1.4 3.5 ns

tPHL CLK to Yx

tPZH Output Enable Time 1.4 5.9 —6 1.1 5 ns

tPZL OE to Yx

tPHZ Output Disable Time 1 4.7 —4.6 1.3 4.2 ns

tPLZ OE to Yx

tWPulse Duration, LE HIGH 3 .3 —3.3 —3.3 —ns

tWPulse Duration, CLK HIGH or LOW 3 .3 —3.3 —3.3 —ns

tSU Set-up Time, data before CLK↑1.8 —1.5 —1—ns

tSU Set-up Time, data before LE↓, CLK HIGH 1 .9 —1.6 —1.5 —ns

tSU Set-up Time, data before LE↓, CLK LOW 1.3 —1.1 —1—ns

tHHold Time, data after CLK↑0.6 —0.6 —0.6 —ns

tHHold Time, data after LE↓, CLK HIGH or LOW 1. 4 —1.7 —1.4 —ns

tSK(O) Output Skew(2) —————500 ps

SWITCHING CHARACTERISTICS FROM 0°C TO 65°C, CL = 50pF

VCC = 3.3V ± 0.15V

Symbol Parameter Min. Max. Unit

tPLH Propagation Delay 1.8 3.5 ns

tPHL CLK to xYx

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCF162835A

3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

Open

VLOAD

GND

VCC

Pulse

Generator D.U.T.

500Ω

VIN VOUT

(1, 2)

ALVC Link

INPUT

VIH

VOH

VOL

tPLH1

tSK (x)

OUT P UT 1

OUT P UT 2

tPHL1

tSK (x )

tPLH2 tPHL2

VOH

VOL

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

ALVC Link

SAME PHASE

IN PU T TR AN SIT ION

OPPOSITE PHASE

IN PU T TR AN SIT ION

VOH

VOL

tPLH tPHL

tPHL

tPLH

OUTPUT

VIH

ALVC Link

DATA

INPUT 0V

tREM

TIMING

INPUT

SYNCHRONOUS

CONTROL

tSU tH

VIH

ALVC Link

ASYNCHRONOUS

CONTROL

LOW-HIGH-LOW

PULSE

HIGH-LOW-HIGH

PULSE

ALVC Link

CONTROL

INPUT tPLZ 0V

OUTPUT

NORMALLY

LOW tPZH

SWITCH

CLOSED

OUTPUT

NORMALLY

HIGH

ENABLE DISABLE

SWITCH

OPEN

tPHZ

VOL + VLZ

VOH

tPZL

VLOAD/2 VLOAD/2

VIH

VOL

VOH - VHZ

ALVC Link

TEST CIRCUITS AND WAVEFORMS

Propagation Delay

Test Circuit for All Outputs

Enable and Disable Times

Set-up, Hold, and Release Times

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.

Output Skew - tSK(X)

Pulse Width

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit

VLOAD 6 6 2 x Vcc V

VIH 2.7 2.7 Vcc V

VT1.5 1.5 Vcc / 2 V

VLZ 300 300 150 mV

VHZ 300 300 150 mV

CL50 50 30 pF

TEST CONDITIONS

SWITCH POSITION

Test Switch

Open Drain

Disable Low VLOAD

Enable Low

Disable High GND

Enable High

All Other Tests Open

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCF162835A

3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

ORDERING INFORMATION

IDT XX ALVC XXX XX

Package

Device Type

Temp. Range

F162

Thin Shrink Small Outline Package

Thin Very Small Outline Package

18-Bit Universal Bus Driver with 3-State Outputs

– 40°C to +85°C

XXXX

FamilyBus-Hold

835

Double-Density with Resistors, ±18mA

No Bus-hold

Blank

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