FEATURES Two independent fall duple: eatiniuls, with separate control and status line far me luins oF other devices. Data rate in the x1 clock meeks af 0 to 2.0M bits/ second with a 10 MEI7 clock NMOS version for cost senellive performance solutions, CMOS version for the deaiyiis saquiring low power consumption NMOS 20844x04 - 4 MI ly 7110044 x06- 6.17 MHz (Where xis the designator for the hanhng option; 0, 1, 2 or 4) CMOS 284C4x06 ft te & f Mtlz, 284C4x08 - DC to 8 MHz, Z84C4x10 HC te 10 Miz (Where x is the designator for the bonding eplian, 0, 1, 2, 3or 4) 6 MHz version supports @ 144 Mliz GPU clock opera- tion. PRODUCT SPECIFICATION 28440/1/2/4, 284040/1/2/3/4 SERIAL INPUT/OUTPUT CONTROLLER @ Asynchioaous protocols everything necessary for Complate messages in 5, 6, 7, or 8 bits/character. Includes variable stop bits and several clock-rate multiplier, break generation and detection: parity; overrun and framing error detection. Synchronous protocols. everything necessary for complete bit- or byte-oriented messages in 5, 6, 7, or 8 bits/character, including IBM Bisync, SDLC, HDLC, CCITT-X.# and others. Automatic CRC generation/ checking, sync character and zero insertion/deletion, abort genoration/detection, and flag insertion. @ Receiver data registers quaciuply buffered, transmitter registers doubly buffered @ Highly sophisticated and flexible daisy-chain interrupt vectoriny for interrupts without external logic. GENERAL DESCRIP HON The Z80 SIO (here in after refered to as the Z80 SIO or, SIO). Serial InpufOutput Contre: te a dual-channel data communication interface with eliaardinary versatility and capability. Its basic functinne ae serial-to-paratlel, paral- lel-to-serial converter/contintier -an be programmed by a CPU for a broad range of eerital communication applica- tions. The device supports all eramicnt asyachronous and synchronous protocols. byte or bil anented, and performs all of the functions traditionally dane by UARTs, USARTs, and synchronous communieaten contoliers combined, plus additional functione Iacitivtally pertormed by the CPU. Moreover, it done thie oi two (ully-independent PIN DESCRIPTION Figures 1 througt 6 illtteteate the Hua 40 pin configurations (bonding options) availatile in the 280C sio (hereafter referred to as SIO or 7A0 Slt) (ie eonstraints of a 40-pin package make it impnesitly be buig out the Receive Clock (RxC), Transmit Clock (hi) ata Terminal Ready (BTR) and Sync SYNC) signale bu bath channels. There- fore, either Channel RB lacte a eiyiial OF two signals are bonded together @ 280 SIO/2 lacks SYNCR @ Z80 SIO/M lacks DTAR channels, with an exceptionally sophisticated interrupt structure that allows very fast transfers. , Full interfacing is provided tor CPU or DMA control. in addition to data communication, the circuit can handle Virtually all types of serial /O with fast, or slow, peripheral devices. While designed primarily as a member of the 280 family, its versatility makes it well suited to many other CPUs. The 280 SIO uses a single 45V power supply and the standard Z80 famity single-phase clock. The SIO/0, SIO/1, and SlO/2 are packaged in a 40-pin DIP, the SI0/4 is packaged In a 44-pin PCC and the SI0/3 is packaged ina 44-pin QFP. Note that SI0/3 is only available in CMOS and in QFP package. @ 280 SIO/0 has all four siqnals, but KCB and RxCB are bonded together The 44-pin package, the 780 SIO/4 for PLCC package, and 280 SIO/3 tor QFP, has all options (Figure 7a and 7b). The first bonding option above (SIO/2) is the preferred version for most applications. Ihe pin descriptions are as follows: B/A. Channot A or B Select (input, High selects Channel B). This input defines which channel is accessed during a data 99{ ++/ d, RRDA _] 0, RxCA J~<__- -+?] 0, TDA - WW CPU } | o, Tita [<_ 11 40 [7] Oo para ats o. . pus | +>]|% SYNCA |<_> Cj 2 3 [> ++| d, WihovA ->> CHANNEL A os (: se f] ++] 0, Oo; CJ 37 [] D6 \ ~<] 0, ATSA }_ int C) 5 36 [] ona | CTSA |~+ | movem eG 35] ce 780 OTRA -} ( CONTROL 0 (7 xf] 8A >} CE S$t0/2 BCOA |< mi(js 3] co +] Reser *VT}9 ogg 06-2 80 >| i wmova (J 10 31 DJ ono CONTROL | +1 ionG ROB |<_ ) syncs (] 1 S10/2 50 C] wove ree) | ol rxoa (] 12 29 [7] Rxoe x08 | axca (I) 13 28 [D] xt ob _ Wee j<___ tea [J 14 27D] ace wk wove -}> \ Hammes 8 toa [15 26 [] pa . OTRA [7] 16 2s [J] ora RTS6 }_ AISA (I) 17 24 [1] Atse DAISY | <J int TTS6 }~. | movem CTSA (} 18 23D] cise Intennurt ] 16 DTAB |_ { CONTROL OCoA [I] 19 22] ote CONTROL | Ico DCDE |j<__ ) cux [J 20 21 [] Reset J Vv GND I Figure 1. Pin Functions Figure 2. 40-pin Dual-In-Line Package (DIP), Pin Assignments ( +ri Dd, AxDA [-<_- \ <_] 0, ReCA [<_ ~++] 0, TxDA -/-> cru | +1 0, na |_ oc ~~ wlio onus 7 0, . SYNCA [-<> os C)2 vo -_} do, WikOYA ->- \, CHANNEL a os (J 3 ssf 0 +>] 0, . i a7 1] o \ +] p, aTsa > iNT q 5 3% a} ora TSA j~+- | wovem es 3s [) ce TRA ->_ { CONTROL iO q 7 ay BA /+l son ocon |}<_ mG 33 os ] RESET +5V a $ z80 320] fo | ii RxDB |q___ wero (} 10 gig/t = 3 LJ GN CONTROL | +] iona ACE |< ) syncs Cts 30 [-] WADYE ran | 15 06 |__ repa [] 12 20D] syace TxCB [<___ fica (13 28 [J px >| or _SYNCB +> iea (J 4 art) rcs +]| 8A wove CHANNEL B toa Ch 1s 6 f) eB DTRA ((] 16 25 [] hoa aYSE ATSA Qw 24 [L] ATSB ase |" eS ee cate shee INTERRUPT el cog }_. DCDA [] 19 22 [] 0coB CONTROL | +7 [0 ceux [J 20 21 [7] Reset +5V Figure 3. Pin Functions GNO CLK Note: Power connections follow conventional descriptions below: Connection | Circuit | Device Power Voc Veo Ground | GNO | V,, Figure 4. 40-pin Dual-in-Line Package (DIP), Pin Assignments 100+] 0, ROA <_ iD, ACA ~~} D, TxOA CPU j +1, TrCA DATA _ sus ) * 1] 9. SYNCA +] 0, WIRDYA ] 0, \ + ] 0, aTSA CTSA MODEM NTROL _ 780 DTRA CONTRO ] CE slov OCDA +] RESET _ >] i CONTROL | +] ioRO Rx08 FROM a cpu +] AD BxTxCB TxOB SYNCB et _ Wihove _ fl BA aTse DAIsy | <-4 iNT CTs MODEM CHAIN ae CONTROL INTERRUPT el pine : contro: | '0 bcos 301 40 [7 0% Os] 2 33 [] 0 CHANNEL A os(j3 36 [J 0 07] at] o mit (5 36 [J tono ei (] 6 as [] ce 10 (7 uf] ea mi] s af] co +sv CJ 9 780 32 7 RD WOYA [] 10 SIO/0. a1 [J GNO syaca (] 1 ao [J wove Rxba (7) 12 29 [] svace fixca (] 13 28 [ fx08 nea 4 27D axtce TOA [7] 15 26 [J os cranes 8 TRA C ts 2 ; oras TSK (CF) 7 24] fts8 CTSA (] 18 23 [] crse OCOA [J 19 22 [J] ocoe ceux (J 20 21 [7] Reset Tt +5V GND CLK Figure 5. Pin Functions Figure 6. 40-pin Dual-In-Line Package (DIP), Pin Assignments N\. 18 19 20 21 22 23 24 2526 27 28 ele Figure 7a. 44-pin Chip Carrier, Pin Assignments < XJF joe wo o 8 alg (BIRIBIE = 8 old (SIE Z84C43 C-MOS Z80 Sl0/3 O EB eBEEEE Figure 7b. 44-pin Quad Fiat Pack Pin Assignments transfer between the CPU and the SIO. Address bit Ay from the CPU is often used for the selection function. C/D. Control or Data Select (input, High selects Control). This input defines the type of information transfer performed between the CPU and the SIO. A High at this input during a CPU write to the SIO causes the information on the data bus to be interpreted as a command for the channel selected by B/A. A Low at C/D means that the information on the data bus is data. Address bit A, is often used for this function. CE. Chip Enable (Input, active Low). A Low level at this input enables the SIO to accept command or data input trom the CPU during a write cycle, or to transmit data to the CPU during a read cycle. CLK. System Clock (input). The SIO uses the standard Z8C System Clock to synchronize internal signals. This is single-phase clock. 101CTSA, CTSB. Clear To Send (inputs, active Low). When programmed as Auto Enables, a Low on these inputs enables the respective transmitter. If not programmed as Auto Enables, these inputs may be programmed as general-purpose inputs. Both inputs are Schmitt-trigger buffered to accommodate slow-risetime signals. The SIO detects pulses on these inputs and interrupts the CPU on both logic level transitions. The Schmitt-trigger buffering does not guarantee a specified noise-level margin. Do-D7. System Data Bus (bidirectional, 3-state). The system data bus transfers data and commands between the CPU and the Z80 SIO. Dg is the least significant bit. DCDA, DCDB. Data Carrier Detect (inputs, active Low). These pins function as receiver enables if the SIO is programmed for Auto Enables; otherwise they may be used as general-purpose input pins. Both pins are Schmitt-trigger buffered to accommodate slow-risetime signals. The SIO detects pulses on these pins and interrupts the CPU on both logic level transitions. Schmitt-trigger buffering does not guarantee a specific noise-level margin. DTRA, DTRB. Data Terminal Ready (outputs, active Low). These outputs follow the state programmed into the Z80 SIO. They can also be programmed as general-purpose outputs. In the Z80 SIO/1 bonding option, DTRB is omitted. fEl. interrupt Enable In (input, active High). This signal is used with IEO to form a priority daisy chain when there is more than one interrupt-driven device. A High on this line indicates that no other device of higher priority is being serviced by a CPU interrupt service routine. IEO. interrupt Enable Out (output, active High). IEO is High only if IEt is High and the CPU is not servicing an interrupt from this SIO. Thus, this signal blocks lower priority devices from interrupting while a higher priority device is being serviced by its CPU interrupt service routine. INT. Interrupt Request (output, open drain, active Low). When the SIO is requesting an interrupt, it pulls INT Low. iORQ. Input/Output Request (input from CPU, active e Low). TORO is used in conjunction with B/A, C/D, CE, and RD to transfer commands and data between the CPU and the SIO. When CE, RD, and JORG are all active, the channel selected by! B/A transfers data to the CPU (a read operation). When CE and IORQ are active, but RD is inactive, the channel selected by B/A is written to by the CPU with either data or contro! information as specified by C/D. As mentioned previously, if IORQ and M1 are active simultaneously, the CPU is acknowledging an interrupt and the SIO automatically places its interrupt vector on the CPU data bus if it is the highest priority device requesting an interrupt. M1. Machine Cycle One(input from Z80 CPU, active Low). When M1 is active and RO is also active, the Z80 CPU is fetching an instruction from memory; when M1 is active while IORQ is active, the SIO accepts M1 andTORG as an interrupt acknowledge if the SIO is the highest priority device that has interrupted the 280 CPU. RxCA, RxCB. Receiver Clocks (inputs). Receive data is sampled on the rising edge of RxC. The Receive Clocks may be 1, 16, 32, or 64 times the data rate in asynchronous modes. These clocks may be driven by the Z80 CTC Counter Timer Circuit for programmable baud rate generation. Both inputs are Schmitt-trigger buffered; no noise level margin is specified. In the Z80 SIO/0 bonding option, RxCB is bonded together with TxCB. RD. Read Cycle Status (input from CPU, active Low). RO is active, a memory or I/O read operation is in progress. RD is used with B/A, CE, and IORQ to transfer data from the SIO to the CPU. RxDA, RxDB. Receive Data (inputs, active High). Serial data at TTL levels. RESET. Reset (input, active Low). ALow RESET disables both receivers and transmitters, forces TkDA and TxDB marking, forces the modem controls High, and disables all interrupts. The control registers must be rewritten after the SIO is reset and before data is transmitted or received. RTSA, RTSB. Request To Send (outputs, active Low). When the RTS bit in Write Register 5 (Figure 14) is set, the RATS output goes Low. When the RTS bit is reset in the Asynchronous mode, the output goes High after the transmitter is empty. In Synchronous modes, the RTS pin strictly follows the state of the RTS bit. Both pins can tbe used as general-purpose outputs. SYNCA, SYNCB. Synchronization (bidirectional, active Low). These pins can act either as inputs or outputs. In the asynchronous receive mode, they are inputs similar to Ts and DCD. In this mode, the transitions on these lings affect the state of the Sync/Hunt status bits in Read Register 0 (Figure 13), but have no other function. In the External Sync mode, these lines-also act as inputs. When xternal synchronization is achieved, SYNC must be driven Low on the second rising edge of RxC after that rising edge pf RxC on which the last bit of the sync character was recejved. In other words, after the sync pattern is detected, the xternal logic must wait for two full Receive Clock cycles to activate the SYNC input. Once SYNC is forced Low, it should be kept Low until the CPU informs the external synchronization detect logic that synchronization has been fost or a new message is about to start. Character assembly begins on the rising edge of RxC that immediately precedes the falling edge of SYNC in the External Sync mode. In the internal synchronization mode (Monosync and Bisync), these pins act as outputs that are active duting the part of the receive clock (RxC) cycle in which sync characters are recognized. The sync condition is not latched, so these outputs are active each time a sync pattern 102is recognized, regardless of character boundaries. In the Z80 SIO/2 bonding option, SYNCB is omitted. TXCA, TxCB, Transmitter Clocks (inputs). In asynchronous modes, the Transmitter Clocks may be 1, 16, 32, or 64 times the data rate; however, the clock multiplier must be the same for the transmitter and the receiver. The Transmit Clock inputs are Schmitt-trigger buffered for relaxed rise- and fall-time requirements; no noise level margin is specified. Transmitter Clocks may be driven by the Z80 CTC Counter Timer Circuit for programmable baud rate generation. In the Z80 SIO/O bonding option, TxCB is bonded together with RxCB. TxDA, TxDB. Transmit Data (outputs, active High). Serial data at TTL levels. TxD changes from the falling edge of TxC. W/RDYA, W/RDYB. Wait/Ready (outputs, open drain when programmed for Wait function; driven High and Low when programmed for Ready function). These dual-purpose outputs may be programmed as Ready lines for a DMA controller or as Wait lines that synchronize the CPU to the SIO data rate. The reset state is open drain. 103FUNCTIONAL DESCRIPTION The functional capabilities of the Z80 SIO can be described from two different points of view: as a data communications device, it transmits and receives serial data in a wide variety of data-communication protocols; as a Z80 family peripheral, it interacts with the Z80 CPU and other peripheral circuits, sharing the data, address and control CHANNEL A CONTROL AND STATUS REGISTERS CHANNEL A ut t | SERIAL ri | DATA [~- | CHANNEL jt | CLOCKS tt SYNC + WAITIREADY buses, as well as being a part of the Z80 interrupt structure. INTERNAL CHANNEL A} MODEM As a peripheral to other microprocessors, the SIO offers CONTROL AND [OR ck valuable features such as non-vectored interrupts, polling, STATUS |__| contRot and simple handshake capability. Figure 8 is a block I diagram. N . . . . DATA E Figure 9 illustrates the conventional devices that the SIO < cpu - R CHANNEL 6 Pe MODEM replaces. = 40 A fetus [oe J OTHER , Controt 7? t StaTUS |__,.. / CONTROL The first part of the following discussion covers SIO 8 data-communication capabilities; the second part s muAL describes interactions between the CPU and the SIO. . _ C| bara TERAUPT ( ~<7 IN RUPT CONTROL {| o CHANNEL fe) Brocrst LINES Loic N i WAITIREADY CHANNEL 6 . CONTROL AND STATUS REGISTERS Figure 8. Block Diagram UART fp~ CHANNEL A SYNCHRONOUS COMMUNICATIONS | CONTROLLER r MICROPROCESSOR Po INTERRUPT INTERFACE ~+| ConTROLLER _, - UART CHANNEL 8 SYNCHRONOUS cc ATION CONTROLLEA rc CHANNEL MICROPROCESSOR a INTERFACE CHANNEL B Figure 9. Conventional Devices Replaced by the Z80 SIO 104DATA COMMUNICATION CAPABILITIES The SIO provides two independent full-duplex channels that can be programmed for use in any common asynchronous, or synchronous data-communication protocol. Figure 10a illustrates some of these protocols. The following is a short description of them. A more detailed explanation of these modes can be found in the Z80 S/O Technical Manual (03-3033-01). Asynchronous Modes. Transmission and reception can be done independently on each channel with five to eight bits per character, plus optional even or odd parity. The transmitters can supply one, one-and-a-half, or two stop bits per character and can provide a break output at any time. The receiver break-detection lagic interrupts the CPU both at the start and end of a received break. Reception is protected from spikes by a transient spike-rejection mechanism that checks the signal one-half a bit time after a Low level is detected on the receive data input (RxDA or RxDB in Figure 5). If the Low does not persist, as in the case of atransient, the character assembly process is not started. Framing errors and overrun errors are detected and buffered together with the partial character on which they occurred. Vectored interrupts allow fast servicing of error conditions using dedicated routines. Furthermore, a built-in checking process avoids interpreting a framing error as a new start bit: a framing error results in the addition of one-half a bit time to the point at which the search for the next start bit is begun. The SIO does not require symmetric transmit and receive clock signals, a feature that allows it to be used with a Z80 CTC or many other clock sources. The transmitter and receiver can handle data at a rate of 1, 1/16, 1/32, or 1/64 of the clock rate supplied to the receive and transmit clock inputs. In asynchronous modes, the SYNC pin may be programmed as an input that can be used for functions such as monitoring a ring indicator. Synchronous Modes. The SIO supports both byte- oriented and bit-oriented synchronous communication. Synchronous byte-oriented protocols can be handled in several modes that allow character synchronization with an 8-bit sync character (Monosync), any 16-bit sync pattern (Bisync), or with an external sync signal. Leading sync characters can be removed without interrupting the CPU. Five-, six-, or seven-bit sync characters are detected with 8- or 16-bit patterns in the SIO by overlapping the larger pattern across multiple incoming sync characters, as shown in Figure 10b. CRC checking for synchronous byte-oriented modes is delayed by one character time so the CPU may disable CRC checking on specific characters. This permits implemen- tation of protocols such as IBM Bisync. Figure 10a. Some Z80 SiO Protocols PARITY START , | i" ae ASYNCHRONOUS | sync | DATA | er | DATA | crc, | CRC: | " MONOSYNG [Teme [sme [one [dy ~eata cmc, | crc: | SIGNAL "" pIsync | DATA / ** | DATA | cAcy | CRCz | EXTERNAL SYNC | Fisa | avoress | INFORMATION | crc, | crcz | FLac | SDLCIHOLC/X.25 Figure 10b. Six-Bit Sync Character Recognition 8 BITS { SYNC | SYNC | SYNC | DATA DATA i DATA | cata | SY 8 re 16 Figure 10. Data Communication 105Both CRC-16 (X16 + X15 + X2 + 1) and CCITT (X16 + X12 + X5 + 1) error checking polynomials are supported. In all non-SDLC modes, the CRC generator is initialized to Os; in SDLC modes, it is initialized to 1s. The SIO can be used for interfacing to peripherals such as hard-sectored floppy disks, but it cannot generate or check CRC for iBM-compatible soft-sectored disks. The SIO also provides a feature that automatically transmits CRC data when no other data is available for transmission. This allows very high-speed transmissions under DMA control with no need for CPU intervention at the end of amessage. When there is no data or CRC to send in synchronous modes, the transmitter inserts 8- or 16-bit sync characters regardiess of the programmed character length. The SiO supports synchronous bit-oriented protocols such as SDLC and HDLC by performing automatic flag sending, zero insertion, and CRC generation. A special command can be used to abort a frame in transmission. At the end of a message the SIO automatically transmits the CRC and trailing flag when the transmit buffer becomes empty. If a transmit underrun occurs in the middle of a message, an external/status interrupt warns the CPU of this status change so that an abort may be issued. One to eight bits per character can be sent, which allows reception of amessage with no prior information about the character structure in the information field of a frame. The receiver automatically synchronizes on the leading flag of a frame in SDLC or HDLC, and provides a synchronization signal on the SYNC pin; an interrupt can also be programmed. The receiver can be programmed to search for frames addressed by a single byte to only a specified user-selected address or to a global broadcast address. In this mode, frames that do not match either the user-selected or broadcast address are ignored. The number of address bytes can be extended under software control. For transmitting data, an interrupt on the first received character or on every character can be selected. The receiver automatically deletes all zeroes inserted by the transmitter during character assembly. It also calculates and automatically checks the CRC to validate frame transmission. At the end of transmission, the status of a received frame is available in the status registers. The S!O can be conveniently used under DMA control to provide high-speed reception or transmission. in reception, for example, the SIO can interrupt the CPU when the first character of a message is received. The CPU then enables the DMA to transfer the message to memory. The SIO then issues an end-of-frame interrupt and the CPU can check the status of the received message. Thus, the CPU is freed for other service while the message is being received. 1/0 INTERFACE CAPABILITIES The SIO offers the choice of polling, vectored or non-vectored interrupts and block-transfer modes to transfer data, status, and control information to, and from, the CPU. The block-transfer mode can also be implemented under DMA control. Polling. Two status registers are updated at appropriate times for each function being performed (for example, CRC error-status valid at the end of amessage). When the CPU is operated in a polling fashion, one of the SIO's two status registers is used to indicate whether the SIO has some data or needs some data. Depending on the contents of this register, the CPU will either write data, read data, or just go on. Two bits in the register indicate that a data transfer is needed. In addition, error and other conditions are indicated. The second status register (special receive conditions) does not have to be read in a polling sequence, until a character has been received. All interrupt modes are disabled when operating the device in a polled environment. Interrupts. The SIO has an elaborate interrupt scheme to provide fast interrupt service in real-time applications. A control register and a status register in Channel B contain the interrupt vector When programmed to do so, the SIO can modify three bits of the interrupt vector in the status register so that it points directly to one of eight interrupt service routines in memory, thereby servicing conditions in both channels and eliminating most of the needs for a status-analysis routine. Transmit interrupts, receive interrupts, and external/status interrupts are the main sources of interrupts. Each interrupt 106 source is enabled under program control, with Channel A having a higher priority than Channel B, and with rceive, transmit, and external/status interrupts prioritized in that order within each channel. When the transmit interrupt is enabled, the CPU is interrupted by the transmit buffer becoming empty. (This implies that the transmitter must have had a data character written into it so it can become empty.) The receiver can interrupt the CPU in one of two ways: - Interrupt on first received character @ Interrupt on all received characters Interrupt-on-first-received-character is typically used with the block-transfer mode. _ Interrupt-dn-all-received- characters has the option of modifying the interrupt vector in the event of a parity error. Both of these interrupt modes will also interrupt under special receive conditions on a character or message basis (end-of-frame interrupt in SDLC, for example). This means that the special-rceive condition can cause an interrupt only if the interrupt-on-first-received-character or interrupt-on-all- received-characters mode is selected. In interrupt-on-first- received-character, an interrupt can occur from special-receive conditions (except parity error) after the first-received-character interrupt (example: receive-overrun interrupt). The main function of the external/status interrupt,is to monitor the signal transitions of the Clear To Send (CTS), Data Carrier Detect (OCD), and Synchronization @YNC) pins (Figures 1 through 7). In addition, an external/statusinterrupt is also caused by a CRC-sending condition, or by the detection of a break sequence (asynchronous mode) or abort sequence (SDLC mode) in the data stream. The interrupt caused by the break/abort sequence allows the SiO to interrupt when the break/abort sequence is detected or terminated. This feature facilitates the proper termination of the current message, correct initialization of the next message, and the accurate timing of the break/abort condition in external logic. In a Z80 CPU environment (Figure 11), SIO interrupt vectoring is automatic: the SIO passes its internally- modifiable 8-bit interrupt vector to the CPU, which adds an additional 8 bits from its interrupt-vector (|) register to form the memory address of the interrupt-routine table. This table contains the address of the beginning of the interrupt routine itself. The process entails an indirect transfer of CPU control to the interrupt routine, so that the next instruction executed after an interrupt acknowledge by the CPU is the first instruction of the interrupt routine itself. CPU/DMA Block Transfer. The SIO's block-transfer mode accommodates both CPU block transfers and DMA controllers (280 DMA or other designs). The block-transfer mode uses the Wait/Ready output signal, which is selected with three bits in an internal control register. The Wait/Ready output signal can be programmed as a WAIT line in the CPU block-transfer mode or as a READY line in the DMA block-transfer mode. To a DMA controller, the SIO READY output indicates that the SIO is ready to transfer data to, or from, memory. To the CPU, the WAIT output indicates that the SIO is not ready to transfer data, thereby requesting the CPU to extend the I/O cycle. SYSTEM BUSES >) (3) cpu DMA INT [+ INT it +5V tet ZCITOy cTc ZCMO2 ITT (Eo 16 160 RxCA iNT ; INT TxcA 10 El AxCcB THB WIRDYA WIRDYB RDY sio DMA Figure 11. Typical Z80 Environment . INTERNAL STRUCTURE The internal structure of the device includes a Z80 CPU interface, internal control and interrupt logic, and two full-duplex channels. Each channel contains its own set of control and status (write and read) registers, and control and status logic that provides the interface to modems or other external devices. The registers for each channel are designated as follows: WRO-WR7 Write Registers 0 through 7 RRO-RR2 Read Registers 0 through 2 The register group includes five 8-bit control registers, two sync-character registers and two status registers. The interrupt vector is written into an additional 8-bit register (Write Register 2) in Channel B that may be read through another 8-bit register (Read Register 2) in Channel B. The bit assignment and functional grouping of each register is configured to simplify and organize the programming process. Table 1 lists the functions assigned to each read or write register. The logic for both channels provides formats, synchronization, and validation for data transferred to and from the channel interface. The modem control inputs, Clear To Send (CTS) and Data Carrier Detect (DCD), are Table 1. Register Functions Read Register Functions RRO RR1 RR2 Transmit/Receive buffer status, interrupt status and external status Special Receive Condition status Modified interrupt vector (Channel B only) Write Register Functions WRO WAR WR2 WR3 WwR4 WR5 WR6 WR7 Register pointers, CRC initialize, and initialization commands for the various modes. Transmit/Receive interrupt and data transfer mode definition. Interrupt vector (Channel B only) Receive parameters and control Transmit/Receive miscellaneous parameters and modes Transmit parameters and controls Sync character or SOLC address field Sync character or SDLC flag 107monitored by the external control and status logic under program control. All external control-and-status-logic signals are general-purpose in nature and can be used for functions other than modem control. Data Path. The transmit and receive data path illustrated for Channel A in Figure 12 is identical for both channels. The receiver has three 8-bit buffer registers in a FIFO arrangement, in addition to the 8-bit receive shift register. This scheme creates additional time for the CPU to service an interrupt at the beginning of a block of high-speed data. Incoming data is routed through one of several paths (data or CRC) depending on the selected mode andin asynchronous modesthe character length. The transmitter has an 8-bit transmit data buffer register that is loaded from the internal data bus, and a 20-bit transmit shift register that can be loaded from the sync-character buffers or from the transmit data register. Depending on the Operational mode, outgoing data is routed through one of four main paths before it is transmitted from the Transmit Data output (TxD). CPU YO us TO CHANNEL B, EXTERNAL STATUS LOGIC, WITERMAL DATA BUS it if gl wa? wre RECEIVE RECEIVE sync atasster | syne DATA DATA EAROR ae 4 -e-- 4 FIFO fifo 7 | 20-0KT TRANSMIT SHIFT REGISTER hl ASYNC sve DATA TRANSMIT _ RECEIVE RECEIVE SDLC SAULTIPLEXER fe TDA FECA e} clock ERROR DATA & 2.017 DELAY Loic HUNT MODE (BISYNC) Loaic ZERO INSERT c @ bir) SYNC ! SDLC-CAC onc RECEIVE ter SYNC REGISTER AxDA T oeLay & ZEAO DELETE seme wwe cnc TRANSAT a GENERATOR clock Logic ASYNC DATA cac CRC DELAY REGISTER @ errs) cac CHECKER = [CAC RESULT SOLC-CAC Figure 12. Transmit and Receive Data Path (Channel! A) 108PROGRAMMING The system program first issues a series of commands that initialize the basic mode of operation and then issues other commands that qualify conditions within the selected mode. For example, the asynchronous mode, character length, clock rate, number of stop bits, even or odd parity might be set first; then the interrupt mode; and finally, receiver or transmitter enable. Both channels contain registers that must be programmed via the system program prior to operation. The channel- select input (B/A) and the control/data (C/D) are the command-structure addressing controls, and are normally controlled by the CPU address bus. Figures 15 and 16 illustrate the timing relationships for programming the write registers and transferring data and status. Read Registers. The SiO contains three read registers for Channel B and two read registers for Channel A (RRO-RR2 in Figure 13) that can be read to obtain the status information; RR2 contains the internally-modifiable interrupt vector and is only in the Channel B register set. The status information includes error conditions, interrupt vector, and standard communications-intertace signals. To read the contents of a selected read register other than RRO, the system program must first write the pointer byte to WRO in exactly the same way as a write register operation. Then, by executing a read instruction, the contents of the addressed read register can be read by the CPU. The status bits of RRO and RR1 are carefully grouped to simplify status monitoring. For example, when the interrupt vector indicates that a Special Receive Condition interrupt has occurred, all the appropriate error bits can be read from a single register (RR1). Write Registers. The SIO contains eight write registers for Channel B and seven write registers for Channel A (WRO-WR7 in Figure 14) that are programmed separately to configure the functional personality of the channels; WR2 contains the interrupt vector for both channels and is only in the Channel B register set. With the exception of WRO, programming the write registers requires two bytes. The first byte is to WRO and contains three bits (Dg-Dz2) that point to the selected register; the second byte is the actual contro! word that is written into the register to configure the SIO. WRO is a special case in that all of the basic commands can be written to it with a single byte. Reset (internal or external) initializes the pointer bits Dp-D2 to point to WRO. This implies that a channel reset must not be combined with the.pointing to any register. REAO REGISTER O Rx CHARACTER AVAILABLE INT PENDING (CH. A ONLY) Tx BUFFER EMPTY oco SYNC/HUNT cts * Tx UNDER 1 BREAK/ABORT * Used With Externai/Status Interrupt Modes. i READ REGISTER 1f ALL SENT I FIELD BITS 1 FIELD BITS IN IN PREVIOUS SECOND PREVIOUS 8 6 O4u-~00440 Ouanuncoe wacoeooo aeannunaws m * PARITY ERROR Rx OVERRUN ERROR CRCIFRAMING ERROR ENDO OF FRAME (SOLC) e-~ouo4~oe- * Residue data for eight Ax bits/character programmed TUsed with special receive condition mode READ REGISTER 2 (Channel B only) vo vit vat INTERRUPT va VECTOR vs v6 vi 4 tVariable if Status Affects Vector is programmed Figure 13. Read Register Bit Functions 109=sco WRITE REGISTER O onc aaa 20000 ~O-a4040 = I o o 1 1 0 o 1 1 aa ecooo a2=co-+00 -eno+-0-0 NULL CODE REGISTER 0 REGISTER 1 REGISTER 2 REGISTER 3 REGISTER 4 REGISTER 5 REGISTER 6 REGISTER 7 NULL CODE SEND ABORT (SDLC) RESET EXTISTATUS INTERRUPTS CHANNEL RESET ENABLE INT ON NEXT Rx CHARACTER RESET TxINT PENDING ERROR RESET RETURN FROM INT (CH-A ONLY) RESET Rx CRC CHECKER RESET Tx CRC GENERATOR RESET Tx UNDERRUN/EOM LATCH WRITE REGISTER 1 | Tx INT ENABLE STATUS AFFECTS VECTOR - aace 2 VECTOR) EXT INT ENABLE (CH. B ONLY) Rx INT DISABLE 1 Rx INT ON FIRST CHARACTER 0 INT ON ALL Rx CHARACTERS (PARITY AFFECTS VECTOR) 1 INT ON ALL Rx CHARACTERS (PARITY DOES NOT AFFECT WAITIREADY ENABLE * Or on special condition WRITE REGISTER 2 (Channet 8 only) cE 4200 WRITE REGISTER 3 =ou0 INTERRUPT VECTOR Rx ENABLE SYNC CHARACTER LOAD INHIBIT ADDRESS SEARCH MODE {SDLC) Rx CRC ENABLE ENTER HUNT PHASE AUTO ENABLES Rx 5 BITSICHARACTER Rx 7 BITSICHARACTER Rx 6 BITSICHARACTER Rx 8 BITSICHARACTER * WRITE REGISTER 4 | Larry ENABLE _ PARITY EVEN/IOOD SYNC MODES ENABLE 1 STOP BITICHARACTER 1% STOP BITSICHARACTER 2 STOP BITS/ICHARACTEA +400 sono 8 BIT SYNC CHARACTER 16 BIT SYNC CHARACTER SOLC MODE (01111110 FLAG) EXTERNAL SYNC MOOE a=s0cc0 sono X1 CLOCK MODE X16 CLOCK MODE X32 CLOCK MODE X64 CLOCK MODE a400 =eu0 WRITE REGISTER 5 Tx CRC ENABLE ITS I SDLCICRC-16 Tx ENABLE SENO BREAK 0 1 0 1 Tx 5 BITS (OR LESSVCHARACTER Tx 7 BITSICRARACTER Tx 6 BITSICHARACTER Tx 8 BITSICHARACTER ws400 OTR WRITE REGISTER 6 SYNC BIT 0 SYNC BIT 1 SYNC BIT 2 sync BIT3 \ SYNC BIT 4 SYNC BIT 5 SYNC BIT 6 SYNC BIT 7 E *Also SDLC address field WRITE REGISTER 7 SYNC BIT 6 SYNC BIT 9 SYNC BIT 10 SYNC BIT11 \, SYNC BIT 12 SYNC BIT 13 SYNC BIT 14 SYNC BIT 15 : *For SOLC it must be programmed to "01111110" for flag recognition Figure 14. Write Register Bit Functions 110TIMING The SiO must have the same clock as the CPU (same phase and frequency relationship, not necessarily the same driver). Read Cycle. The timing signals generated by a Z80 CPU input instruction to read a data or status byte from the SIO are illustrated in Figure 15. Write Cycle. Figure 16 illustrates the timing and data signals generated by aZ80 CPU output instruction to write a data or control byte into the SIO. Interrupt-Acknowledge Cycle. After receiving an interrupt-request signal from an SIO (INT pulled Low), the Z80 CPU sends an interrupt-acknowledge sequence, M1 Low and |ORQ Low, a few cycles later (Figure 17). The SIO contains an internal daisy-chained interrupt structure for prioritizing nested interrupts for the various functions of its two channels, and this structure can be used within an external user-defined daisy chain that prioritizes several peripheral circuits. The IEI of the highest-priority device is terminated High. A device that has an interrupt pending or under service forces its IEO Low. For devices with no interrupt pending or under service, [EO =IEl. To insure stable conditions in the daisy chain, all interrupt status signals are prevented from changing while M1 is Low. When IORQ is Low, the highest priority interrupt requestor v T Tw % 1 SE, C10, BK a @ | x. iona | f aD | f/f mi DA { \ TA 4 our } Figure 15. Read Cycle % % Tw Ts ty KL fo mi DATA iN, Figure 16. Write Cycle (the one with IE! High) places its interrupt vector on the data bus and sets its internal interrupt-under-service latch. Return From Interrupt Cycle. Figure 18 illustrates the return from interrupt cycle. Normally, the Z80 CPU issues a Return From Interrupt (RETI) instruction at the end of an interrupt service routine. RET! is a 2-byte opcode (ED-4D) that resets the interrupt-under-service latch in the SIO to terminate the interrupt that has just been processed. This is accomplished by manipulating the daisy chain in the following way. The normal daisy-chain operation can be used to detect a pending interrupt; however, it cannot distinguish between an interrupt under service and a pending unacknowledged interrupt of a higher priority. Whenever ED is decoded, the daisy chain is modified by forcing High the 1EO of any interrupt that has not yet been acknowledged. Thus the daisy chain identifies the device presently under service as the only one with an IEI High and an [EO Low. If the next opcode byte is 4D, the interrupt-under-service latch is reset. The ripple time of the interrupt daisy chain (both the High-to-Low and the Low-to-High transitions) lirnits the number of devices that can be placed in the daisy chain. Ripple time can be improved with carry-look-ahead, or by extending the interrupt-acknowledge cycle. For further information about techniques for increasing the number of daisy-chained devices, refer to the Z8400 Z80 CPU Product Specification (00-2001-04). A th Tw Tw T Ts Figure 17. Interrupt Acknowledge Cycle Ty To 3 Te Ty Tr Tr Te Ty e\ YS \ ST DoD? lay _fay ! Nee / ec rs { ------ / | | | ra Figure 18. Return from Interrupt Cycle 111ABSOLUTE MAXIMUM RATINGS Voltages in Voc with respect toVsg ..... . -0.3V to +0.7V Voltages on all inputs with respect toVeg 2 eee eee 0.3V to Voc + 0.3V Storage Temperature.............. ~65C to + 150C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only: operation of the device at any condition above these indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. STANDARD TEST CONDITIONS The characteristics below apply for the following test conditions, unless otherwise noted. All voltages are referenced to GND (OV). Positive current flows into the referenced pin. Available operating temperature range is: S=0C to +70C, V., Range NMOS: +4.75V < Voc +5.25V CMOS: +4.50V < V,,. < +5.50V E = -40C to 100C, =4.50V < Voc s +5.50V 2.1K FROM OUTPUT UNDER TEST | $8 112DC CHARACTERISTICS Z84C40 CMOS Z80 SIO, Z84C40/41/42/43/44 DC CHARACTERISTICS Voc=5.0V + 10%, unless otherwise specified Symbol Parameter Min Max Typ Unit Condition Vac Clock input Low Voltage -0.3 +0.45 V Ve Clock Input High Voitage Voc-0-6 -V,,+0.3 V Vai Input High Voltage 2.2 Vee Vv Vu Input Low Voltage -0.3 0.8 Vv Vo Output Low Voltage 0.4 Vv I o=2-OMA Vout Output High Voltage 2.4 Vv l= 1 .6MA Vow Output High Voltage Vo_-0.8 V lg4=-250pA ly input Leakage Current -10 10 pA V,,=0.4V to V,, lo 3-state Output Leakage Current in Float -10 10 pA Vour=0.4V to Vi, (SY) SYNC Pin Leakage Current -40 10 pA loc Power Supply Current - 4MHz 10{1]) 7 mA Vog=5V - 6MHz 10[1] 7 mA CLK=4,6,8, 10MHz - 8MHz 12(1] 8 mA Ve=Voc0-2V - 10MHz is{i] 8 mA V, =0.2V loc Standby Supply Current 10 pA Vog=5V CLK=(0) Ve Veg-0-2V V, =0.2V Note: [1] Measurements made with outputs floating. CAPACITANCE Symbol Parameter Min Max Unit Cc Clock Capacitance 7 pf Cin Input Capacitance 5 pf Cout Output Capacitance 10 pf Over specified temperature range; f = 1 MHz. Unmeasured pins returned to ground. 113AC CHARACTERISTICS* 284C40/41/42/43/44 AC CHARACTERISTICS . Z84C4X04* Z84C4X06 284C4X08 284C4X10 = Note No Symbol Parameter Min Max Min Max Min Max Min Max 1 TcC Clock Cycle Time 250 DC 162 DC 125 DC 100 =6DC 2 Twoh Clock Pulse Width (High) 105 DC 65 DC 5 DC 42 DC 3 TIC Clock Fall Time 30 20 10 10 4 Tr Clock Rise Time 30 20 10 10 5 Twel Clock Pulse Width (Low) 105 DC 65 DC 55 DC 42 DC 6 TsAD ICE,B//A,C//D to Clock 145 60 40 35 Rise Setup Time 7 TsCS(C) AORQ, /RD to Clock Rise 115 60 40 35 8 TdC(DO) Clock Rise to Data Out 220 150 100 85 Delay 9 TsDI(C) Data In to Clock Rise 50 30 20 20 Setup Time (Write or (Mi Cycle) 10 TdRD(DOz) /RD Rise to Data Out 110 90 75 65 Float Delay 11 TdiIO(DOl) ORO Fall to Data Out 160 120 90 80 Delay (ANTACK Cycle) 12 TsM1(C) /M1 to Clock Rise Setup 90 75 55 40 Time 13 TsIEI(iO) IEI to JORG Fall Setup 140 120 80 60 Time (ANTACK Cycle) 14 TdMi(IEO) M1 Fall to IEO Fall Delay 190 160 130 100 (Interrupt Before /M1) 15 TdIEKIEOr) II Rise to IEO Rise Detay 100 70 60 50 (After ED Decode) 16 TdIEKIEOF) /M1 Fall to 1EO Fall Delay 100 70 60 50 17 TdC(INT) Clock Rise to /INT 200 150 120 100 Fall Delay 18 TdiO(WRWE) /IORQ or /CE Fall to 210 175 130 110 /WIRDY Delay (Wait Mode) 19 TdC(W/RR) Clock Rise to (W//RDY 120 100 90 85 Delay (Ready Mode) , 20 TdC(W/RWz) Clock Falt to W//RDY 130 110 90 80 Float Delay (Wait Mode) When Setup is Specified 21 Th Any Unspecified Hold 0 0 0 0 Note: * Units in nanoseconds (nS). * 4 MHz 84C4x is obsoleted and replaced by 6 MHz. 114AC CHARACTERISTICS TIMING cLUxK io WmRDY (Z84C4X CMOS Z80 SiO) 115AC CHARACTERISTICS TIMING (Z84C4X CMOS Z80 SIO; Continued) EFS, DCD, SYNC \ J KA int Axc int 116AC CHARACTERISTICS (Z84c4x CMOS Z80 SIO; Continued) 284C40/41/42/43/44 AC CHARACTERISTICS ZB4C4X04" ZB4C4X06 284C4X08 Z84C4X10 Note No Symbol Parameter Min Max Min Max Min Max Min Max 1 TwPh Pulse Width (High) 200 200 150 150 (2} 2 TwPl Pulse Width (Low) 200 200 150 150 [2] 3. TcTxC /TxG Cycle Time 400 330 250 200 {2} 4 TwTxCl [Tx Width (Low) 180 100 85 80 (2] 5 TwIxCh {TxC Width (High) 180 100 85 80 [2] 6 TdTxC(TxD) /TxC Falt to TxD Delay 300 220 160 120 (2] 7 = TdTxC(W/RRf) /TxC Fall to W//RDY 5 9 5 9 5 9 5 9 {1] Fall Delay (Ready Mode) 8 TdTxC(INT) {TxC Fall to ANT Fali Delay 5 9 5 9 5 9 5 9 {1] 9 TeRxC /RxC Cycle Time 400 330 250 200 {2] 10 TwRxCl /RxC Width (Low) 180 100 85 80 [2] 11. TwRxCh IRxC Width (High) 180 100 85 80 {2] 12 TsRxD(RxC) RxD to /RxC Setup Time 0 0 0 0 {2] (X1 Mode) 13. ThAxD(RxC) /RxC Rise to RxD Hold 140 100 80 60 (2] Time (X1 Mode) 14 TdRxC(W/RRf) /RxC Rise to W//RDY Fall 10 13 10. 13 10 13 10 613 [1] Delay (Ready Mode) 15 TdRxC(INT) /RxC Rise to ANT Fall Delay 10 13 10 13 10 13 10 13 (1] 16 TdRxC(SYNC) /RxC Rise to /SYNC Fall 4 7 4 7 4 7 7 (1] Delay (Output Modes) 17 TSSYNC(RxC) /SYNC Fall to /RxC -100 -100 -100 -100 {2] Rise Setup (External Sync Modes) * In All Modes, the System Clock rate must be at least five times the maximum data rate. JRESET must be active a minimum of one complete clock cycle. Notes: [1] Units equal to System Clock Periods. [2] Units in nanoseconds (nS). * 4 MHz 84C4x is obsoleted and replaced by 6 MHz. 117DC CHARACTERISTICS (Z844x / NMOS Z80 SIO) Symbol Parameter Min Max Unit Test Condition ViLC Clock Input Low Voltage -0.3 +0.45 Vv VHC Clock Input High Voltage Veco - 0.6 Voc + 0.3 V Vit Input Low Voltage -0.3 +0.8 Vv Vin Input High Voltage +2.0 Voc Vv VoL Output Low Voltage +0.4 Vv Von, Output High Voltage +24 V fo. = 2.0mMA VOH2 Output High Voitage Vv loH = 250 pA toy Input Leakage Current +10 pA Vin = 0.4 to Voc llo 3-State Output Leakage Current in Float +10 pA Vout = 0.4 to Voc ILisyy SYNC Pin Leakage Current +10/- 40 pA 0<Vin<Voc ICC, Power Supply Current 100 mA Over specified temperature and voltage range. CAPACITANCE Symbol Parameter Min Unit Cc Clock Capacitance pt Cin Input Capacitance pf Court Output Capacitance pf Over specified temperature range; f = 1 MHz. Unmeasured pins returned to ground. 118AC CHARACTERISTICS* (2844x / NMOS Z80 SIO) Z0844X04 Z0844X06 Number Symbol Parameter Min Max Min Max 1 TC Clock Cycle Time 250 4000 162 4000 2 Wh Clock Width (High) 105 2000 70 2000 3. Tt Clock Fail Time 30 15 4 TC Clock Rise Time 30 15 5 Wo Clock Width (Low) 105 2000 70 2000 6 _TsAD{C) CE, C/O. B/A to Clock t Setup Time 145 60 7 ~~ TsCS(C) TORQ, RD to Clock t Setup Time 115 60 8 TdC(D0) Clock t to Data Out Delay 220 150 9 TsDKC) Data In to Clock t Setup (Write or Mi Cycle) 50 30 10 TdRO(OOz) RO tto Data Out Float Delay 110 90 11 TdIQ(OO!) ~~ IORO 4 to Data Out Delay (INTACK Cycle) 160 120 12. TsM1(C) M1 to Clock t Setup Time 90 78 13. TsIEKIO) IE to IORG # Setup Time (INTACK Cycle) 140 120 14. TdM1(1EO) M1 4 to EO $ Delay (interrupt before M1) 190 160 15 TalENIEOr) ~IEI ttoIEO t Delay (ater ED decode) 100 70 16 TdIEKIEO)~IEI 4 to 1EO 4 Delay 100 70 17 TaC(INT) Clock t to INT Delay 200 150 18 TdlQ(w/RW!) IGRO 4 or CE 4 10 WiRDY + Delay (Wait Mode) 210 175 19 TdC(W/RR) Clock tto W/ADY 4 Delay (Ready Mode) 120 100 20 TAC(WIRWz) Clock 4 to W/ADY Float Delay (Wait Mode) 130 110 21) Th Any unspecified Hold when Setup is specified 0 0 *Units in nanoseconds (ns). 119AC CHARACTERISTICS TIMING (Z844X/ NMOS Z80 SIO; Continued) _ TxD WiRoY - Ax winDy SYNC 120AC CHARACTERISTICS TIMING (2844X / NMOS 280 SIO) cUK CE, Cid, BA {co aT 121AC CHARACTERISTICS (Z644X/ NMOS Z80 SIO; Continued) 20844X04 Z0844X06 No. Symbol Parameter Min Max Min Max Notes 1 TwPh Pulse Width (High) 200 200 2 2 Twi Pulse Width (Low) 200 200 2 3 TeTxc THE Cycle Time 400 330. & 2 4 TwTxcl TxC Width (Low) 180 100 @ 2 5 TwTxCh TxC Width (High) 180 100 2 6 TdTxC(TxD) Txt L to TxD Delay 300 220 0~C 2 7 TdTxC(W/RRA) TxC 1 to W/ADY J Delay (Ready Mode) 5 9 5 9 1 8 = TdTxC(INT) Tx 1 to INT | Delay 5 9 5 9 1 9 TeRxC FxC Cycle Time . 400 = 330 2 10 TwRxcl Fx Width (Low) 180 100 @ 2 11 TwRxCh | "FE Width (High) 180 100 o 2 12 TsRxO(RxC) RxD to FxCTSetup Time (x1 Mode) 0 0 2 13 ThRxXD(AxC) = Ax T RxD Hold Time (x1 Mode) 140 100 2 14 TdAxC(W/RR{) Fxt T to WARDY J Delay (Ready Mode) 10 13 10 13 1 15 TdRxC(INT) . RKC Tto INT | Delay 10 #13 #10 )~=#(43 1 16 TdRxC{SYNC) AxC T to SYNC J Delay (Output Modes) 4 7 4 7 1 17 TsSYNC(RxC) SYNT J to Fixt T Setup (Extemal Syne Modes) -100 =100 2 in all modes, the System Clock rate must be at least five timies the maximum data rate. RESET must be active a minimum of one complete clock cycle. 1. Units equal to System Clock Periods. 2. Units in nanoseconds (ns). 122