S1C88409
13
●Analog Circuit Characteristics and Current Consumption
Characteristic
SVD voltage
SVD circuit response time
Power current
Low-power mode
VD1C1="0", VD1C0="1"
Power current
Normal mode
VD1C1="0", VD1C0="0"
Power current
High-speed mode 1
VD1C1="1", VD1C0="0"
Power current
High-speed mode 2
VD1C1="1", VD1C0="1"
SVD circuit current
OSC1 CR oscillation current
(Unless otherwise specified: VDD=1.8 to 5.5V, VSS=0V, Ta=25°C, OSC1=32.768kHz crystal oscillation, OSC3=external clock input)
Symbol
VSVD
t
SVD
IDD1
IDD2
IDD3
IDD4
IDD1
IDD2
IDD3
IDD4
IDD1
IDD2
IDD3
IDD4
IDD1
IDD2
IDD3
IDD4
ISVDN
ICR1
Unit
V
V
V
µs
µA
µA
µA
mA
µA
µA
µA
mA
µA
µA
µA
mA
µA
µA
µA
mA
µA
µA
Note
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
5
6
Max.
3.75
3.05
2.1
100
1.0
5.0
20.0
0.5
1.5
7.0
25.0
0.7
2.0
12.0
35.0
1.0
3.0
20.0
50.0
1.4
15
50
Typ.
3.4
2.8
1.9
0.45
1.8
9.0
0.3
0.55
3.0
14.0
0.45
0.65
5.0
21.0
0.65
0.75
9.0
32.0
0.9
7
20
Min.
3.05
2.55
1.7
Condition
SVD1="1", SVD0=X
SVD1="0", SVD0="1"
SVD1="0", SVD0="0"
In SLEEP status
In HALT status
CPU is in operating (32.768 kHz)
CPU is in operating (1 MHz)
In SLEEP status
In HALT status
CPU is in operating (32.768 kHz)
CPU is in operating (1 MHz)
In SLEEP status
In HALT status
CPU is in operating (32.768 kHz)
CPU is in operating (1 MHz)
In SLEEP status
In HALT status
CPU is in operating (32.768 kHz)
CPU is in operating (1 MHz)
VDD=5.0 V
RCR=1.5MΩ, normal mode
Note) 1.
2.
3.
4.
5.
6.
OSC1: Stop OSC3: Stop CPU, ROM, RAM: Stop Clock Timer: Stop SVD: Off Others: Stop
OSC1: On OSC3: Stop CPU, ROM, RAM: Stop Clock Timer: Run SVD: Off Others: Stop
OSC1: On OSC3: Stop CPU, ROM, RAM: Run Clock Timer: Run SVD: Off Others: Stop
OSC1: On OSC3: On CPU, ROM, RAM: Run Clock Timer: Run SVD: Off Others: Stop
OSC1: On OSC3: Stop CPU, ROM, RAM: Stop Clock Timer: Run SVD: On Others: Stop
When the OSC1 CR oscillation circuit is selected by mask option.
●AC Characteristics
External memory access
• Read cycle
Item
Address set-up time in read cycle
Address hold time in read cycle
Read signal pulse width
Data input set-up time in read cycle
Data input hold time in read cycle
Address set-up time in read cycle
Address hold time in read cycle
Read signal pulse width
Data input set-up time in read cycle
Data input hold time in read cycle
Address set-up time in read cycle
Address hold time in read cycle
Read signal pulse width
Data input set-up time in read cycle
Data input hold time in read cycle
Address set-up time in read cycle
Address hold time in read cycle
Read signal pulse width
Data input set-up time in read cycle
Data input hold time in read cycle
Note) 1.
Symbol
tras
trah
trp
trds
trdh
tras
trah
trp
trds
trdh
tras
trah
trp
trds
trdh
tras
trah
trp
trds
trdh
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
1
1
1
1
1
1
1
Max.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min.
t
c+
t
l-200+n∗
t
c/2
t
h-160
t
c-40+n∗
t
c/2
600
0
t
c+
t
l-100+n∗
t
c/2
t
h-80
t
c-20+n∗
t
c/2
300
0
t
c+
t
l-50+n∗
t
c/2
t
h-40
t
c-10+n∗
t
c/2
150
0
t
c+
t
l-50+n∗
t
c/2
t
h-40
t
c-10+n∗
t
c/2
150
0
Substitute the number of states for wait insertion in n.
t
c=input clock cycle time,
t
h=input clock H pulse width,
t
l=input clock L pulse width
Condition
V
DD
=1.8 to 5.5 V
V
D1
=1.6 V
V
DD
=2.6 to 5.5 V
V
D1
=2.4 V
V
DD
=3.5 to 5.5 V
V
D1
=3.2 V
V
DD
=4.5 to 5.5 V
V
D1
=4.2 V
(Unless otherwise specified: V
DD
=5.5V, V
SS
=0V, f
OSC1
=32.768kHz, f
OSC3
=1.0MHz, Ta=-20 to 70°C, C
L
=100 pF,
V
IH
=0.8V
DD
, V
IL
=0.2V
DD
, V
OH
=0.8V
DD
, V
OL
=0.2V
DD
)