PF952-02 S1C88409 8-bit Single Chip Microcomputer ge oltan V o Lowerati ts p c u O od Pr Original Architecture Core CPU Low Current Consumption Wide-range Operating Voltage (1.8V to 5.5V) High Speed Operation in Low Voltage A/D Converter DESCRIPTION The S1C88409 is a single chip microcomputer which consists of a CMOS 8-bit core CPU S1C88 (MODEL3), 8KB ROM, 3.75KB RAM, dot-matrix LCD controller, 3 types of timers/counters, serial interface (IR input/output function is available), touch panel controller, A/D converter and D/A converter. The S1C88409 operates faster even with low supply voltage, and is most suitable for various application equipment such as information terminals needing low power operation. Furthermore, the S1C88409 can control up to 4M x 3 bytes of memory with the 22-bit outside address bus and 3-bit chip enable signals, therefore it can also be applied to systems such as electronic dictionaries and organizers. FEATURES Core CPU .............................................. CMOS 8-bit core CPU S1C88 (MODEL3) OSC1 oscillation circuit ......................... Crystal oscillation circuit/CR oscillation circuit/external clock input 32.768 kHz (Typ.) OSC3 oscillation circuit ......................... Crystal oscillation circuit/ceramic oscillation circuit/CR oscillation circuit/external clock input 8 MHz (Max.) Instruction set ........................................ Basic instruction: 54 types, Total: 608 types (multiplication/division instructions are usable) Addressing mode: 12 types Min. instruction execution time ............. 0.25 sec/8 MHz (2 clocks) Internal ROM capacity .......................... 8K bytes Internal RAM capacity ........................... 3.75K bytes (display memory is included; data/display memory size can be set by mask option) Bus line ................................................. Address bus: Data bus: CE signal: WR signal: RD signal: 22 bits 8 bits 3 bits 1 bit 1 bit (usable as general output port or I/O port when it is not used as a bus signal) Input port ............................................... 12 bits * 2 bits are usable for event counter input Output port ............................................ 30 bits * They are used as address bus and bus control signals when external bus is set * Usable for clock output and buzzer output I/O port .................................................. 28 bits * 8 bits are used as data bus when external bus is set * Usable for serial interface input/output, A/D converter input, D/A converter output and touch panel output Serial interface ...................................... 1 channel * Clock synchronous mode/asynchronous mode selectable * Usable as IrDA interface 1 S1C88409 16-bit programmable timer .................... 1 channel * Usable for 16 bits x 1 channel or 8 bits x 2 channels * Usable as event counter 8-bit programmable timer ...................... 1 channel * Usable as baud rate generator for serial interface Clock timer ............................................ 1 channel * Generating 1 sec signal with 32 kHz oscillation * 60S counter available LCD controller ....................................... Dot-matrix type * B&W or 4 gray scale display * A 240 x 100 dot LCD panel can be driven with external drivers (S1D16305 or S1D16700, S1D16006 or S1D15700) * Scroll function available Touch panel controller .......................... Supports pressure sensitive and resistive membrane type analog touch panels A/D converter ........................................ Resolution 10 bits (input: 8 channels) D/A converter ........................................ Resolution 8 bits (output: 2 channels) Sound generator ................................... Equipped with envelope and volume control functions Supply voltage detection (SVD) ............ Possible to detect 3 voltage levels Watchdog timer ..................................... Possible to generate NMI Interrupt ................................................. External: Input interrupt Internal: 16-bit programmable timer interrupt 8-bit programmable timer interrupt Clock timer interrupt Watchdog timer interrupt Serial interface interrupt LCD controller interrupt Touch panel interrupt A/D converter interrupt 2 systems (5 types) 2 systems (4 types) 1 system (1 type) 1 system (5 types) 1 system (1 type) 1 system (3 types) 1 system (1 type) 1 system (2 types) 1 system (1 type) Supply voltage ...................................... 1.8 V to 5.5 V (operating frequency Max. 1.1 MHz) 2.6 V to 5.5 V (operating frequency Max. 4.4 MHz) 3.5 V to 5.5 V (operating frequency Max. 6.6 MHz) 4.5 V to 5.5 V (operating frequency Max. 8.8 MHz) Current consumption ............................ SLEEP HALT (32 KHz) Run (32 KHz) Run (4 MHz) Run (8 MHz) 0.6 A Typ. (at 3.0 V) 3.0 A Typ. (at 3.0 V) 15 A Typ. (at 3.0 V) 2 mA Typ. (at 3.0 V) 9 mA Typ. (at 5.0 V) Supply form ........................................... QFP15-100pin or chip 2 (Normal mode) (Normal mode) (Normal mode) (Normal mode) (High speed mode) S1C88409 BLOCK DIAGRAM VDD VSS Core CPU S1C88 OSC1, OSC3 OSC2, OSC4 Oscillator (FOUT3) (FOUT1) Prescaler Interrupt Controller Serial Interface (Synchronous/Asynchronous/IrDA) (SIN/IRI, SOUT/IRO) (SCLK, SRDY) LCDEN, DOFF XSCL, LP, YD, FR SD0-SD7 VD1 Voltage Regulator LCD Controller MCU/MPU System Controller Supply Voltage Detector Reset/Test External Memory Interface 16-bit Programmable Timer Input Port K00-K07 K10-K13 Output Port R00-R07 R10-R17 R20-R27 R30-R32 R40-R42 I/O Port P00-P07 P10-P17 P20-P23 P30-P37 RESET TEST (TOUT0) (TOUT1) 8-bit Programmable Timer (A0-A21) (D0-D7) (RD, WR, CE0-CE2) Clock Timer Watchdog Timer (BZ) (BYH, BYL) (BXH, BXL) Sound Generator A/D Converter Touch Panel Controller D/A Converter RAM 3.75K-byte (Data RAM, Display RAM) (AD0-AD7) AVDD AGND AVSS AVREF (DA0, DA1) ROM 8K-byte The terminals that are shown in ( ) are shared with Pxx or Rxx terminals. 3 (TOUT1/FOUT1) R41 (BZ) R42 (SIN) P10 (SOUT) P11 (SCLK) P12 (SRDY) P13 (SIN/IRI) P14 (SOUT/IRO) P15 (SCLK) P16 (SRDY) P17 (BYH) P20 (BYL) P21 (BXH) P22 (BXL) P23 TEST (AD7/DA1) P37 (AD6/DA0) P36 (AD5) P35 (AD4) P34 (AD3) P33 (AD2) P32 (AD1) P31 (AD0) P30 AVDD AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 R02 R01 R00 P07 P06 P05 P04 P03 P02 P01 P00 RESET K13 K12 K11 (EXCL11) K10 (EXCL00) K07 K06 K05 K04 K03 K02 K01 K00 MCU/MPU S1C88409 PIN CONFIGURATION * Pin layout for single chip mode (initial setting) R03 R04 R05 R06 R07 R10 R11 R12 R13 R14 R15 R16 R17 R20 R21 R22 R23 R24 R25 R26 R27 R30 R31 R32 (TOUT0/FOUT3) R40 4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 S1C88409 INDEX 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS OSC1 OSC2 VD1 OSC3 OSC4 VDD LCDEN DOFF YD FR XSCL LP SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 N.C. N.C. AGND AVREF S1C88409 Pin name VDD VSS VD1 AVDD AGND AVSS AVREF OSC1 OSC2 OSC3 OSC4 MCU/MPU K00~K07 K10 (EXCL00) K11 (EXCL01) K12~K13 R00~R07 R10~R17 R20~R27 R30~R32 R40 (TOUT0/FOUT3) R41 (TOUT1/FOUT1) R42 (BZ) P00~P07 P10 (SIN) P11 (SOUT) P12 (SCLK) P13 (SRDY) P14 (SIN/IRI) P15 (SOUT/IRO) P16 (SCLK) P17 (SRDY) P20 (BYH) P21 (BYL) P22 (BXH) P23 (BXL) P30~P35 (AD0~AD5) P36, P37(AD6/DA0, AD7/DA1) LCDEN DOFF YD FR XSCL LP SD0~SD7 RESET TEST Pin No. 44 50 47 24 27 25 26 49 48 46 45 51 52~59 60 61 62~63 73~80 81~88 89~96 97~99 100 1 2 65~72 3 4 5 6 7 8 9 10 11 12 13 14 23~18 17,16 43 42 41 40 39 38 37~30 64 15 I/O - - O - - - I I O I O I I I I I O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O I I Function Power supply (+) pin Power supply (GND) pin Voltage regulator output pin Power supply (+) pin for analog circuit system GND pin for analog circuit system Power supply (GND) pin for analog circuit system Reference voltage input pin for analog circuit system OSC1 oscillation input pin (32 kHz crystal, CR oscillation, external clock input) OSC1 oscillation output pin OSC3 oscillation input pin (crystal/ceramic, CR oscillation, external clock input) OSC3 oscillation output pin MCU/MPU mode setting pin*1 Input port pin Input port pin or external clock input pin for event counter (Timer 0) Input port pin or external clock input pin for event counter (Timer 1) Input port pin Output port pin Output port pin Output port pin Output port pin Output port pin or TOUT0/FOUT3 clock output pin Output port pin or TOUT1/FOUT1 clock output pin Output port pin or buzzer signal output pin I/O port pin I/O port pin or serial I/F data input pin I/O port pin or serial I/F data output pin I/O port pin or serial I/F clock input/output pin I/O port pin or serial I/F ready signal output pin I/O port pin, serial I/F data input or IR receiver input pin I/O port pin, serial I/F data output or IR transmitter output pin I/O port pin or serial I/F clock input/output pin I/O port pin or serial I/F ready signal output pin I/O port pin or touch panel controller BYH signal output pin I/O port pin or touch panel controller BYL signal output pin I/O port pin or touch panel controller BXH signal output pin I/O port pin or touch panel controller BXL signal output pin I/O port pin or A/D converter analog signal input pin I/O port pin, A/D converter analog signal input pin or D/A converter analog signal output pin LCD controller enable signal output pin LCD controller forced blank signal output pin LCD controller scan start pulse output pin LCD controller frame signal output pin LCD controller shift clock output pin LCD controller latch pulse output pin LCD controller data output pin Initial reset input pin Test input pin*2 1 The MCU/MPU terminal should be connected to VDD. 2 TEST is the terminal used for factory inspection of the IC. For normal operation, be sure to connect the TEST terminal to VDD. 5 (TOUT1/FOUT1) R41 (BZ) R42 (SIN) P10 (SOUT) P11 (SCLK) P12 (SRDY) P13 (SIN/IRI) P14 (SOUT/IRO) P15 (SCLK) P16 (SRDY) P17 (BYH) P20 (BYL) P21 (BXH) P22 (BXL) P23 TEST (AD7/DA1) P37 (AD6/DA0) P36 (AD5) P35 (AD4) P34 (AD3) P33 (AD2) P32 (AD1) P31 (AD0) P30 AVDD AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 RESET K13 K12 K11 (EXCL11) K10 (EXCL00) K07 K06 K05 K04 K03 K02 K01 K00 MCU/MPU S1C88409 * Pin layout for expanded 64K mode (for multi-chip system) A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 R20 R21 R22 R23 R24 R25 RD WR CE0 (CE1) R31 (CE2) R32 (TOUT0/FOUT3) R40 6 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 S1C88409 INDEX 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS OSC1 OSC2 VD1 OSC3 OSC4 VDD LCDEN DOFF YD FR XSCL LP SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 N.C. N.C. AGND AVREF S1C88409 Pin name VDD VSS VD1 AVDD AGND AVSS AVREF OSC1 OSC2 OSC3 OSC4 MCU/MPU K00~K07 K10 (EXCL00) K11 (EXCL01) K12~K13 A00~A15 R20~R25 RD WR CE0 CE1 (R31) CE2 (R32) R40 (TOUT0/FOUT3) R41 (TOUT1/FOUT1) R42 (BZ) D0~D7 P10 (SIN) P11 (SOUT) P12 (SCLK) P13 (SRDY) P14 (SIN/IRI) P15 (SOUT/IRO) P16 (SCLK) P17 (SRDY) P20 (BYH) P21 (BYL) P22 (BXH) P23 (BXL) P30~P35 (AD0~AD5) P36, P37(AD6/DA0, AD7/DA1) LCDEN DOFF YD FR XSCL LP SD0~SD7 RESET TEST Pin No. 44 50 47 24 27 25 26 49 48 46 45 51 52~59 60 61 62~63 73~88 89~94 95 96 97 98 99 100 1 2 65~72 3 4 5 6 7 8 9 10 11 12 13 14 23~18 17,16 43 42 41 40 39 38 37~30 64 15 I/O - - O - - - I I O I O I I I I I O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O I I Function Power supply (+) pin Power supply (GND) pin Voltage regulator output pin Power supply (+) pin for analog circuit system GND pin for analog circuit system Power supply (GND) pin for analog circuit system Reference voltage input pin for analog circuit system OSC1 oscillation input pin (32 kHz crystal, CR oscillation, external clock input) OSC1 oscillation output pin OSC3 oscillation input pin (crystal/ceramic, CR oscillation, external clock input) OSC3 oscillation output pin MCU/MPU mode setting pin Input port pin Input port pin or external clock input pin for event counter (Timer 0) Input port pin or external clock input pin for event counter (Timer 1) Input port pin Address bus Output port pin Read signal output pin Write signal output pin Chip enable signal output pin Chip enable signal output pin or output port pin Chip enable signal output pin or output port pin Output port pin or TOUT0/FOUT3 clock output pin Output port pin or TOUT1/FOUT1 clock output pin Output port pin or buzzer signal output pin Data bus I/O port pin or serial I/F data input pin I/O port pin or serial I/F data output pin I/O port pin or serial I/F clock input/output pin I/O port pin or serial I/F ready signal output pin I/O port pin, serial I/F data input or IR receiver input pin I/O port pin, serial I/F data output or IR transmitter output pin I/O port pin or serial I/F clock input/output pin I/O port pin or serial I/F ready signal output pin I/O port pin or touch panel controller BYH signal output pin I/O port pin or touch panel controller BYL signal output pin I/O port pin or touch panel controller BXH signal output pin I/O port pin or touch panel controller BXL signal output pin I/O port pin or A/D converter analog signal input pin I/O port pin, A/D converter analog signal input pin or D/A converter analog signal output pin LCD controller enable signal output pin LCD controller forced blank signal output pin LCD controller scan start pulse output pin LCD controller frame signal output pin LCD controller shift clock output pin LCD controller latch pulse output pin LCD controller data output pin Initial reset input pin Test input pin*1 1 TEST is the terminal used for factory inspection of the IC. For normal operation, be sure to connect the TEST terminal to VDD. 7 (TOUT1/FOUT1) R41 (BZ) R42 (SIN) P10 (SOUT) P11 (SCLK) P12 (SRDY) P13 (SIN/IRI) P14 (SOUT/IRO) P15 (SCLK) P16 (SRDY) P17 (BYH) P20 (BYL) P21 (BXH) P22 (BXL) P23 TEST (AD7/DA1) P37 (AD6/DA0) P36 (AD5) P35 (AD4) P34 (AD3) P33 (AD2) P32 (AD1) P31 (AD0) P30 AVDD AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 RESET K13 K12 K11 (EXCL11) K10 (EXCL00) K07 K06 K05 K04 K03 K02 K01 K00 MCU/MPU S1C88409 * Pin layout for expanded 4M mode (for multi-chip system) A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 RD WR CE0 (CE1) R31 (CE2) R32 (TOUT0/FOUT3) R40 8 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 S1C88409 INDEX 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS OSC1 OSC2 VD1 OSC3 OSC4 VDD LCDEN DOFF YD FR XSCL LP SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 N.C. N.C. AGND AVREF S1C88409 Pin name VDD VSS VD1 AVDD AGND AVSS AVREF OSC1 OSC2 OSC3 OSC4 MCU/MPU K00~K07 K10 (EXCL00) K11 (EXCL01) K12~K13 A00~A21 RD WR CE0 CE1 (R31) CE2 (R32) R40 (TOUT0/FOUT3) R41 (TOUT1/FOUT1) R42 (BZ) D0~D7 P10 (SIN) P11 (SOUT) P12 (SCLK) P13 (SRDY) P14 (SIN/IRI) P15 (SOUT/IRO) P16 (SCLK) P17 (SRDY) P20 (BYH) P21 (BYL) P22 (BXH) P23 (BXL) P30~P35 (AD0~AD5) P36, P37(AD6/DA0, AD7/DA1) LCDEN DOFF YD FR XSCL LP SD0~SD7 RESET TEST Pin No. 44 50 47 24 27 25 26 49 48 46 45 51 52~59 60 61 62~63 73~94 95 96 97 98 99 100 1 2 65~72 3 4 5 6 7 8 9 10 11 12 13 14 23~18 17,16 43 42 41 40 39 38 37~30 64 15 I/O - - O - - - I I O I O I I I I I O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O I I Function Power supply (+) pin Power supply (GND) pin Voltage regulator output pin Power supply (+) pin for analog circuit system GND pin for analog circuit system Power supply (GND) pin for analog circuit system Reference voltage input pin for analog circuit system OSC1 oscillation input pin (32 kHz crystal, CR oscillation, external clock input) OSC1 oscillation output pin OSC3 oscillation input pin (crystal/ceramic, CR oscillation, external clock input) OSC3 oscillation output pin MCU/MPU mode setting pin Input port pin Input port pin or external clock input pin for event counter (Timer 0) Input port pin or external clock input pin for event counter (Timer 1) Input port pin Address bus Read signal output pin Write signal output pin Chip enable signal output pin Chip enable signal output pin or output port pin Chip enable signal output pin or output port pin Output port pin or TOUT0/FOUT3 clock output pin Output port pin or TOUT1/FOUT1 clock output pin Output port pin or buzzer signal output pin Data bus I/O port pin or serial I/F data input pin I/O port pin or serial I/F data output pin I/O port pin or serial I/F clock input/output pin I/O port pin or serial I/F ready signal output pin I/O port pin, serial I/F data input or IR receiver input pin I/O port pin, serial I/F data output or IR transmitter output pin I/O port pin or serial I/F clock input/output pin I/O port pin or serial I/F ready signal output pin I/O port pin or touch panel controller BYH signal output pin I/O port pin or touch panel controller BYL signal output pin I/O port pin or touch panel controller BXH signal output pin I/O port pin or touch panel controller BXL signal output pin I/O port pin or A/D converter analog signal input pin I/O port pin, A/D converter analog signal input pin or D/A converter analog signal output pin LCD controller enable signal output pin LCD controller forced blank signal output pin LCD controller scan start pulse output pin LCD controller frame signal output pin LCD controller shift clock output pin LCD controller latch pulse output pin LCD controller data output pin Initial reset input pin Test input pin*1 1 TEST is the terminal used for factory inspection of the IC. For normal operation, be sure to connect the TEST terminal to VDD. 9 S1C88409 OPTION LIST 1 OSC1 SYSTEM CLOCK 1. Crystal 2. External Clock 3. CR 4. Crystal (with Gate Capacity) 2 OSC3 SYSTEM CLOCK 1. Crystal 2. Ceramic 3. CR 4. External Clock 3 MULTIPLE KEY ENTRY RESET 1. Not Use 2. Use K00, K01 3. Use K00, K01, K02 4. Use K00, K01, K02, K03 4 MPU MODE INITIAL SET 1. 4M MAXIMUM 2. 4M MINIMUM 3. 64K 5 INPUT PORT PULL UP RESISTOR * K00 ....................... * K01 ....................... * K02 ....................... * K03 ....................... * K04 ....................... * K05 ....................... * K06 ....................... * K07 ....................... * K10 ....................... * K11 ....................... * K12 ....................... * K13 ....................... * RESET ................. * MCU/MPU ............ 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 6 I/O PORT PULL UP RESISTOR * P00 ....................... * P01 ....................... * P02 ....................... * P03 ....................... * P04 ....................... * P05 ....................... * P06 ....................... * P07 ....................... * P10 ....................... * P11 ....................... * P12 ....................... * P13 ....................... * P14 ....................... * P15 ....................... * P16 ....................... * P17 ....................... 10 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor S1C88409 * P20 ....................... * P21 ....................... * P22 ....................... * P23 ....................... * P30 ....................... * P31 ....................... * P32 ....................... * P33 ....................... * P34 ....................... * P35 ....................... * P36 ....................... * P37 ....................... 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. LCD RAM 2. LCD RAM 3. LCD RAM 4. LCD RAM 5. LCD RAM 6. LCD RAM 7. LCD RAM 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 7 RAM OPTION 2K Byte 2.25K Byte 2.5K Byte 2.75K Byte 3K Byte 3.25K Byte 3.5K Byte 8 TOUCH PANEL CONTROLLER DRIVE PORT 1. Use 2. Not Use 9 TPC INPUT PORT * P30 ....................... * P31 ....................... * P32 ....................... * P33 ....................... * P34 ....................... * P35 ....................... 1. Use 1. Use 1. Use 1. Use 1. Use 1. Use 2. Not Use 2. Not Use 2. Not Use 2. Not Use 2. Not Use 2. Not Use 2. X Input 2. Y Input 2. X Input 2. X Input 2. X Input 2. X Input 10 TPC INPUT PORT TYPE * P30 ....................... * P31 ....................... * P32 ....................... * P33 ....................... * P34 ....................... * P35 ....................... 1. Y Input 1. X Input 1. Not Use 1. Not Use 1. Not Use 1. Not Use 3. Not Use 3. Not Use 3. Y Input 3. Y Input 3. Y Input 3. Y Input ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Rating Supply voltage Analog supply voltage Reference supply voltage Input voltage Output voltage High-level output current Low-level output current Operating temperature Storage temperature Permissible disspation Note) 1. In case of plastic package. Symbol Condition VDD AVDD AVREF VI VO 1 terminal IOH Total of all terminals 1 terminal IOL Total of all terminals Topr Tstg Ta=25C PD Value -0.3 to +7.0 -0.3 to +7.0 -0.3 to AVDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -5 -20 -5 -20 -20 to +70 -65 to +150 200 (VSS=0V) Unit Note V V V V V mA mA mA mA C C mW 1 11 S1C88409 Recommended Operating Conditions (VSS=0V) Remark Symbol Min. Typ. Max. Unit Note Supply voltage VDD 1.8 5.5 V Analog supply voltage AVDD AVDD2.7 V VDD-0.05 VDD+0.05 V Clock frequency fOSC1 VDD=1.8 to 5.5 V 30.000 32.768 50.000 kHz 1 fOSC3 VDD=1.8 to 5.5 V 0.03 1.1 MHz 1 VDD=2.6 to 5.5 V 0.03 4.4 MHz 1 VDD=3.5 to 5.5 V 0.03 6.6 MHz 1 VDD=4.5 to 5.5 V 0.03 8.8 MHz 1 Operating temperature Topr -20 +70 C Capacitor between VSS and VD1 0.1 F C1 Note) 1. When an external clock is input from the OSC1 terminal by setting the mask option, do not connect anything to the OSC2 terminal. When an external clock is input from the OSC3 terminal, do not connect anything to the OSC4 terminal. Condition DC Characteristics (Unless otherwise specified: VDD=1.8 to 5.5V, VSS=0V, Ta=-20 to 70C) Symbol Condition Min. Typ. Max. Unit Note VIH1 Pxx, MCU/MPU, Kxx 0.8VDD VDD V VIL1 0 0.2VDD Pxx, MCU/MPU, Kxx V 1.3 VIH2 VDD OSC1, OSC3, VD1 = 1.6V V 1,3 VDD 1.8 OSC1, OSC3, VD1 = 2.4V V 1,4 VDD OSC1, OSC3, VD1 = 3.2V 2.4 V 1,5 VDD OSC1, OSC3, VD1 = 4.2V 3.2 V 1,6 Low-level input voltage OSC1, OSC3, VD1 = 1.6V VIL2 0.3 0 V 1,3 OSC1, OSC3, VD1 = 2.4V 0.6 0 V 1,4 OSC1, OSC3, VD1 = 3.2V 0.8 0 V 1,5 OSC1, OSC3, VD1 = 4.2V 1.0 0 V 1,6 High-level schmitt trigger input voltage RESET VT+ 0.9VDD 0.5VDD V Low-level schmitt trigger input voltage VT0.1VDD 0.5VDD RESET V Schmitt trigger hysteresis voltage VHS 0.2 RESET, VHS=VT+-VTV High-level output current -0.5 IOH Pxx, Rxx, VOH=VDD-0.2 V mA 7 Low-level output current IOL 0.5 Pxx, Rxx, VOL=0.2 V mA 7 Input leak current Kxx, Pxx, MCU/MPU, RESET 1 ILI1 -1 A Input leak current ILI2 OSC1, OSC3 1 -1 A 1 Output leak current ILO Pxx, Rxx 1 -1 A Input pull-up resistance RIN Kxx, Pxx, MCU/MPU, RESET 500 100 k 2 Input terminal capacitance CIN Kxx, Pxx, VIN=0 V, =1 MHz, Ta=25C 15 pF Note) 1. When external clock is selected by mask option. 2. When pull-up resistor is added by mask option. 3. Low-power mode (VD1C1 = "0", VD1C0 = "1") 4. Normal mode (VD1C1 = "0", VD1C0 = "0") 5. High-speed mode 1 (VD1C1 = "1", VD1C0 = "0") 6. High-speed mode 2 (VD1C1 = "1", VD1C0 = "1") 7. Characteristics when only one terminal is driven. If two or more terminals are driven simultaneously, the characteristics had happen to reduced because the VOH and VOL voltages drop due to the parasitic resistance on the power line in the IC. Characteristic High-level input voltage Low-level input voltage High-level input voltage VOUT [V] VDD 0 VT- VT+ VDD VIN [V] 12 S1C88409 Analog Circuit Characteristics and Current Consumption (Unless otherwise specified: VDD=1.8 to 5.5V, VSS=0V, Ta=25C, OSC1=32.768kHz crystal oscillation, OSC3=external clock input) Characteristic Symbol Condition Min. Typ. Max. Unit Note SVD voltage VSVD SVD1="1", SVD0=X 3.05 3.4 3.75 V SVD1="0", SVD0="1" 2.55 2.8 3.05 V SVD1="0", SVD0="0" 1.7 1.9 2.1 V tSVD SVD circuit response time 100 s IDD1 Power current In SLEEP status 0.45 1.0 A 1 IDD2 Low-power mode In HALT status 1.8 5.0 A 2 IDD3 VD1C1="0", VD1C0="1" CPU is in operating (32.768 kHz) 9.0 20.0 A 3 IDD4 CPU is in operating (1 MHz) 0.3 0.5 mA 4 IDD1 Power current In SLEEP status 0.55 1.5 A 1 IDD2 Normal mode In HALT status 3.0 7.0 A 2 IDD3 VD1C1="0", VD1C0="0" CPU is in operating (32.768 kHz) 14.0 25.0 A 3 IDD4 CPU is in operating (1 MHz) 0.45 0.7 mA 4 IDD1 Power current In SLEEP status 0.65 2.0 A 1 IDD2 High-speed mode 1 In HALT status 5.0 12.0 A 2 IDD3 VD1C1="1", VD1C0="0" CPU is in operating (32.768 kHz) 21.0 35.0 A 3 IDD4 CPU is in operating (1 MHz) 0.65 1.0 mA 4 IDD1 Power current In SLEEP status 0.75 3.0 A 1 IDD2 High-speed mode 2 In HALT status 9.0 20.0 A 2 IDD3 VD1C1="1", VD1C0="1" CPU is in operating (32.768 kHz) 32.0 50.0 A 3 IDD4 CPU is in operating (1 MHz) 0.9 1.4 mA 4 ISVDN VDD=5.0 V SVD circuit current 7 15 A 5 ICR1 RCR=1.5M, normal mode OSC1 CR oscillation current 20 50 A 6 Note) 1. OSC1: Stop OSC3: Stop CPU, ROM, RAM: Stop Clock Timer: Stop SVD: Off Others: Stop 2. OSC1: On OSC3: Stop CPU, ROM, RAM: Stop Clock Timer: Run SVD: Off Others: Stop 3. OSC1: On OSC3: Stop CPU, ROM, RAM: Run Clock Timer: Run SVD: Off Others: Stop 4. OSC1: On OSC3: On CPU, ROM, RAM: Run Clock Timer: Run SVD: Off Others: Stop 5. OSC1: On OSC3: Stop CPU, ROM, RAM: Stop Clock Timer: Run SVD: On Others: Stop 6. When the OSC1 CR oscillation circuit is selected by mask option. AC Characteristics External memory access * Read cycle (Unless otherwise specified: VDD=5.5V, VSS=0V, fOSC1=32.768kHz, fOSC3=1.0MHz, Ta=-20 to 70C, CL=100 pF, VIH=0.8VDD, VIL=0.2VDD, VOH=0.8VDD, VOL=0.2VDD) Item Symbol Condition Min. Typ. Max. Unit Note Address set-up time in read cycle - - ns 1 tras VDD=1.8 to 5.5 V tc+tl-200+ntc/2 Address hold time in read cycle - - ns trah VD1=1.6 V th-160 trp tc-40+ntc/2 Read signal pulse width - - ns 1 600 Data input set-up time in read cycle - - ns trds 0 Data input hold time in read cycle - - ns trdh Address set-up time in read cycle - - ns 1 tras VDD=2.6 to 5.5 V tc+tl-100+ntc/2 Address hold time in read cycle - - ns trah VD1=2.4 V th-80 Read signal pulse width - - ns 1 trp tc-20+ntc/2 Data input set-up time in read cycle - - ns 300 trds Data input hold time in read cycle - - ns 0 trdh Address set-up time in read cycle - - ns 1 tras VDD=3.5 to 5.5 V tc+tl-50+ntc/2 Address hold time in read cycle - - ns trah VD1=3.2 V th-40 Read signal pulse width - - ns 1 trp tc-10+ntc/2 Data input set-up time in read cycle - - ns 150 trds Data input hold time in read cycle - - ns 0 trdh Address set-up time in read cycle - - ns 1 tras VDD=4.5 to 5.5 V tc+tl-50+ntc/2 Address hold time in read cycle - - ns trah VD1=4.2 V th-40 Read signal pulse width - - ns 1 trp tc-10+ntc/2 Data input set-up time in read cycle - - ns 150 trds Data input hold time in read cycle - - ns 0 trdh tc=input clock cycle time, th=input clock H pulse width, tl=input clock L pulse width Note) 1. Substitute the number of states for wait insertion in n. 13 S1C88409 * Write cycle (Unless otherwise specified: VDD=5.5V, VSS=0V, fOSC1=32.768kHz, fOSC3=1.0MHz, Ta=-20 to 70C, CL=100pF, VIH=0.8VDD, VIL=0.2VDD, VOH=0.8VDD, VOL=0.2VDD) Item Symbol Condition Min. Typ. Max. Unit Note twas VDD=1.8 to 5.5 V tc-360 Address set-up time in write cycle - - ns twah VD1=1.6 V th-160 Address hold time in write cycle - - ns twp tl-80+ntc/2 Write signal pulse width - - ns 1 Data output set-up time in write cycle twds tc-360+ntc/2 - - ns 1 Data output hold time in write cycle twdh th-160 th+160 - ns twas VDD=2.6 to 5.5 V tc-180 Address set-up time in write cycle - - ns twah VD1=2.4 V th-80 Address hold time in write cycle - - ns twp tl-40+ntc/2 Write signal pulse width - - ns 1 Data output set-up time in write cycle twds tc-180+ntc/2 - - ns 1 Data output hold time in write cycle twdh th-160 th+160 - ns twas VDD=3.5 to 5.5 V tc-90 Address set-up time in write cycle - - ns twah VD1=3.2 V th-40 Address hold time in write cycle - - ns twp tl-20+ntc/2 Write signal pulse width - - ns 1 Data output set-up time in write cycle twds tc-90+ntc/2 - - ns 1 Data output hold time in write cycle twdh th-160 th+160 - ns Address set-up time in write cycle - twas VDD=4.5 to 5.5 V tc-90 - ns Address hold time in write cycle - twah VD1=4.2 V th-40 - ns twp tl-20+ntc/2 Write signal pulse width - - ns 1 Data output set-up time in write cycle twds tc-90+ntc/2 - - ns 1 Data output hold time in write cycle twdh th-160 th+160 - ns tc=input clock cycle time, th=input clock H pulse width, tl=input clock L pulse width Note) 1. Substitute the number of states for wait insertion in n. * Read cycle tc * VIH ICLK VIL th * A00-A21 CE tl * VOH VOL tras trah VOH VOL RD trp trds trdh VIH VIL DIN In the case of crystal or ceramic oscillation: th=0.5tc0.05tc, tl=tc-th In the case of CR oscillation: th=0.5tc0.10tc, tl=tc-th (1/tc: oscillation frequency) * Write cycle tc * VIH ICLK VIL th * A00-A21 CE tl * VOH VOL twas twah VOH VOL WR twp twds DIN VIH VIL In the case of crystal or ceramic oscillation: th=0.5tc0.05tc, tl=tc-th In the case of CR oscillation: th=0.5tc0.10tc, tl=tc-th (1/tc: oscillation frequency) 14 twdh S1C88409 Serial interface * Clock synchronous master mode Item Transmit data output delay time Receive data input set-up time Receive data input hold time Transmit data output delay time Receive data input set-up time Receive data input hold time Transmit data output delay time Receive data input set-up time Receive data input hold time Transmit data output delay time Receive data input set-up time Receive data input hold time (Unless otherwise specified: VDD=5.5V, VSS=0V, fOSC1=32.768kHz, fOSC3=100kHz, Ta=-20 to 70C, CL=100pF, VIH=0.8VDD, VIL=0.2VDD, VOH=0.8VDD, VOL=0.2VDD) Symbol Condition Min. Typ. Max. Unit Note tsmd VDD=1.8 to 5.5 V - - 400 ns tsms VD1=1.6 V 1000 - - ns tsmh 400 - - ns tsmd VDD=2.6 to 5.5 V - - 200 ns tsms VD1=2.4 V 500 - - ns tsmh 200 - - ns tsmd VDD=3.5 to 5.5 V - - 100 ns tsms VD1=3.2 V 250 - - ns tsmh 100 - - ns tsmd VDD=4.5 to 5.5 V - - 100 ns tsms VD1=4.2 V 250 - - ns tsmh 100 - - ns SCLK OUT VOH VOL tsmd VOH VOL SOUT tsms tsmh VIH VIL SIN OSC3 VOH SCLK OUT VOL tscd tscd * Clock synchronous slave mode Item Transmit data output delay time Receive data input set-up time Receive data input hold time Transmit data output delay time Receive data input set-up time Receive data input hold time Transmit data output delay time Receive data input set-up time Receive data input hold time Transmit data output delay time Receive data input set-up time Receive data input hold time (Unless otherwise specified: VDD=5.5V, VSS=0V, fOSC1=32.768kHz, fOSC3=100kHz, Ta=-20 to 70C, CL=100pF, VIH=0.8VDD, VIL=0.2VDD, VOH=0.8VDD, VOL=0.2VDD) Symbol Condition Min. Typ. Max. Unit Note tssd VDD=1.8 to 5.5 V - - 1000 ns tsss VD1=1.6 V 400 - - ns tssh SCKIN=100 kHz 400 - - ns tssd VDD=2.6 to 5.5 V - - 500 ns tsss VD1=2.4 V 200 - - ns tssh SCKIN=100 kHz 200 - - ns tssd VDD=3.5 to 5.5 V - - 250 ns tsss VD1=3.2 V 100 - - ns tssh SCKIN=100 kHz 100 - - ns tssd VDD=4.5 to 5.5 V - - 250 ns tsss VD1=4.2 V 100 - - ns tssh SCKIN=100 kHz 100 - - ns SCLK IN VIH VIL tssd VOH VOL SOUT tsss tssh VIH VIL SIN tsccy SCLK IN tsch tckf VIH VIL tckr tscl 15 S1C88409 * Asynchronous mode (Unless otherwise specified: VDD=1.8 to 5.5 V, VSS=0 V, Ta=-20 to 70C, VIH=0.7VDD, VIL=0.3VDD, VOH=0.7VDD, VOL=0.3VDD) Item Symbol Condition Min. Typ. Max. Unit Note tsa1 Start bit detection error time tsa2 Erroneous start bit detection range time 0 - t/16 s 1 8t/16 - 9t/16 s 2 Note) 1. Start bit detection error time is a logical delay time from inputting a start bit until the internal sampling starts operating. (AC time is not included.) 2. Erroneous start bit detection range time is a logical time from starting sampling clock (detecting a start bit) until the start bit is detected again whether a low level (start bit) has still been input. When a high level is detected, the start bit detection circuit is reset and goes into a start bit waiting status. (AC time is not included.) Start bit Stop bit SIN tsa1 Sampling clock t Erroneous start bit detection signal tsa2 Input clock * OSC1, OSC3 external clock Item Symbol Cycle time "H" pulse width "L" pulse width Cycle time "H" pulse width "L" pulse width OSC1 input clock time OSC3 input clock time Input clock rising time Input clock falling time OSC1 input clock time Cycle time "H" pulse width "L" pulse width Cycle time "H" pulse width "L" pulse width OSC3 input clock time Input clock rising time Input clock falling time OSC1 input clock time Cycle time "H" pulse width "L" pulse width Cycle time "H" pulse width "L" pulse width OSC3 input clock time Input clock rising time Input clock falling time OSC1 input clock time Cycle time "H" pulse width "L" pulse width Cycle time "H" pulse width "L" pulse width OSC3 input clock time Input clock rising time Input clock falling time to1cy to1h to1l to3cy to3h to3l tosr tosf to1cy to1h to1l to3cy to3h to3l tosr tosf to1cy to1h to1l to3cy to3h to3l tosr tosf to1cy to1h to1l to3cy to3h to3l tosr tosf (Unless otherwise specified: VSS=0V, Ta=-20 to 70C) Condition Min. Typ. Max. Unit Note VDD=1.8 to 5.5 V 20 - 32 s 10 - 16 s VD1=1.6 V 10 - 16 s VIH=1.3 V 1000 - 32000 ns VIL=0.3 V 500 - 16000 ns 500 - 16000 ns - - 25 ns - - 25 ns 20 - 32 s VDD=2.6 to 5.5 V 10 - 16 s VD1=2.4 V 10 - 16 s VIH=1.8 V 240 - 32000 ns VIL=0.6 V 120 - 16000 ns 120 - 16000 ns - - 25 ns - - 25 ns 20 - 32 s VDD=3.5 to 5.5 V 10 - 16 s VD1=3.2 V 10 - 16 s VIH=2.4 V 155 - 32000 ns VIL=0.8 V 77.5 - 16000 ns 77.5 - 16000 ns - - 25 ns - - 25 ns 20 - 32 s VDD=4.5 to 5.5 V 10 - 16 s VD1=4.2 V 10 - 16 s VIH=3.2 V 115 - 32000 ns VIL=1.0 V 57.5 - 16000 ns 57.5 - 16000 ns - - 25 ns - - 25 ns to1cy OSC1 to1h tosf VIH VIL tosr to1l to3cy OSC3 to3h tosf VIH VIL tosr to3l 16 S1C88409 * RESET input clock (Unless otherwise specified: VDD=1.8 to 5.5V, VSS=0V, Ta=-20 to 70C, VIH=0.5VDD, VIL=0.1VDD) Symbol Condition Min. Typ. Max. Unit Note tsr 100 - - s Item RESET pulse width tsr VIH RESET VIL LCD controller (Unless otherwise specified: VDD=5.5V, VSS=0V, fOSC1=32.768kHz, fOSC3=2.0MHz, Ta=-20 to 70C, CL=100pF, VIH=0.8VDD, VIL=0.2VDD, VOH=0.8VDD, VOL=0.2VDD) Item Symbol Condition Min. Typ. Max. Unit Note tHXS(1) VDD=1.8 to 5.5 V tc-360 XSCL H-level pulse width (B&W, 4 bits) - - ns XSCL H-level pulse width (gray, 4 bits) tHXS(2) VD1=1.6 V tc-tl-360 - - ns tLPXS LP falling edge to XSCL rising edge 6tc-360 - - ns tDS tc-360 LCD data setup time - - ns tDH tc-360 LCD data hold time - - ns tHYD tc(fOSC1)-3 YD H-level pulse width - - ns tHLP tl(fOSC1)-1.5 LP H-level pulse width - - ns tYDLPL tl(fOSC1)-1.5 YD setup time - - ns tLPYD th(fOSC1)-1.5 YD hold time - - ns -300 tLPFR FR change from LP falling edge - 300 ns tHXS(1) VDD=2.6 to 5.5 V tc-180 XSCL H-level pulse width (B&W, 4 bits) - - ns tHXS(2) VD1=2.4 V tc-tl-180 XSCL H-level pulse width (gray, 4 bits) - - ns 6tc-180 tLPXS LP falling edge to XSCL rising edge - - ns tDS tc-180 LCD data setup time - - ns tDH tc-180 LCD data hold time - - ns tHYD tc(fOSC1)-3 YD H-level pulse width - - ns tHLP tl(fOSC1)-1.5 LP H-level pulse width - - ns tYDLPL tl(fOSC1)-1.5 YD setup time - - ns tLPYD th(fOSC1)-1.5 YD hold time - - ns -200 tLPFR FR change from LP falling edge - 200 ns tHXS(1) VDD=3.5 to 5.5 V tc-90 XSCL H-level pulse width (B&W, 4 bits) - - ns tHXS(2) VD1=3.2 V tc-tl-90 XSCL H-level pulse width (gray, 4 bits) - - ns 6tc-90 tLPXS LP falling edge to XSCL rising edge - - ns tDS tc-90 LCD data setup time - - ns tDH tc-90 LCD data hold time - - ns tHYD tc(fOSC1)-3 YD H-level pulse width - - ns tHLP tl(fOSC1)-1.5 LP H-level pulse width - - ns tYDLPL tl(fOSC1)-1.5 YD setup time - - ns tLPYD th(fOSC1)-1.5 YD hold time - - ns -100 tLPFR FR change from LP falling edge - 100 ns tHXS(1) VDD=4.5 to 5.5 V tc-90 XSCL H-level pulse width (B&W, 4 bits) - - ns tHXS(2) VD1=4.2 V tc-tl-90 XSCL H-level pulse width (gray, 4 bits) - - ns tLPXS 6tc-90 LP falling edge to XSCL rising edge - ns tDS tc-90 LCD data setup time - ns tDH tc-90 LCD data hold time - ns tHYD tc(fOSC1)-3 YD H-level pulse width - ns tHLP tl(fOSC1)-1.5 LP H-level pulse width - ns tYDLPL tl(fOSC1)-1.5 YD setup time - ns tLPYD th(fOSC1)-1.5 YD hold time - ns -100 tLPFR FR change from LP falling edge 100 ns tc=OSC3 clock cycle time, th=OSC3 clock H pulse width, tl=OSC3 clock L pulse width, tc(fOSC1)=OSC1 clock cycle time th(fOSC1)=OSC1 clock H pulse width, tl(fOSC1)=OSC1 clock L pulse width FR tHYD YD tYDLPL tHLP tLPYD tLPFR LP tLPXS tHXS XSCL tDS tDH SD0-SD3 17 S1C88409 Power-on reset Item Symbol Vsr Operating voltage RESET input width tpsr Condition (Unless otherwise specified: VSS=0V, Ta=-20 to 70C) Min. Typ. Max. Unit Note 2.6 - - V 10 - - ms Vsr VDD tpsr 0.5VDD RESET Power ON 0.1VDD VDD *2 *1 *1 When the built-in pull up resistor is not used. *2 Because the potential of the RESET terminal not reached VDD level or higher. RESET VSS Switching operating mode (Unless otherwise specified: VDD=1.8 to 5.5V, VSS=0V, Ta=-20 to 70C) Condition Min. Typ. Max. Unit Note Stabilization time 5 - - ms tvdc 1 Note) 1. Stabilization time is the time from switching on the operating mode until operating mode is stabilized. For example, when turning the OSC3 oscillation circuit on, stabilization time is needed after the operating mode is switched on. Item Symbol Oscillation Characteristics Oscillation characteristics change depending on conditions (board pattern, components used, etc.). Use the following characteristics as reference values. In particular, when a ceramic oscillator or crystal oscillator is used for OSC3, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance. The oscillation start time is important because it becomes the waiting time when OSC3 clock is used. (If OSC3 is used as CPU clock before oscillation stabilizes, the CPU may malfunction.) * OSC1 crystal oscillation (Unless otherwise specified: VDD=1.8 to 5.5V, VSS=0V, Ta=25C, Crystal oscillator=Q12C2(made by Seiko Epson corporation), CG1=25pF(External), CD1=Built-in) Item Symbol Condition Min. Typ. Max. Unit Note Oscillation start time 3 s tsta CG1 External gate capacitance Including board capacitance 5 25 pF 1 Built-in drain capacitance In case of the chip 15 pF CD1 f/IC VDD=constant Frequency/IC deviation -10 10 ppm f/V Frequency/supply voltage deviation ppm/V 1 Frequency adjustment range f/CG VDD=constant, CG=5 to 25 pF ppm 25 Frequency/operating mode deviation f/MD VDD=constant ppm 20 Note) 1. When crystal oscillation is selected by mask option. * OSC1 CR oscillation Item Oscillation start time Frequenct/IC deviation (Unless otherwise specified: VDD=1.8 to 5.5V, VSS=0V, Ta=25C, RCR=1.8M) Symbol Condition Min. Typ. Max. Unit Note tsta 3 ms f/IC RCR=constant -25 25 % * OSC3 crystal oscillation (Unless otherwise specified: VDD=2.6/3.5/4.5 to 5.5V, VSS=0V, Ta=25C, Crystal oscillator=Q21CA301xxx(made by Seiko Epson corporation), RF=1M, CG2=CD2=15pF) Item Symbol Condition Min. Typ. Max. Unit Note tsta Oscillation start time 20 ms 1 Note) 1. The crystal oscillation start time changes by the crystal oscillator to be used, CG2 and CD2. 18 S1C88409 * OSC3 CR oscillation Item Symbol tsta Oscillation start time Frequenct/IC deviation f/IC (Unless otherwise specified: VDD=2.6/3.5/4.5 to 5.5V, VSS=0V, Ta=25C) Condition Min. Typ. Max. Unit Note 1 ms -25 25 % RCR=constant * OSC3 ceramic oscillation Oscillation start time (Unless otherwise specified: VDD=2.6/3.5/4.5 to 5.5V, VSS=0V, Ta=25C, Ceramic oscillator=CSA4.00MG/CSA8.00MTZ(made by Murata Mfg. corporation), RF=1M, CG2=CD2=30 pF) Item Symbol Condition Min. Typ. Max. Unit Note tsta 5 ms * OSC1 CR oscillation characteristics (for reference) Ta = 25C, Typ. value CRoscillation frequency fOSC1 [kHz] 100 VD1 = 4.2V VD1 = 3.2V VD1 = 2.4V VD1 = 1.6V 10 1 100 1000 10000 CR oscillatiing resistor value RCR [k] * OSC3 CR oscillation characteristics (for reference) Ta = 25C, Typ. value 100000 VD1 = 4.2V VD1 = 3.2V VD1 = 2.4V VD1 = 1.6V CR oscillation frequency fOSC3 [kHz] 10000 1000 100 10 1 1 10 100 1000 10000 CR oscillatiing resistor value RCR [k] 19 S1C88409 A/D Converter Characteristics The following characteristics apply to the plastic package model only. (Unless otherwise specified: VDD=AVDD=AVREF=5.0 V, VSS=AVSS=AGND=0 V, fOSC1=32.768 kHz, fOSC3=4.0 MHz, Ta=25C) Item Symbol Condition Min. Typ. Max. Unit Note Zero-scale error Ezs VDD=AVDD=AVREF=2.7 to 5.5V, AVSS=0V, -1.50 - 1.50 LSB ADCLK=2MHz, Ta=25C Full-scale error Efs -1.50 - 1.50 LSB Non-linearity error El -1.50 - 1.50 LSB Total error Et -3.00 - 3.00 LSB VDD=AVDD=AVREF=3.0V, ADCLK=2MHz, Ta=25C A/D converter IAD - 0.50 1.00 mA AVREF and ADCLK divider current not included current consumption VDD=AVDD=AVREF=5.0V, ADCLK=2MHz, Ta=25C - 1.80 3.50 mA AVREF and ADCLK divider current not included VDD=AVDD=AVREF=2.7 to 5.5 V, Ta=25C f Input clock frequency - 2 4 MHz Zero-scale error: Ezs = deviation from the ideal value at zero point Full-scale error: Efs = deviation from the ideal value at the full scale point Non-linearity error: El = deviation of the real conversion curve from the end point line Total error: Et = max(Ezs, Efs, Eabs), Eabs = deviation from the ideal line (including quantization error) D/A Converter Characteristics The following characteristics apply to the plastic package model only. (Unless otherwise specified: VDD=AVDD=AVREF=5.0 V, VSS=AVSS=AGND=0 V, fOSC1=32.768 kHz, fOSC3=1.0 MHz, Ta=25C) Item Symbol Condition Min. Typ. Max. Unit Note tDA D/A conversion speed VDD=AVDD=AVREF=VD1=5.5 V - - 10 s Load capacitance=parasitic capacitance only VDD=AVDD=AVREF=VD1=5.5 V - - 30 s Load capacitance=100 pF+parasitic capacitance ElDA VDD=AVDD=VD1=AVREF=3.0 V, Integral linearity error -1.50 - 1.50 LSB IL=1 A, Ta=-20 to 70C VDD=AVDD=VD1=AVREF=5.0 V, -1.50 - 1.50 LSB IL=1 A, Ta=-20 to 70C EdDA VDD=AVDD=VD1=AVREF=3.0 V, Differential linearity error -1.00 - 1.00 LSB IL=1 A, Ta=-20 to 70C VDD=AVDD=VD1=AVREF=5.0 V, -1.00 - 1.00 LSB IL=1 A, Ta=-20 to 70C EtDA VDD=AVDD=VD1=AVREF=3.0V, Total error -2.50 - 2.50 LSB IL=1A, Ta=-20 to 70C VDD=AVDD=VD1=AVREF=5.0V, -2.50 - 2.50 LSB IL=1A, Ta=-20 to 70C IDA VDD=AVDD=AVREF=3.0V, Ta=25C, 55H output D/A converter - 0.35 1 mA Reference resistor current not included current consumption VDD=AVDD=AVREF=5.5V, Ta=25C, 55H output - 0.7 2 mA Reference resistor current not included Integral linearity error: ElDA = difference between the real conversion characteristic and the end point line Differential linearity error: EdDA = difference between the real step width and the ideal step width Total error: EtDA = max(Ezs, Efs, Eabs) Eabs = deviation from the ideal line (including quantization error) Ezs = deviation from the ideal value at zero point (zero-scale error) Efs = deviation from the ideal value at the full scale point (full-scale error) 20 S1C88409 BASIC EXTERNAL CONNECTION DIAGRAM VSS AGND SD0-SD7 LCDEN DOFF YD FR XSCL LP LCD panel/driver AVSS K00-K07 K10-K13 CG1 Input OSC1 RCR X'tal1 OSC2 CG2 OSC3 X'tal2 or CR Rf OSC4 CD2 - C1 + S1C88409 VD1 RESET (D0-D7) P00-P07 (SIN) P10 (SOUT) P11 (SCLK) P12 (SRDY) P13 (SIN/IRI) P14 (SOUT/IRO) P15 (SCLK) P16 (SRDY) P17 (BYH, BYL, BXH, BXL) P20-P23 (AD0-AD5) P30-P35 (AD6/DA0, AD7/DA1) P36, P37 Cres 1.8-5.5 V + CP3 + CP2 + CP1 VDD MCU/MPU TEST AVDD Coil (A00-A07) R00-R07 (A08-A15) R10-R17 (A16-A21) R20-R25 (RD) R26 (WR) R27 (CE0) R30 (CE1) R31 (CE2) R32 (TOUT0/FOUT3) R40 (TOUT1/FOUT1) R41 Output I/O BZ (R42) Piezo AVREF [The potential of the substrate (back of the chip) is VSS] Recommended values for external parts Symbol X'tal1 RCR X'tal2 CR Rf CG1 CG2 CD2 C1-3 CP Cres Name Crystal oscillator Resistor for CR oscillation Crystal oscillator Ceramic oscillator Feedback resistor Trimmer capacitor Gate capacitor Drain capacitor Capacitor between VSS and VD1 Capacitor for power supply Capacitor for RESET terminal Recommended value 32.768 kHz, CI(Max.) = 35 k 1.8 M 4, 6, 8 MHz 4, 6, 8 MHz 1 M 5-25 pF 15 pF 15 pF 0.1 F 3.3 F 0.47 F Note: The above table is simply an example, and is not guaranteed to work. 21 S1C88409 PAD COORDINATES Diagram of Pad Layout 30 25 20 15 10 1 5 108 31 105 35 100 X (0, 0) 7.58 mm Y 40 45 95 50 90 55 85 56 60 65 70 75 81 80 Die No. 6.47 mm 22 Chip thickness: 400 m Pad opening: 100 m (PAD No. 1-80, 84-108) 60 m (PAD No. 81-83) S1C88409 Pad Coordinates No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Pad name MCU/MPU K00 K01 K02 K03 K04 K05 K06 K07 K10/EXCL00 K11/EXCL11 K12 K13 RESET P00/D0 P01/D1 P02/D2 P03/D3 P04/D4 P05/D5 P06/D6 P07/D7 R00/A0 R01/A1 R02/A2 N.C. N.C. N.C. N.C. N.C. R03/A3 R04/A4 R05/A5 R06/A6 R07/A7 R10/A8 R11/A9 R12/A10 R13/A11 R14/A12 R15/A13 R16/A14 R17/A15 R20/A16 R21/A17 R22/A18 R23/A19 R24/A20 R25/A21 R26/RD R27/WR R30/CE0 R31/CE1 R32/CE2 X 2,143 1,943 1,793 1,593 1,443 1,293 1,143 993 843 693 543 393 243 93 -80 -230 -380 -530 -680 -830 -990 -1,150 -1,330 -1,530 -1,790 -2,146 -2,306 -2,466 -2,616 -2,776 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 -3,107 Y 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 3,664 2,131 1,865 1,412 1,259 1,106 953 800 647 494 341 188 35 -118 -271 -424 -577 -730 -883 -1,036 -1,189 -1,342 -1,495 -1,648 -1,798 No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pad name R40/TOUT0/FOUT3 R41/TOUT1/FOUT1 R42/BZ P10/SIN P11/SOUT P12/SCLK P13/SRDY P14/SIN/IRI P15/SOUT/IRO P16/SCLK P17/SRDY P20/BYH P21/BYL P22/BXH P23/BXL TEST P37/AD7/DA1 P36/AD6/DA0 P35/AD5 P34/AD4 P33/AD3 P32/AD2 P31/AD1 P30/AD0 AVDD AVSS N.C. N.C. N.C. AVREF AGND N.C. N.C. SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 LP XSCL FR YD DOFF LCDEN VDD OSC4 OSC3 VD1 OSC2 OSC1 VSS X -3,107 -2,069 -1,869 -1,689 -1,519 -1,369 -1,219 -1,069 -919 -769 -619 -469 -319 -169 -19 131 281 431 582 732 882 1,032 1,232 1,432 1,632 1,882 3,127 3,127 3,127 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 3,107 Unit: m Y -2,100 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,665 -3,390 -3,137 -2,870 -2,600 -2,400 -2,173 -2,018 -1,863 -1,708 -1,553 -1,398 -1,243 -1,088 -933 -774 -610 -463 -259 -88 92 262 1,313 1,495 1,650 1,805 1,987 2,148 2,318 23 S1C88409 PACKAGE Plastic QFP15-100pin 160.4 140.1 75 51 140.1 160.4 50 76 INDEX 26 100 1.40.1 25 0.5 +0.1 0.18 -0.05 +0.05 0.125 -0.025 0 10 0.50.2 0.1 1.7max 1 1 (Unit: mm) Note: The dimensions are subject to change without notice. NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) Seiko Epson Corporation 2001 All right reserved. SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ IC Marketing & Engineering Group ED International Marketing Department Europe & U.S.A. 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone : 042-587-5812 FAX : 042-587-5564 ED International Marketing Department Asia 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone : 042-587-5814 FAX : 042-587-5110 First issue June, 1998 M Printed July, 2001 in Japan L