PIC16F627A/628A/648A PIC16F627A/628A/648A EEPROM Memory Programming Specification 1.0 This document includes the programming specifications for the following devices: * * * * * * The PIC16F627A/628A/648A is programmed using a serial method. The Serial mode will allow the PIC16F627A/628A/648A to be programmed while in the user's system. This allows for increased design flexibility. This programming specification applies to PIC16F627A/628A/648A devices in all packages. PIC16F627A PIC16F628A PIC16F648A PIC16LF627A PIC16LF628A PIC16LF648A Note: PROGRAMMING THE PIC16F627A/628A/648A 1.1 Hardware Requirements The PIC16F627A/628A/648A requires one programmable power supply for VDD (2.0V to 5.5V) and a VPP of 12V to 14V, or VPP of 4.5V to 5.5V, when using low voltage. Both supplies should have a minimum resolution of 0.25V. All references to PIC16F627A/628A/648A also apply to PIC16LF62XA devices. 1.2 Programming Mode The Programming mode for the PIC16F627A/628A/648A allows programming of user program memory, data memory, special locations used for ID, and the Configuration Word. FIGURE 1-1: PIN DIAGRAM PDIP, SOIC *1 RA3/AN3/CMP1 2 RA4/T0CKI/CMP2 3 RA5/MCLR/VPP 4 VSS 5 RB0/INT 6 RB1/RX/DT 7 RB2/TX/CK 8 RB3/CCP1 9 (c) 2007 Microchip Technology Inc. 18 RA1/AN1 RA2/AN2/VREF *1 17 RA0/AN0 RA3/AN3/CMP1 2 16 RA7/OSC1/CLKIN 3 15 RA6/OSC2/CLKOUT RA4/T0CKI/CMP2 RA5/MCLR/VPP 14 VDD VSS 5 13 RB7/DATA/T1OSI 12 RB6/CLOCK/T1OSO/T1CKI 11 RB5 10 RB4/PGM 4 VSS 6 RB0/INT 7 RB1/RX/DT 8 RB2/TX/CK 9 RB3/CCP1 10 Preliminary PIC16F627A/628A/648A RA2/AN2/VREF PIC16F627A/628A/648A SSOP 20 RA1/AN1 19 RA0/AN0 18 RA7/OSC1/CLKIN 17 16 RA6/OSC2/CLKOUT VDD 15 VDD 14 RB7/DATA/T1OSI 13 RB6/CLOCK/T1OSO/T1CKI 12 RB5 11 RB4/PGM DS41196G-page 1 PIC16F627A/628A/648A 28-PIN QFN PIC16F627A/628A/648A DIAGRAM NC 28 27 26 25 24 23 22 NC RA1/AN1 RA0/AN0 RA4/T0CKI/CMP2 RA3/AN3/CMP1 RA2/AN2/VREF FIGURE 1-2: 1 NC 2 VSS 3 NC 4 PIC16F627A/628A/ VSS 5 648A NC 6 7 RB0/INT 21 20 19 18 17 16 15 RA7/OSC1/CLKIN RA6/OSC2/CLKOUT VDD NC VDD RB7/DATA/T1OSI RB6/CLOCK/T1OSO/T1CKI TABLE 1-1: Pin Name NC RB4/PGM RB5 RB1/RX/DT RB2/TX/CK RB3/CCP1 NC 8 9 10 11 12 13 14 RA5/MCLR/VPP PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16F627A/628A/648A During Programming Function Pin Type Pin Description RB4 PGM I Low-voltage programming input if Configuration bit equals 1 RB6 CLOCK I Clock input RB7 DATA I/O Data input/output Programming Mode P(1) Program Mode Select VDD VDD P Power Supply VSS VSS P Ground MCLR/VPP Legend: I = Input, O = Output, P = Power Note 1: In the PIC16F627A/628A/648A, the programming high voltage is internally generated. To activate the Programming mode, high voltage needs to be applied to MCLR input. Since the MCLR is used for a level source, this means that MCLR does not draw any significant current. DS41196G-page 2 Preliminary (c) 2007 Microchip Technology Inc. PIC16F627A/628A/648A 2.0 PROGRAM DETAILS 2.3 2.1 User Program Memory Map The EE Data memory space extends from 0x00 to 0xFF and is separate from both program memory space and RAM space. The user memory space extends from 0x0000 to 0x1FFF. In Programming mode, the program memory space extends from 0x0000 to 0x3FFF, with the first half (0x0000-0x1FFF) being user program memory and the second half (0x2000-0x3FFF) being configuration memory. In the user program memory space, the PC will increment from 0x0000 to the end of implemented user program memory (see Figure 2-1) and wraps around to 0x0000. Additionally, the high order bit is not affected by the Increment Address command. Thus, in configuration memory, the PC increments from 0x2000 to 0x3FFF and wraps around to 0x2000 (not to 0x0000). The only way to set the PC back to user program memory is to reset the part and re-enter Program/Verify mode as described in Section 2.4 "Program/Verify Mode". Configuration memory space is entered via the Load Configuration command (see Section 2.4.3 "Load Data for Configuration Memory"). Only addresses 0x2000-0x200F of configuration memory space are physically implemented. However, only locations 0x2000 through 0x2007 are available. Other locations are reserved. Locations beyond 0x200F will physically access user memory. 2.2 EE Data Memory Only the lower 128 bytes are implemented in the PIC16F627A/628A devices, while the PIC16F648A implements the full 256 bytes. Programming the EE Data memory uses the same PC as program memory, though only the lower bits are decoded and used. TABLE 2-1: EE DATA CAPACITY EE Data Memory Device PC Bits Decoded PIC16F627A/628A 128 7 PIC16F648A 256 8 TABLE 2-2: Device PROGRAM FLASH Program Flash PIC16F627A 1K PIC16F628A 2K PIC16F648A 4K User ID Locations A user may store identification information (user ID) in four user ID locations. The user ID locations are mapped in [0x2000 : 0x2003]. These locations read out normally even after the code protection is enabled. Note 1: All other locations in PIC(R) MCU configuration memory are reserved and should not be programmed. 2: Only the low order 4 bits of the user ID locations may be included in the device checksum. See Section 3.10 "Checksum Computation" for checksum calculation details. (c) 2007 Microchip Technology Inc. Preliminary DS41196G-page 3 PIC16F627A/628A/648A FIGURE 2-1: PROGRAM MEMORY MAPPING 1 KW 2 KW 4 KW Implemented Implemented 0x3FF Implemented 0x7FF 0xFFF 2000 User ID Location 1FFF 2000 2001 2008 2002 2003 2004 2005 2006 User ID Location Implemented Implemented User ID Location User ID Location Reserved Not Implemented Reserved Device ID 2007 Configuration Word DS41196G-page 4 Implemented 3FFF Preliminary (c) 2007 Microchip Technology Inc. PIC16F627A/628A/648A 2.4 Program/Verify Mode The programming module operates on simple command sequences entered in serial fashion with the data being latched on the falling edge of the clock pulse. The sequences are entered serially, via the clock and data lines, which are Schmitt Trigger inputs in this mode. The general form for all command sequences consists of a 6-bit command and conditionally a 16-bit data word. Both command and data word are clocked LSb first. The signal on pin DATA is required to have a minimum setup and hold time (see AC/DC specifications), with respect to the falling edge of the clock. Commands that have data associated with them (Read and Load), require a minimum delay of TDLY1 between the command and the data. The 6-bit command sequences are shown in Table 2-3. TABLE 2-3: COMMAND MAPPING FOR PIC16F627A/PIC16F628A/PIC16F648A Command Load Configuration Mapping (MSb ... LSb) X X 0 0 0 Data 0 0, data (14), 0 Load Data for Program Memory X X 0 0 1 0 0, data (14), 0 Load Data for Data Memory X X 0 0 1 1 0, data (8), zero (6), 0 Increment Address X X 0 1 1 0 Read Data from Program Memory X X 0 1 0 0 0, data (14), 0 0, data (8), zero (6), 0 Read Data from Data Memory X X 0 1 0 1 Begin Programming Only Cycle X 0 1 0 0 0 Bulk Erase Program Memory X X 1 0 0 1 Bulk Erase Data Memory X X 1 0 1 1 (c) 2007 Microchip Technology Inc. Preliminary DS41196G-page 5 PIC16F627A/628A/648A The optional 16-bit data word will either be an input to, or an output from the PIC(R) microcontroller, depending on the command. Load Data commands will be input, and Read Data commands will be output. The 16-bit data word only contains 14 bits of data to conform to the 14-bit program memory word. The 14 bits are centered within the 16-bit word, padded with a leading and trailing zero. Program/Verify mode may be entered via one of two methods. High voltage Program/Verify is entered by holding CLOCK and DATA pins low while raising MCLR first, then VDD as shown in Figure 2-2. Low voltage Program/Verify mode is entered by raising VDD, then MCLR and PGM, as shown in Figure 2-3. The PC will be set to `0' upon entering into Program/Verify mode. The PC can be changed by the execution of either an increment PC command, or a Load Configuration command, which sets the PC to 0x2000. All other logic is held in the Reset state while in Program/Verify mode. This means that all I/O are in the Reset state (high-impedance inputs). FIGURE 2-3: ENTERING LOW VOLTAGE PROGRAM/ VERIFY MODE Thld0 Tlvpp Tppdp VDD PGM MCLR DATA CLOCK Note: If the device is in LVP mode, raising VPP to VIHH will override LVP mode. If LVP is not being used for programming and the LVP Configuration bit is set (i.e., LVP feature is enabled), the PGM pin must not be allowed to toggle while programming. The PGM pin is edge sensitive and if an edge is detected during programming, it may cause the PC to reset. If the LVP feature is disabled, the PGM pin will have no effect on programming. Note: The LVP feature is enabled by default when the LVP bit of the Configuration Word is set. FIGURE 2-2: ENTERING HIGH VOLTAGE PROGRAM/ VERIFY MODE Tppdp Thld0 MCLR VDD LVP DATA CLOCK Note: If the LVP fuse is enabled, PGM should be held low to prevent inadvertent entry into LVP mode. DS41196G-page 6 Preliminary (c) 2007 Microchip Technology Inc. PIC16F627A/628A/648A 2.4.1 LOAD DATA FOR PROGRAM MEMORY Load data for program memory receives a 14-bit word, and readies it to be programmed at the PC location. See Figure 2-4 for timing details. FIGURE 2-4: LOAD DATA COMMAND FOR PROGRAM MEMORY TDLY2 1 2 3 4 5 1 6 2 3 4 5 15 16 RB6 (CLOCK) RB7 (DATA) 0 1 0 0 0 X 0 X X X strt_bit LSb TSET1 stp_bit MSb THLD1 2.4.2 LOAD DATA FOR DATA MEMORY Load data for data memory receives an 8-bit byte and readies it to be programmed into data memory. Though the data byte is only 8-bits wide, all 16 clock cycles are required to allow the programming module to reset properly. FIGURE 2-5: LOAD DATA COMMAND FOR DATA MEMORY TDLY2 1 2 3 4 5 6 1 2 3 4 5 15 16 RB6 (CLOCK) RB7 (DATA) TSET1 1 1 0 0 0 X 0 strt_bit LSb X X X MSb stp_bit THLD1 (c) 2007 Microchip Technology Inc. Preliminary DS41196G-page 7 PIC16F627A/628A/648A 2.4.3 LOAD DATA FOR CONFIGURATION MEMORY The Load Configuration command advances the PC to the start of configuration memory (0x2000-0x200F), and loads the data for the first ID location. Once it is set to the configuration region, only exiting and re-entering Program/Verify mode will reset PC to the user memory space. FIGURE 2-6: LOAD CONFIGURATION TDLY2 1 2 3 4 5 First Data Word 1 6 2 3 4 5 15 16 RB6 (CLOCK) RB7 (DATA) 2.4.4 0 0 0 0 0 X 0 X X X strt_bit LSb MSb stp_bit BEGIN PROGRAMMING ONLY CYCLE Begin programming only cycle programs the previously loaded word into the appropriate memory (User Program, Data or Configuration memory). A Load command must be given before every Programming command. Programming begins after this command is received and decoded. An internal timing mechanism executes the write. The user must allow for program cycle time before issuing the next command. No "End Programming" command is required. The device must be Bulk Erased before starting a series of programming only cycles. FIGURE 2-7: BEGIN PROGRAMMING ONLY CYCLE TDPROG - Data Memory TPROG - Program Memory Next Command RB6 (CLOCK) RB7 (DATA) 1 0 2 3 0 0 4 5 1 0 1 6 0 2 X TSET1 THLD1 } } DS41196G-page 8 Preliminary (c) 2007 Microchip Technology Inc. PIC16F627A/628A/648A 2.4.5 INCREMENT ADDRESS The PC is incremented when this command is received. See Figure 2-8. FIGURE 2-8: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY) TDLY2 RB6 (CLOCK) RB7 (DATA) 1 2 3 0 1 1 4 5 6 X 0 Next Command 1 2 X X TSET1 0 TDLY1 THLD1 } } 2.4.6 READ DATA FROM PROGRAM MEMORY Read data from program memory reads the word addressed by the PC and transmits it on the DATA pin during the data phase of the command. This command will report words from either user or configuration memory, depending on the PC setting. The DATA pin will go into Output mode on the second rising clock edge and revert back to Input mode (high-impedance) after the 16th rising edge. FIGURE 2-9: READ DATA FROM PROGRAM MEMORY TDLY2 1 2 3 4 5 1 6 2 RB6 (CLOCK) RB7 (DATA) 3 4 5 15 16 TDLY3 0 0 1 0 X X strt_bit TDLY1 TSET1 stp_bit LSb MSb THLD1 RB7 = Input (c) 2007 Microchip Technology Inc. RB7 = Output Preliminary RB7 Input DS41196G-page 9 PIC16F627A/628A/648A 2.4.7 READ DATA FROM DATA MEMORY Read data from data memory reads the byte in data memory addressed by the low order bits of PC and transmits it on the DATA pin during the data phase of the command. The DATA pin will go into Output mode on the second rising clock edge and revert back to Input mode (high-impedance) after the 16th rising edge. As only 8 bits are transmitted, the last 8 bits are zero padded. FIGURE 2-10: READ DATA FROM DATA MEMORY TDLY2 1 2 3 4 5 1 0 1 0 X 6 1 2 RB6 (CLOCK) 3 4 5 15 16 TDLY3 RB7 (DATA) Tset1 X strt_bit TDLY1 stp_bit MSb LSb THLD1 } } RB7 = Output RB7 = Input DS41196G-page 10 Preliminary RB7 Input (c) 2007 Microchip Technology Inc. PIC16F627A/628A/648A 3.0 COMMON PROGRAMMING TASKS 3.1 Bulk Erase Program Memory The program memory can be erased with the Bulk Erase Program Memory command. These programming commands may be combined in several ways, in order to accomplish different programming goals. Note: All Bulk Erase operations must take place with VDD between 4.5-5.5V. To perform a Bulk Erase of the program memory, the following sequence must be performed: 1. 2. 3. Execute a Load Data for Program Memory with the data word set to all `1's (0x3FFF). Execute a Bulk Erase Program Memory command Wait TERA for the erase cycle to complete. If the address is pointing to the configuration memory (0x2000-0x200F), then both user ID locations and program memory will be erased. FIGURE 3-1: BULK ERASE PROGRAM MEMORY TERA 1 RB6 (CLOCK) RB7 (DATA) TABLE 3-1: 2 1 3 0 0 4 5 1 1 6 0 2 X 0 EFFECTS OF ERASING CODE PROTECTED MEMORY Initial State ACTION Serial & Parallel Operation Result CP ON=0 OFF=1 CPD ON=0 OFF=1 PC= Config. Mem. Program Memory Data EE Memory Config. Word User ID location Bulk Erase Data Memory X OFF X Unaffected Erased Unaffected Unaffected Bulk Erase Data Memory X ON X Unaffected Erased Unaffected Unaffected Bulk Erase Program Memory X ON YES Erased Erased Erased Erased Bulk Erase Program Memory X OFF YES Erased Unaffected Erased Erased Bulk Erase Program Memory X ON NO Erased Erased Erased Unaffected Bulk Erase Program Memory X OFF NO Erased Unaffected Erased Unaffected (c) 2007 Microchip Technology Inc. Preliminary Comment CPD=ON DS41196G-page 11 PIC16F627A/628A/648A 3.2 Bulk Erase Data Memory To perform a Bulk Erase of the data memory, the following sequence must be performed: The data memory can be erased with the Bulk Erase Data memory command. Note: 1. 2. Execute a Bulk Erase Data memory command. Wait TERA for the erase cycle to complete. All Bulk Erase operations must take place with VDD between 4.5-5.5V. FIGURE 3-2: BULK ERASE DATA MEMORY COMMAND TERA Next Command RB6 (CLOCK) RB7 (DATA) 1 2 3 4 5 1 6 2 TDLY3 1 1 0 1 0 0 X TSET1 THLD1 } } DS41196G-page 12 Preliminary (c) 2007 Microchip Technology Inc. PIC16F627A/628A/648A 3.3 Programming Program Memory FIGURE 3-3: PROGRAM FLOWCHART - PIC16F627A/628A/648A PROGRAM MEMORY Start Low Voltage Programming Start High Voltage Programming Set VDD = VDD Set PGM = VSS Set PGM = VDD Set MCLR = VIHH Set MCLR = VDD Set VDD = VDD Program Cycle PROGRAM CYCLE Load Data for Program Memory Command Read Data from Program Memory Data Correct? No Report Programming Failure Begin Programming Command Yes Increment Address Command No All Locations Done? Wait TPROG Yes Verify all Locations Report Verify Error @ VDDNOM No Data Correct? Yes Done (c) 2007 Microchip Technology Inc. Preliminary DS41196G-page 13 PIC16F627A/628A/648A FIGURE 3-4: PROGRAM FLOWCHART - PIC16F627A/628A/648A CONFIGURATION MEMORY Start Load Configuration Data No Program ID Location? Yes Report Programming Failure Increment Address Command Read Data Command Program Cycle No Data Correct? Yes No Address = 0x2004? Yes Increment Address Command Increment Address Command Increment Address Command Report Program Configuration Word Error No Program Cycle (Config. Word) Set VDD = VDDNOM Data Correct? Read Data Command Yes Done DS41196G-page 14 Preliminary (c) 2007 Microchip Technology Inc. PIC16F627A/628A/648A 3.4 Program Data Memory FIGURE 3-5: PROGRAM FLOWCHART - PIC16F627A/628A/648A DATA MEMORY Start PROGRAM CYCLE Program Cycle Load Data for Data Memory Command Read Data from Data Memory Data Correct? Begin Programming Command No Report Programming Failure Wait TDPROG Yes Increment Address Command No All Locations Done? Yes Data Correct? No Report Verify Error Yes Done (c) 2007 Microchip Technology Inc. Preliminary DS41196G-page 15 PIC16F627A/628A/648A 3.5 Programming Range of Program Memory FIGURE 3-6: PROGRAM FLOWCHART - PIC16F627A/628A/648A PROGRAM MEMORY Start High Voltage Programming Start Low Voltage Programming Set PGM = VSS Set VDD = VDD Set PGM = VDD Set MCLR = VIHH Set MCLR = VDD Set VDD = VDD Increment Address Command No Address = Start Address? Yes PROGRAM CYCLE Load Data for Program Memory Command Program Cycle Begin Programming Command Read Data from Program Memory Data Correct? No Report Programming Failure Wait TPROG Yes Increment Address Command No All Locations Done? Yes Verify all Locations @ VDDNOM Done DS41196G-page 16 Preliminary (c) 2007 Microchip Technology Inc. PIC16F627A/628A/648A 3.6 Configuration Word TABLE 3-2: The PIC16F627A/628A/648A has several Configuration bits. These bits can be set (reads `0') or left unchanged (reads `1'), to select various device configurations. 3.7 DEVICE ID VALUES Device ID Value Device Device ID Word Dev Rev PIC16F627A 01 0000 010 x xxxx PIC16F628A 01 0000 011 x xxxx PIC16F648A 01 0001 000 x xxxx The device ID word for the PIC16F627A/628A/648A is hard coded at 2006h. REGISTER 3-1: CONFIGURATION WORD FOR PIC16F627A/PIC16F628A/PIC16F648A (ADDRESS: 2007h) R/P-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CP -- -- -- -- CPD LVP BOREN MCLRE FOSC2 PWRTE WDTE FOSC1 FOSC0 bit 13 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `1' P = Programmable -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 13 CP: FLASH Program Memory Code Protection bit (PIC16F648A) 1 = Code protection off 0 = 0000h to 0FFFh code-protected (PIC16F628A) 1 = Code protection off 0 = 0000h to 07FFh code-protected (PIC16F627A) 1 = Code protection off 0 = 0000h to 03FFh code-protected bit 12-9 Unimplemented: Read as `1' bit 8 CPD: Data Code Protection bit(2) 1 = Data memory code protection off 0 = Data memory code-protected bit 7 LVP: Low Voltage Programming Enable bit 1 = RB4/PGM pin has PGM function, low-voltage programming enabled 0 = RB4/PGM is digital I/O, HV on MCLR must be used for programming bit 6 BOREN: Brown-out Reset Enable bit(1) 1 = BOR enabled 0 = BOR disabled bit 5 MCLRE: RA5/MCLR Pin Function Select bit 1 = RA5/MCLR pin function is MCLR 0 = RA5/MCLR pin function is digital I/O, MCLR internally tied to VDD bit 3 PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled bit 2 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 4, 1-0 FOSC<2:0>: Oscillator Selection bits(3) 111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor & Capacitor on RA7/OSC1/CLKIN 110 = RC oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor & Capacitor on RA7/OSC1/CLKIN 101 = INTOSC internal oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN 100 = INTOSC internal oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN 011 = EXTCLK: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN 010 = HS oscillator: High speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN 000 = LP oscillator: Low power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN Note 1: 2: 3: Enabling Brown-out Reset does not automatically enable the Power-up Timer (PWRT). Only a Bulk Erase will reset the Configuration Word, including the CP bits. While MCLR is asserted in INTOSC mode, the internal clock oscillator is disabled. (c) 2007 Microchip Technology Inc. Preliminary DS41196G-page 17 PIC16F627A/628A/648A 3.8 Embedding Configuration Word and ID Information in the Hex File To allow portability of code, the programmer is required to read the Configuration Word and ID locations from the hex file when loading the hex file. If Configuration Word information was not present in the hex file, then a simple warning message may be issued. Similarly, while saving a hex file, Configuration Word and ID information must be included. An option to not include this information may be provided. Specifically for the PIC16F627A/628A/648A, the EEPROM data memory should also be embedded in the hex file (see Section 3.9 "Embedding Data EEPROM Contents in Hex File"). Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. DS41196G-page 18 Preliminary (c) 2007 Microchip Technology Inc. PIC16F627A/628A/648A 3.9 Embedding Data EEPROM Contents in Hex File The checksum is calculated by summing the following: The programmer should be able to read data EEPROM information from a hex file and conversely (as an option) write data EEPROM contents to a hex file, along with program memory information and fuse information. The data memory locations are logically mapped starting at address 0x2100. The format for data memory storage is one data byte per address location, LSB aligned. 3.10 * The contents of all program memory locations * The Configuration Word, appropriately masked * Masked ID locations (when applicable) The Least Significant 16 bits of this sum is the checksum. The following table describes how to calculate the checksum for each device. Note: Checksum Computation 3.10.1 CHECKSUM Checksum is calculated by reading the contents of the PIC16F627A/628A/648A memory locations and adding up the opcodes up to the maximum user addressable location (e.g., 0x7FF for the PIC16F628A). Any carry bits exceeding 16 bits are neglected. Finally, the Configuration Word (appropriately masked) is added to the checksum. Checksum computation for each member of the PIC16F627A/628A/648A devices is shown in Table 3-3. TABLE 3-3: The checksum calculation differs depending on the code-protect setting. Since the program memory locations read out differently depending on the code-protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum, by reading a device, the entire program memory can simply be read and summed. The Configuration Word and ID locations can always be read. CHECKSUM COMPUTATION 0x25E6 at 0 and Max Address Device Code Protect PIC16F627A OFF SUM[0x0000:0x03FF] + CFGW & 0x21FF 1DFF E9CD ON CFGW & 0x21FF + SUM_ID 1FFE EBCC PIC16F628A PIC16F648A Checksum* Blank Value OFF SUM[0x0000:0x7FF] + CFGW & 0x21FF 19FF E5CD ON CFGW & 0x21FF + SUM_ID 1BFE E7CC OFF SUM[0x0000:0x0FFF] + CFGW & 0x21FF 11FF DDCD ON CFGW & 0x21FF + SUM_ID 13FE DFCC Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a to b inclusive] SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the Most Significant nibble. For example, ID0 = 0x1, ID1 = 0x2, ID3 = 0x3, ID4 = 0x4, then SUM_ID = 0x1234 *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND (c) 2007 Microchip Technology Inc. Preliminary DS41196G-page 19 PIC16F627A/628A/648A 4.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS TABLE 4-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE AC/DC Characteristics Characteristics Standard Operating Conditions (unless otherwise stated) Operating Temperature: 0C TA +70C Operating Voltage: 4.5V VDD 5.5V Sym Min Typ Max Units VDD level for word operations, program memory VDD 2.0 -- 5.5 V level for word operations, data memory VDD 2.0 -- 5.5 V VDD level for Bulk Erase operations, program and data memory VDD 4.5 -- 5.5 V High voltage on MCLR VIHH 10.0 -- 13.5 V MCLR rise time (VSS to VIHH) for Programming mode entry TVHHR -- -- 1.0 s Hold time after MCLR TPPDP 5 -- -- s Hold time after LVP Conditions/ Comments General VDD TLVPP 5 -- -- s (CLOCK, DATA) input high level VIH1 0.8 VDD -- -- V Schmitt Trigger input (CLOCK, DATA) input low level VIL1 -- -- 0.2 VDD V Schmitt Trigger input CLOCK, DATA setup time before MCLR TSET0 100 -- -- ns Hold time after VDD THLD0 5 -- -- s Data in setup time before clock TSET1 100 -- -- ns Data in hold time after clock THLD1 100 -- -- ns Data input not driven to next clock input (delay required between command/data or command/ command) TDLY1 1.0 -- -- s Delay between clock to clock of next command or data TDLY2 1.0 -- -- s Clock to data out valid (during read data) TDLY3 -- -- 80 ns Programming cycle time TPROG -- -- 4 ms Data EEPROM Programming cycle time TDPROG -- -- 6 ms TERA -- -- 6 ms Serial Program/Verify Bulk Erase cycle time DS41196G-page 20 Preliminary (c) 2007 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2007 Microchip Technology Inc. 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