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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

UCC28710

UCC28711

UCC28712

UCC28713

SLUSB86C –NOVEMBER 2012–REVISED JUNE 2017

UCC2871x Constant-Voltage, Constant-Current Controller With Primary-Side Regulation

1 Features

1• < 10-mW No-Load Power

• Primary-Side Regulation (PSR) Eliminates Opto-

Coupler

• ±5% Voltage and Current Regulation Across Line

and Load

• 700-V Start-Up Switch

• 100-kHz Maximum Switching Frequency Enables

High-Power Density Charger Designs

• Resonant Valley-Switching Operation for Highest

Overall Efficiency

• Frequency Jitter to Ease EMI Compliance

• Wide VDD Range Allows Small Bias Capacitor

• Clamped Gate-Drive Output for MOSFET

• Overvoltage, Low-Line, and Overcurrent

Protection Functions

• Programmable Cable Compensation (UCC28710)

• NTC Resistor Interface (UCC28711, UCC28712

and UCC28713) with Fixed Cable Compensation

Options

• SOIC-7 Package

• Create a Custom Design Using the UCC28710

With the WEBENCH®Power Designer

2 Applications

• USB-Compliant Adapters and Chargers for

Consumer Electronics

– Smart Phones

– Tablet Computers

– Cameras

• Standby Supply for TV and Desktop

• White Goods

3 Description

The UCC2871x family of flyback power supply

controllers provides isolated-output Constant-Voltage

(CV) and Constant-Current (CC) output regulation

without the use of an optical coupler. The devices

process information from the primary power switch

and an auxiliary flyback winding for precise control of

output voltage and current.

An internal 700-V start-up switch, dynamically-

controlled operating states and a tailored modulation

profile support ultra-low standby power without

sacrificing start-up time or output transient response.

Control algorithms in the UCC28710 family allow

operating efficiencies to meet or exceed applicable

standards. The output drive interfaces to a MOSFET

power switch. Discontinuous conduction mode (DCM)

with valley switching reduces switching losses.

Modulation of switching frequency and primary

current peak amplitude (FM and AM) keeps the

conversion efficiency high across the entire load and

line ranges.

The controllers have a maximum switching frequency

of 100 kHz and always maintain control of the peak-

primary current in the transformer. Protection features

help keep primary and secondary component

stresses in check. The UCC28710 allow the cable

compensation to be programmed. The UCC28711,

UCC28712 and UCC28713 devices allow remote

temperature sensing using a negative temperature

coefficient (NTC) resistor while providing fixed cable-

compensation levels.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

UCC28710

SOIC (7) 4.91 mm × 3.90 mm

UCC28711

UCC28712

UCC28713

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Application

UCC28710

UCC28711

UCC28712

UCC28713

SLUSB86C –NOVEMBER 2012–REVISED JUNE 2017

www.ti.com

Product Folder Links: UCC28710 UCC28711 UCC28712 UCC28713

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Device Comparison Table..................................... 3

6 Pin Configuration and Functions......................... 3

7 Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information.................................................. 4

7.5 Electrical Characteristics........................................... 5

7.6 Typical Characteristics.............................................. 6

8 Detailed Description.............................................. 9

8.1 Overview................................................................... 9

8.2 Functional Block Diagram......................................... 9

8.3 Feature Description................................................. 10

8.4 Device Functional Modes........................................ 12

9 Application and Implementation ........................ 17

9.1 Application Information............................................ 17

9.2 Typical Application.................................................. 17

10 Power Supply Recommendations ..................... 23

11 Layout................................................................... 23

11.1 Layout Guidelines ................................................. 23

11.2 Layout Example .................................................... 25

12 Device and Documentation Support................. 26

12.1 Device Support...................................................... 26

12.2 Documentation Support ........................................ 28

12.3 Receiving Notification of Documentation Updates 28

12.4 Community Resources.......................................... 28

12.5 Trademarks........................................................... 28

12.6 Electrostatic Discharge Caution............................ 29

12.7 Glossary................................................................ 29

13 Mechanical, Packaging, and Orderable

Information........................................................... 29

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (July 2015) to Revision C Page

• Deleted all references to the UCC28714, UCC28715, and UCC28716 devices.................................................................... 1

• Deleted quasi from quasi-resonant......................................................................................................................................... 1

• Added the Development Support,Receiving Notification of Documentation Updates, and Community Resources

sections................................................................................................................................................................................. 26

Changes from Revision A (December 2014) to Revision B Page

• Updated Layout Guidelines section...................................................................................................................................... 23

Changes from Original (November 2012) to Revision A Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional

Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

VDD

NTC

GND

DRV

VDD

CBC

GND

DRV

UCC28710

UCC28711

UCC28712

UCC28713

www.ti.com

SLUSB86C –NOVEMBER 2012–REVISED JUNE 2017

Product Folder Links: UCC28710 UCC28711 UCC28712 UCC28713

(1) See Mechanical, Packaging, and Orderable Information section for specific device ordering information.

(2) For other fixed cable compensation options, call TI.

5 Device Comparison Table

PART NUMBER(1) MINIMUM SWITCHING

FREQUENCY OPTIONS(2)

UCC28710

680 Hz

Programmable cable compensation

UCC28711 NTC option, 0-mV (at 5-V output) cable compensation

UCC28712 NTC option, 150-mV (at 5-V output) cable compensation

UCC28713 NTC option, 300-mV (at 5-V output) cable compensation

6 Pin Configuration and Functions

UCC28710 D Package

7-Pin SOIC

Top View

UCC28711, UCC28712, UCC28713 D Package

7-Pin SOIC

Top View

Pin Functions

I/O DESCRIPTION

NAME UCC28710 UCC28711

UCC28712

UCC28713

CBC 3 — I Cable compensation is a programming pin for compensation of cable voltage drop. Cable

compensation is programmed with a resistor to GND.

CS 5 5 I Current sense input connects to a ground-referenced current-sense resistor in series with

the power switch. The resulting voltage is used to monitor and control the peak primary

current. A series resistor can be added to this pin to compensate the peak switch current

levels as the AC-mains input varies.

DRV 6 6 O Drive is an output used to drive the gate of an external high voltage MOSFET switching

transistor.

GND 4 4 — The ground pin is both the reference pin for the controller and the low-side return for the

drive output. Special care should be taken to return all AC decoupling capacitors as close

as possible to this pin and avoid any common trace length with analog signal return paths.

HV 7 7 I The high-voltage pin connects directly to the rectified bulk voltage and provides charge to

the VDD capacitor for start-up of the power supply.

NTC — 3 I NTC an interface to an external negative temperature coefficient resistor for remote

temperature sensing. Pulling this pin low shuts down PWM action.

VDD 1 1 I VDD is the bias supply input pin to the controller. A carefully-placed bypass capacitor to

GND is required on this pin.

VS 2 2 I Voltage sense is an input used to provide voltage and timing feedback to the controller.

This pin is connected to a voltage divider between an auxiliary winding and GND. The

value of the upper resistor of this divider is used to program the AC-mains run and stop

thresholds and line compensation at the CS pin.

UCC28710

UCC28711

UCC28712

UCC28713

SLUSB86C –NOVEMBER 2012–REVISED JUNE 2017

www.ti.com

Product Folder Links: UCC28710 UCC28711 UCC28712 UCC28713

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages

are with respect to GND. Currents are positive into, negative out of the specified terminal. These ratings apply over the operating

ambient temperature ranges unless otherwise noted.

7 Specifications

7.1 Absolute Maximum Ratings

See (1).MIN MAX UNIT

VHV Start-up pin voltage, HV 700 V

VVDD Bias supply voltage, VDD 38 V

IDRV Continuous gate current sink 50 mA

IDRV Continuous gate current source Self-limiting mA

IVS Peak current, VS −1.2 mA

VDRV Gate drive voltage at DRV −0.5 Self-limiting V

Voltage VS −0.75 7 V

CS, CBC, NTC −0.5 5 V

TJOperating junction temperature −55 150 °C

Lead temperature 0.6 mm from case for 10 s 260 °C

Tstg Storage temperature −65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. .

7.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic

discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

VDD Bias supply operating voltage 9 35 V

CVDD VDD bypass capacitor 0.047 1 µF

RCBC Cable-compensation resistance 10 kΩ

IVS VS pin current −1 mA

TJOperating junction temperature −40 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.4 Thermal Information

THERMAL METRIC(1) UCC2871x

UNITD (SOIC)

7 PINS

RθJA Junction-to-ambient thermal resistance 141.5 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 73.8 °C/W

RθJB Junction-to-board thermal resistance 89 °C/W

ψJT Junction-to-top characterization parameter 23.5 °C/W

ψJB Junction-to-board characterization parameter 88.2 °C/W

UCC28710

UCC28711

UCC28712

UCC28713

www.ti.com

SLUSB86C –NOVEMBER 2012–REVISED JUNE 2017

Product Folder Links: UCC28710 UCC28711 UCC28712 UCC28713

(1) The regulating level at VS decreases with temperature by 0.8 mV/˚C. This compensation is included to reduce the power supply output

voltage variance over temperature.

7.5 Electrical Characteristics

over operating free-air temperature range, VVDD = 25 V, HV = open, RCBC(NTC) = open, TA= –40 °C to 125 °C, TA= TJ

(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

HIGH-VOLTAGE START UP

IHV Start-up current out of VDD VHV = 100 V, VVDD = 0 V, start state 100 250 500 µA

IHVLKG Leakage current at HV VHV = 400 V, run state 0.1 1 µA

BIAS SUPPLY INPUT

IRUN Supply current, run IDRV = 0, run state 2 2.65 mA

IWAIT Supply current, wait IDRV = 0, wait state 95 120 µA

ISTART Supply current, start IDRV = 0, VVDD = 18 V, start state, IHV = 0 18 30 µA

IFAULT Supply current, fault IDRV = 0, fault state 95 125 µA

UNDERVOLTAGE LOCKOUT

VVDD(on) VDD turnon threshold VVDD low to high 19 21 23 V

VVDD(off) VDD turnoff threshold VVDD high to low 7.7 8.1 8.5 V

VS INPUT

VVSR Regulating level Measured at no-load condition, TJ= 25 °C(1) 4.01 4.05 4.09 V

VVSNC Negative clamp level IVS = –300 µA, volts below ground 190 250 325 mV

IVSB Input bias current VVS = 4 V –0.25 0 0.25 µA

CS INPUT

VCST(max) Maximum CS threshold voltage VVS = 3.7 V 738 780 810 mV

VCST(min) Minimum CS threshold voltage VVS = 4.35 V 175 195 215 mV

KAM AM control ratio VCST(max) / VCST(min) 3.6 4 4.4 V/V

VCCR Constant current regulating level CC regulation constant 318 330 343 mV

KLC Line compensation current ratio IVSLS = –300 µA, IVSLS / current out of CS pin 24 25 28.6 A/A

TCSLEB Leading-edge blanking time DRV output duration, VCS = 1 V 180 235 280 ns

DRIVERS

IDRS DRV source current VDRV = 8 V, VVDD = 9 V 20 25 mA

RDRVLS DRV low-side drive resistance IDRV = 10 mA 6 12 Ω

VDRCL DRV clamp voltage VVDD = 35 V 14 16 V

RDRVSS DRV pulldown in start state 150 190 230 kΩ

0.0001

0.001

0.01

0.1

0 5 10 15 20 25 30 35

IVDD - Bias Supply Current (mA)

VDD - Bias Supply Voltage (V)

C001

Run State

VDD Turn-Off

Wait State

VDD Turn-On

Start State

0.0001

0.001

0.01

0.1

-50 -25 0 25 50 75 100 125

IVDD - Bias Supply Current (mA)

TJ - Temperature (oC)

C002

IRUN, VDD = 25V

IWAIT, VDD = 25V

ISTART, VDD = 18V

UCC28710

UCC28711

UCC28712

UCC28713

SLUSB86C –NOVEMBER 2012–REVISED JUNE 2017

www.ti.com

Product Folder Links: UCC28710 UCC28711 UCC28712 UCC28713

Electrical Characteristics (continued)

over operating free-air temperature range, VVDD = 25 V, HV = open, RCBC(NTC) = open, TA= –40 °C to 125 °C, TA= TJ

(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TIMING

fSW(max) Maximum switching frequency VVS = 3.7 V 92 100 106 kHz

fSW(min) Minimum switching frequency VVS = 4.35 V UCC28710

UCC28711

UCC28712

UCC28713 600 680 755 Hz

tZTO Zero-crossing timeout delay 1.8 2.1 2.55 µs

PROTECTION

VOVP Overvoltage threshold At VS input, TJ= 25 °C(1) 4.55 4.6 4.71 V

VOCP Overcurrent threshold At CS input 1.4 1.5 1.6 V

IVSL(run) VS line-sense run current Current out of VS pin increasing 190 225 275 µA

IVSL(stop) VS line-sense stop current Current out of VS pin decreasing 70 80 100 µA

KVSL VS line sense ratio IVSL(run) / IVSL(stop) 2.45 2.8 3.05 A/A

TJ(stop) Thermal shut-down temperature Internal junction temperature 165 °C

CABLE COMPENSATION

VCBC(max) Cable compensation maximum

voltage Voltage at CBC at full load UCC28710 2.9 3.2 3.5 V

VCVS(min) Compensation at VS VCBC = open, change in VS

regulating level at full load UCC28710 –55 –15 25 mV

VCVS(max) Maximum compensation at VS VCBC = 0 V, change in VS regulating

level at full load UCC28710 275 320 375 mV

VCVS Compensation at VS Change in VS regulating level at full

load

UCC28711 –55 –15 25 mVUCC28712 103

UCC28713 206

NTC INPUT

VNTCTH NTC shut-down threshold Fault UVLO cycle when below this

threshold UCC28711

UCC28712

UCC28713 0.9 0.95 1 V

INTC NTC pullup current Current out of pin UCC28711

UCC28712

UCC28713 90 105 125 µA

7.6 Typical Characteristics

VDD = 25 V, unless otherwise noted.

Figure 1. Bias Supply Current vs. Bias Supply Voltage Figure 2. Bias Supply Current vs. Temperature

550

575

600

625

650

675

700

725

750

775

-50 -25 0 25 50 75 100 125

fSW(min) - Minimum Switching Frequency (Hz)

TJ - Temperature (oC)

C007

-50 -25 0 25 50 75 100 125

IDRS - DRV Source Current (mA)

TJ - Temperature (oC)

C008

VDRV = 8 V, VVDD = 9 V

170

175

180

185

190

195

200

205

210

-50 -25 0 25 50 75 100 125

VCST(min) - Minimum CS Threshold Voltage (mV)

TJ - Temperature (oC)

C005

310

315

320

325

330

335

340

345

350

-50 -25 0 25 50 75 100 125

VCCR - Constant Current Regulating Level (mV)

TJ - Temperature (oC)

C006

3.94

3.96

3.98

4.02

4.04

4.06

4.08

4.1

4.12

-50 -25 0 25 50 75 100 125

VVSR - VS Regulation Voltage (V)

TJ - Temperature (oC)

C003

100

150

200

250

300

-50 -25 0 25 50 75 100 125

VS Line Sense Current (A)

TJ - Temperature (oC)

C004

IVSLRUN

IVSLSTOP

UCC28710

UCC28711

UCC28712

UCC28713

www.ti.com

SLUSB86C –NOVEMBER 2012–REVISED JUNE 2017

Product Folder Links: UCC28710 UCC28711 UCC28712 UCC28713

Typical Characteristics (continued)

VDD = 25 V, unless otherwise noted.

Figure 3. VS Regulation Voltage vs. Temperature Figure 4. VS Line Sense Current vs. Temperature

Figure 5. Minimum CS Threshold vs. Temperature Figure 6. Constant Current Regulating Level vs.

Temperature

Figure 7. Minimum Switching Frequency vs. Temperature

VDRV = 8 V VVDD = 9 V

Figure 8. DRV Source Current vs. Temperature

4.52

4.54

4.56

4.58

4.60

4.62

4.64

4.66

4.68

-50 -25 0 25 50 75 100 125

VOVP - VS Over-Voltage Threshold (V)

TJ - Temperature (oC)

C011

120

160

200

240

280

320

-50 -25 0 25 50 75 100 125

IHV - HV Start-Up Current (A)

TJ - Temperature (oC)

C012

0.90

0.92

0.94

0.96

0.98

1.00

-50 -25 0 25 50 75 100 125

VNTCTH - NTC Shutdown Threshold Voltage (V)

TJ - Temperature (oC)

C009

100

105

110

115

120

-50 -25 0 25 50 75 100 125

INTC - NTC Pull-Up Current (A)

TJ - Temperature (oC)

C010

UCC28710

UCC28711

UCC28712

UCC28713

SLUSB86C –NOVEMBER 2012–REVISED JUNE 2017

www.ti.com

Product Folder Links: UCC28710 UCC28711 UCC28712 UCC28713

Typical Characteristics (continued)

VDD = 25 V, unless otherwise noted.

Figure 9. NTC Shutdown Threshold Voltage vs. Temperature Figure 10. NTC Pull-Up Current vs. Temperature

Figure 11. VS Overvoltage Threshold vs. Temperature Figure 12. HV Start-Up Current vs. Temperature

DRV

25 mA

S Q

CS+

VS SAMPLER

+E/A

4.05 V + VCVS

CBC

VDD

POWER

& FAULT

MANAGEMENT

UVLO

21 V / 8 V

VALLEY

SWITCHING

CONTROL

LAW

LEB

1 / fSW

VCST

SECONDARY

TIMING

DETECT

CURRENT

REGULATION VCST

200 kΩ

VDD

LINE

SENSE

ICBC

0 V-VCVS(max)

GND

CABLE

COMPENSATION

VCVS = ICBC x 3 kΩ

VOVP OV FAULT

OV FAULT

TSD/SD FAULT

IVSLS

10 kΩ LINE

FAULT

LINE FAULT

14 V

2.2 V / 0.80 V

+VNTCTH

NTC

INTC

TSD/SD

FAULT

UCC28710/14/15 UCC28711 /12/13

1.5 V

OC FAULT

IVSLS / KLC

IVSLS

28 kΩ

5 V

IHV

UCC28710

UCC28711

UCC28712

UCC28713

www.ti.com

SLUSB86C –NOVEMBER 2012–REVISED JUNE 2017

Product Folder Links: UCC28710 UCC28711 UCC28712 UCC28713

8 Detailed Description

8.1 Overview

The UCC2871x family is a flyback power supply controller which provides accurate voltage and constant current

regulation with primary-side feedback, eliminating the need for opto-coupler feedback circuits. The controller

operates in discontinuous conduction mode with valley-switching to minimize switching losses. The modulation

scheme is a combination of frequency and primary peak current modulation to provide high conversion efficiency

across the load range. The control law provides a wide-dynamic operating range of output power which allows

the power designer to achieve the <10-mW stand-by power requirement.

During low-power operating ranges the device has power management features to reduce the device operating

current at operating frequencies below 33 kHz. The UCC2871x family includes features in the modulator to

reduce the EMI peak energy of the fundamental switching frequency and harmonics. Accurate voltage and

constant current regulation, fast dynamic response, and fault protection are achieved with primary-side control. A

complete charger solution can be realized with a straightforward design process, low cost and low component

count.

8.2 Functional Block Diagram

( )

S1 VSR

AS OCV F VSR

R V

N V V V

=´ + -

IN(run)

PA VSL(run)

V 2

RN I

UCC28710

UCC28711

UCC28712

UCC28713

SLUSB86C –NOVEMBER 2012–REVISED JUNE 2017

www.ti.com

Product Folder Links: UCC28710 UCC28711 UCC28712 UCC28713

8.3 Feature Description

8.3.1 Detailed Pin Description

8.3.1.1 VDD (Device Bias Voltage Supply)

The VDD pin is connected to a bypass capacitor to ground and a start-up resistance to the input bulk capacitor

(+) terminal. The VDD turnon UVLO threshold is 21 V and turnoff UVLO threshold is 8.1 V, with an available

operating range up to 35 V. The USB charging specification requires the output current to operate in constant-

current mode from 5 V to a minimum of 2 V; this is easily achieved with a nominal VDD of approximately 25 V.

The additional VDD headroom up to 35 V allows for VDD to rise due to the leakage energy delivered to the VDD

capacitor in high-load conditions. Also, the wide VDD range provides the advantage of selecting a relatively small

VDD capacitor and high-value start-up resistance to minimize no-load stand-by power loss in the start-up

resistor.

8.3.1.2 GND (Ground)

This is a single ground reference external to the device for the gate drive current and analog signal reference.

Place the VDD bypass capacitor close to GND and VDD with short traces to minimize noise on the VS and CS

signal pins.

8.3.1.3 VS (Voltage-Sense)

The VS pin is connected to a resistor divider from the auxiliary winding to ground. The output-voltage feedback

information is sampled at the end of the transformer secondary current demagnetization time to provide an

accurate representation of the output voltage. Timing information to achieve valley-switching and to control the

duty cycle of the secondary transformer current is determined by the waveform on the VS pin. Avoid placing a

filter capacitor on this input which would interfere with accurate sensing of this waveform.

The VS pin also senses the bulk capacitor voltage to provide for AC-input run and stop thresholds, and to

compensate the current-sense threshold across the AC-input range. This information is sensed during the

MOSFET on-time. For the AC-input run/stop function, the run threshold on VS is 220 µA and the stop threshold

is 80 µA. The values for the auxilliary voltage divider upper-resistor RS1 and lower-resistor RS2 can be

determined by the equations below.

where

• NPA is the transformer primary-to-auxiliary turns ratio,

• VIN(run) is the AC RMS voltage to enable turnon of the controller (run),

• IVSL(run) is the run-threshold for the current pulled out of the VS pin during the MOSFET on-time. (see the

Electrical Characteristics table) (1)

where

• VOCV is the converter regulated output voltage,

• VFis the output rectifier forward drop at near-zero current,

• NAS is the transformer auxiliary to secondary turns ratio,

• RS1 is the VS divider high-side resistance,

• VVSR is the CV regulating level at the VS input (see the Electrical Characteristics table). (2)

( )

CBC(max) OCV F

CBC

VSR OCBC

V 3 k V V

R 28 k

V V

´ W ´ +

= - W

LC S1 CS D PA

K R R T N

´´ ´ ´

CCR PS

CS XFMR

OCC

V N

= ´ h

UCC28710

UCC28711

UCC28712

UCC28713

www.ti.com

SLUSB86C –NOVEMBER 2012–REVISED JUNE 2017

Product Folder Links: UCC28710 UCC28711 UCC28712 UCC28713

Feature Description (continued)

8.3.1.4 DRV (Gate Drive)

The DRV pin is connected to the MOSFET gate pin, usually through a series resistor. The gate driver provides a

gate-drive signal limited to 14 V. The turnon characteristic of the driver is a 25-mA current source which limits the

turnon dv/dt of the MOSFET drain and reduces the leading-edge current spike, but still provides gate-drive

current to overcome the Miller plateau. The gate-drive turnoff current is determined by the low-side driver RDS(on)

and any external gate-drive resistance. The user can reduce the turnoff MOSFET drain dv/dt by adding external

gate resistance.

8.3.1.5 CS (Current Sense)

The current-sense pin is connected through a series resistor (RLC) to the current-sense resistor (RCS). The

current-sense threshold is 0.75 V for IPP(max) and 0.25 V for IPP(min). The series resistor RLC provides the function

of feed-forward line compensation to eliminate change in IPP due to change in di/dt and the propagation delay of

the internal comparator and MOSFET turnoff time. There is an internal leading-edge blanking time of 235 ns to

eliminate sensitivity to the MOSFET turnon current spike. It should not be necessary to place a bypass capacitor

on the CS pin. The value of RCS is determined by the target output current in constant-current (CC) regulation.

The values of RCS and RLC can be determined by the equations below. The term ηXFMR is intended to account for

the energy stored in the transformer but not delivered to the secondary. This includes transformer resistance and

core loss, bias power, and primary-to-secondary leakage ratio.

Example: With a transformer core and winding loss of 5%, primary-to-secondary leakage inductance of 3.5%,

and bias power to output power ratio of 1.5%. The ηXFMR value is approximately: 1 - 0.05 - 0.035 - 0.015 = 0.9.

where

• VCCR is a current regulation constant (see the Electrical Characteristics table),

• NPS is the transformer primary-to-secondary turns ratio (a ratio of 13 to 15 is recommended for 5-V output),

• IOCC is the target output current in constant-current regulation,

•ηXFMR is the transformer efficiency. (3)

where

• RS1 is the VS pin high-side resistor value,

• RCS is the current-sense resistor value,

• TDis the current-sense delay including MOSFET turnoff delay, add ~50 ns to MOSFET delay,

• NPA is the transformer primary-to-auxiliary turns ratio,

• LPis the transformer primary inductance,

• KLC is a current-scaling constant (see the Electrical Characteristics table). (4)

8.3.1.6 CBC (Cable Compensation), Pin 1 UCC28700

The cable compensation pin is connected to a resistor to ground to program the amount of output voltage

compensation to offset cable resistance. The cable compensation block provides a 0-V to 3-V voltage level on

the CBC pin corresponding to 0 to IOCC output current. The resistance selected on the CBC pin programs a

current mirror that is summed into the VS feedback divider therefore increasing the output voltage as IOUT

increases. There is an internal series resistance of 28 kΩto the CBC pin which sets a maximum cable

compensation of a 5-V output to 400 mV when CBC is shorted to ground. The CBC resistance value can be

determined by the equation below.

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Feature Description (continued)

where

• VOis the output voltage,

• VFis the diode forward voltage,

• VOCBC is the target cable compensation voltage at the output terminals,

• VCBC(max) is the maximum voltage at the cable compensation pin at the maximum converter output current (see

the Electrical Characteristics table),

• VVSR is the CV regulating level at the VS input (see the Electrical Characteristics table). (5)

8.3.1.7 NTC (NTC Thermistor Shut-down), Pin 1 UCC28701/2/3

These versions of the UCC28700 family utilize pin 1 for an external NTC thermistor to allow user-programmable

external thermal shut-down. The shut-down threshold is 0.95 V with an internal 105-µA current source which

results in a 9.05-kΩthermistor shut-down threshold. These controllers have either zero or fixed internal cable

compensation.

8.3.2 Fault Protection

There is comprehensive fault protection. Protection functions include:

• Output overvoltage fault

• Input undervoltage fault

• Internal overtemperature fault

• Primary overcurrent fault

• CS pin fault

• VS pin fault

A UVLO reset and restart sequence applies for all fault protection events.

The output overvoltage function is determined by the voltage feedback on the VS pin. If the voltage sample on

VS exceeds 115% of the nominal VOUT, the device stops switching and the internal current consumption is IFAULT

which discharges the VDD capacitor to the UVLO turnoff threshold. After that, the device returns to the start state

and a start-up sequence ensues.

The UCC2871x family always operates with cycle-by-cycle primary peak current control. The normal operating

range of the CS pin is 0.78 V to 0.195 V. There is additional protection if the CS pin reaches 1.5 V. This results

in a UVLO reset and restart sequence.

The line input run and stop thresholds are determined by current information at the VS pin during the MOSFET

on-time. While the VS pin is clamped close to GND during the MOSFET on-time, the current through RS1 is

monitored to determine a sample of the bulk capacitor voltage. A wide separation of run and stop thresholds

allows clean start-up and shut-down of the power supply with the line voltage. The run current threshold is 225

µA and the stop current threshold is 80 µA.

The internal over-temperature protection threshold is 165°C. If the junction temperature reaches this threshold

the device initiates a UVLO reset cycle. If the temperature is still high at the end of the UVLO cycle, the

protection cycle repeats.

Protection is included in the event of component failures on the VS pin. If complete loss of feedback information

on the VS pin occurs, the controller stops switching and restarts.

8.4 Device Functional Modes

8.4.1 Primary-Side Voltage Regulation

Figure 13 illustrates a simplified flyback convertor with the main voltage regulation blocks of the device shown.

The power train operation is the same as any DCM flyback circuit but accurate output voltage and current

sensing is the key to primary-side control.

VS Sample

0 V

( )

OUT F S S A

V V I R N

+ + ´ ´

( )

BLK A

V N

- ´

RS1

RS2

VS Discriminator and

Sampler Control Law

Minimum Period

and Peak

Primary Current

VCL

Timing

Zero Crossings

DRV

RCS

RLOAD

COUT VOUT

Bulk Voltage ± VBLK

Primary Secondary

+ VF±

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Device Functional Modes (continued)

Figure 13. Simplified Flyback Convertor

(With the Main Voltage Regulation Blocks)

In primary-side control, the output voltage is sensed on the auxiliary winding during the transfer of transformer

energy to the secondary. As shown in Figure 14 it is clear there is a down slope representing a decreasing total

rectifier VFand resistance voltage drop (ISRS) as the secondary current decreases to zero. To achieve an

accurate representation of the secondary output voltage on the auxiliary winding, the discriminator reliably blocks

the leakage inductance reset and ringing, continuously samples the auxiliary voltage during the down slope after

the ringing is diminished, and captures the error signal at the time the secondary winding reaches zero current.

The internal reference on VS is 4.05 V. Temperature compensation on the VS reference voltage of -0.8-mV/°C

offsets the change in the output rectifier forward voltage with temperature. The resistor divider is selected as

outlined in the VS pin description.

Figure 14. Auxiliary Winding Voltage

The UCC2871x family includes a VS signal sampler that signals discrimination methods to ensure an accurate

sample of the output voltage from the auxiliary winding. There are however some details of the auxiliary winding

signal to ensure reliable operation, specifically the reset time of the leakage inductance and the duration of any

subsequent leakage inductance ring. Refer to Figure 15 below for a detailed illustration of waveform criteria to

ensure a reliable sample on the VS pin. The first detail to examine is the duration of the leakage inductance reset

pedestal, tLK_RESET in Figure 15. Because this can mimic the waveform of the secondary current decay, followed

by a sharp downslope, it is important to keep the leakage reset time less than 600 ns for IPRI minimum, and less

Control Voltage, E/A Output - VCL

Control Law Profile in Constant Voltage (CV) Mode

fSW (1 / MINP)

IPP (peak primary current)

5 V3.55 V2.2 V1.3 V

0.75 V

IPP(max)

100 kHz

fSW(min)

fSW

IPP

IPP(max) / 4.033 kHz

3.3 kHz

AMFM FM

VS Ring (p-p)

tLK_RESET

tDM

tSMPL

UDG-12202

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Device Functional Modes (continued)

than 2.2 µs for IPRI maximum. The second detail is the amplitude of ringing on the VAUX waveform following

tLK_RESET. The peak-to-peak voltage at the VS pin should be less than approximately 100 mVp-p at least 200 ns

before the end of the demagnetization time, tDM. If there is a concern with excessive ringing, it usually occurs

during light or no-load conditions, when tDM is at the minimum. The tolerable ripple on VS is scaled up to the

auxiliary winding voltage by RS1 and RS2, and is equal to 100 mV x (RS1 + RS2)/RS2.

Figure 15. Auxiliary Waveform Details

During voltage regulation, the controller operates in frequency modulation mode and amplitude modulation mode

as illustrated in Figure 16 below. The internal operating frequency limits of the device are 100 kHz maximum and

fSW(min). The transformer primary inductance and primary peak current chosen sets the maximum operating

frequency of the converter. The output preload resistor and efficiency at low power determines the converter

minimum operating frequency. There is no stability compensation required for the UCC2871x family.

Figure 16. Frequency and Amplitude Modulation Modes

(During Voltage Regulation)

VOCV

IOCC

Output Voltage (V)

UDG-12201

Output Current

4.75 V

5.25 V

±5%

PP P DM

OUT

S SW

I N t

2 N t

= ´ ´

IPP

UDG-12203

tON tDM

tSW

IS S

N´

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Device Functional Modes (continued)

8.4.2 Primary-Side Current Regulation

Timing information at the VS pin and current information at the CS pin allow accurate regulation of the secondary

average current. The control law dictates that as power is increased in CV regulation and approaching CC

regulation the primary-peak current is at IPP(max). Referring to Figure 17 below, the primary-peak current, turns

ratio, secondary demagnetization time (tDM), and switching period (tSW) determine the secondary average output

current. Ignoring leakage inductance effects, the average output current is given by Equation 6. When the

average output current reaches the regulation reference in the current control block, the controller operates in

frequency modulation mode to control the output current at any output voltage at or below the voltage regulation

target as long as the auxiliary winding can keep VDD above the UVLO turnoff threshold.

Figure 17. Transformer Currents

(6)

Figure 18. Typical Target Output V-I Characteristic

8.4.3 Valley Switching

The UCC2871x family utilizes valley switching to reduce switching losses in the MOSFET, to reduce induced-

EMI, and to minimize the turnon current spike at the sense resistor. The controller operates in valley-switching in

all load conditions unless the VDS ringing has diminished.

VDRV

VDS

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Device Functional Modes (continued)

Referring to Figure 19 below, the UCC2871x family operates in a valley-skipping mode in most load conditions to

maintain an accurate voltage or current regulation point and still switch on the lowest available VDS voltage.

Figure 19. Valley-Skipping Mode

8.4.4 Start-Up Operation

The internal high-voltage start-up switch connected to the bulk capacitor voltage (VBLK) through the HV pin

charges the VDD capacitor. During start up there is typically 300 µA available to charge the VDD capacitor.

When VDD reaches the 21-V UVLO turnon threshold, the controller is enabled, the converter starts switching and

the start-up switch is turned off. The initial three cycles are limited to IPP(min). After the initial three cycles at

minimum IPP(min), the controller responds to the condition dictated by the control law. The converter will remain in

discontinuous mode during charging of the output capacitor(s), maintaining a constant output current until the

output voltage is in regulation.

+ VFA -

RCS

–

DRV

CDD

VDD

GND

RS1

RS2

COUT VOUT

CB2 Np Ns

VAUX

RPL

VAC

CBC

UCC28710

SOIC-7

RLC

+ VF-

VBLK

CB1

RCBC

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The UCC2871x family of flyback power supply controllers provides constant voltage (CV) and constant current

(CC) output regulation to help meet USB-compliant adaptors and charger requirements. These devices use the

information obtained from auxiliary winding sensing (VS) to control the output voltage and do not require

optocoupler/TL431 feedback circuitry. Eliminating the optocoupler feedback reduces component count and

makes the design more cost effective. Refer to Figure 20 for details.

9.2 Typical Application

The procedure in the Detailed Design Procedure section outlines the steps to design a constant-voltage,

constant-current flyback converter using the UCC2871x family of controllers. Refer to the typical application

schematic for component location (Figure 20) and the Device Nomenclature section for variable definitions.

Figure 20. Design Procedure Application Example

9.2.1 Design Requirements

Table 1. Design Parameters

PARAMETER NOTES AND CONDITIONS MIN NOM MAX UNIT

INPUT CHARACTERISTICS

VIN Input Voltage 100 115/230 240 V

fLINE Line Frequency 47 50/60 64 Hz

PSB_CONV No Load Input Power VIN = Nom, IO= 0 A 10 mW

VIN(RUN) Brownout Voltage IO= Nom 70 V

OUTPUT CHARACTERISTICS

VOOutput Voltage VIN = Nom, IO= Nom 4.75 5 5.25 V

VRIPPLE Output Voltage Ripple VIN = Nom, IO= Max 0.1 V

IOOutput Current VIN = Min to Max 1 1.05 A

SB SB _ CONV

P P 2.5 mW= +

OCV

SB _ CONV

RP 2.5 mW

OUT MIN

SB _ CONV 2

SB AM MAX

P f

K f

h ´ ´

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Typical Application (continued)

Table 1. Design Parameters (continued)

PARAMETER NOTES AND CONDITIONS MIN NOM MAX UNIT

VOVP Output OVP IOUT = Min to Max 5.75 V

Transient Response

VOΔLoad Step (VO= 4.1 V to 6 V) (0.1 to 0.6 A) or (0.6 to 0.1 A)

VOΔ= 0.9 V for COUT calculation

in applications section 4.1 5 6 A

SYSTEMS CHARACTERISTICS

Switching Frequency 90 kHz

ηFull Load Efficiency (115/230 V RMS

Input) IO= 1 A 74% 76%

9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the UCC28710 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.2.2 Stand-by Power Estimate

Assuming no-load stand-by power is a critical design parameter, determine estimated no-load power based on

target converter maximum switching frequency and output power rating.

The following equation estimates the stand-by power of the converter.

(7)

For a typical USB charger application, the bias power during no-load is approximately 2.5 mW. This is based on

25-V VDD and 100-µA bias current. The output preload resistor can be estimated by VOCV and the difference in

the converter stand-by power and the bias power. The equation for output preload resistance accounts for bias

power estimated at 2.5 mW.

(8)

The capacitor bulk voltage for the loss estimation is the highest voltage for the stand-by power measurement,

typically 325 VDC.

For the total stand-by power estimation add an estimated 2.5 mW for snubber loss to the converter stand-by

power loss.

(9)

CCR PS

CS XFMR

OCC

V N

= ´ h

( )

MAX BULK(min)

PS(max)

MAGCC OCV F OCBC

D V

ND V V V

=´ + +

MAX MAX MAGCC

D 1 f D

æ ö

= - ´ -

ç ÷

è ø

( )

BULK(min)

IN(min)

BULK 2 2

IN(min) BULK(min) LINE

2P 0.25 arcsin

22 V

2V V f

æ ö

ç ÷

´ + ´ ç ÷

ç P ÷

è ø

=- ´

OCV OCC

V I

P´

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9.2.2.3 Input Bulk Capacitance and Minimum Bulk Voltage

Determine the minimum voltage on the input capacitance, CB1 and CB2 total, in order to determine the maximum

Np to Ns turns ratio of the transformer. The input power of the converter based on target full-load efficiency,

minimum input RMS voltage, and minimum AC input frequency are used to determine the input capacitance

requirement.

Maximum input power is determined based on VOCV, IOCC, and the full-load efficiency target.

(10)

The below equation provides an accurate solution for input capacitance based on a target minimum bulk

capacitor voltage. To target a given input capacitance value, iterate the minimum capacitor voltage to achieve the

target capacitance.

(11)

9.2.2.4 Transformer Turns Ratio, Inductance, Primary-Peak Current

The maximum primary-to-secondary turns ratio can be determined by the target maximum switching frequency at

full load, the minimum input capacitor bulk voltage, and the estimated DCM resonant time.

Initially determine the maximum available total duty cycle of the on time and secondary conduction time based on

target switching frequency and DCM resonant time. For DCM resonant time, assume 500 kHz if you do not have

an estimate from previous designs. For the transition mode operation limit, the period required from the end of

secondary current conduction to the first valley of the VDS voltage is ½ of the DCM resonant period, or 1 µs

assuming 500-kHz resonant frequency. DMAX can be determined using the equation below.

(12)

Once DMAX is known, the maximum turns ratio of the primary to secondary can be determined with the equation

below. DMAGCC is defined as the secondary diode conduction duty cycle during constant-current, CC, operation. It

is set internally by the UCC2871x family at 0.425. The total voltage on the secondary winding needs to be

determined; which is the sum of VOCV, the secondary rectifier VF, and the cable compensation voltage (VOCBC).

For the 5-V USB charger applications, a turns ratio range of 13 to 15 is typically used.

(13)

Once an optimum turns ratio is determined from a detailed transformer design, use this ratio for the following

parameters.

The UCC2871x family constant-current regulation is achieved by maintaining a maximum DMAG duty cycle of

0.425 at the maximum primary current setting. The transformer turns ratio and constant-current regulating

voltage determine the current sense resistor for a target constant current.

Since not all of the energy stored in the transformer is transferred to the secondary, a transformer efficiency term

is included. This efficiency number includes the core and winding losses, leakage inductance ratio, and bias

power ratio to rated output power. For a 5-V, 1-A charger example, bias power of 1.5% is a good estimate. An

overall transformer efficiency of 0.9 is a good estimate to include 3.5% leakage inductance, 5% core and winding

loss, and 1.5% bias power.

(14)

The primary transformer inductance can be calculated using the standard energy storage equation for flyback

transformers. Primary current, maximum switching frequency and output and transformer power losses are

included in the equation below. Initially determine transformer primary current.

Primary current is simply the maximum current sense threshold divided by the current sense resistance.

RIPPLE

ESR

PP(max) PS

V 0.8

RI N

TRAN

SW(min)

OUT

I 150 s

CVD

æ ö

+ m

ç ÷

è ø

( )

ON IN max

DMAG min

PS OCV F

t V 2

N V V

´ ´

=´ +

( ) ( )

( )

PP max CST min

ON min

CST max

IN max

I V

V 2

= ´

 

DSPK IN(max) OCV F OCBC PS LK

V V 2 V V V N V u    u 

IN(max)

REV OCV OCBC

V 2

V V V

= + +

DD(off ) FA

OCC F

V V

NV V

( )

OCV F OCBC OCC

XFMR PP(max) MAX

2 V V V I

LI f

+ + ´

h ´ ´

CST(max)

PP(max)

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(15)

(16)

The secondary winding to auxiliary winding transformer turns ratio (NAS) is determined by the lowest target

operating output voltage in constant-current regulation and the VDD UVLO of the UCC2871x family. There is

additional energy supplied to VDD from the transformer leakage inductance energy which allows a lower turns

ratio to be used in many designs.

(17)

9.2.2.5 Transformer Parameter Verification

The transformer turns ratio selected affects the MOSFET VDS and secondary rectifier reverse voltage so these

should be reviewed. The UCC2871x family does require a minimum on time of the MOSFET (tON) and minimum

DMAG time (tDMAG) of the secondary rectifier in the high line, minimum load condition. The selection of fMAX, LP

and RCS affects the minimum tON and tDMAG.

The secondary rectifier and MOSFET voltage stress can be determined by the equations below.

(18)

For the MOSFET VDS voltage stress, an estimated leakage inductance voltage spike (VLK) needs to be included.

(19)

Equation 20 and Equation 21 are used to determine if the minimum tON target of 300 ns and minimum tDMAG

target of 1.2 µs is achieved.

(20)

(21)

9.2.2.6 Output Capacitance

The output capacitance value is typically determined by the transient response requirement from no-load. For

example, in some USB charger applications there is a requirement to maintain a minimum VOof 4.1 V with a

load-step transient of 0 mA to 500 mA . The equation below assumes that the switching frequency can be at the

UCC2871x family's minimum of fSW(min).

(22)

Another consideration of the output capacitor(s) is the ripple voltage requirement which is reviewed based on

secondary peak current and ESR. A margin of 20% is added to the capacitor ESR requirement in the equation

below.

(23)

Output Power

Efficiency

10% 20% 30% 40% 50% 60% 70% 80% 90% 100%

64%

66%

68%

70%

72%

74%

76%

78%

D001

Efficiency at 115 VRMS

Efficiency at 230 VRMS

( )

CBC(max) OCV F

CBC

VSR OCBC

V 3 k V V

R 28 k

V V

´ W ´ +

= - W

LC S1 CS D PA

K R R t N

´ ´ ´ ´

( )

S1 VSR

AS OCV F VSR

R V

N V V V

=´ + -

IN(run)

PA VSL(run)

V 2

RN I

( )

OUT OCC

RUN

OCC

DD(on) DD(off )

C V

I 1 mA I

V V 1 V

+ ´

- -

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9.2.2.7 VDD Capacitance, CDD

The capacitance on VDD needs to supply the device operating current until the output of the converter reaches

the target minimum operating voltage in constant-current regulation. At this time the auxiliary winding can sustain

the voltage to the UCC2871x family. The total output current available to the load and to charge the output

capacitors is the constant-current regulation target. The equation below assumes the output current of the

flyback is available to charge the output capacitance until the minimum output voltage is achieved. There is an

estimated 1 mA of gate-drive current in the equation and 1 V of margin added to VDD.

(24)

9.2.2.8 VS Resistor Divider, Line Compensation, and Cable Compensation

The VS divider resistors determine the output voltage regulation point of the flyback converter, also the high-side

divider resistor (RS1) determines the line voltage at which the controller enables continuous DRV operation. RS1

is initially determined based on transformer auxiliary to primary turns ratio and desired input voltage operating

threshold.

(25)

The low-side VS pin resistor is selected based on desired VOregulation voltage.

(26)

The UCC2871x family can maintain tight constant-current regulation over input line by utilizing the line

compensation feature. The line compensation resistor (RLC) value is determined by current flowing in RS1 and

expected gate drive and MOSFET turnoff delay. Assume a 50-ns internal delay in the UCC2871x family.

(27)

On the UCC28710, which has adjustable cable compensation, the resistance for the desired compensation level

at the output terminals can be determined using Equation 28.

(28)

9.2.3 Application Curves

Figure 21. Efficiency Figure 22. Output at Startup at 115-V RMS

(No Load)

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Figure 23. Output at Startup at 115-V RMS

(5-ΩLoad) Figure 24. Output at Startup at 230-V RMS

(No Load)

Figure 25. Output at Startup at 230-V RMS

(5-ΩLoad)

CH1 = IO, CH4 = VOWith a 5-V Offset

Figure 26. Load Transients:

(0.1-A to 0.6-A Load Step)

CH1 = IO, CH4 = VOWith a 5-V Offset

Figure 27. Load Transients:

(0.6-A to 0.1-A Load Step)

CH4 = VO, Output voltage at EVM output

CH2 = VO, Output voltage measured at the end of the 3M of

cable in parallel with a 1-uF capacitor. The output voltage has

less than 50 mV of output ripple at the end of the cable.

Figure 28. Output Ripple Voltage at Full Load

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10 Power Supply Recommendations

The UCC2871x family is intended for AC/DC adapters and chargers with input voltage range of 85 VAC(rms) to 265

VAC(rms) using Flyback topology. It can be used in other applications and converter topologies with different input

voltages. Be sure that all voltages and currents are within the recommended operating conditions and absolute

maximum ratings of the device. To maintain output current regulation over the entire input voltage range, design

the converter to operate close to fMAX when in full-load conditions. To improve thermal performance increase the

copper area connected to GND pins.

11 Layout

11.1 Layout Guidelines

• High frequency bypass Capacitor C5 should be placed across Pin 1 and 4 as close as you can get it to the

pins.

• Resistor R4 and C5 form a low pass filter and the connection of R4 and C5 should be as close to the VDD

pin as possible.

• The VS pin controls the output voltage through the transformer turns ratio and the voltage divider of R5 and

R11. Note the trace length between the R5, R11 and VS pin should be as short as possible to reduce or

eliminate possible EMI coupling.

• Note the IC ground and power ground should meet at the bulk capacitor’s (C6 and C7) return. Try to ensure

that high frequency/high current from the power stage does not go through the signal ground.

– The high frequency/high current path that you need to be cautious of on the primary is C7 +, T1 (P5, P3),

Q1d, Q1s, R8 to the return of C6 and C7. Try to keep all high current loops as short as possible.

• Try to keep all high current loops as short as possible.

• Keep all high current/high frequency traces away from or perpendicular to other traces in the design.

• Traces on the voltage clamp formed by D1, R2, D3 and C2 as short as possible.

• C6 return needs to be as close to the bulk capacitor supply as possible. This reduces the magnitude of dv/dt

caused by large di/dt.

• Avoid mounting semiconductors under magnetics.

Line

Neutral

VOUT +

VOUT -

VIN = 90V to 256V RMS

Vout = 5V/1A

+C3

560 uF

+C4

560 uF

+C6

4.7 uF

+C7

4.7 uF

B340LB-13-F

10.0k

10 R8

1.96

R11

27.4k

82.5k

R10

100k R12

1.00k

330nF

RS1B-13-F

TP3

TP4

TP1

TP2

22.5

SMBJP6KE82A

1nF

649

15.4k

HD06

STD2HNK70Z-1

7508110127REV01

1VDD

2VS

3CBC/NTC

4GND

DRV

UCC28711D

470 uH

MURS160-13-F

1nF

10 ohm Fusible Resistor

JP1

UCC28710

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UCC28712

UCC28713

SLUSB86C –NOVEMBER 2012–REVISED JUNE 2017

www.ti.com

Product Folder Links: UCC28710 UCC28711 UCC28712 UCC28713

No value means not populated.

Figure 29. 5-W USB Adapter Schematic

TP3

TP4

LINE

NEUTRAL

VOUT+

VOUT-

TP1

TP2

C6 C7

R10

R11 R5

R12

JP1

UCC28710

UCC28711

UCC28712

UCC28713

www.ti.com

SLUSB86C –NOVEMBER 2012–REVISED JUNE 2017

Product Folder Links: UCC28710 UCC28711 UCC28712 UCC28713

11.2 Layout Example

Figure 30. Layout Example Schematic

UCC28710

UCC28711

UCC28712

UCC28713

SLUSB86C –NOVEMBER 2012–REVISED JUNE 2017

www.ti.com

Product Folder Links: UCC28710 UCC28711 UCC28712 UCC28713

12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

For design tools see the UCC2871x Calculator,UCC2871x PSpice Transient Model,UCC2871x TINA-TI

Transient Spice Model, and UCC2871x TINA-TI Transient Reference Design.

12.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the UCC28710 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

12.1.2 Device Nomenclature

12.1.2.1 Capacitance Terms in Farads

•CBULK:total input capacitance of CB1 and CB2.

•CDD:minimum required capacitance on the VDD pin.

•COUT:minimum output capacitance required.

12.1.2.2 Duty Cycle Terms

•DMAGCC:secondary diode conduction duty cycle in CC, 0.425.

•DMAX:MOSFET on-time duty cycle.

12.1.2.3 Frequency Terms in Hertz

•fLINE:minimum line frequency.

•fMAX:target full-load maximum switching frequency of the converter.

•fMIN:minimum switching frequency of the converter, add 15% margin over the fSW(min) limit of the device.

•fSW(min):minimum switching frequency (see Electrical Characteristics).

12.1.2.4 Current Terms in Amperes

•IOCC:converter output constant-current target.

•IPP(max):maximum transformer primary current.

•ISTART:start-up bias supply current (see Electrical Characteristics).

•ITRAN: required positive load-step current.

•IVSL(run):VS pin run current (see Electrical Characteristics).

12.1.2.5 Current and Voltage Scaling Terms

•KAM:maximum-to-minimum peak primary current ratio (see Electrical Characteristics).

•KLC:current-scaling constant (see Electrical Characteristics).

UCC28710

UCC28711

UCC28712

UCC28713

www.ti.com

SLUSB86C –NOVEMBER 2012–REVISED JUNE 2017

Product Folder Links: UCC28710 UCC28711 UCC28712 UCC28713

Device Support (continued)

12.1.2.6 Transformer Terms

•LP:transformer primary inductance.

•NAS:transformer auxiliary-to-secondary turns ratio.

•NPA:transformer primary-to-auxiliary turns ratio.

•NPS:transformer primary-to-secondary turns ratio.

12.1.2.7 Power Terms in Watts

•PIN:converter maximum input power.

•POUT:full-load output power of the converter.

•PRSTR:VDD start-up resistor power dissipation.

•PSB:total stand-by power.

•PSB_CONV:PSB minus start-up resistor and snubber losses.

12.1.2.8 Resistance Terms in Ω

•RCS:primary current programming resistance.

•RESR:total ESR of the output capacitor(s).

•RPL:preload resistance on the output of the converter.

•RS1:high-side VS pin resistance.

•RS2:low-side VS pin resistance.

12.1.2.9 Timing Terms in Seconds

•tD:current-sense delay including MOSFET turn-off delay; add 50 ns to MOSFET delay.

•tDMAG(min):minimum secondary rectifier conduction time.

•tON(min):minimum MOSFET on time.

•tR:resonant frequency during the DCM (discontinuous conduction mode) time.

12.1.2.10 Voltage Terms in Volts

•VBLK:highest bulk capacitor voltage for stand-by power measurement.

•VBULK(min):minimum voltage on CB1 and CB2 at full power.

•VOCBC:target cable compensation voltage at the output terminals.

•VCBC(max):maximum voltage at the CBC pin at the maximum converter output current (see Electrical

Characteristics).

•VCCR:constant-current regulating voltage (see Electrical Characteristics).

•VCST(max):CS pin maximum current-sense threshold (see Electrical Characteristics).

•VCST(min):CS pin minimum current-sense threshold (see Electrical Characteristics).

•VDD(off):UVLO turn-off voltage (see Electrical Characteristics).

•VDD(on):UVLO turn-on voltage (see Electrical Characteristics).

•VOΔ:output voltage drop allowed during the load-step transient.

•VDSPK:peak MOSFET drain-to-source voltage at high line.

•VF:secondary rectifier forward voltage drop at near-zero current.

•VFA:auxiliary rectifier forward voltage drop.

•VLK:estimated leakage inductance energy reset voltage.

•VOCV:regulated output voltage of the converter.

•VOCC:target lowest converter output voltage in constant-current regulation.

•VREV:peak reverse voltage on the secondary rectifier.

•VRIPPLE:output peak-to-peak ripple voltage at full-load.

•VVSR:CV regulating level at the VS input (see Electrical Characteristics).

12.1.2.11 AC Voltage Terms in VRMS

•VIN(max):maximum input voltage to the converter.

UCC28710

UCC28711

UCC28712

UCC28713

SLUSB86C –NOVEMBER 2012–REVISED JUNE 2017

www.ti.com

Product Folder Links: UCC28710 UCC28711 UCC28712 UCC28713

Device Support (continued)

•VIN(min):minimum input voltage to the converter.

•VIN(run):converter input start-up (run) voltage.

12.1.2.12 Efficiency Terms

•ηSB:estimated efficiency of the converter at no-load condition, not including start-up resistance or bias losses.

For a 5-V USB charger application, 60% to 65% is a good initial estimate.

•η:converter overall efficiency.

•ηXFMR:transformer primary-to-secondary power transfer efficiency.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

•Choosing Standard Recovery Diode or Ultra-Fast Diode in Snubber

•Control Challenges for Low Power AC/DC Converters

•Troubleshooting TI PSR Controllers

•Using the UCC28711 EVM-160, Evaluation Module

•Leakage Current Measurement Reference Design for Determining Insulation Resistance

•100-V/200-V AC Input 30-W Flyback Isolated Power Supply Reference Design for Servo Drives

12.2.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

PARTS PRODUCT FOLDER ORDER NOW TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

UCC28710 Click here Click here Click here Click here Click here

UCC28711 Click here Click here Click here Click here Click here

UCC28712 Click here Click here Click here Click here Click here

UCC28713 Click here Click here Click here Click here Click here

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.5 Trademarks

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

UCC28710

UCC28711

UCC28712

UCC28713

www.ti.com

SLUSB86C –NOVEMBER 2012–REVISED JUNE 2017

Product Folder Links: UCC28710 UCC28711 UCC28712 UCC28713

12.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 30-May-2017

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

UCC28710D ACTIVE SOIC D 7 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 U28710

UCC28710DR ACTIVE SOIC D 7 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 U28710

UCC28711D ACTIVE SOIC D 7 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 U28711

UCC28711DR ACTIVE SOIC D 7 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 U28711

UCC28712D ACTIVE SOIC D 7 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 U28712

UCC28712DR ACTIVE SOIC D 7 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 U28712

UCC28713D ACTIVE SOIC D 7 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 U28713

UCC28713DR ACTIVE SOIC D 7 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 U28713

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

PACKAGE OPTION ADDENDUM

www.ti.com 30-May-2017

Addendum-Page 2

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

UCC28710DR SOIC D 7 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

UCC28711DR SOIC D 7 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

UCC28712DR SOIC D 7 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

UCC28713DR SOIC D 7 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 30-May-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

UCC28710DR SOIC D 7 2500 367.0 367.0 35.0

UCC28711DR SOIC D 7 2500 367.0 367.0 35.0

UCC28712DR SOIC D 7 2500 367.0 367.0 35.0

UCC28713DR SOIC D 7 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 30-May-2017

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

.100

[2.54]

7X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X .050

[1.27]

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

(.041)

[1.04]

SOIC - 1.75 mm max heightD0007A

SMALL OUTLINE INTEGRATED CIRCUIT

4220728/A 01/2018

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

4X (.050 )

[1.27]

7X (.061 )

[1.55]

7X (.024)

[0.6] (.100 )

[2.54]

SOIC - 1.75 mm max heightD0007A

SMALL OUTLINE INTEGRATED CIRCUIT

4220728/A 01/2018

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

7X (.061 )

[1.55]

7X (.024)

[0.6]

4X (.050 )

[1.27] (.213)

[5.4]

(.100 )

[2.54]

SOIC - 1.75 mm max heightD0007A

SMALL OUTLINE INTEGRATED CIRCUIT

4220728/A 01/2018

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

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Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

UCC28712DR UCC28712D