National Semiconductor COP620C/COP621C/COP622C/COP640C/COP641C/ COP642C/COP820C/COP821C/COP822C/COP840C/ COP841C/COP842C Single-Chip microCMOS Microcontrollers General Description The COP820C and COP840C are members of the COPS microcontroller family. They are fully static parts, fabricated using double-metal silicon gate microCMOS technology. This low cost microcontroller is a complete microcomputer containing all system timing, interrupt logic, ROM, RAM, and I/O necessary to implement dedicated control functions in a variety of applications. Features include an 8-bit memory mapped architecture, MICROWIRE/PLUS serial 1/O, a 16-bit timer/counter with capture register and a multi- sourced interrupt. Each 1/O pin has software selectable op- tions to adapt the COP820C and COP840C to the spacific application. The part operates over a voltage range of 2.5 to 6.0V. High throughput is achieved with an efficient, regular instruction set operating at a 1 microsecond per instruction rate. The part may be operated in the ROMless mode to provide for accurate emulation and for applications requiring external program memory. Features a Low Cost 8-bit microcontroller w Fully static CMOS m 1 us instruction time (20 MHz clock) @ Low current drain (2.2 mA at 3 ys instruction rate} Low current static HALT mode (Typically < 1 pA) m Single supply operation: 2.5 to 6.0V @ 1024 bytes ROM/64 Bytes RAMCOP820C m@ 2048 bytes ROM/128 Bytes RAMCOPS840C w 16-bit read/write timer operates in a variety of modes Timer with 16-bit auto reload register 16-bit external event counter Timer with 16-bit capture register (selectable edge) @ Multi-source interrupt Reset master clear External interrupt with selectable edge Timer interrupt or capture interrupt Software interrupt 8-bit stack pointer (stack in RAM) Powerful instruction set, most instructions single byte BCD arithmetic instructions MICROWIRE PLUS serial [/O 28 pin package (cptionally 24 or 20 pin package) 24 input/output pins (28-pin package) Software selectable |/O options (TRIFSTATE, push- pull, weak pull-up) Schmitt trigger inputs on Port G Temperature ranges: 40C to +85C, +125C ROMless mode for accurate emulation and external program capabilityexpandable to 32k bytes in ROM- less mode mg Form, (COP8720C} m Piggyback emulation devices (COP820CP/COP840CP) wg Fully supported by Nationals MOLET development system -56C to fit and function EEPROM emulation device Block Diagram cxl RESET vec GND ROM RAM $4 + + clock eS 16=BIT TMER/COUNTER > INTERRUPT [Eee comm] | | Cosas] Cur] ["Letinnens J | srmot - + t t bh i. a hm * a Pu - REGISTERS So] wicrowne |S! A alu PLUS te Xt eX y y | SP \ OUTPUTS yo INPUTS 4 CNTRL vo v 1 PSW INSTRUCTION 4 DECODER PORT L PORT 0 PORT G PORT | TL/DD/ 9103-1 FIGURE 1 9Z$8d09/D1 8d09/908d09/D278d09/91.78d09/90%8d09/92'9d09/91-$9d09/90'9d09/9229d09/9129d09/9029d09COP620C/COP621C/COP622C/COP640C/COP641C/COP642C/COP820C/COP821C/COP822C/COP840C/COP841C/ COP842C COP820C/COP821C/COP822C/COP840C/COP841C/COP842C Absolute Maximum Ratings (f Military/Aerospace specified devices are required please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (Voc) 7V Total Current out of GND Pin (Sink) 60 mA Storage Temperature Range 65C to + 140C Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electri- cal specifications are not ensured when operating the de- Voltage at any Pin ESD Susceptibility (Note 4) Total Current into Voc Pin (Source) 0.3V to Veg + 0.3V 2000V vice at absolute maximum ratings. 50 mA DC Electrical Character istics 4o-c < Ta < + 85C unless otherwise specified Parameter Condition Min Typ Max Units Operating Voltage 2.5 6.0 Vv Power Supply Ripple (Note 1) Peak to Peak 0.1 Voc V Supply Current High Speed Moce, CKI = 20 MHz Voc = 6V, te = 1 us 9 mA Normal Mode, CKI = 5 MHz Voc = 6V, tc = 2s 4 mA Normal Mode, CKI = 2 MHz Voc = 2.5V, te = 5 ys 0.7 mA (Note 2) HALT Current Voc = 6V, CKI = 0 MHz <4 10 pA (Note 3) Input Levels RESET, CKI Logic High 0.9 Voc Vv Logic Low 0.1 Veo v All Other Inputs Logic High 0.7 Voc Vv Logic Low 0.2 Voc v Hi-Z Input Leakage Veco = 6.0V -2 +2 pA Input Pullup Current Voc = 6.0V 40 250 pA G Port Input Hysteresis 0.05 Voc Vv Output Current Levels D Outputs Source Veco = 4.5V, Vow = 3.8V 0.4 mA Veco = 2.5V, Vou = 1.8V 0.2 mA Sink Voc = 4.5V, Vor = 1.0V 10 mA Voc = 2.5V, VoL = 0.4V 2 mA All Others Source (Weak Pull-Up) Voc = 4.5V, Voy = 3.2V 10 110 BA Voc = 2.5V, Voy = 1.8V 25 33 pA Source (Push-Pull Mode) Voc = 4.5V, Von = 3.8V 0.4 mA Voc = 2.5V, Vou = 1.8V 0.2 Sink (Push-Pull Mode) Voc = 4.5V, VoL = 0.4V 1.6 mA Voc = 2.5V, VoL = 0.4V 0.7 TRI-STATE Leakage 2.0 +2.0 pA Allowable Sink/Source Current Per Pin D Outputs (Sink) 15 mA All Others 3 mA Maximum Input Current (Note 5) Without Latchup (Room Temp) Room Temp +100 mA RAM Retention Voltage, Vr 500 ns Rise and Fall Time (Min) 2.0 Vv Input Capacitance 7 pF Load Capacitance on D2 1000 pF Note 1: Rate of voltage change must be less than 0.5V/ms. Note 2; Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open. Note 3: The HALT mode will stop CKI from oscillating in the RC and the C and tied to ground, all outputs low and tied to ground. Note 4: Human body mode, 100 pF through 150020. Note 5: Except pins G6, G7, RESET pins G6, RESET: +60mA, 100mA pin G7: +100 mA, 25 mA Sampled but not 100% tested. rystal configurations. Test conditions: All inputs tied to Vcc, L and G ports TRISTATE 2-8COP820C/COP821C/COP822C/COP840C/COP841C/COP842C AC Electrical Characteristics 40c < T, < +85C unless otherwise specified Parameter Condition Min Typ Max Units Instruction Cycle Time (tc) High Speed Mode Voc = 4.5V 1 pc ps (Div-by 20) 2.5V < Voc < 4.5V 2.5 DC ps Normal Mode Voc 2 4.5V 2 DBC ys (Div-by 10) 2.5V < Voc < 4.5V 5 DC ps R/C Oscillator Mode Voc 2 4.5V 3 DC BS (Div-by 10) 2.5V < Voc < 4.5V 7.5 DC BS CKI Clock Duty Cycle (Note 6) fr = Max (+ 20 Mode) 33 66 % Rise Time (Note 6) fr = 20 MHz Ext Clock 12 ns Fall Time (Note 6) fr = 20 MHz Ext Clock 8 ns Inputs tsETUP Voc 2 4.5V 200 ns 2.5V < Vcc < 4.5V 500 ns tHoLD Voc = 4.5V 60 ns 2.5V < Voc < 4.5V 150 ns Output Propagation Delay GL = 100 pF, RL = 2.2kn tpp1, tppo $0, SK Voc 2 4.5V 0.7 ps 2.5V < Voc < 4.5V 1.75 ps All Others Voc 2 4.5V 1 ps 2.5V < Vcc < 4.5V 2.5 pS MICROWIRET Setup Time (tuws) 20 ns MICROWIRE Hold Time (tuwn) 56 ns MICROWIRE Cutput Propagation Delay (tupp) 220 ns Input Pulse Width Interrupt Input High Time tc Interrupt Input Low Time tc Timer Input High Time tc Timer Input Low Time tc Reset Pulse Width 1.0 ps Note 6: Parameter sampled but nat 100% tested. AC Electrical Characteristics in Romiess Mode 40C < T, < 85C unless otherwise specified Parameter Condition Min Typ Max Units Instruction Cycle Time (tc) - High Speed Mode Voc 2 4.5V 2 DC ps (Div-by 20) 2.5V < Voc < 4.5V 5 DC ps Normal Mode Voc 2 4.5V 4 DC ps (Div-by 10) 25V < Voc < 4.5V 10 DC Bs R/C Oscillator Mode Voc = 4.5V 6 DC ps 2.5V < Voc < 4.5V 15 DC ps CKI Clock Duty Clock fr = Max (+ 20 Mode) 40 60 % Rise Time fr = 10 MHz Ext Clock 24 ns Fall Time fr = 10 MHz Ext Clock 16 ns Inputs isetuP Voc 2 4.5V 400 ns 25V < Voc < 4.5V B00 ns tHOLD Voc 2 4.5V 120 ns 2.5V < Voc < 4.5V 300 ns Output Propagation Delay Cy. = 100 pF, RL = 2.2k tpp1, tppo SO, SK Voc 2 4.5V 1.4 ps 2.5V < Voc < 4.5V 3.5 BS All Others Voc 2 4.6V 2 pS 2,5V < Voc < 4.5V 5 ps Minimum Pulse Width Interrupt Input tc Timer Input te Reset Pulse Width 1.0 ps 9Zb8dOD/D18dO0D/20'8d00/97278d09/91Z78d09/9078d09/97'9d09/91-F9d09/90P9d09/9229d09/9129d09/9029d09COP620C/COP621C/COP622C/COP640C/COP641C/COP642C/COP820C/COP821C/COP822C/COP840C/COP841C/COP842C COP620C/COP621C/COP622C/COP640C/COP641C/COP642C Absolute Maximum Ratings if Military/Aerospace specified devices are required, Please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (Vcc) 6V Voltage at any Pin 0.3V to Voc + 0.3V ESD Susceptibility (Note 4) 2000V Total Current into Vcc Pin (Source) 40 mA Total Current out of GND Pin (Sink) 48 mA Storage Temperature Range 65C to + 140C Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC elactri- cal specifications are not ensured when operating the de- vice at absolute maximum ratings. DC Electrical Characteristics ss-c < 1, < +125C unless otherwise specified Parameter Condition Min Typ Max Units Operating Voltage 4.5 5.5 Vv Power Supply Ripple (Note 1) Peak to Peak 0.1 Veco Vv Supply Current High Speed Mode, CKI = 18 MHz Voc = .5V, te = 1.1 ys 16 mA Normal Mode, CKI = 4.5 MHz Voc = 5.5V, tc = 2.2 ws 5 mA {Note 2) HALT Current Voo = .5V, CKI = 0 MHz <10 30 pA (Note 3} Input Levels RESET, CKI Logic High 0.9 Vcc Vv Logic Low 0.1 Voc v Ail Other Inputs Logic High 0.7 Voc Vv Logic Low 0.2 Voc Vv Hi-Z Input Leakage Voc = 5.5V 5 +5 BA input Pullup Current Voc = 4.5V 35 300 pA G Port input Hysteresis 0.05 Voc Vv Output Current Levels D Outputs Source Voc = 4.5V, Vou = 3.8V 0.35 mA Sink Veco = 4.5V, VoL = 1.0V 9 mA All Others Source (Weak Pull-Up) Veco = 4.5V, Voy = 3.2V 9 120 pA Source (Push-Pull Mode) Voc = 4.5V, Vou = 3.8V 0.35 mA Sink (Push-Pull Mode) Voc = 4.5V, VoL = 0.4V 1.4 mA TRI-STATE Leakage 5.0 +5.0 pA Allowable Sink/Source Current Per Pin D Outputs (Sink) 12 mA All Others 2.5 mA Maximum Input Current (Room Temp) Without Latchup (Note 5) Room Temp +100 mA RAM Retention Voltage, Vr 500 ns Rise and Fall Time (Min) 2.5 Vv input Capacitance 7 pF Load Capacitance on D2 1000 pF Note 1: Rate of voltage change must be less than 0.5V/ms. Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open. Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: AN inputs tied to Voc, L and G ports TRI-STATE and tied to ground, all outputs low and tied to ground. Note 4: Human body mode, 100 pF through 15002. Note 5: Except pins G6, G7, RESET pins G6, +60 mA, ~ 100 mA pin G?: +100, 25 mA Sampled but not 100% tested. 2-10COP620C/COP621C/COP622C/COP640C/COP641C/COP642C AC Electrical Characteristics -ss-c < T, < +125C unless otherwise specified Parameter Condition Min Typ Max Units Instruction Cycle Time (tc) High Speed Mode Veco 2 4.5V 1.4 DC ps (Div-by 20) Normal Mode Veco = 4.5V 2.2 DC ps (Div-by 10) CKI Clock Duty Cycle fr = Max (+ 20 Mode) 33 66 % (Note 6) Rise Time (Note 6} fr = 18 MHz Ext Clock 12 ns Fail Time (Note 6) fr = 18 MHz Ext Clock 8 ns Inputs tsETUP Voc 2 4.5V 220 ns tHOLD Voc 2 4.5V 66 ns Output Propagation Delay R, = 2.2k, C, = 100 pF tpp1. tppa SO, SK Voc 2 4.5V 0.8 pS All Others Voc 2 4.5V 1.1 pS MICROWIRE Setup Time (tyuws) 20 ns MICROWIRE Hold Time (tywr) 56 ns MICROWIRE Output Valid Time (tupp) 220 ns Input Pulse Width Interrupt Input High Time tc Interrupt Input Low Time tc Timer Input High Time tc Timer Input Low Time te Reset Pulse Width 1 ys Note 6: Parameter sampled but not 100% tested. AC Electrical Characteristics in Romiess Mode 55C < Ta < + 125C unless otherwise specified Parameter Condition Min Typ Max Units Instruction Cycle Time (tc) High Speed Mode Voc = 4.5V 2.2 DG ps (Div-by 20) Normal Mode Voc = 4.5V 4.4 DC 4s {Div-by 10) CKI Clock Duty Clock fr = Max (+ 20 Mode) 40 60 % Rise Time fr = 9 MHz Ext Clock 24 ns. Fall Time fr = 9 MHz Ext Clock 16 ns Inputs tseTuP Voc = 4.5V 440 ns tHOLD Voc 2 4.5V 132 ns Output Propagation Delay Ry = 2.2k, CO, = 100 pF tpp1, tppo SO, SK Voc 2 4.5V 1.55 ps All Others Voc 2 4.5V 2.2 ps Minimum Pulse Width Interrupt Input tc Timer Input tc Reset Pulse Width 1 pS 2-11 JZP8d09/D1.8d02/20'8d09/2Z78d09/912Z8d09/D028d09/92'9d09/91P9d09/D0'9d09/9279d09/9129d09/9029d09COP620C/COP621C/COP622C/COP640C/COP641C/COP642C/COP820C/COP821C/COP822C/COP840C/COP841C/COP842C Timing Diagrams CKl (+20 MODE) cK {+10 MODE) >| trp e! tens MH we te _ | tpoo +| tps f > tpoo - DO, D1, D3 / \ setup ~ XE FIGURE 2a. AC Timing Diagrams In ROMiess Mode _ f-LS tuws tuwh Ss 50 - upp x TL/DD/0103-19 FIGURE 2b. MICROWIRE/PLUS Timing TL/DD/9103-2 2-12Connection Diagrams DUAL-IN-LINE PACKAGE 20 DIP 64/so|1 ad 20) 63/T0 G5/sK 42 19 f= G2 68 /si-1 3 18iG1 GT /CKO =] 4 17} GO/INT CKI=ES 16 |= Reset vec 46 15) GND lo47 1417 LB 13 }L6 w9 12Pt5 3410 11 Pa TL/DD/9103-3 Top View Order Number COP622C-XXX/D, COP&822C-XXX/N, COP842C-XXX/D or COP842C-XXX/N See NS Package Number D20A or N20A SURFACE MOUNT 20 SO Wide J 2063/T0 19 F G2 189 G1 17/co/inT p> RESET 15 = GND 1417 13%L 12-15 me L4 g l So Oo OF bk No = a G | = TL/BD/9103-3 Top View Order Number COP822C-XXX/WM or COP842C-XXX/WM See NS Package Number M20B cops22c COPs42c =] kK) CKil-| RESET PORT G home INTR cKO MICROWIRE/PLUS TL/DD/9103-6 24 DIP G4/sof1 ed 24) 63/TIO 65/skK42 23- G2 C6/SIVS 22-61 G7 /CKO 44 21 |= GO/INT Kis 20 | RESET OC 16 19} GND o-47 +8/ D3 isda 17 = 00 Log 16).7 Lito 15 f= L6 Laa11 14,15 L312 13;L4 TL/DD/9109-4 Order Number COP821C-XXX/D, COP821C-XXX/N, COP841C-XXX/D or COP841C-XXX/N See NS Package Number D24C or N24A 24 SO Wide G4/sot1 24; G3/TI0 5/SK42 23 ; G2 G6/SI-13 22;41 G7/CKO =44 21 f= GO/INT cKi-45 20 f RESET vec 46 19 GND \o47 18 f= D3 13-48 17]|00 Lo49 16 L7 ii fio 151L6 ait 14FL5 isi 137-L4 TL/DD/9103-4 Order Number COP821C-XXX/WM or COPB41C-XXX/WM See NS Package Number M24B copse21c CoPs4ic PORT | veC{ = PORT D [p> GID =| CKi = PORT RESET = PORT & INTR Ko MICROWIRE/PLUS TL/DD/S103-7 FIGURE 3 28 DIP ca/so41 ol 28) 3/T10 G5/SK ~42 27 = G2 G6/SI43 26,61 67/CKO <4 4 25 f= CO/INT CK ES 24 f= RESET vec 46 23} GND lod? 22; D3 11-48 21 b= b2 1z49 20/Di 13410 19/po tot 18). Lid42 1716 2413 16715 L3414 15La TL/DD/9103-5 Order Number COP820C-XXX/D, COP820C-XXX/N, COP640C-XXX/D or COP840C-XXX/N See NS Package Number D2s6C or N26B 28 PLCC $228 eee os 32 1 28 27 26 cKla5 255 60/INT Vor =] 6 24 p= RESET io-47 23) GND Hs 22 D3 9 21;F D2 3410 20-01 Lod 19} bo 12 13 14 15 16 17 18 S393 8885 TL/OD/9103-18 Order Number COP820C-XXX/V or COPB40C-XXX/V See NS Package Number V28A cop20c coPps40c PORT | VOC] PORT D 7 ono C1 pow KF RESET = PORT G NTR Ko MICROWIRE/PLUS TL/DD/9109-8 2. _ 3 92'8d09/91b8d09/D0%8d09/9278d09/9128d09/9078d090/9279d09/91 9d09/30F9d09/9229d09/91-29d00/9029d09COP620C/COP621C/COP622C/COP640C/COP641C/COP642C/COP820C/COP821C/COP822C/COP840C/COP841C/COP842C Pin Descriptions Vcc and GND are the power supply pins. CKI is the clock input. This can come from an external source, a R/C generated oscillator or a crystal (in conjunc- tion with CKO). See Oscillator description. RESET is the master reset input. See Reset description. PORT | is a four bit Hi-Z input port. PORT L is an 8-bit 1/0 port. There are two registers associated with each L I/O port: a data register and a configuration register. Therefore, each L I/O bit can be individually configured under software control as shown below: Port L Port L Port L Contig. Data Setup 0 0 Hi-Z Input (FRI-STATE) 0 1 Input With Weak Pull-Up 1 0 Push-Pull 0 Output 1 1 Push-Pull 1 Output Three data memory address locations are allocated for these ports, one for data register, one for configuration reg- ister and one for the input pins. PORT G is an 8-bit port with 6 [/O pins (GOG5) and 2 input pins (G6, G7). All eight G-pins have Schmitt Triggers on the inputs. The G7 pin functions as an input pin under normal operation and as the continue pin to exit the HALT mode. There are two registers with each |/O port: a data register and a configuration register. Therefore, each I/O bit can be individually configured under software control as shown be- low. PortG PortG PortG Config. Data Setup 0 0 Hi-Z Input (TRI-STATE) 0 1 Input With Weak Pull-Up 1 0 Push-Pull 0 Output 1 1 Push-Pull 1 Output Three data memory address locations are allocated for these ports, one for data register, one for configuration reg- ister and one for the input pins. Since G6 and G7 are input only pins, any attempt by the user to set them up as outputs by writing a one to the configuration register will be disre- garded. Reading the G6 and G7 configuration bits will return zeros. Note that the chip will be placed in the HALT mode by setting the G7 data bit. Six bits of Port G have alternate features: GO INTR (an external interrupt) G3 TIC (timer/counter input/output) G4 SO (MICROWIRE serial data output) G5 SK (MICROWIRE clock I/O) GB SI (MICROWIRE serial data input) G7 CKO crystat oscillator output (selected by mask option) or HALT restart input (general purpose input) Pins G1 and G2 currently do not have any alternate func- tions. PORT 0 is a four bit output port that is set high when RESET goes low. The D2 pin is sampled at reset. If it is held low at reset the COP&20C/COP840C enters the ROMless mode of opera- tion. Functional Description Figure 7 shows the block diagram of the internal architec- ture. Data paths are illustrated in simplified form to depict how the various logic elements communicate with each oth- er in implementing the instruction set of the device. ALU AND CPU REGISTERS The ALU can do an 8-bit addition, subtraction, logical or shift operation in one cycle time. There are five CPU registers: Ais the 18-bit Program Counter register PU is the upper 7 bits of the program counter (PC) Pi is the lower 8 bits of the program counter (PC) B is the 8-bit address register, can be auto incremented or decremented. X is the 8-bit atternate address register, can be incremented or decremented. SP is the 8-bit stack pointer, points to subroutine stack (in RAM). B, X and SP registers are mapped into the on chip RAM. The B and X registers are used to address the on chip RAM. The SP register is used to address the stack in RAM during Subroutine calls and returns. PROGRAM MEMORY Program memory for the COP820C consists of 1024 bytes of ROM (2048 bytes of ROM for the COP840C). These bytes may hold program instructions or constant data. The program memory is addressed by the 15-bit program coun- ter (PC). ROM can be indirectly raad by the LAID instruction for table lookup. DATA MEMORY The data memory address space includes on chip RAM, I/O and registers. Data memory is addressed directly by the in- struction or indirectly by the B, X and SP registers. The COP820C has 64 bytes of RAM and the COP840C has. 128 bytes of RAM. Sixteen bytes of RAM are mapped as registers that can be loaded immediately, decremented or tested. Three specific registers: B, X and SP are mapped into this space, the other bytes are available for general usage. The instruction set permits any bit in memory to be set, reset or tested. All 1/O and registers (except the A & PC) are memory mapped; therefore, |/O bits and register bits can be directly and individually set, raset and tested. RESET The RESET input when pulled low initializes the microcon- troller, Initialization will occur whenever the RESET input is pulled low. Upon initialization, the ports L and G are placed in the TRI-STATE mode and the Port D is set high. The PC, PSW and CNTARL registers are cleared. The data and con- figuration registers for Ports L & G are cleared. The external RC network shown in Figure 4 should be used to ensure that the RESET pin is held low until the power supply to the chip stabilizes, 2-14Functional Description (continued Vcc rues VMEOV + TL/DD/9103-9 AC = 5X Powar Supply Rise Time FIGURE 4. Recommended Reset Circuit OSCILLATOR CIRCUITS Figure & shows the three clock oscillator configurations available for the COP820C and COP840C. A. CRYSTAL OSCILLATOR The COP820C/COPS840C can be driven by a crystal clock. The crystai network is connected between the pins CKI and CKO. Table | shows the component values required for various standard crystal values. B. EXTERNAL OSCILLATOR CKI can be driven by an external clock signal. CKO is avail- able as a general purpose input and/or HALT restart con- trol. . GC. R/C OSCILLATOR CKI is configured as a single pin RC controlled Schmitt trig- ger oscillator. CKO is available as a general purpose input and/or HALT restart control. Table || shows the variation in the oscillator frequencies as functions of the component (R and C) values. Cki ckKo { RESTART SJ EXTERNAL CLOCK c ckl cko v ee a T TL/DD/9103-10 FIGURE 5. Crystal and R-C Connection Diagrams OSCILLATOR MASK OPTIONS The COP820C and COP840C can be driven by clock inputs between DC and 20 MHz. For low input clock fraquencies (s 5 MHz) the instruction cycle frequency can be selected to be the input clock frequency divided by 10. This mode is known as the Normal Mode. For oscillator frequencies that are greater than 5 MHz the chip must run with a divide by 20. This is known as the High Speed mode. TABLE I. Crystal Oscillator Configuration, Ta = 25C R1 R2 Ci C2 CKI Freq Conditions (kQ) (MQ) (PF) (pF) (MHz) 0 { 30 30-36 20 Veco = 5V 0 1 30 30-36 10 Voc = 5V 0 1 30 30-36 4(+ 20) Voc = 2.5V 0 1 200 100-450 0.455 Voc = 2.5V TABLE It. RC Oscillator Configuration, Ta = 25C R CG CKI Freq. instr. Cycle Conditions {kQ) (PF) (MHz) {8) 3.3 82 2.8 to 2.2 3.6 to 4.5 Voc = 5V 5.6 100 1.5to1.1 6.7 to9 Voc = BV 6.8 100 1.1 to 0.8 9to 12.5 Voc = 2.5V 2-15 J2r8dO9/D1 P8dO9/D0F8dOD/9228dO9/91-28dO9/9028dO9/9279d09/91-49d09/90'9d09/9229d09/9129d09/9079d09COP620C/COP621C/COP622C/COP640C/COP641C/COP642C/COP820C/COP821C/COP822C/COP840C/COP841C/COP842C Functional Description (Continued) Tne COP820C and COP840C microcontrollers have five mask options for configuring the clock input. The CKI and CKO pins are automatically configured upon selecting a par- ticular option. High Speed Crystal (CKI/20) CKO for crystal configura- tion Normal Mode Crystal (CKI/10) CKO for crystal contigu- ration High Speed External (CKI/20) CKO available as G7 in- put Normal Mode External (CKI/10) CKO available as G7 input R/C (CKI/10) CKO available as G7 input G7 can be used either as a general purpose input or as a contrel input to continue from the HALT mode. CURRENT DRAIN The total current drain of the chip depends on: 1) Oscillator operating model1 2) Internal switching currentl2 3) Internal leakage currenti3 4) Output source currenti4 5) DC current caused by external input not at Voc or GND 15 Thus the total current drain, It is given as t=4+ 12+ 18+14+15 To reduce the total currant drain, each of the above compo- nents must be minimum. The chip will draw the least current when in the normal mode. The high speed mode will draw additional current. The A/G mode will draw the most. Operating with a crystal network will draw more current than an external square- wave. Switching current, governed by the equation below, can be reduced by lowering voltage and frequency. Leak- age current can be reduced by lowering voltage and tem- perature. The other two items can be reduced by carefully designing the end-users system. l2@=CxVxf Where C = equivalent capacitance of the chip. V = operating voltage f = CKI frequency Some sample current drain values at Voc = 6V are: CKI (MHz) Inst. Cycle (us) . It (mA) 20 1 Q 3.58 3 2.2 2 5 1.2 0.3 33 0.2 0 (HALT) <0.0001 HALT MODE The COP820C and COP840 support a power saving mode of operation: HALT. The controller is placed in the HALT mode by setting the G7 data bit, alternatively the user can stop the clock input. In the HALT mode all internal proces- sor activities including the clock oscillator are stopped. The fully static architecture freezes the state of the control- ler and retains all information until continuing. In the HALT mode, power requirements are minimal as it draws only leakage currents and output current. The applied voltage (Vcc) may be decreased down to Vr (minimum RAM reten- tion voltage) without altering the state of the machine. There are two ways to exit the HALT mode: via the RESET or by the CKO pin. A low on the RESET line reinitializes the microcontroller and starts executing from the address O000H. A low to high transition on the CKO pin causes the microcontroller to continue with no reinitialization from the address following the HALT instruction. This also resets the G7 data bit. INTERRUPTS The COP820C and COP840C have a sophisticated interrupt structure to allow easy interface to the real word. There are three possible interrupt sources, as shown below. A maskable interrupt on external GO input (positive or nega- tive edge sensitive under software control) A maskable interrupt on timer carry or timer capture A non-maskable software/error interrupt on opcode zero INTERRUPT CONTROL The GIE (global interrupt enable) bit enables the Interrupt function. This is used in conjunction with ENI and ENT! to select one or both of the interrupt sources. This bit is reset when interrupt is acknowledged. ENI and ENTI bits select external and timer interrupt re- spectively. Thus the user can select either or both sources to interrupt the microcontroller when GIE is enabled. IEDG selects the external interrupt edge (0 = rising edge, 1 = falling edge}. The user can get an interrupt on both rising and falling edges by toggling the state of IEDG bit after each interrupt. IPND and TPND bits signal which interrupt is pending. After interrupt is acknowledged, the user can check these two bits to determine which interrupt is pending. This permits the interrupts to be prioritized under software. The pending flags nave to be cleared by the user. Setting the GIE bit high inside the interrupt subroutine allows nested interrupts. The software interrupt does not reset the GIE bit. This means that the controller can be interrupted by other inter- rupt sources while servicing the software interrupt. INTERRUPT PROCESSING The interrupt, once acknowledged, pushes the program counter (PC) onto the stack and the stack pointer (SP) is decremented twice. The Giobal Interrupt Enable (GIE) bit is reset to disable further interrupts. The microcontroller then vectors to the address OOFFH and resumes execution from that address. This process takes 7 cycles to complete. At the end of the interrupt subroutine, any of the following three instructions return the processor back to the main pro- gram: RET, RETSK or RETI. Either one of the three instruc- tions will pop the stack into the program counter (PC). The stack pointer is then incremented twice. The RETI instruc- tion additionally sets the GIE bit to re-enable further inter- rupts. Any of the three instructions can be used to return from a hardware interrupt subroutine. The RETSK instruction should be used when returning from a software interrupt subroutine to avoid entering an infinite loop. 2-16Functional Description (continued EXTERNAL TER TPND ENT i [ Gie ] PND INT. PIN] Hr C UNDERFLOW SOFTWARE De 10 INTERRUPT LOGIC INTERRUPT TL/DD/9103-11 FIGURE 6. Interrupt Block Diagram DETECTION OF ILLEGAL CONDITIONS The COP820C and COP840C incorporate a hardware mechanism that allows it te detect illegal conditions which may occur from coding errors, noise and brown out voltage drop situations. Specifically it detects cases of executing out of undefined ROM area and unbalanced stack situations. Reading an undefined ROM location returns CO (hexadeci- mai) as its contents. The opcode for a software interrupt is also 00. Thus a program accessing undefined ROM will cause a software interrupt. Reading an undefined RAM location retums an FF (hexade- cimal). The subroutine stack on the COP820C and COP840C grows down for each subroutine call. By initializ- ing the stack pointer to the top of RAM, tha first unbalanced return instruction will cause the stack pointer to address undefined RAM. As a result the program will attempt to exe- cute from FFFF (hexadecimal), which is an undefined ROM location and will trigger a software interrupt. MICROWIRE/PLUST MICROWIRE/PLUS is a serial synchronous bidirectional communications interface. The MICROWIRE/PLUS capabil- ity enables the COP820C and COPS840C to interface with any of National Semiconductor's MICROWIRE peripherals (i.e. A/D converters, display drivers, EEPROMS, etc.) and with other microcontrollers which support the MICROWIRE/ PLUS interface. It consists of an 8-bit serial shift register (SIO) with seriat data input (SI), serial data output (SO) and serial shift clock (SK). Figure 7 shows the block diagram of the MICROWIRE/PLUS interface. The shift clock can be selectad from either an internal source or an external source. Operating the MICROWIRE/ PLUS interface with the internal clock source is called the Master mode of operation. Similarly, operating the MICRO- WIRE/PLUS interface with an external shift clock is called the Slave mede of operation. The CNTRL register is used to configure and control the MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS , the MSEL bit in the CNTRL register is set to one. The SK clock rate is selected by the two bits, SO and S1, in the CNTRL register. Tabie Ill details the different clock rates that may be selected. TABLE Ili SK Cycle Time 2tc $1 $0 0 1 4tc x 0 4) 1 8tc where, tc is the instruction cycle clock. MICROWIRE/PLUS OPERATION Setting the BUSY bit in the PSW register causes the MI- CROWIRE/PLUS arrangement to start shifting the data. It gets reset when eight data bits have been shifted. The user may resat the BUSY bit by software to allow less than 8 bits to shift. The COP820C and COP840C may enter the MI- CROWIRE/PLUS mode sither as a Master or as a Slave. Figure & shows how two COP820C microcontrollers and several peripherals may be interconnected using the MI- CROWIRE/PLUS arrangement. Master MICROWIRE/PLUS Operation In the MICROWIRE/PLUS Master mode of operation the shift clock (SK) is generated internally by the COP820C. The MICROWIRE/PLUS Master always initiates all data ex- changes. (See Figure 8). The MSEL bit in the CNTRL regis- ter must be set to enable the SO and SK functions onto the G Port. The SO and SK pins must also be selected as out- puts by setting appropriate bits in the Port G configuration register. Table IV summarizes the bit settings required for Master mode of operation. SLAVE MICROWIRE/PLUS OPERATION in the MICROWIRE/PLUS Slave mode of operation the SK clock is generated by an external source. Setting the MSEL bit in the CNTRL register enabies the SO and SK functions onto the G Port. The SK pin must be selected as an input and the SO pin is selected as an output pin by appropriately setting up the Port G configuration register. Table IV sum- marizes the settings required to enter the Slava mode of operation. The user must set the BUSY flag immediately upon entering the Slave mode. This will ensure that all data bits sent by the Master will be shifted properly. After sight clack pulses the BUSY flag will be claared and the sequence may be repeated. (See Figure 4.) 2-17 Jer8dO9/91 8d09/D0b8dO9/9278dOD/91728dO9/9028d09/9ZP9d09/91- P9d09/D0h9d09/9229d09/51-29d09/3079d09COP620C/COP621C/COP622C/COP640C/COP641C/COP642C/COP820C/COP821C/COP822C/COP840C/COP841C/COP842C Functional Description (continued) TABLE IV G4 Gs G4 GS | G6 Contig. | Config. Fun Fun. | Fun Operation BE Bit \. . \. 1 1 so Int. SK | SI 7 MICROWIRE Master 0 1 TRI-STATE | int. SK | S! | MICROWIRE Master t 0 so Ext. SK] SI | MICROWIRE Slave 0 0 TRI-STATE | Ext. SK] SI | MICROWIRE Slave TIMER/COUNTER The COP820C and COP840C have a powerful 16-bit timer with an associated 16-bit register enabling them to perform extensive timer functions. The timer T1 and its register R1 are each organized as two 8-bit read/write registers. Controi bits in the register CNTRL allow the timer to be started and stopped under software control. The timer-register pair can be operated in one of three possible modes. Table V details various timer operating modes and their requisite control settings. = so 8- BIT SIO si D RecsTeR Jo A T SHIFT CLOCK A y CLOCK U 2 s| 7 L_- setect [* > * > CRTRL TL/DD/9103-12 FIGURE 7. MICROWIRE/PLUS Block Diagram MODE 1. TIMER WITH AUTO-LOAD REGISTER In this mode of operation, the timer T1 counts down at the instruction cycle rate. Upon underflow the value in the regis- ter R1 gets automatically reloaded into the timer which con- tinues to count down. The timer underflow can be pro- grammed to interrupt the microcontroller. A bit in the control register CNTRL enables the TIO (G3) pin to toggle upon timer underflows. This allow the generation of square-wave outputs or pulse width modulated outputs under software contral. (See Figure 9) MODE 2. EXTERNAL COUNTER In this mode, the timer T1 bacomes a 16-bit external event counter. The counter counts down upon an edge on the TIO pin. Control bits in the register CNTRL program the counter to decrement either on a positive edge or on a negative edge. Upon underflow the contents of the register R1 are automaticaly copied into the counter. The underflow can also be programmed to generate an interrupt. (See Figure 9) MODE 3. TIMER WITH CAPTURE REGISTER Timer T1 can be used to precisely measure external fre- quencies or events in this mode of operation. The timer T1 counts down at the instruction cycle rate. Upon the occur- rence of a specified edge on the TIO pin the contents of the timer T1 are copied into the register A1. Bits in the control register CNTRL allow the trigger edge to be specified either as a positive edge or as a negative edge. in this mode the user can elect to be interrupted on the specified trigger edge. (See Figure 10.) CHIP SELECT LINES q [ ts cs cs cs cs \/o Low Vi 0 LINES = COP 8- BIT 1024- Bit POWER FREQ. LoD cop | LINES 820 A/D CON= EEPROM cMos GEN. & DISPLAY 820C (MASTER) VERTER copags RAM COUNTER DRIVER (SLAVE) COPA3X & TIMER COPAS2L cop472 cops po pick | [po oiciK | Loo oicix | foo pick DI CLK a & a + ah A A A a - sike 5 y y 50 so + - SI SK aed ISK FIGURE 8. MICROWIRE/PLUS Application TL/DD/9103-13 2-18Functional Description (Continued TABLE V. Timer Operating Modes CNTRL Timer Bits Operation Mode T Interrupt Counts 765 On 000 External Counter W/Auto-Load Reg. Timer Carry TIO Pos. Edge 001 External Counter W/Auto-Load Reg. Timer Carry TIO Neg. Edge 010 Not Allowed Not Allowed Not Allowed 011 Not Alkowed Not Allowed Not Allowed 100 Timer W/Auto-Load Reg. Timer Carry tc 101 Timer W/Auto-Load Reg./Toggle TIO Out Timer Carry tc 110 Timer W/Capture Register TIO Pos. Edge tc 111 Timer W/Capture Register TIO Neg. Edge tc [ INTERNAL DATA BUS | TIMER PWM APPLICATION Zz Figure 1f shows how a minimal component D/A converter can be built out of the Timer-Register pair in the Auto-Re- load mode. The timer is placed in the Timer with auto re- 16-BIT AUTO TIMER load* made and the TIO pin is selected as the timer output. RELOAD REG. UNDERFLOW At the outset the TIO pin is set high, the timer T1 holds the INTERRUPT on time and the register R1 holds the signal off time. Setting TRUN bit starts the timer which counts down at the instruc- tion cycle rate. The underflow toggles the TIO output and i> 16 Garr MMER/ aan Me NTPUT copies the off time into the timer, which continues to run. By alternately loading in the on time and the off time at each TL/DD/9103-15 successive interrupt a PWM frequency can be easily gener- FIGURE 9. Timer/Counter Auto ated. Reload Mode Block Diagram wager | | tt oi} re > 16= eon CAPTURE REG. 16= BT THE TL/DD/9109-14 FIGURE 10. Timer Capture Mode Block Diagram A SIMPLE D-A CONVERTER USING THE TIMER TO GENERATE A PWM OUTPUT. ws Tv OND VOO TL/DD/9103-16 FIGURE 11. Timer Application 2-19 2278dOD/91 P8dOD/D0F8d0D/9228dO9/91Z8d09/9028dO9/92F9d09/91 F9d09/D009d09/9229d09/9129d09/9029d09 aCOP620C/COP621C/COP622C/COP640C/COP641C/COP642C/COP820C/COP821C/COP822C/COP840C/COP841C/COP842C Control Registers CNTRL REGISTER (ADDRESS X00EE) The Timer and MIGROWIRE/PLUS control register contains the following bits: $1&S0 Select the MICROWIRE/PLUS clock divide-by IEDG External interrupt edge polarity select (0 = rising edge, 1 = falling edge) MSEL Enable MICROWIRE/PLUS functions SO and SK TRUN Start/Stop the Timer/Counter (1 = run, 0 = stop) TC3 Timer input edge polarity select (0 = rising edge, 1 = falling edge) TG2 Selects the capture mode TGi Selects the timer mode [ tc1 | tc2| 103 | TauN| mseL| 1eoa | si} so | BIT7 BIT 0 PSW REGISTER (ADDRESS X00EF) Thea PSW register contains the following select bits: GIE Global interrupt enable ENI External interrupt enable BUSY MICROWIRE/PLUS busy shifting IPND = External interrupt pending ENTI Timer interrupt enable TPND Timer interrupt pending Cc Carry Flag HC Half carry Flag | Hc | c] Teno | enti | tend | Busy | EN! | ie | Bit7 Bito Operating Modes These controllers have two operating modes: Single Chip mode and the ROMless mode. The operating mode is deter- mined by the state of the D2 pin at power on reset. SINGLE CHIP MODE In the Single Chip mode, the controller functions as a self contained microcontroller. it can address internal RAM and ROM. All ports configured as memory mapped I/O ports. ROMLESS MODE The COP820C and COP840C enter the ROMless mode of operation if the D2 pin is held at logical 0 at reset. In this case the internal ROM is disabled and the controller can now address up to 32 kbytes of external program memory. In the ROMless mode of operation, the COP820C uses the 64 bytes of onboard RAM and the COP840C uses the 128 bytes of onboard RAM. The ports D and { are used to ac- cess the external program memory. By providing a serial interface to external program memory, a large address space can be managed without the penalty of losing a large number of I/O pins in the process. Figure 12 shows in sche- matic form the logic required for the ROMless mode opera- tion and all support logic required to recreate the 1/0. Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space. Address Contents COP&20C 00 to 2F |On Chip RAM Bytes 30 to 7F |Unused RAM Address Space (Reads as all Ones} COPs40Cc 00 to 6F |On Chip RAM Bytes 70 to 7F | Unused RAM Address Space (Reads as all Ones) COP820C and COP840C 80 to BF |Expansion Space for on Chip EERAM CO to CF|Expansion Space for {/O and Registers DO to DF/On Chip I/O and Registers DO |Port L Data Register Di {Port L Configuration Register D2 = |PortL Input Pins (Read Only) D3 =| Reserved for Port L D4 = {Port G Data Register D5 =| Port G Configuration Register D6 =| Port G input Pins (Read Only} D7 | Port| Input Pins (Read Only) D8DB | Reserved for Port C DG Port D Data Register DD-DF |Reserved for Port D EC to EF |On Chip Functions and Registers E0-&7 |Reserved for Future Parts E& |Reserved ES |MICROWIRE/PLUS Shift Register EA _|Timer Lower Byte EB |Timer Upper Byte EC _|Timer Autoload Register Lower Byte ED__|Timer Autoload Register Upper Byte EE |CNTRAL Control Register EF |PSW Register FO to FF |On Chip RAM Mapped as Registers FG |X Register FD |SP Register FE |B Register Reading unused memory locations below 7FH will return alt ones. Reading other unused memory locations will return undefined data. Addressing Modes REGISTER INDIRECT This is the normal mode of addressing for COP820C and COP840C. The operand is the memory addressed by the 8 register or X register. DIRECT The instruction contains an 8-bit address field that directly points to the data memory for the operand. IMMEDIATE The instruction contains an 8-bit immediate field as the op- erand. REGISTER INDIRECT (AUTO INCREMENT AND DECREMENT) This is a register indirect mode that automatically incre- ments or decrements the B or X register after executing the instruction.COP620C/COP621C/COP622C/COP640C/COP641C/COP642C/COP820C/COP821C/COP822C/COP840C/COP841C/COP842C 2i-e01e/das1b DREWALYS SpOW SS3/WOH DOrsdOD Pus D0ZTBdOD TI JUNDIA (eep WOH 4 SUS) WLYGH OPO wus BIBG) 410 (Pop pecy) GVOIN (evep | Og peywennel Ul SINS) VVC! (yep q. y0d peyeesdeu Ino sys) NIG {epow sseyOY UI da oun Sind) ONS (9d 40 Sq uoAas Jeddn jno SYS) Nd (Od 40 Suiq 1yBe sean] INO SyIES) Td ZEIZTIAN nus5Sgaskso a B siesusseasaunsaanl 7v wm 8 BeSsBaeeIsIIII ASH st zl it o1 2-21COP620C/COP621C/COP622C/COP640C/COP641C/COP642C/COP820C/COP821C/COP822C/COP840C/COP841C/COP842C Addressing Modes (Continued) PC 15-bit Program counter register PU upper 7 bits of PC RELATIVE PL _ lower & bits of PC This mode is used for the JP instruction, the instruction field G 1-bit of PSW register for carry is added to the program counter to get the new program HG Half Carry location. JP has a range of from 31 to +32 to allow aone GIE _1-bit of PSW register for global interrupt enable byte relative jump (JP + 1 is implemented by a NOP instruc- tion). There are no pages when using JP, all 15 bits of PC Symbols . are used. iB] Memory indirectly addressed by B register . {x] Memory indirectly addressed by X register Instruction Set Mem Direct address memory or [B] REGISTER AND SYMBOL DEFINITIONS Meml Direct address memory or [B) or Immediate data Imm _8-bit Immediate data Regleters Reg Register memory: addresses FO to FF (Includes B, X A 8-bit Accumulator register and SP) B 8-bit Address register Bit Bit number (0 to 7) x 8-bit Address register < ___ Leaded with SP &-bit Stack pointer register < > Exchanged with Instruction Set ADD add A < A+ Mem ADC add with carry A A+ Meml+C,C < Cary HG < Half Carry SUBC subtract with cary A A+ Memi+C,C < Cary HC < Half Carry AND Logical AND A < Aand Memt OR Logical OR A < AorMeml xXOR Logical Exclusive-OR A < Axor Mem IFEQ IF equal Compare A and Mami, Do next if A = Mem! IFGT IF greater than Compare A and Mem, Do next if A > Mem! IFBNE IF B not equal Do next if lower 4 bits of B # Imm DRSZ Decrement Reg. ,skip if zero Reg Reg 1, skip if Rag goes ta 0 SBIT Set bit 1 to bit, Mem {bit= 0 to 7 immediate) RBIT Reset bit 0 to bit, Mem IFBIT if bit If bit, Mem is true, do next instr. x Exchange A with memory A + Mam LDA Load A with memory A < Meml LD mem Load Direct memory immed. Mem < Imm LD Reg Load Register memory Immed. Reg < Imm x Exchange A with memory [B] A <> [B] (B < Bt) x Exchange A with memory [X] A> DX) (K X+1) LDA Load A with memory [B] A<([B) (8B < B+1) LDA Load A with memory [x] A < [x] (X X+1) LDM Load Mamory Immediate {B] < tmm(B B+t1) CLRA Clear A A<-od INCA Increment A A<A+1 DECA Decrement A A<-A-1 LAID Load A indirect from ROM A - ROM(PU,A)} DCORA DEGIMAL CORRECT A A < BCD correction (follows ADC, SUBC) RACA ROTATE A RIGHT THAU G C A? ...7 AQ? C SWAPA Swap nibbles of A A7...A4 <> AS.:.A0 sc Set C Ge 1,HC < 1 RC Reset C C<0,HC 0 IFC lfc If C is true, do next instruction IFNG lf not Cc If C is not true, do next instruction JMPL Jump absolute long PC < ji(i = 15 bits, 0 to 32k) JMP Jump absolute PC11..0 < i(i = 12 bits} JP Jump relative short PG - PO + r(ris 31 to + 32, not 1) JSRL Jump subroutine long [SP] <- PL[SP-1] < PU,SP-2,PC < ij JSR Jump subroutine [SP] < PL{SP-1] < PU,SP-2,PC11..0 < i JID , Jump indirect PL < ROM(PU,A) RET Retum from subroutine SP+2,PL < [SP],PU < [SP-1] RETSK Return and Skip SP+2,PL < [SP],PU < [SP-1],Skip next instruction RETt Return from Interrupt SP+2,PL ~ [SP],PU < [SP-1],GIE < 1 INTA Generate an interrupt (SP] <- PL[SP1] < PU,SP-2,PC < OFF NOP No operation PG PC+ 1 2-22COP620C/COP621C/COP622C/COP640C/COP641C/COP642C/COP820C/COP821C/COP822C/COP840C/COP841C/COP842C Bits 3-0 OPCODE LIST (e198) Buimoyjo) ees) epoodo pesnun ue si! , uojeso] Aiowew pessesppe Ajjaoup & St Py Byep sjeipewul oy] ss | elOyM 4440-0040 | 4440-0040 fa)'2 | tale * 91 +df|2e+dr dwr usr dOANasI | O'8O1 } Ligy | lias |} ay 430 ZSHO | + #'45001]| 9I-d? | o-dt 4430-0030 | 4450-0030 [a]9 | [al9 '# [a] | [al (x] Sl+drile+dr dar usr AOSNes| + 807 | iigy | lias | 13y aq Vat! val | 340zZSud | #34007 | ZI-dt | tot 44q0-00c0 } 4400-0000 {al's | [al's Pw pl+df joe+dr die usr GOaNSs4!| zaqr | Lid | lias | slay} vaT | qusr|] uid | G40 ZSHa | !d4001 | 8I-df | ede 4490-0000 | 4400-0090 (aly | [a}'r * ; Ie et+df|6+de dir usr OO SNe4!| aan | Ligy | Lias PAY xX | Td | PAT | O40 ZSHC | !'04007 | 6l-dt | &- af 4480-0080 | 4180-0080 fale | [ale t#[-a@] | [-al | [-xl ai+dfj}ee+dr die usr g03Nesi | aqq | Ligu | lias | vosd qa VG1] VOI | a40ZSHC | !#'as001 | 02- df | & of dsvo-00ve | 44'v0-00vo lale | [a}'2 t#'[+9] |} [+9] } {+x] tLt+dfjzet+de dir ust VOSNas!| Sdqq | Ligdy | LiIgS | VON) a VaT| VOT | 4d0ZSHC | !#'vs007 | le-dt | Sd 4460-0060 | 3460-0060 fay) | [ale x + p ol + df |924+dr die ' usr S4Nes! | 9'aqq | Ligy | LiIas | ONdI 640 ZSHQ | !#'64001 | 2e-dr | ode 3480-0080 | 4380-0080 [a}o | [alo i# * 6+df |se+de dar usr saNnesd! | 4'aqy | Lligu | iias | Oz! vq dON | 840 ZSud | !#84001 | ee-dt |} Zo 4420-0020 | 4420-0020 la]2 | [I'v \ etd? |ret+ade dar usr ZaNadl | @'aqq Ligsl| HO vy HO 240 ZSHO | 1#'43001 | be- dt | ede 4430-0090 | 4390-0090 [al9 | [al'v \# [al [x] Z+df |+de dar usr 94NasI | 6'aq1 | VHOOd | LiasI| YOX | VHOX | Vx | VX | 930ZSHC | !'94001 | Se-df | 6dr - | dAg0-0060 | 4450-0050 fals | [s]V \# @+dr |z+dr dar usr SANs! | VO'a CT | VdvMS | Ligsl| ONy | VONV | air G40 ZSuC | 1#'S4007 | 9- df | OL- df A4v0-00%0 | 44h0-00%0 fai'y | [al'v \# * G+df|te+dc dar usr vangsi | go'aq1| vu1d j Liasl| day | vaav | aw P40 ZSHG | 1#PaOC | Ze of | bE- df dse0-0080 | 440-0060 | fale} falv \# [-a) |} (-x] yp+dr |oz+de dar usr 3Na4i | 90's digal | LOsal | Vaosl | Wx | VX | e4OzSHC } !#'e4007 | 8-dr | 2b df 4420-0020 | 3420-00Z0 (ale | fal'v \ (+a) | [+x] +dr |er+ar dir usr @ anges! | coam Liasl | O34) | VOSsI | VX | VX | 240ZSHO | !#'24007 | 62 df | eld? A4LO-0010 | 34L0-0010 * [alt | falv 1# * a@+d |est+de dar usr b3NSsI | 30'8q1 ligsl | O9NS | voans| OSs L430 ZSHO | !#'bd007 | 0&- dt | #l- dt 4400-0000 | 4400-0000 (a]o | [al \# MLNI | Zh +P dir usr ONS! | 40a Ligst | Voav | vodv | O8 | VOHH | 0J0ZSHO | !#'0J007 | le- dt | sid? 0 L z t r s 9 Z 8 6 v a 9 a 4 4 e-2 Sue 2-23COP620C/COP621C/COP622C/COP640C/COP641C/COP642C/COP820C/COP821C/COP822C/COP840C/COP841C/COP842C Instruction Execution Time BYTES and CYCLES per Most instructions are single byte (with immediate address- INSTRUCTION ing mode instruction taking two bytes). The following table shows the number of bytes and cycles Most single instructions take one cycle time (1 us at for each instruction in the format of byte/cycle (a cycle is 20 MHz) to execute. 1 ps at 20 MHz). See the BYTES and CYCLES per INSTRUCTION table for details. iB) Direct immed. ADD w1 3/4 2/2 ADG /1 3/4 2/2 SUBG Ww 3/4 2/2 AND W1 3/4 2/2 OR v1 3/4 2/2 XOR v4 3/4 2/2 \FEQ TAI a/4 2/2 iFGT 1/1 3/4 2/2 {FBNE v1 DRSZ 1/3 SBIT Wv/1 3/4 RBIT 1/1 3/4 (FBIT "1 3/4 Memory Transfer Instructions Register Register Indirect Indirect | Direct|Immed.| Auto Iner & Decr XA," 1/11/38) 2/3 1/2 1/3 LDA," 1/1 1/8) 2/3 2/2 1/2 V3 LD B,Imm 1/1 (ifB < 16) LD B,Imm 2/3 (lfB > 15) LD Mem,lmm| 2/2 3/3 2/2 LD Reg,|mm 2/3 * => Memory location addressed by B or X or directly. Instructions Using A & C Transfer of Control Instructions CLRA 1/1 JMPL 3/4 INCA /1 JMP 2/3 DECA 4 JP 1/3 LAID 1/3 JSAL 3/5 DCORA 1/4 JSR 2/5 RRACA 1/4 JID 1/3 SWAPA 1 RET 1/5 Sc 1/1 RETSK 1/5 RC 1/1 RETI 1/5 IFC /1 INTR 1/7 IFNC 1/4 NOP 1/1 2-24The following table shows the instructions assigned to un- used opcodes. This table is for information only. The opera- tions performed are subject to change without notice. Do not use these opcodes. Opeode instruction Oponde Instruction 60 NOP AQ NOP 61 NOP AF LD A, [B] 62 NOP Bi Cc HC 63 NOP B4 NOP 67 NOP B5 NOP 8C RET B7 XA, [xX] 99 NOP Bo NOP OF LD [B), #i BF LDA, [xX] A7 XA, [B] AS NOP Development Support MOLE DEVELOPMENT SYSTEM The MOLE (Microcomputer On Line Emulator) is a low cost development system and emulator for all micrecontroiler products. These include COPS and the HPC family of products. The MOLE consists of a BRAIN Board, Personali- ty Board and optional host software. The purpose of the MOLE is to provide the user with a tool to emulate code for the target microcontrolier and assist in both software and hardware debugging of the system. It is a self contained computer with its own firmware which provides for all system operation, emulation contrat, com- munication, PROM programming and diagnostic operations. It contains three serial ports to optionally connect to a termi- nal, a host system, a printer or a modem, or to connect to other MOLEs in a muiti-MOLE environment. MOLE can be used in either a stand alone mode or in con- junction with a selected host system using PC-DOS commu- nicating via a RS-232 port. Single Chip Emulator Device The COP820C is fully supported by a form, fit and function emulator device, the COP8720C. Option List The COP820C/COP840C mask programmable options are listed out below. The options are programmed at the same time as the ROM pattern to provide the user with hardware flexibility to use a variety of oscillator configuration. OPTION 1: CKI INPUT = 1 Norma! Mode Crystal (CKI/10) CKO for crystal con- figuration = 2 Normal Mode External (CKI/10) CKO available as G7 input (CKI/10) CKO available as G7 input (CKI/20) CKO for crystal con- figuration (CKI/20) CKO available as G7 input OPTION 2: COP620C/COP840C BONDING = 1 26 pin package = 2 24 pin package = 3 20 pin package The following option information is ta be sent to National along with the EPROM. Option Data Option 1 Value__is: CK} Input Option 2 Value__is: COP Bonding How to Order To order a complete development package, select the sec- tion for the microcontroller to be developed and order the parts listed. =3R/C = 4 High Speed Crystal = 5 High Speed External Development Tools Selection Table Order Manual Microcontroller Part Number Description Includes Number MGLE-BRAIN Brain Board Brain Board Users Manual 420408188-001 MOLE-COP8-PB1 Personality Board COP820/840 Personality Board 420410806-001 Users Manual COP820/ MOLE-COP8-IBM Assembler Software for IBM COP800 Software Users Manual 424410527-001 cOPs40 and Software Disk PC-DOS Gommunications Software Users Manual 4200404 16-001 420410703-001 Programmer's Manuai 420410703-001 2-25 QZ8d09/91-'8d09/D0'8d09/D9778d09/91+28d09/9078d09/9ZP9d09/91-9d09/90P9d09/9Z79d09/9129d09/9029d09COP620C/COP621C/COP622C/COP640C/COP641C/COP642C/COP820C/COP821C/COP822C/COP840C/COP841C/COP842C DIAL-A-HELPER Dial-A-Helper is a service provided by the Microcontroller Applications Group. The Dial-A-Helper is an Electronic Bul- letin Board information system and additionally, provides the capability of remotely accessing the MOLE development system at a customer site. INFORMATION SYSTEM The Dial-A-Helper system provides access to an automated information storage and retrieval system that may be ac- cessed over standard dial-up telephone lines 24 hours a day. The system capabilities include a MESSAGE SECTION (electronic mail} for communications to and from the Micro- controller Applications Group and a FILE SECTION which consists of several file areas where valuable application software and utilities could be found. The minimum require- ment for accessing the Dial-A-Helper is a Hayes compatible modem. If the user has a PC with a communications package then files from the FILE SECTION can be down-loaded to disk for later use. ORDER P/N: MOLE-DIAL-A-HLP Information System Package contains: Dial-A-Helper Users Manual Public Domain Communications Software FACTORY APPLICATIONS SUPPORT Dial-A-Helper also provides immediate factory applications support. If a user is having difficulty in operating a MOLE, he can leave messages on our eiectronic bulletin board, which we will raspond to, or under extraordinary circumstances he can arrange for us to actually take control of his system via modem for debugging purposes. (408) 721-5582 (408) 739-1162 300 or 1200 baud Length: 8-Bit Parity: None Stop Bit: 1 Operation: 24 Hrs. 7 Days CC DIAL-A-HELPER Beeeez een ean wenzwzeeneeene ee HOST Voice: Modem: Baud: Setup: Peewee waweewwewomeencweacny ' USER'S TARGET SYSTEM t t 4 a g as ' MODEM ' a a a a HOST ' MOLE computer |! 4 t 6 + s USER SITE JF MODEM COMPUTER NATIONAL SEMICONDUCTOR SITE TL/DD/9108-20 2-26