HD63PO05Y0,HD63PA05Y0, HD63PBO5Y0 CMOS MCU (Microcomputer Unit) The HD63PO05Y0 is an CMOS 8-bit single-chip microcom- puter unit which has a 4k-byte or 8k-byte EPROM on the, package. It is compatible with the HD6305Y0 except for ROM which is not included in the HD63PO5Y0. It can be used not only for debugging and evaluating the internal program of HD6305X0 or HD63050, but also for small-sized production preceding mask ROM. FEATURES Pin compatible with HD6305X0 and HD6305Y6 256-byte of RAM A total of 55 terminals, including 32 |/Os, 7 inputs and 16 outputs. Two timers 8-bit timer with a 7-bit prescaler (programmable prescaler; event counter) 15-bit timer {commonly used with the SCI clock divider) @ Oncthiop serial interface circuit (synchronized with clock} Six interrupts (two external, two timer, one serial and one software} @ Low power dissipation modes Wait, Stop and Standby Mode @ Minimum instruction cycte time HD63P05Y0...... 1 ps (f = 1 MHz) HD63PA0SY0 ... .0.67 ps (f = 1.5 MHz) HD63PB05Y0..... 0.5 ps (f = 2 MHz} Similar to HD6B00 instruction set Bit manipulation Bit test and branch Versatite interrupt handling Full set of conditional branches New instructions STOP, WAIT, DAA Applicable to 4k or 8k bytes of EPROM 4k bytes; HN482732A 8k bytes; HN482764, HN27C64 = TYPE OF PRODUCTS HD63P0570, HD63PA05Y0, HD63PB05Y0 (DC-645P) 8 PIN ARRANGEMENT Type No. Bus Timing Applied EPROM HD63P05Y0 1 MHz HN482732A-30, HN482764-3, HN27C64-30 HD63PAQ05Y0 | 1.5 MHz | HN482732A-30, HN482764-3, HN27C64-30 HD63PBOSY0 | 2 MHz HN482732A-25, HN482764, HN27C64-25 (Note) EPROM is not attached to the MCU, @ PROGRAM DEVELOPMENT SUPPORT TOOLS @ Cross assembier software for use with IBM PCs and compat- ibles @ Incircuit emulator for use with IBM PCs and compatibles (Top View) @ HITACHI Hitachi America, Ltd. Hitachi Piaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 571HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 = BLOCK DIAGRAM > TIMER Prescaler Timer/ & Counter Timer control ya Port A HO Terminals Port B ie) Terminals Port C 40 Terminats Clk t- C)<+ C- C,.+__ Port A Register Data Direc- tion Register XTAL EXTAL ORES NUM Oscillator 1 int Accumulator A FE index Register cPu Control x Condition Cade Register cc Stack Pointer cru SP Port B Register Data Direc- tion Register Port C Register C/A Data Direc- tion Register Cytx Serial Data Register Serial Controi Register Serial Status Register On Package t I I I l t I :; EPROM ( | }HN4827324 1 1} HN482764 | Wf HN27C64 i ft I I I i i I I I I I 572 As A, ba As | a4 Address, Aa le E Program Counter High PCH alu 8 Program Counter "Low" PCL LI 256x8 RAM @ HITACHI = STBY Miscella- _ neous Register oO &- CJ gt & fh 6 5 a }_i- . { h w & -e ] 33 > este c} } - pnt -- i. 2. , 2 2- & 2 vg _- jj - . oe yo @ o_o 3] 0 Sh ) 22] ss = of)] 5 Shee a Sr bee og $a Pil D, OwinTy ps Port 0 a D, Input Oo, Terminals QO, & BE B Port E e. Output &, Terminals E, E, Fo F, fF, Port F Ff) Output fe Terminals Fe F; Go G G PoentG G 1/0 G& = Terminal: G rminas G G Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 8 ABSOLUTE MAXIMUM RATINGS Item Symbol Value Unit Supply voltage Vec -0.3~ +7.0 Vv Input voltage Vin -0.3~ Vec + 0.3 Vv Operating temperature Topr O~ +70 C Storage temperature Tstg -55 ~ +150 C [NOTE] These products have s protection circuit in their input terminals against high electrostatic voltage or high electric fields. Notwithstanding, be creful nat to epply any voltage higher than the absolute maximum rating to these high input impedance circuits. To assure normal operation, we recommended Vin, Your! Vss S [Vin OF Vout! S Vc: B ELECTRICAL CHARACTERISTICS DC Characteristics (Vee = 5.0V + 10%, Vgs = GND and T,= 0 ~ +70C unless otherwise specified) Test . + Item Symbol condition min typ max Unit RES, STBY Vec- 0.5 - Vect+ 0.3 Vv Input voltage EXTAL VoH Veo x 0.7 ~_ Vecot 0.3 v High' Others 2.0 - Veet 0.3 Vv et ow" All Input Vin 0.3 7 9.8 V Operating - 5 10 mA one Wait - 2 5 mA Current lec f= 1MHz* issipation Stop _ 2 10 uA Standby - 2 10 uA Input TIMER, leakage INT, Ihe - - 1 pA current ae Vi,=05~ Three- Ao ~ Ar, ima 08 state e ~ e ' IItsi} Vec - 0.5V A current wh. - - 1 rf Go ~ Gr. Eo ~ E, ae Fo ~F>** Input All ; f = iMHz, _ _ F capacity terminals Cin Vin = OV 5 P The value at f = xMHz can be calculated by the fallowing equation: lec (= xMHz) = tee (fF 1MHz} multiplied by x ** At standby mode *** All ourput and RES terminals are open (Viy min = Voc- 1.0, Vit max = 0.8V), and Ice of EPROM is nat included, @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 573HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 @ AC Characteristics (Voc = 5.0V + 10%, Vsg = GND and Tg = 0 ~ +70C unless otherwise specified} Test HD63P05Y0 HD63PA05Y0 HD63PBO5Y0 ; Item Symbol ee - . - Unit condition min typ | max | min typ | max | min typ | max Clock frequency fet 04 | 4/04 |] - 6] 04 | - 8 | MHz Cycle time teye 1.0 - 10 | 0.666 | - 10 | O5 - 10 | ps iNT pulse teve teye teyc width tiwe +250 | ~ ~ | 4200 | 7 ~ | 4200 | ~ 7" INT2 pulse teye teye teye _ width tIWL2 +250 | ~ | 49001 7 | +200 - ns RES pulse width TRWL - ~ 5 - - 5 ~ | teye TIMER pulse teyc _ _ teye _ _ teye _ _ width tTWL +250 +200 +200 ms = + Oscillation & pol start time tosc Rs = 60Q - ~_ 20 - - 20 _ _ 20 ms (crystal) max Reset delay External cap. time tRHL 2.2uF 80 - - 80 - - 80 - ~- ms Port Electrical Characteristics (Vcc = 5.0V + 10%, Vgg = GND and Tg = 0 ~ +70C unless otherwise specified) Item Symbol congaton min typ max Unit Output voit- Vou lon = -200uA 2.4 ~ - age High Ports A, lon = -10pA Vee -07 - - Vv B,C, 6. OH et cc . Output volt- E,F - age Low VoL lo, = 1.6mA _ - 0.55 v Input volt- age High Vin 2.0 - Veco + 0.3 Vv Input volt: Ports A, age Low 8. C,D, Vie -0.3 - 0.8 Vv Input leak- Vin = 0.5 ~ _ _ age current Wiel Veco - 0.5V | HA @ SCI Timing (Veg = 5.0V110%, Vgc = GND and Ty = 0 ~ +70C unless otherwise specified) HD6&3P05Y0 H P Item Symbol Test D6 |! D63PA05Y0 HD63PB05Y0 Unit condition | min | typ [ max | min | typ | max | min | typ | max Clock cycle tscye 1 |32768] 0.67 |21845|) 0.5 |16384| ys Data cutput delay time trxp Fig. 1, - - 250 - - 250 - - 250 | ns Data set-up time tsRx Fig. 2 200 - - 200 - - 200 - - ns Data hold time tHAX 100 - - 100 - 100 - - ns @ HITACHI 574 Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 -[- BSeye = Clock Output 24Vv : Cs/CK o6v ov oBv Data Output 7 av CHtx 0av I Data inpat 20v 20V CasRy oO 8v CBv I __ Clock Input | fp 70v cath oev cay aay _4 byxp le ' i ; _ Data Output 24Vv : | Cutx osv |, i ee ee +e Data Input f2av 20v CofRx o By oev t 1 Figure2 SCI Timing(External Clock) Vec TTL Load {Port} lo. =1.6mA 2.4kQ Test point . ._. _ La terminal o | 40pF 12kQ [NOTES] 1. The load capacitance includes stray capacitance caused by the probe, etc. 2. Ali diodes are 182074 (H). Figure 3 Test Load SDESCRIPTION ON PIN FUNCTIONS Here is the description of HD63P0SYO MCU input and output signals. eVcc. Vss Power is supplied to the MCU using these two pins. When the operating voltage of the EPROM is 5.0V + 5%, change Vee according to that of EPROM. @iNT, INT? Used for requesting an external interrupt to the MCU, For details, see INTERRUPT. The INT: is used as the port De pin. @XTAL, EXTAL Are input pins to the internal clock circuit. A crystal oscillator (AT cut, 2.0 to 8.0 MHz) or ceramic oscillator is con- nected to these pins. For instance, in order to obtain the system clock 1 MHz, a 4 MHz resonant fundamental crystal is useful because the divide-by-4 circuitry is included. EXTAL accepts an external clock input of duty 50% (+10%) to drive, then the internal clock is a quarter the frequency of the external clock. External drive frequency will be 4 or less times the maximum internal clock. For external driving, no XTAL should be connected. Refer to INTERNAL OSCILLATOR for using these input pins. @TiIMER Is an external input pin to control the internal Timer. For details, see TIMER. @RES Is used for resetting MCU. For details, see RESET. eNUM Is not for user application. It must be grounded to Vgs. @iNPUT/OUTPUT PINS (Ac~A7, Bo~B7, Co~C7, Go~G7) 32 pins consist of four 8-bit 1/0 ports (A, B, C, G). Each of them is used as input or output pin, through program control of the data direction register. For details, see I/O PORTS. @ INPUT PINS (Di ~ D7) Are 7 input-only pins compatible with the TTL and CMOS. Ds is used as INT2. When the De is used as the port, set the INT? interrupt mask bit of the miscellaneous register to 1 to prevent an INTz from accidental interruption. OUTPUT PINS (Eo ~ 7, Fo ~ F7) Are 16 output-only pins compatible with the TTL and CMOS. eSTBY Used for bringing the MCU into the standby mode. With STBY at Low level, the oscillation stops and internal situa- tion is reset. Fore details, see STANDBY MODE. The following are 1/O pins for serial communication interface (SCI), and used as ports Cs, Ce, and Cr. For details, see SERIAL COMMUNICATION INTERFACE. @CK (Cs) Used to input or output clocks when receiving o7 transmit- ting serial data. Rx (Ce) Used to receive serial data. @Tx (C7) Used to transmit serial data. =MEMORY MAP The memory map of the HD63POSYO MCU is shown in Fig. 4. During interrupt, the contents of the registers are saved in the stack as shown in Fig. 5, The saving begins with the lower byte (PCL) of the program counter. Then the stack pointer value is decremented, and the higher byte (PCH) of the program counter, index register (X), accumulator (A) and condition code register (CC) are stacked in this order. In subroutine calls, only the contents of the program counter (PCH and PCL) are stacked, @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 * (415) 589-8300 575HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 0 $0000 O|__PORT A__]$00 1/0 Ports 1] PORTB {S01 pr 2{ PORT C |$02 63 soo3r >| PORT D $03" 64 RAM 0040 4] PORTADDR $04" (192Bytes} 5] Porta por |S$05 s 6] Port c opR |$06 255 tack leooee 7 port G DOR /$07 256 RAM $0100 8] Timer Data Reg |$O8 Q| Timer CTRL Rea |$09 (64Bytes) 319 $013F 10[ Misc Reg [goa 320 $0140 11[ PORTE |$08 12] PORTF |goc 13} PORT G EPROM $00 {7,87 2Bytes} Not Used eee 167 SCICTRL Reg 1$10 an Vectors. SiFFe 17} sCrsts Reg 1$11 8191 ectors S1FFF 18] SCI Data Reg $12 8192 $2000 Not Used Not Used 63 $3F * Write only register 16383) $3FFF ** Read only register Figure 4 Memory Map of HD63P05Y0 MCU 765432 10 = Pull Condition n-4ai1 14 Code Register |" + n-3 Accumulator n+2 n-2 Index Register nt+3 n-110 0 PCH n+4 n PCL n+5 Push * In a subroutine call, only PCL and PCH are stacked. Figure 5 Sequence of Interrupt Stacking @ REGISTERS There are five registers which the programmers can handle. Accumulator (A) The accumulator is a general purpose 8-bit register which holds operands, the results of arithmetic operations or data processing. Index Register (X) The index register is an 8-bit register used for the index addressing mode, It contains an 8-bit value to be added to an instruction value to create an effective address. The index register can also be used for data manipulations using the read- modify-write instruction. The index register may also be used as a temporary storage area, Program Counter (PC} 7 0 7 o 4 (Fi 13 9, | PC Counter 13 65 0 ofofojofojofi]s] SP Pointer Condition fx] | [Nn] z] Cc] Code Register Carr Borrow Zero Negative Interrupt Mask Half Carry Figure 6 Programming Model The program counter is a 14-bit register which contains the address of the next instruction to be executed. Stack Pointer (SP) The stack pointer is a 14-bit register which indicates the address of the next free location in the stack, Initially, the stack pointer is set to S00FF. It is decremented as data is pushed in, and incremented as it is pulled out. The upper 8 bits of the stack pointer are fixed to 0000001 1. During an MCU reset or when the reset stack pointer (RSP) instruction is executed, the pointer is set to the location $00FF, A subroutine or interrupt may be nested down to location $00C1 which allows programmers to use up to 31 levels of subroutine call or 12 levels of interrupt response, Condition Code Register (CC) The condition code register is a 5-bit register. Each bit indicates the result of the executed instruction, These bits can be individually tested by conditional branch instructions. The CC bits are as follows. Half Carry (H}: Used to indicate a carry occurring between bits 3 and 4 during an arithmetic operation (ADD, ADC). Setting this bit causes all interrupts to be masked except for software ones, If an inter- rupt occurs while the bit lis set, the interrupt is latched, and processed as soon as the interrupt mask bit (I is reset. (Exactly, the interrupt enters the processing routine after the instruction next to the CLI is executed.) Used to indicate that the result of the Jatest arithmetic operation, logical operation or data processing is negative (Bit 7 is logical 1"). Used to indicate that the result of the latest arithmetic operation, logical operation or data processing is zero. Carry/Borrow Shows a carry or borrow occurring in the (C): jatest arithmetic operation. This bit is also affected by the Bit Test and Branch, Shift and Interrupt (1): Negative (N): Zero (Z): @ HITACHI 576 Hitachi America, Lid. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 Rotate instructions. SINTERRUPT There are six different types of interrupt: external inter- rupt (INT, INT2), internal timer interrupts (TIMER, TIMER 2), serial interrupt (SCI) and interrupt by an instruction (SWI). Of these six interrupts, the INT2 and TIMER, and SCI and TIMER 2 respectively generate the same vector address. When an interrupt occurs, the program in execution stops and CPU state at the interrupt is saved onto the stack, In addition, the interrupt causes the interrupt mask bit (1) in the condition code register to be set and obtains the start address of the interrupt routine from an assigned interrupt vector address before the interrupt routine starts frofn the state address. The system exits from the interrupt routine by RT! instruction. When the RTI instruction is executed, the CPU state before the interrupt (saved in the stack) is pulled and the CPU starts the program again from the next step to the interrupted one. Table 1. lists the priority of interrupts and their vector addresses. Table 1 Priority of Interrupts Interrupt Priority Vector Address RES 1 SIFFE, S1FFF Swi 2 $1FFC, $1FFD INT 3 $IFFA, $1FFB TIMER/INT2 4 $1FF8, $1FF9 SCI/TIMER2 5 $1FF6, $1FF7 A flow chart of the interrupt is shown in Fig. 7. Also a block diagram of the interrupt request source is shown in Fig. 8. In_the block diagram, both the external interrupts INT and INT2 are edge trigger inputs. At the falling edge of the input, an interrupt request is generated and latched. The INT interrupt request is automatically cleared if a program jumps to the INT routine. In the case of INT2, the (Reset ) $FF-SP 0--DDR'S Fetch CLR INT Logic Instruction SFFTDR $7FTimer Prescaler $50-TCR $3F-SSR $o0SCR $S7F--MR Stack t PC, X, A, CC Load PC From I Reset:$1FFE, $1FFF 1-1 Bit Y Feta i Load PC From N Swi $9FFC.$1FFD (NT S1FFA.S$1FFQ TIMER SIFFA. SIFFS Execute Execute INT, S1FRG.S1EFO . . SCi $1FFO.S1FF7 Instructian Instruction TIMER 2 STFFO.$TFF? Figure 7 Interrupt Flowchart interrupt request is cleared when O is written in bit 7 of the miscellaneous register. For external interrupts(INT,INT2 ), internal timer interrupts (TIMER, TIMER2) and serial inter- rupt (SCH), these interrupt requests are held, but not operated, while bit I of the condition code register is set. Immediately after the bit I is cleared, the corresponding interrupt is activated. The INT2 interrupt can be masked by setting bit 6 of the miscellaneous register; the TIMER interrupt by bit 6 of the timer control register, the SCI interrupt by bit 5 of the serial status register and the TIMER? interrupt by bit 4 of the serial status register. __ The state of the INT pin is tested by BIL or BIH instruc- tions. The INT falling edge detector circuit and its latch circuit are independent of tests by these instructions. The state of INTz2 pin is also independent. @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 577HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 BIH/BIL Test INT tnter- rupt Latch Vectoring generated $IFFA, $1FFB Condition Code Register (CC) = m 4+ Falling Edge Detector \ Miscellaneous Register (MR) Timer Control Register (TCR) TIMER TIMER Serial Status Register (SSR} SCI TIMER2 [ SSR? [ssne[ssas [ssra] TIMER, LI Sci Interrupt Control Circuit Vectoring generated SIFFS, SIFFS > Vectoring generated STFFG6, $1FF7 Figure 8 Interrupt Request Generation Circuitry Miscellaneous Register (MR: $O00A) The interrupt vector address for external interrupt INT? is the same as that for the TIMER interrupt, as shown in Table 1. For this reason, a special register called a miscellaneous register (MR: $000A) is available for INT interrupt control. Bit 7 of the miscellaneous register is of INT2 interrupt request flag. When the falling edge is detected at the INT2 pin, 1 is set in bit 7. The software in the interrupt routine (vector address: $1FF8, $1FF9) checks to see if it is INT2 interrupt. Bit 7 is reset by software. Bit 6 is the INT2 interrupt mask bit. If the bit is set to 1, the INT2 interrupt is disabled. Miscellaneous Register (MR ;S000A) 7 6 5 4 3. 2 1 0 mere A111 Lo {imer interrupt routine address from address $1FF& and $1FF9. The timer interrupt can be masked by setting the timer interrupt mask bit (bit 6) in the timer control register. The mask bit (I) in the condition code register can also disable the timer interrupt. The source clock for the timer can be either an external signal from the timer input pin or the internal E signal (oscillator clock divided by 4). If the E signal is selected as the source, the clock input can be gated by the input to the timer input pin. When the timer counter reaches OQ, it starts counting down from $FF. The count can be monitored at any time by reading the timer data register. This function allows knowledge of the length of time after a timer interrupt with a program, without destroying the contents of the counter. When the MCU is reset, both the prescaler and counter retum to the initial state of logical 1. At the same time, the timer interrupt request bit (bit 7) is cleared and the timer INT2 Interrupt Mask : pire . INT? Interrupt Request Flag interrupt mask bit (bit 6) is set. Write O in the timer inter- Tupt request bit (bit 7) to clear it, Both READ and WRITE are possible with bit 7, but " 1 can not be written to in this bit by software. Therefore, TCR? Timer interrupt request interrupt requests by software are not possible, By resetting, 0 Absent bit 7 is cleared and bit 6 is entered 1. 1 Present TIMER The MCU timer block diagram is shown in Fig. 9. The 8- , . bit counter is loaded under program control and is decre- TCAG Timer interrupt mask mented by the clock input. When the timer data register 0 Enabled (TDR) reaches 0, the timer interrupt request bit (bit 7) in the timer control register is set. The MCU responds to this inter- 1 Disabled tupt by saving the present CPU state in the stack, fetching the @ HITACHI 578 Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 Timer Control Register (TCR; $0009) Selection of a clock source, selection of a prescaler fre- quency division ratio, and a timer interrupt can be controlled by the timer control register (TCR; $0009). For the selection of a clock source, any one of the four modes (see Table 2) can be selected by bits 5 and 4 of the After resetting, the TCR is initialized to E under timer terminal control (bit 5 = 0, bit 4 = 1). If the timer terminal is 1, the counter starts counting down with SFF immediately after the reset. Table 2 Clock Source Selection timer control register (TCR). Timer Control Register (TCR; $0009) 7 6 5 4 3 2 +21 =O rerrfronsfrcrs TORS rerafrcnalrcR! TCRO | ___1/ L Prescaler division ratio sel Prescaler initialize Clock input source TCR . - Clock input source Bit 5 Bit 4 0 0 Internal clock E 0 1 E under timer terminal control 1 0 No clock input (counting stopped) 1 1 Event input from timer terminal Timer interrupt mask Timer interrupt request Initialize Timer Control Register te + (TCR;$0009) E Prescaier TCR? regen Tras roger TCR ren TIMER +t +2|/+4)/+8 16 32 64 +128 Lt Input 3 Terminal Multiplexer - Timer Data Register (TDR; $0008) Timer Interrupt B-Bit Counter Clock Input Write Read Figure 9 Timer Table 3 Prescaler Division Ratio Selection TCR Bit 2 Bit 1 Bit 0 Prescaler division ratio 0 0 0 71 0 0 1 +2 0 1 0 +4 0 1 1 +8 1 0 0 +16 1 9 1 +32 1 1 0 +64 1 1 1 +128 Block Diagram The prescaier is initialized by writing 1 in bit 3. The bit is always O, when READ. A prescaler division ratio is selected by a combination of the three bits (bits 0, 1 and 2) of the timer control register (See Table 3). There are eight division ratios; +1, +2, +4, +8, +16, +32, +64 and +128, After resetting, the TCR returns to the =i mode. The timer interrupt is enabled when the timer interrupt mask bit is 0, and disabled when the bit is 1. When a timer interrupt occurs, I is set in the timer interrupt request bit. The bit is cleared by writing O into it. SSERIAL COMMUNICATION INTERFACE (SCI) Used for 8-bit data communication. Transfer rate ranges from Iys to about 32 ms (when oscillated at 4 MHz), and there are sixteen selections. The SCI consists of three registers, one octal counter and one prescaler, (See Fig. 10) The SCI communicates with the CPU through the data bus, and with peripherals through bits 5, 6 and 7 of port C, Operations of the registers and data transfer are described below. @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 579HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 SCi Control Registers (SCR; $0010) SCR7]SCR6E/SCR5} SCR4 SCR3] SCR2] SCR1/SCRO E > E> Multi] Pre | Crock plexer| scaler Generator cs(CK} ! > ' ' SCI Data Registers i ! (SDR- $0012) Octal ' ! Counter i ' Initialize ! Zz 5 4 2 1 O Ca(Rx) | | MSB LSB CATx) : t | ] benno 4 ce ee ee SSR7|SSR6|SSR5|SSA4/SsR3 Sor eee eaters Yd a ttt Not Used SCt/TIMER2 #SCI Control Register (SCR; $0010) 7 6 5 4 3 2 SCR7/SCRBISCRS|SCR4 SCR3ISCA2Z/SCR1 SCRO Figure 10 SCI Block Diagram Bit 7 (SCR7) When this bit is set, the DDR corresponding to the C, becomes ]" and this terminal serves for output of SCI data. After resetting the bit is cleared to 0. Bit 6 (SCR6) When this bit is set, the DDR corresponding to the C, SCR? Cy terminal becomes 0 and this terminal serves for input of SCI data. After resetting the bit is cleared to 0. 0 Used as {/O terminal (by DDR). - Bits 5 and 4 (SCRS,SCR4) 1 Serial data output (DDR output) These bits are used to select a clock source. After resetting the bits are cleared to 0". SCRE Ce terminal Bits 3~ 0 (SCR3 ~ SCRO) 0 Used as 1/0 terminal (by DDR). These bits are used to select a transfer clock rate. After resetting the bits are cleared to 0. 1 Serial data input (DOR input) Fransfer clock rate SCR3 | SCR2 | SCR1 | SCRO SCR5 /SCR4| Clock source Cs termina! 4.00 MHz | 4.194 MHz 0 0 ~ Used as 1/0 terminal (by 0 Q Q 0 us 0.95 us 0 1 _ DDR}. 0 0 1 2 ps 1.91 us 0 0 1 0 4 82 1 0 tnternai Clock output (DDR output} Hs 5.82 ys 0 0 1 1 8 us 7.64 us 1 1 External Clock input (DDR input} 2 2 2 ? a a 1 1 1 1 32768 ys 1/32 s @ HITACHI 580 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy, * Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 @SCt Date Register (SDA; $0012) A serial-parallel conversion register that is used for transfer of data. @SCI Status Register (SSR; $0011) i g 4 3. 2 1 SSR7| SSRG]SSAS | SSA4) ssA3 Bit 7 (SSR7) Bit 7 is the SCI interrupt request bit which is set on com- pletion of transmitting or receiving 8-bit data. It is cleared when reset or data is written to or read from the SCI data register with the SCR5=1", The bit can be cleared by writing O into it. Bit 6 (SSR6) Bit 6 is the TIMER: interrupt request bit, TIMER: is com- monly used with the serial clock generator, and SSR6 is set each time the internal transfer clock falls. When resetting , the bit is cleared. It can also be cleared by writing O into it. (For details, see TIMER: ). Bit 5 (SSRS) Bit 5 is the SCI interrupt mask bit which can be set or cleared by software. When it is 1, the SC] interrupt (SSR7) is masked, When resetting, it is set to 1. ~ Bit 4 (SSR4) Bit 4 is the TIMER, interrupt mask bit which can be set or cleared by software. When the bit is 1, the TIMER; interrupt (SSR6) is masked. When resetting, it is set to 1. Bit 3 (SSR3) When 1 is written into this bit, the prescaler of the trans- fer clock generator is initialized. When READ, the bit is always 0. Bits 2 ~~ 0 Not used. SSA? SCI interrupt request 0 Absent 1 Present SSR6 TIMER, interrupt request 0 Absent 1 Present SSR5 SCI interrupt mask 0 Enabied 1 Disabled SSR4 TIMER, interrupt mask Q Enabled 1 Disabled @ Data Transmission By writing the desired control bits into the SCI control registers, a transfer rate and a transfer clock source are deter- mined and bits 7 and 5 of port C are set at the serial data output terminal and the serial clock terminal, respectively. The transmit data should be stored from the accumulator or index register into the SCI data register. The data written in the SCI data register is output from the C7/Tx terminal, starting with the LSB, synchronously with the falling edge of the serial clock (See Fig. 11). When 8 bits of data have been transmitted, the interrupt request bit is set in bit 7 of the SCI status register with the rising edge of the last serial clock. This request can be masked by setting bit 5 of the SCI status re- gister. Once the data has been sent, the 8th bit data (MSB) stays at the C7/Tx terminal. If an external clock source has been selected, the transfer rate determined by bits 0 to 3 of the SCI control register is ignored, and the Cs/CK terminal is set as input. If the internal clock has been selected, the Cs / CK terminal is set as output and clocks are output at the transfer rate selected by bits 0 to 3 of the SCI control re- gister. Sesiat Clock (C4 /ERi 1 an CX) Tay Pe Guinan Daun C/T ae (iseXf XX XD input Dawa Latch Torung (Cg/Fox Figure 11 SCl Timing Chart Data Reception By writing the desired control bits into the SCI control register, a transfer rate and a transfer clock source are de- termined and bit 6 and 5 of port C are set at the serial data input terminal and the serial clock terminal, respectively. Then dummy-writing or -reading the SCI data register, the system is ready for receiving data. (This procedure is not needed after reading subsequent received data. It must be taken after reset and after not reading subsequent received data.) The data from the C,/Rx terminal is input to the SCI data register synchronously with the rising edge of the serial clock (see Fig. 11). When 8 bits of data have been re- ceived, the interrupt request bit is set in bit 7 of the SCI status register. This request can be masked by setting bit 5 of the SCI status register. If an external clock source have been selected, the transfer rate determined by bits 0 ~ 3 of the SCI control register is ignored, and the data is received synchro- nously with the clock from the Cs /CK terminal. If the internal clock has been selected, the C,/CK terminal is set as output and elocks are output at the transfer rate selected by bits 0 ~ 3 of the SCI control register. TIMER2 The SCJ transfer clock generator can be used as a timer. The clock selected by bits 3 to 0 of the SCI control register (4 us to approx. 32 ms (when oscillated at 4 MHz)) is input to bit 6 of the SCI status register and the TIMER2 interrupt request bit is set at each falling edge of the clock. Since inter- Tupt requests occur periodically, TIMER2 can be used as a reload counter or clock. HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 581HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 @ @ 4 ; ' eed : Transfer clock generator is reset and mask bit (bit 4 of SCI status register) is cleared. @ : TIMER2 interrupt request : TIMER? interrupt request bit cleared @ TIMER: is commonly used with the SCI transfer clock generator. If wanting to use TIMER2 independently of the SCI, specify External (SCR5 = 1, SCR4 = 1) as the SCI clock source. If internal is selected as the clock source, reading or writing the SDR causes the prescaler of the transfer clock generator to de initialized. =1/O PORTS There are 32 input/output terminals (ports A, B, C, G). Each I/O terminal can be selected for either input or output by the data direction register. Specifically, an 1/O port will be input if O is written in the data direction register, and out- put if 1 is written in the data direction register. Port A, B or C reads latched data if it has been programmed as output, even with the output load, the output level fluctuating. (See Fig. 12-a.) For port G, in this case, the level of the pin is always read when it is read. (See Fig. 12-b.) This implies that, even when 1 stays output, port G may read O if the load con- Dew Direction Rogice: = [> Bit of data Bit of direction output Status of Input to i output MCU register data 1 1 1 1 0 x 3-state Pin a. Ports A, B and Cc Oem -+ Direction Flegrstes Ovtpet 0 > Daw ' <| b. Port G Figure 12 Input/Output Port Diagram dition causes the output voltage less than 2.0V. When resetting the data direction register and data register go to O and all input/output terminals are used as input. There are 16 output-only terminals (ports E and F). Each of them can also read. In this case, latched data is read even with the output terminal level being fluctuated by the output load (as with ports A, B and C). When resetting, Low level is output from each output terminal. Seven input-only terminals are available (port D). Writing to these ones is invalid. All input/output terminals, output terminals and input terminals are TTL compatible and CMOS compatible in re- spect of both input and output. If I/O ports or input ports are not used, they should be connected to Vgg via resistors. With none connected to these terminals, there is the possibility of power being consumed despite their not being used. =RESET _ The MCU can be reset either by extemal reset input (RES) or power-on reset. (See Fig. 13.) On power up, the reset input must be held Low for at least tgsc to assure that the internal oscillator is stabilized. A sufficient delay time can be obtained by connecting a capacitance to the RES input as shown in Fig. 14. 5V 4.5V Vee / ov AES | Mi RES Terminat tae Internal Reset Figure 13. Power On and Reset Timing 100k ty p} Vee WAr4 HD63P05Y0 MCU Figure t4 Input Reset Delay Circuit SINTERNAL OSCILLATOR The internal oscillator circuit is designed to meet the requirement for minimum external configurations. It can be driven by connecting a crystal (AT cut 2.0 ~ 8.0MHz) or ceramic oscillator between pins 5 and 6 depending on the re- quired oscillation frequency stability. Three different terminal connections are shown in Fig. 15. Figs. 16 and 17 illustrate the specifications and typical arrange- ment of the crystal. HITACHI 582 Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 6 EXTAL 2.0~8.0MHZ 5 HD63P05Y0 yt L XTAL MCU F 10~22pF + 20% ~~" Crystal Oscillator a EXTAL Co 5 xTaL NDG3PO5Y0 MCU External Ceramic Oscillator Clock Input_6JEXTAL NC 5] XTAL HDE3P05Y0 MCU J External Clock Drive Figure #5 = Internal Oscillator Circuit Cy AT Cut III enn Parallel -_? a= 7pF max. xTAL Co EXTAL =2.0~8.0MHz +f Rs=602 max. Figure 16 Parameters of Crystal (b) Ci Crystal xT, EXTAL Crystal MCU {NOTE] Use as short wirings as possible for connection of the crystal with the EXTAL and XTAL terminals. Do not allow these wirings to cross others. Figure 17 Typical Crystal Arrangement @LOW POWER DISSIPATION MODE The HD63PO05Y0O has three low power dissipation modes: wait, stop and standby. o Wait Mode When a WAIT instruction being executed, the MCU enters into the wait mode. In this mode, the oscillator stays active but the internal clock stops. The CPU stops but the peripheral functions the timer and the serial communication inter- face stay active. (NOTE: Once the system has entered the wait mode, the serial communication interface can no longer be retriggered.) In the wait mode, the registers, RAM and 1/0 terminals hold the condition just before entering the wait mode. Both address (Ao ~ A12) and chip enable (CE) for the EPROM are in 1 state. Release from this mode can be done by interrupt {INT, TIMER/INT: or SCI/TIMER2), RES or STBY. The RES resets the MCU and the STBY brings it into the standby mode. (This will be mentioned later.) When interrupt is requested to the CPU and accepted, the wait mode is released and the CPU is brought to the operation mode and vectors to the interrupt routine. If the interrupt is masked by the I bit of the condition code register, after release from the wait mode the MCU executes the instruction follow- ing WAIT. If an interrupt other than the INT (i.e., TIMER/ INT2 or SCI/TIMER2) is masked by the timer control re- gister, miscellaneous register or serial status register, there is no interrupt request to the CPU, so the wait mode cannat be released. Fig. 18 shows a flowchart of the wait function. Stop Mode When STOP instruction is being executed, the MCU enters the stop mode. In this mode, the oscillator stops and the CPU and peripheral functions become inactive but the RAM, register and I/O terminals hold the condition they had just before entering the stop mode. Both address (Ao ~ Aiz) and chip enable (CE) for the EPROM are in 1 state. Release from this mode can be done by an external inter- rupt (INT or INT2), RES or STBY. The RES resets the MCU and the STBY brings it into the standby mode. When an interrupt is requested and accepted by the CPU, the stop mode is released and the CPU is brought in the opera- tion mode and vectors to the interrupt routine, If the inter- rupt is masked by the IJ bit of the condition code register, after release from the stop mode, the MCU executes the instruction following STOP. If the INT2 interrupt is masked by the miscellaneous register, there is no interrupt request to the MCU, so the stop mode cannot be released. Fig. 19 shows the flowchart of the stop function. Fig. 20 shows a timing chart of the return to the operation mode from the stop mode. For releasing from the stop mode by an interrupt, oscilla- tion starts upon input of the interrupt and, after the internal delay time for stabilized oscillation, the CPU becomes active. For testarting by RES, oscillation starts when the RES goes 0 and the CPU restarts when the RES goes 1. The dura- tion of RES="0" must exceed tose to assure stabilized oscil- lation. * Standby Mode The MCU enters the standby mode when the STBY terminal goes Low. In this made, all operations stop and the internal condition is reset but the contents of the RAM are held. The 1/O terminals turn to high-impedance state. Both address (Ao ~ Ai2) and chip enable (CE) for the EPROM are in 1 state. The standby mode should be released by bringing STBY High. The CPU must be restarted by resetting. The @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. * Brishane, CA 94005-1819 (415) 589-8300 583HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 timing of input signals at the RES and STBY terminals is low power dissipation modes. Transitions between each mode shown in Fig. 21. are shown in Fig. 22. Table 4 lists the status of each parts of the MCU in each { Wait } Oscillator Active Timer and Serial Clock Active All Other Clocks Stop to Standby Mode Restart Processor Clocks Initialize CPU, TIMER, SCI, 1/0 and All Other Functions No TIMER: SSAG = 13 No RES S Yes Load PC from $1FFE, $1FFF Restart Processor Clocks Load PC from Interrupt Vector Addresses Fetch Instruction Figure 18 Wait Mode Flow Chart @ HITACHI 584 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 Oscillator and All Clocks Stop. to Standby Mode Turn on Oscillator Wait for Time Delay to Stabilize Load PC from Turn on Qscillator $1FFE, $1FFF Wait for Time Delay to Stabilize Load PC from interrupt Vector Addresses Fetch Instruction Figure 19 Stop Mode Flow Chart @ HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 585HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 Osciltator PARALEHNEATAUUAAH Mn | t Time required for oscillation to become I ae ret - STOP instruction Interrupt stabilized (built-in detay time) Instructions executed restart (a) Restart by Interrupt Oscillator |]]| fT HUTT My Th Time required for oscillation to become stabilized (tys) executed Reset start STOP instruction | =z m on rf v _ {b) Restart by Reset Figure 20 Timing Chart of Releasing from Stop Mode af ; ur losc | Restart Figure 21 Timing Chart of Releasing from Standby Mode Table 4 Status of Each Part of MCU in Low Power Dissipation Modes Condition Mode Start Oscil- Timer, , 170 Escape lator CPU Serial Register RAM terminal WAIT WAIT in- Active | Stop | Active | Hold Hold | Hold | each in terat request of Soft- struction TIMER, TIMER, , SCI ware | STOP in- aay EEE UY STOP struction Stop Stop Stop Hold Hold Hold | STBY, RES, INT, INT; Stand- | Hard- STAVE"! aw" High im- | ema _ogye per by ware STBY="Low Stop Stop Stop Reset Hold fance STBY="High @ HITACHI 586 Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415} 589-8300HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 Figure 22 Transitidns among Active Mode, Wait Mode, Stop Mode, Standby Mode and Reset PRECAUTION TO THE BOARD DESIGN OF OSCILLA TION CIRCUIT As shown in Fig.23, the cross talk may disturb normal oscillation if signal lines are set near the oscillation circuit. When designing a board, be careful of this. Crystal and Cy must be put near XTAL and EXTAL pins as possible. ~ Signal line c he 5 AxTAW) fit 6 (EXTAL) -- Signal tine ey HD63P05Y0 Figure 23 Precaution to the board design of oscillation circuit PRECAUTION TO USE THE EPROM ON-PACKAGE 8-BIT SINGLE-CHIP MICROCOMPUTER Please be careful of the following, since this MCU has a special structure with pin socket on the package. (1) Dont apply high static voltage or surge voltage over MAXIMUM RATINGS to the socket pins as well as the LSI pins. If so, that may cause permanent damage to the device, (2) When using 32k EPROM (24-pin), insert it leaving the four pins above open. (3) When inserting this into system products like mask ROM type single chip microcomputer, be careful of the follow- ing to give effective contact between the EPROM pins and socket pins. @ HITACHI 4 Pins (On index side) open. 24 Pin EPROM should be inserted on the mark side with 4 above open. ooocoaoa00c 0 OD o 0 oO o o o Qo a oO 4G2 JAPAN (J HD&3PO5Y0 (a) When soldering the LSI onto a printed circuit board, the recommended condition is Temperature: lower than 250C Time: within 10 sec. (b) Be careful that detergent or coating does not get into the socket during flux washing or board coating after soldering, because that may cause bad effect on socket contact, (c} Avoid permanent application of this under conditions Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 587HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 of continuous vibration. (d) The socket, repeatedly inserted and removed, loses its contactability. it is recommended to use new one when used in production. SBIT MANIPULATION The HD63POSY0 MCU can use a single instruction (BSET or BCLR) to set or clear one bit of the RAM within page 0 or an 1/O port (except the write-only registers such as the data direction register}. Every bit of memory or I/O within page 0 ($00 ~ $FF) can be tested by the BRSEF or BRCLR instruc- tion; depending on the result of the test, the program can branch to required destinations. Since bits in the RAM on page 0, or I/O can be manipulated, the user may use a bit within the RAM on page O as a flag or handle a single 1/0 bit as an independent 1/O terminal. Fig. 24 shows an example of bit manipulation and the validity of test instructions. In the example, the program is configured assuming that bit 0 of port A is connected to a zero cross detector circuit and bit 1 of the same port to the trigger of a triac. The program shown can activate the triac within a time of 10us from zero-crossing through the use of only 7 bytes on the memory, The on-chip timer provides a required time of delay and pulse width mudulation of power is also possible. SELF 1. BRCLRO, PORT A, SELF 1 BSET 1,PORT A BCLR 1, PORTA Figure 24 Example of Bit Manipulation S ADDRESSING MODES Ten different addressing modes are available to the HD63P0SY0 MCU. o immediate See Fig. 25. The immediate addressing mode provides access to a constant which does not vary during execution of the program. This access requires an instruction length of 2 bytes. The effective address (EA) is PC and the operand is fetched from the byte that follows the operation code. Direct See Fig. 26. In the direct addressing mode, the address of the operand is contained in the 2nd byte of the instruction. The user can gain direct access to memory up to the lower 255th address. 192 byte RAM and I/O registers are on page 0 of address space so that the direct addressing mode may be utilized. e Extended See Fig. 27. The extended addressing is used for referenc- ing to all addresses of memory. The EA is the contents of the 2 bytes that follow the operation code. An extended addressing instruction requires a length of 3 bytes. Relative See Fig. 28. The relative addressing mode is used with branch instructions only. When a branch occurs, the program counter is loaded with the contents of the byte fallawing the Operation code. EA = (PC) + 2 + Rel., where Rel. indicates a signed 8-bit data following the operation code. If no branch occurs, Rel. = 0. When a branch occurs, the program jumps to any byte in the range +129 to -127. A branch instruction requires a length of 2 bytes. Indexed (No Offset) See Fig. 29. The indexed addressing mode allows access up to the lower 255th address of memory. In this mode, an instruction requires a length of one byte. The EA is the contents of the index register. Indexed (8-bit Offset) See Fig. 30. The EA is the contents of the byte foilow- ing the operation code, plus the contents of the index register. This mode allows access up to the lower 511th address of memory. Each instruction when used in the index addressing mode (8-bit offset) requires a length of 2 bytes. eindexed (16-bit Offset) See Fig. 31. The contents of the 2 bytes following the operation code are added to content of the index register to compute the value of EA. In this mode, the complete memory can be accessed. When used in the indexed address- ing mode (16-bit offset), an instruction must be 3 bytes long. Bit Set/Clear See Fig. 32, This addressing mode is applied to the BSET and BCLR instructions that can set or clear any bit on page 0. The lower 3 bits of the operation code specify the bit to be set or cleared. The byte that follows the operation code indicates an address within page 0. Bit Test and Branch See Fig. 33. This addressing mode is applied to the BRSET and BRCLR instructions that can test any bit within page 0 and can be branched in the relative addressing mode. The byte to be tested is addressed depending on the contents of the byte following the operation code. Individual bits within the byte to be tested are specified by the lower 3 bits of the operation code. The 3rd byte represents a relative value which will be added to the program counter when a branch condition is established. Each of these instructions should be 3 bytes long. The value of the test bit is written in the carry bit of the condition code register. Implied See Fig. 34. This mode involves no EA. All information needed for execution of an instruction is contained in the operation code. Direct manipulation on the accumulator and index register is included in the implied addressing mode. Other instructions such as SWI and RTI are also used in this mode. All instructions used in the implied addressing mode should have a length of one byte. @ HITACHI 588 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 { EA Memory : Adder Y. A Le Index Reg : Stack Point PROG LDA & F& OSBE) AB Prog Count OSBF Fa cc . . ' nt Figure 25 Example of Immediate Addressing Memory CAT FCB 32 0048 PROG LDA CAT 0520 O52 | Figure 26 Example of Direct Addressing PROG LOA CAT Cc Index Reg OE | J Stack Pant : Prog Count cc bt Figure 27 Example of Extended Addressing @ HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 589HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 Memory PROG BEQ PROG2 04a7 0448 Figure 28 Example of Reiative Addressing TABL FCC Lt 0088 PROG LDA x O5F4 Figure 29 Example of Indexed (No Offset) Addressing EA Memory ooBc ot } Adder TABL FCB BF OOB9 BF FCB #86 OOBA 85 A FCR #DB OOBB DB i FCB ACF OOBC CF index Reg Los Stack Point PROG LDA TABL x 0758 E6 O75C a9 Prog Count 0750. cc Co Figure 30 Example of index (8-bit Offset) Addressing @ HITACHI 596 Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 _ Ys. A Index z 02 PROG LDA TABL 0692 06 Stack Point 0693 o1 0694 TE og Count . cc TABL FCB MBF O77E BF a | FCB H&6 O77F BE FCB #DB 0780 DB FCB MCF 0781 CF ' bl Figure 31 Example of tndex {16-bit Offset) Addressing Memory + ' ' PORT BEQU 1 0001 A Index Reg PROG BCLR 6 POAT B O58F Stack Pot 0590 og Count cc Figure 32 Example of Bit Set/Clear Addressing Memary PORT C EQU2 ODOZ PROG BRCLA 2.PORT C PROG 2 0574 0575 0576 Figure 33 Example of Bit Test and Branch Addressing @ HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 591HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 EA Memory PROG TAX OSBA | A Index Keg Stack Point Prog Count OSBB cc Co Figure 34 Example of Imptied Addressing FINSTRUCTION SET There are 62 basic instructions available to the HD63P05Y0 MCU. They can be classified into five categories: register/ memory, read/modify/write, branch, bit manipulation, and control. The details of each instruction are described in Tables 5 through 11. Register/Memory instructions Most of these instructions use two operands, One operand is either an accumulator or index register. The other is derived from memory using one of the addressing modes used on the MCU. There is no register operand in the unconditional jump instruction (JMP) and the subroutine jump instruction (JSR). See Table 5. + Read/Modify/Write Instructions These instructions read a memory or register, then modify or test its contents, and write the modified value into the memory or register, Zero test instruction (TST) does not write data, and is handled as an exception in the read/modify/ write group. See Table 6. # Branch Instructions A branch instruction branches from the program sequence in progress if a particular condition is established. See Table 7. e Bit Manipulation Instructions These instructions can be used with any bit located up to the lower 255th address of memory. Two groups are available; one for setting or clearing and the other for bit testing and branching. See Table 8. Control Instructions The control instructions control the operation of the MCU which is executing a program, See Table 9. List of Instructions in Alphabetical Order Table 10 lists all the instructions used on the MCU in the alphabetical order. Operation Code Map Table 11 shows the operation code map for the instructions used on the MCU. @ HITACHI 592 Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 Table 5 Register/Memory Instructions Addressing Modes Indexed | Indexed | Indexed Boolean/ Condition Operations Mnemonic | medic | Direct | Extended |{No Oftsat)|(8-B1 Otset{i16-B OMen| Grevettan Code OP) # | ~ |OP/ s | - jOP] # | ~ /OP| = | |OP] 2 | ~ |OP| a Hi I ITN | zie Load A from Memory LDA AG) 2] 2/86] 2 | 3 |C6 4/F6| 113 /6/2 | 4/06) 3;5)mMA o;e ,ztal Load X from Memory Lox AE( 2) 2 /BE] 2/3 /CE| 3) 4 /FE} 1) 3 EE) 2) 4 /DE, 3 | 5 | Mx ere] ,ial Store A in Memory STA 87/2), 3/C7| 3) 4 /F7; 1) 4/E7| 2) 4/07/3)5)/A-mM elel;,],l/@ Store X in Memory STX BF) 2) 3;CF/3)4/FF) 1) 4/EF|/ 2) 4/DF)3)5)/xX+M @ie@l,zjale Add Memory to A aoD AB) 2 | 2 (8B) 2/3 |cB) 3 | 4) FB) 1) 3 )EB) 2/4 |B!) 3) 5) A+MA Al@]>aAlaATA Add Memory and Carry - toA aoc AS} 2/2 (B89) 2/3 (C9) 3) 4/)/F9) 1,3 /9) 2) 4/09) 3 | 5 ;A+M4+CA @laial Subtract Memory sus a0} 2/2/80) 2/3 (CO) 3/4 )/FO! 1) 3 /E0) 2/4/00) 3| 5) A-M-aA @l@lalala Subtract Memory from A with Borrow spc A2( 2/2/82} 2/39 j(C2| 3) 4 /F2] 1) 3 )E2| 2) 4 /02'3 | 5) A-M-C -A @)@laApala AND Memory ta A AND A4/ 2/2/84) 2/3 /C4) 3) 4/F4) 1) 3/64) 2; 4/04) 3) 5);A-MA *@ epajarye OR Memory with A ona faal2!2{eal2{alcalal4|ral1]alealz}4loalsis[aem-a @lelalale Exclusive OR Mamory with A OR Aa| 2; 2 |eB] 2; 3 (cB) 3) 4)F8; 1; 3 Jee} 2) 4 |ps! 3) 5 | AGMA @lefaiale Arithmetic Compare A with Memory CMP Al} 2]2 |/81;7 2/3 /C1)3/ 4 )F1/ 1)-3 ]61) 2/4/01) 3)5)4-M @lepri Arya Arithmetic Compare K with Memory CPX A3| 2 | 2 )83;) 2 | 3 (C3) 3) 4 /F3;} 1)73 /E3/ 2) 4/03) 3/5 )]x-M @jealr 4) Bit Test Mamory with A (Logical Compare) BIT A5| 2/2/85) 253 /C5) 3/4 )/F5) 1), 3 /E8)/ 2,4 )/DS) 315)/A-M @le@e;ris4le Jump Unconditional JMP Bc] 2) 2 \cCl 3) SFC} 1) 2 C) 213 |OC) 3; 4 e,e;elele Jump to Subroutine JSR BD/ 2/5 ico} 3) 6 FD) 1) 5 JED] 2/5 |DD] 3/6 *#\e;eleje Symbols: Op = Operation # == Number of bytes ~ = Number of cycles Table 6 Read/ModifyMrite Instructions Addressing Modes Operations Mnemonic indexed indexed Boolean/ Arithmetic Operation Code imphed{A) | ImphediX) Deract | (No Offset) |(8-Bat Offser OP) s | - }OP| 3 | - JOP] # | - |OP) =| - OP; s] - Hj FEIN] 2) C increment INC 4C/ 1) 2/5C) 1) 273C) 2) 5 |7C; 115 (6C! 2] 6 | A+1 Aor X+1-X or M+1-+-M | @]e@)* ae Decrement 1 pec aati] 2{sal1[2|aa)2/5]7al1 | 516A) 2] 6[At -Aorx-1-XorM-1-M lolol +[ale Clear con [ar] 12 {sel ata }ar)2)5 rel +. s [er 2| 6 | 00- of 00x or 00 -M elelaolile Complement com [43] 12/53/11 2[a3} 2/5 73/1) 8 lea! 2[6|% -Aor Kx or MM elefs| [1 Negate l T OOA -A or OO-X-X (2's Complement) NEG 40/ + | 2 {60,1 | 2/30) 2| 5 | 70! 145 (60) 2] 6 | or OO-M +M @le;r]ris Rotate Left Thru Carry ROL 49) 1) 2799) 1) 2739) 2), 5 779) 1,5 169) 276 @le@;r]r]* Rotate Right Thru Carry ROR 46|1|2 [68/1 | 2/36) 2/5 |76/1 | 5 leg} 2] 6 @iois Logical Shit Left LSL 48} 1 | 2 (58/1 | 2/38) 2] 5 |78) 1/5 {66; 2/6 @l@; pris Logical Shift Right LSR a4). | 2isal 1] 2/34) 2] 5|7a) 1] s|ea) 246 elelatals Arthmetic Shift Right ASR 47/1 [2/157] 1/ 2/37) 2) 5/77) 1)5 1/67) 276 @;a@a;apays Arighmetic Shitt Left ASL 48) 1) 2/58) 1 | 2/38; 2) 5);78) 15 5 |68) 2; 6 | Equal to LSL elelalala Test for Negative or Zero TST 4D] 1/2/50] 1 | 2/30; 2) 4 |70;) 1; 4 (80) 21] 5 | A-00 or X-00 of M00 @elel/ajal,se Symbols: Op = Operation # == Number of bytes ~ = Number of cycles @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 593HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 Table ? Branch Instructions Addressing Modes .. Operations Mnemonic Relative Branch Test Condition Code OP | # ~ Hi TIN] ZI Cc Branch Always BRA 20 2 3 | None e e;/eltele Branch Never BRN 21 2 3. | None e;@ eljele Branch tF Higher BHI 22 2 3 | C+Z=0 *e:;e@el/e;e\e Branch IF Lower or Same BLS 23 | 2 3 | C+Z=1 ele, el/e ie Branch IF Carry Clear BCC 24/2) 3 |c=0 elelelele (Branch IF Higher or Same) (BHS) 24 2 3 /C=0 eielele ie Branch iF Carry Set BcsS 25 2 3 |C=1 ele\/e;ele (Branch iF Lower) {BLO} 25 2 3 }C=1 eiei\/e:e/e Branch IF Not Equal BNE 26 2 3 |Z=0 @el\/eielele Branch IF Equal BEQ 27 | 2 | 3 /z=1 elelelele Branch IF Half Carry Clear BHCC 28 2 3 |} H=0 /elelete Branch IF Half Carry Set BHCS 29) 2 | 3 |H=1 elelelele Branch IF Plus BPL 2A 2 3. |N=0 @,;e/el/ele Branch IF Minus BMI 2B 2 3 |N=1 ei elelele Branch IF interrupt Mask Bit is Clear BMC 2c | 2 3 |1=0 ei\elelele Branch IF Interrupt Mask Bit is Set BMS 2D | 2 3 jl=1 @el\|e@el/e/e ,e Branch IF Interrupt Line is Low BIL 2E 2 3 | INT=C e\/eleleie Branch IF Interrupt Line is High BIH 2F 2 3 | INT=1 @e@ie\/e\ele Branch to Subroutine BSR AD | 2 5 | eielelieie Symbols: Op = Operation # == Number of bytes ~ = Number of cycles Table 8 Bit Maniputation Instructions Addressing Modes Operations Mnemonic Bit Set Clear | Bit Test and Branch Arithmetic Branch Condition Code op [#|/~/] OP |x | ~ | Operation H| ITN] z[C Branch {F Bit n is set BRSET nin=0.--7) = -j- 2-n 3/5 Mn=1 @e\/e ee! + Branch IF Bit n is clear | BRCLR n(n=0.--7} - |{|]01+2-n|) 3/5 . Mn=0 @ e@elerealns Set Bit n BSET nin=0---7} [10+2-n/2/5[ | !!y>mMn lel elelele Clear Bit n BCLR nin=0---7} | 114+2-n|/ 2/5 - -~!||0-Mn~ @el/eielieie Symbols: Op = Operation # == Number of bytes ~ = Number of cycles @ HITACHI 594 Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 Table 9 Control Instructions Addressing Modes . Operations Mnemonic Implied Boolean Operation Condition Code oP | # ~ HI I IN] ZC Transfer A to X TAX 97 1 2 | A>X ele\/e|/eje Transfer X to A TXA SF 1 2 | XA eje\|eje ie Set Carry Bit SEC 99 1 1 |1- @lel/e;e| Clear Carry Bit cLe 98 1 1 |Q-C ele;ele|/a0 Set Interrupt Mask Bit SEI 9B 1 2 | 1-41 ei/llele|le Clear Interrupt Mask Bit cul SA 1 2 | 0-4 e'dOle/\e;e Software Interrupt SWI a3 1 10 e ije@elele Return from Subroutine RTS a1 1 5 e e@el,eleie Return from Interrupt RTI 80 1 8 7/7/7127] 9 Reset Stack Pointer RSP 9c 1 2 | $FF--SP e eleie ie No- Operation NOP 9D 1 1. | Advance Prog. Catr. Only @el\e\|el ele Decimal Adjust A DAA so | 1 2 | Gapverts binary add of BCD charctars into elelalata Stop STOP 8E 1 4 elelelele Wait WAIT 8F 1 4 e ele ele Symbols: rial partion bytes * Are BCD characters of upper byte 10 or more? (They are not cleared if set in advance.) ~ = (Number of cycles Table 10 Instruction Set (in Alphabetical Order) Addressing Modes Condition Code Bit Bit Mnemonic Indexed | Indexed | Indexed Set/ Tast & Implied | immediate | Oirect | Extended Relative {(No Offset)| {8-Bit) | (16-Bit) | Clear Branch | H}| || N |) ZI) C ADC x x x x x x ALT@LALTALA ADD x x x x x x Al@lLAT ALA AND x x x x x x elelrisaie ASL x x x x @elelalalta ASR x bed x @l@lajyaya gcc x @eieleleie BCLA x elelelele acs x eleijeleie BEO x elelelele BHCC x ejelelele BHCS x eleleiele BHI x ejlelele je (BHS} x elejiele |e aiH x elelelele BIL x elelele|s BIT x x x x x x @l/@;Alale (BLO) x elele|;e\e BLS x eleleiele BMC x elele/ele BMI x elei|e|\/e,e BMS x el/e;e\|e)|e BNE x eljelele |e BPL x elele|e\@ BRA x | elieleiele Condition Code Symbols: (to be continued) o Half Carry (From Bit 3) i Interrupt Mask N Negative (Sign Bit} 2 Zero Carry Borrow Test and Set if True. Cleared Otherwise Not Affected Load CC Register From Stack ~@>ro @ HITACHI Hitachi America, Ltd. Hitachi Plaza # 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 595HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 Table 10 Instruction Set (in Alphabetical Order} Addressing Modes Condition Code Mnemonic Implied | Immediate indexed Direct |Extended| Relative | (No Offset) indexed (8-Bit) Indexed (16-Bit} Bit Clear Bit Test & Branch BRN x BRCLR BRSET BSET BSR cic x cul x CLR x CMP COM x ~|>|/@ @/;o;@!;e@);>)>]/e@eloa CPX Mx) x] x x KI xXx xX KX| XxX] X DAA x BEC x ePl>l]>l>|>)/ > /Olelele@e/e@e el/e@e/e/2 EOR INC x JMP JSR LDA LDX x) wK | K) x x) x LK LX LSL LSR NEG KEM| MI) RK) RM) MYM] | KK x, xX] xX) x) KL KL RL KT Kx XLRI) XX] RK] RK] KR KEK x) x | x] NOP ORA x x x x ROL x x x ROR RSP ATI wi@] >] >/)@/)@; >|] >]>)@/@)/@/@)@)@)@)>o)> ML xX) KK] xX ATS SBC Sec x SEI x STA STOP x STX @\/@\;e/e@e;-|> |e SUB > Swi |@/@/e/@e;/-|e/e@/@)~/@ ;e@ @e/e ee ee ee a ee eo elese e/a /@#, /olelel/e/e;e/@ TAX @l/@/ >| > lel; > ele: >) @i-s,la@i>] >) >i ee); >) >) >y >) >]/e]/@) > >] r]/>]/>)/>1 > ejelelele|le@elelnNn TST a TXA KML xX | xX] xX WAIT e/e\/e ee @ oe /ele/e ae ee; ~/e/e ee ee ele/eie ele eie;ei/e ei ecie/sel/e/e/eje/e ,e,e/z @)/@)> ee) >) >) e@l>] el) el >| @) yw e@y >) >] >] @)] > aol >] >| > e)@ Condition Code Symbols: H Half Carry (From Bit 3) | Interrupt Mask N Negative (Sign Bit) 2 Zero ~e nn Carry Borrow Test and Set if True, Cleared Otherwise Not Affected Load CC Register From Stack @ HITACHI 596 Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 Table 11 Operation Code Map Bit Manipulation Branch Read Modify /Write Contra! | Register Memory Test & Set/ Branch Clear Rel DIR | A x X17 | XO] IMP | IMP | IMM) DIR | EXT | .X2) .X1 | XO 0 1 2 3/4/5!/6f7{[e8f[9;Aj;B!]c) Di E |} F |+HIGH 0 | BRSETO BSETO BRA NEG RTI" SUB 0 1 BRCLRO BCLRO BRN RTS CMP 1 2 | SRSET1 BSET1 BHI SBC \ 2 3 | BRCLRI BCLR1 BLS COM swr CPX 3/4 4) BRSET2 BSET2 BCC LSR AND 4 Q 5, BRCLR2 BCLR2 BCS BIT 5 6 | BRSET3 BSET3 BNE ROR LDA 6 7 | BRCER3 BCLR3 BEQ ASR TAX STA STAI+1}| 7 8 | BRSET4 BSET4 BHCC LSL/ASL CLC EOR 8 9 | BRCLR4 BCLR4 BHCS ROL SEC ADC 9 A | BRSET5 BSET5 BPL DEC cLi* ORA A B | BRCLR5 BCLRS BMI SEI* ADD B C | BRSET6 BSET6 BMC INC RSP* JMP( 1) Cc D| BRCLA6 | BCLR6 | BMS |rst-n| TST | TSTI1) [DAA[NOP|BSRY) JSR(+2) | JSA(+1) [s9A+2)| D E | BRSET? BSET?7 BIL STOP] LDXx E F } BRCLR7 BCLR7 BIH CLR WAIT") TXA STX STX(+1}) F | 3/5 2/5 2/3 2/5] 1/2] 172 | 2/6 | 1 6/1[i1)2/2/23]/34/35/24/13 (NOTES) 1. " is an undefined operation code. 2. The lowermost numbers in aach column represant a byte count and the number of cycles required (byte count/number of cycles). The number of cycles for tha mnemonics asterisked (*) is as follows: RTI 8 TAX 2 RTS 5 RSP 2 swi 10 TXA 2 DAA 2 BSR 5 STOP 4 cL 2 WAIT 4 SE! 2 3. The parenthesized numbers must be added to the cycle count of the particular instruction. @ Additional Instructions WAIT Causes the MCU to enter the wait mode. For this mode, The following new instructions are used on the HD63P0SY0: see the topic, Wait Mode. DAA Converts the contents of the accumulator into BCD STOP Causes the MCU to enter the stop mode. For this mode, code. see the topic, Stop Mode. @ HITACHI Hitachi America, Ltd. * Hitachi Piaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 597HD63P05Y0, HD63PA05Y0, HD63PBO5Y0 BB PRECAUTION 1BOARD DESIGN OF OSCILLATION CIRCUIT When connecting crystal and ceramic resonator with the XTAL and EXTAL pins to oscillate, observe the followings in designing the board. (1} Locate crystal, ceramic resonator, and load capacity C, and C> as near the LSI as possible. (Induction of noise from outside to the XTAL and EXTAL pins may cause trouble in oscillation.) (2) Wire the signal lines to the neighboring XTAL and EXTAL pins as far apart as possible. (3) Board design of situating signal lines or power supply lines near the oscillator circuit as shown as Figure 36, should not be used because of trouble in oscillation by induction. The resis- tor between the XTAL and EXTAL, and pins close to them should be 1(OMQ or more. The circuit in Fig. 35 is an example of good board design. @ PRECAUTION 2PROGRAM OF WRITE ONLY REGISTER Read/Modify/Write instructions are unavailable for changing the contents of Write Only Register (e.g. DDR; Data Direction Register of I/O port) of HD6305X, HD6305Y and HD63P0SY. {L) Data cannot be read from Write Only Register. (e.g. DDR of T/O port While Read/Modify/Write instructions are executed in the following sequence. (i) Reads the contents from appointed address. (ii) Changes the data which has been read. (iii) Turn the data back to the original address. Thus, Read/Modify/Write instructions cannot be ap- plied to Write Only Register such as DOR. (2) For the same reason, do not set DOR of I/O port using BSET and BCLR instructions. (3) Stored instructions (e.g. STA and STX, etc.) are available for writing into the Write Only Register. | C1 XTAL EXTAL M PRECAUTION 4WAIT/STOP INSTRUCTIONS PROGRAM When I bit of condition code register is 1 and interrupt (INT, TIMER/INT}, SCI/TIMER 2) is held, the MCU does not enter into WAIT mode by executing WAIT instruction. In that case, after the 4 dummy cycles, the MCU executes the next instruction. In the same way, when external interrupts (INT, INT>) are held at the bit I set, the MCU does not enter into the STOP mode by execut- ing STOP instruction. In that case the MCU executes the best in- struction after the 4 dummy cycles. ~Signal B ----|}-_+ Signal a -|- -j--Signal A i XTAL EXTAL HD6305X HD6305Y HD63P05 Figure 36 Example of Circuit Causing Trouble in Oscillation @ PRECAUTION WHEN USING BIL/BIH INSTRUCTION (1) Execute Instruction after the INT Voltage level has stabilized above Vy or below Vy, . (2) INT voltage level needs to be stabilized while BIL/BIH Instruc- tion Execution. There may be a malfunction by glitch on control signal if BIL/BIH Instruction Execution has exercized in unstablized INT signal level. ce VIH HD6305X INT HD6305Y vit x ; HDE3PO5Y ; BILBIH | BIL/BIH | Figure 35 Design of Oscillation Circuit Board Avoid BIU/GIH instruction Execution BH PRECAUTION 3SENDING/RECEIVING PROGRAM OF SERIAL DATA Be careful that malfunction may occur if SDR (SERIAL DATA REGISTER: $0012) is read or written during transmitting or receiv- ing serial data. HITACHI 598 Hitachi America, Ltd. Hitachi Piaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300