LH53V32500 FEATURES * 4,194,304 words x 8 bit organization (Byte mode) 2,097,152 words x 16 bit organization (Word mode) * Access time: 150 ns (MAX.) * Power consumption: Operating: 126 mW (MAX.) Standby: 108 W (MAX.) * Static operation * Three-state outputs * Low power supply: 2.7 V to 3.6 V * Packages: 44-pin, 600-mil SOP 48-pin, 12 x 18 mm2 TSOP (Type I) DESCRIPTION The LH53V32500 is a 32M-bit mask-programmable ROM organized as 4,194,304 x 8 bits (Byte mode) or 2,097,152 x 16 bits (Word mode) that can be selected by a BYTE input pin. It is fabricated using silicon-gate CMOS process technology. CMOS 32M (4M x 8/2M x 16) 3 V-Drive Mask-Programmable ROM PIN CONNECTIONS TOP VIEW 44-PIN SOP NC 1 44 A20 A18 2 43 A19 A17 3 42 A8 A7 4 41 A9 A10 A6 5 40 A5 6 39 A11 A4 7 38 A12 A3 8 37 A13 A2 9 36 A14 A1 10 35 A15 A0 11 34 A16 CE 12 33 BYTE GND 13 32 GND OE 14 31 D15/A-1 (LSB) D0 15 30 D7 D8 16 29 D14 D1 17 28 D6 D9 18 27 D13 D2 19 26 D5 D10 20 25 D12 D3 21 24 D4 D11 22 23 VCC 53V32500-1 Figure 1. Pin Connections for SOP Package 5-330 CMOS 32M Mask-Programmable ROM LH53V32500 48-PIN TSOP (Type I) TOP VIEW BYTE 1 48 A16 2 47 GND A15 3 46 D15/A-1 GND A14 4 45 D7 A13 5 44 D14 A12 6 43 D6 A11 7 42 D13 A10 8 41 D5 A9 9 40 D12 A8 10 39 D4 A19 11 38 VCC GND 12 37 VCC A20 13 36 GND A18 14 35 D11 A17 15 34 D3 A7 16 33 D10 A6 17 32 D2 A5 18 31 D9 A4 19 30 D1 A3 20 29 D8 A2 21 28 D0 A1 22 27 OE A0 23 26 GND CE 24 25 GND NOTE: Reverse bend available on request. 53V32500-2 Figure 2. Pin Connections for TSOP Package 5-331 LH53V32500 CMOS 32M Mask-Programmable ROM A20 44 A19 43 A18 2 A17 3 A16 34 A15 35 ADDRESS DECODER A10 40 A9 41 A8 42 A7 4 A6 5 29 D14 27 D13 25 D12 DATA SELECTOR/OUTPUT BUFFER ADDRESS BUFFER A14 36 A13 37 A12 38 A11 39 31 D15 MEMORY MATRIX (4,194,302 x 8) (2,097,152 x 16) A5 6 A4 7 A3 8 A2 9 COLUMN SELECTOR A1 10 A0 11 22 D11 20 D10 18 D9 16 D8 30 D7 28 D6 26 D5 24 D4 21 D3 19 D2 17 D1 CE 12 CE BUFFER OE 14 OE BUFFER BYTE 33 TIMING GENERATOR BYTE/WORD SWITCHOVER CIRCUIT 15 D0 SENSE AMPLIFIER ADDRESS BUFFER 31 A-1 23 VCC 13 32 GND NOTE: Pin numbers apply to the 44-pin SOP. 53V32500-3 Figure 3. LH53V32500 Block Diagram PIN DESCRIPTION SIGNAL A-1 - A20 D0 - D15 BYTE CE PIN NAME Address input NOTE SIGNAL PIN NAME 1 OE Output Enable input Data output 1 VCC Power supply (2.7 V to 3.6 V) Byte/word mode switch 1 GND Ground Chip Enable input NC NOTE No connection NOTE: 1. The D15/A-1 pin becomes LSB address input (A-1) when the BYTE pin is set to be LOW in byte mode, and data output (D15) when set to be HIGH in word mode. 5-332 CMOS 32M Mask-Programmable ROM LH53V32500 A20 13 A19 11 A18 14 A17 15 A16 2 A15 3 A9 9 A8 10 A7 16 A6 17 42 D13 40 D12 A5 18 A4 19 A3 20 A2 21 44 D14 COLUMN SELECTOR A1 22 A0 23 DATA SELECTOR/OUTPUT BUFFER A12 A11 7 A10 8 ADDRESS DECODER 4 5 6 ADDRESS BUFFER A14 A13 46 D15 MEMORY MATRIX (4,194,302 x 8) (2,097,152 x 16) 35 D11 33 D10 31 D9 29 D8 45 D7 43 D6 41 D5 39 D4 34 D3 32 D2 30 D1 CE 24 CE BUFFER OE 27 OE BUFFER BYTE 1 BYTE/WORD SWITCHOVER CIRCUIT 28 D0 TIMING GENERATOR SENSE AMPLIFIER ADDRESS BUFFER 46 A-1 37 38 VCC 12 25 26 36 47 48 GND NOTE: Pin numbers apply to the 48-pin TSOP (Type I). 53V32500-4 Figure 4. LH53V32500 Block Diagram 5-333 LH53V32500 CMOS 32M Mask-Programmable ROM TRUTH TABLE CE OE BYTE DATA OUTPUT ADDRESS INPUT A-1 (D15) D0 - D7 D8 - D15 LSB MSB SUPPLY CURRENT H L X H X X X X High-Z High-Z High-Z High-Z - - - - Standby (ISB) Operating (ICC ) L L L L H L - L D0 - D7 D0 - D7 L L L H D8 - D15 D8 - D15 High-Z High-Z A0 A-1 A-1 A20 A20 A20 Operating (ICC ) Operating (ICC ) Operating (ICC ) NOTE: X = H or L; High-Z = High-impedance ABSOLUTE MAXIMUM RATINGS SYMBOL RATING UNIT Supply voltage Input voltage Output voltage Operating temperature PARAMETER VCC VIN VOUT Topr - 0.3 to +4.6 - 0.3 to VCC + 0.3 - 0.3 to VCC + 0.3 0 to +70 V V V C Storage temperature Tstg - 65 to +150 C RECOMMENDED OPERATING CONDITIONS (TA = 0C to +70C) PARAMETER SYMBOL MIN. VCC 2.7 Supply voltage TYP. MAX. UNIT 3.6 V DC CHARACTERISTICS (VCC = 2.7 V to 3.6 V, TA = 0C to +70C) PARAMETER SYMBOL Input `High' voltage Input `Low' voltage V IH VIL Output `High' voltage Output `Low' voltage VOH Input leakage current Output leakage current Operating current Standby current Input capacitance Output capacitance VOL | ILI | | ILO | ICC1 ISB1 ISB2 CIN COUT NOTES: 1. CE/OE = VIH 2. VIN = VIH or VIL, CE = VIL, outputs open 5-334 CONDITIONS I OH = -400 A I OL = 1.6 mA V IN = 0 V to VCC V OUT t RC = CE = CE = = 0 V to VCC 150 ns VIH VCC - 0.2 V f = 1 MHz T A = 25C MIN. MAX. UNIT 0.7 VCC -0.3 VCC +0.3 0.2 VCC V V 0.4 5 V VCC - 0.4 V NOTE V 5 35 1 A A mA mA 30 10 10 A pF pF 1 2 CMOS 32M Mask-Programmable ROM LH53V32500 AC CHARACTERISTICS (VCC = 2.7 V to 3.6 V, TA = 0C to +70C) PARAMETER SYMBOL MIN. Read cycle time Address access time Chip enable access time Output enable delay time Output hold time CE to output in High-Z OE to output in High-Z tRC tAA tACE tOE tOH tCHZ tOHZ 150 MAX. 150 150 70 5 60 60 UNIT ns ns ns ns ns ns ns NOTE 1 NOTE: 1. This is the time required for the outputs to become high-impedance. AC TEST CONDITIONS PARAMETER Input voltage amplitude Input rise/fall time Input reference level Output reference level Output load condition RATING 0.2 V to 0.7 V 10 ns 1.4 V 1.4 V 1TTL + 100 pF CAUTION To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the VCC pin and the GND pin. 5-335 LH53V32500 CMOS 32M Mask-Programmable ROM tRC A-1 - A20 tAA (NOTE) CE tACE tCHZ (NOTE) OE tOHZ tOE (NOTE) D0 - D7 tOH DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. 53V32500-5 Figure 5. Byte Mode (BYTE = VIL) tRC A0 - A20 tAA (NOTE) CE tACE tCHZ (NOTE) OE tOHZ tOE (NOTE) D0 - D15 tOH DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. 53V32500-6 Figure 6. Word Mode (BYTE = VIH) 5-336 CMOS 32M Mask-Programmable ROM LH53V32500 PACKAGE DIAGRAMS 44SOP (SOP044-P-0600) 0.50 [0.020] 0.30 [0.012] 1.27 [0.050] TYP. 44 23 13.40 [0.528] 13.00 [0.512] 1 16.40 [0.646] 15.60 [0.614] 14.40 [0.567] SEE DETAIL 22 0.20 [0.008] 0.10 [0.004] 28.40 [1.118] 28.00 [1.102] 2.9 [0.114] 2.5 [0.098] DETAIL 1.275 [0.050] 0.15 [0.006] 1.275 [0.050] 0.25 [0.010] 0.05 [0.002] 2.9 [0.114] 2.5 [0.098] 3.25 [0.128] 2.45 [0.096] 0.25 [0.010] 0.05 [0.002] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 0 - 10 0.80 [0.031] 44SOP 44-pin, 600-mil SOP 5-337 LH53V32500 CMOS 32M Mask-Programmable ROM 48TSOP (TSOP048-P-1218) 0.50 [0.020] TYP. 0.30 [0.012] 0.10 [0.004] 25 48 16.60 [0.654] 16.20 [0.638] 1 18.40 [0.724] 17.60 [0.693] 17.00 [0.669] 24 12.20 [0.480] 11.80 [0.465] 0.15 [0.006] 0.425 [0.017] 0.20 [0.008] 0.10 [0.004] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] DIMENSIONS IN MM [INCHES] 0.20 [0.008] 0.00 [0.000] MAXIMUM LIMIT MINIMUM LIMIT 48TSOP 2 48-pin, 12 x 18 mm TSOP (Type I) ORDERING INFORMATION LH53V32500 Device Type X Package N 44-pin, 600-mil SOP (SOP044-P-0600) T 48-pin, 12 x 18 mm2 TSOP (Type I) (TSOP048-P-1218) TR 48-pin, 12 x 18 mm2 TSOP (Type I) Reverse bend (TSOP048-P-1218) CMOS 32M (4M x 8 or 2M x 16) Mask-Programmable ROM, Low-Voltage Operation Example: LH53V32500N (CMOS 32M (4M x 8 or 2M x 16) Mask-Programmable ROM, Low-Voltage Operation, 44-pin, 600-mil SOP) 5-338 53V32500-7