LTC3823
1
3823fd
FEATURES
APPLICATIONS
DESCRIPTION
Fast No RSENSE
TM
Step-Down
Synchronous DC/DC Controller
with Differential Output Sensing,
Tracking and PLL
The LTC
®
3823 is a synchronous step-down switching regu-
lator controller with true remote differential output sensing
and output voltage up/down tracking capability. Its advanced
functions and high accuracy reference are ideal for powering
high performance server, ASIC and computer memory
systems.
The LTC3823 uses a constant on-time, valley current
mode control architecture to deliver very low duty fac-
tors without requiring a sense resistor. The operating
frequency is selected by an external resistor and is com-
pensated for variations in input supply voltage. An internal
phase-locked loop allows the IC to be synchronized to an
external clock.
Fault protection is provided by an overvoltage compara-
tor and input undervoltage lockout. The regulator current
limit is user programmable. A wide supply range allows
voltages as high as 36V to be stepped down to as low as
a 0.6V output. When using remote sense, output voltages
up to 3.3V can be developed, and up to 90% of VIN without
remote sense. Power supply sequencing is accomplished
using an external soft-start timing capacitor.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents including 5481178, 5847554,
6580258, 6304066, 6476589, 6774611.
n Wide VIN Range: 4.5V to 36V
n ±0.67%, 0.6V Reference Voltage
n Output Voltage Tracking Capability
n True Remote Sensing Differential Amplifi er
n Sense Resistor Optional
n True Current Mode Control
n 2% to 90% Duty Cycle at 200kHz
n t
ON(MIN) < 100ns
n Phase-Locked Loop Frequency Synchronization
n Powerful Dual N-Channel MOSFET Driver
n Adjustable Cycle-by-Cycle Current Limit
n Adjustable Switching Frequency
n Programmable Soft-Start
n Current Foldback Protection (Disabled at Start-Up)
n Output Overvoltage Protection
n Micropower Shutdown: 30μA
n Power Good Output Voltage Monitor Tracks the
Reference Input Pin
n Available in (5mm × 5mm) 32-Lead QFN and
28-Lead SSOP Narrow Packages
n Distributed Power Systems
n Server Power Supplies
CMDSH-3
B340A
9.5k
1.8μH
10μF
10μF
35V
s3
V
IN
5V TO 28V
V
OUT
2.5V
10A
180μF
4V
s2
Si4874
Si4884
68k
0.1μF
0.22μF
10k
1000pF
V
OUT
3k
10k
0.01μF
+
I
ON
V
IN
TG
SW
BOOST
PLLIN
RUN
I
TH
SGND INTV
CC
BG
PGND
SENSE
–
SENSE
+
V
OUTSENSE+
V
FB
LTC3823
DRV
CC
PGOOD
V
OUTSENSE–
V
DIFFOUT
V
ON
V
RNG
TRACK/SS
PLLFLTR
3823 TA01a
LOAD CURRENT (A)
0.1
87
EFFICIENCY (%)
POWER LOSS (W)
88
90
91
92
97
94
0.01
0.1
10
1
1
3823 TA01b
89
95
96
93
10
VIN = 5V
VOUT = 2.5V
FIGURE 12 CIRCUIT
EFFICIENCY
POWER LOSS
Effi ciency and Power Loss
vs Load Current
High Effi ciency Step-Down Converter
TYPICAL APPLICATION
LTC3823
2
3823fd
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
Input Supply Voltage VIN,
V
INSNS ....................................................–0.3V to 36V
DRVCC, (BOOST – SW) ............................–0.3V to 7V
BOOST ................................................... –0.3V to 42V
SENSE+, SW Voltage .................................–5V to 36V
TRACK/SS, FCB, Z0, Z1/SSENABLE, Z2,
PLLIN, VOUTSENSE+, VOUTSENSE–
Voltages .................................. –0.3V to (INTVCC + 0.3)V
VON, VRNG, PGOOD Voltages .. –0.3V to (INTVCC + 0.3)V
VDIFFOUT ................................................–0.3V to INTVCC
(Note 1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
GN PACKAGE
28-LEAD PLASTIC SSOP NARROW
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FCB
RUN
VON
PGOOD
VRNG
VFB
ITH
SGND
ION
VDIFFOUT
VOUTSENSE+
VOUTSENSE–
TRACK/SS
PLLFLTR
Z0
BOOST
TG
SW
SENSE+
SENSE–
PGND
BG
INTVCC
Z2
Z1/SSENABLE
ZVCC
VIN
PLLIN
TJMAX = 125°C, θJA = 80°C/W
32 31 30 29 28 27 26 25
9 10 11 12
TOP VIEW
33
SGND
UH PACKAGE
32-LEAD
(
5mm s 5mm
)
PLASTIC QFN
13 14 15 16
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1VRNG
VFB
ITH
SGND
ION
VDIFFOUT
NC
VOUTSENSE+
SENSE+
SENSE–
PGND
BG
DRVCC
INTVCC
Z2
Z1/SSENABLE
PGOOD
VON
RUN
FCB
Z0
BOOST
TG
SW
VOUTSENSE–
NC
TRACK/SS
PLLFLTR
PLLIN
VIN
VINSNS
ZVCC
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 33) IS SGND, MUST BE SOLDERED TO PCB
RUN, ION .................................................... –0.3V to 12V
PLLFLTR, ITH, VFB Voltages ...................... –0.3V to 2.7V
INTVCC, ZVCC Voltages ................................–0.3V to 7V
TG, BG, INTVCC Peak Currents ....................................4A
TG, BG, INTVCC RMS Currents ...............................50mA
Operating Temperature Range .................–40°C to 85°C
Junction Temperature (Note 2) ............................. 125°C
Storage Temperature Range ..................–65°C to 125°C
Lead Temperature (Soldering, 10 sec)
SSOP ................................................................300°C
PIN CONFIGURATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3823EGN#PBF LTC3823EGN#TRPBF LTC3823EGN 28-Lead Plastic SSOP Narrow –40°C to 85°C
LTC3823IGN#PBF LTC3823IGN#TRPBF LTC3823IGN 28-Lead Plastic SSOP Narrow –40°C to 85°C
LTC3823EUH#PBF LTC3823EUH#TRPBF 3823 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C
LTC3823IUH#PBF LTC3823IUH#TRPBF 3823 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
ORDER INFORMATION
LTC3823
3
3823fd
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop
IQInput DC Supply Current Normal Operation
Shutdown Supply Current
1400
30
2200
50
μA
μA
VFB Feedback Voltage Accuracy (Note 3) ITH = 1.2V (0°C to 85°C)
ITH = 1.2V l
0.596
0.594
0.6
0.6
0.604
0.606
V
V
VFB(LINEREG) Feedback Voltage Line Regulation VIN = 4.5V to 30V, ITH = 1.2V (Note 3) 0.002 %/V
VFB(LOADREG) Feedback Voltage Load Regulation ITH = 0.5V to 1.9V (Note 3) –0.04 –0.3 %
VRUN RUN Pin On Threshold VRUN Rising 1 1.5 1.9 V
ISS/TRACK Soft-Start Charge Current VSS/TRACK = 0V –1.3 –1.7 –2.3 μA
IFB Feedback Pin Input Current –100 –20 100 nA
gm(EA) Error Amplifi er Transconductance ITH = 1.2V (Note 3) l1.65 mS
VFCB Forced Continuous Threshold l0.57 0.6 0.63 V
IFCB Forced Continuous Pin Current VFCB = 0V –1 –2 μA
tON On-Time ION = –60μA, VON = 1.5V
ION = –60μA, VON = 0V
210
80
250
115
290
150
ns
ns
tON(MIN) Minimum On-Time ION = –180μA, VON = 0V 50 100 ns
tOFF(MIN) Minimum Off-Time 280 400 ns
VSENSE(MAX) Maximum Current Sense Threshold VRNG = 1V, VFB = 570mV (0°C to 85°C)
VRNG = 0V, VFB = 570mV (0°C to 85°C)
VRNG = INTVCC, VFB = 570mV (0°C to 85°C)
120
50
240
140
70
280
160
85
320
mV
mV
mV
VSENSE(MIN) Minimum Current Sense Threshold VRNG = 1V, VFB = 630mV
VRNG = 0V, VFB = 630mV
VRNG = INTVCC, VFB = 630mV
–60
–30
–120
mV
mV
mV
ΔVFB(OV) Output Overvoltage Fault Threshold Offset 8 11 14 %
VIN(UVLO+)Undervoltage Lockout VIN Falling 3.1 3.4 V
VIN(UVLO–)Undervoltage Lockout VIN Rising 3.9 4.1 V
TG RUP TG Driver Pull-Up On-Resistance TG High 1.9 2.5 Ω
TG RDOWN TG Driver Pull-Down On-Resistance TG Low 1.2 2.5 Ω
BG RUP BG Driver Pull-Up On-Resistance BG High 1.9 3 Ω
BG RDOWN BG Driver Pull-Down On-Resistance BG Low 0.7 1.5 Ω
TG trTG Rise Time CLOAD = 3300pF 20 ns
TG tfTG Fall Time CLOAD = 3300pF 20 ns
BG trBG Rise Time CLOAD = 3300pF 20 ns
BG tfBG Fall Time CLOAD = 3300pF 20 ns
Internal VCC Regulation
VINTVCC Internal VCC Voltage 6V < VIN < 36V l4.75 5 5.45 V
ΔVLDO(LOADREG) Internal VCC Load Regulation ICC = 0mA to 20mA –0.1 ±2 %
Phase-Locked Loop
RPLLIN PLLIN Input Resistance 50 kΩ
IPLLFLTR Phase Detector Sink Current
Phase Detector Source Current
fPLLIN < fO
fPLLIN > fO
–15
15
μA
μA
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = 15V unless otherwise specifi ed.
LTC3823
4
3823fd
Current Sense Threshold
vs ITH Voltage On-Time vs ION Current On-Time vs VON Voltage
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PGOOD Output
ΔVFBH PGOOD Upper Threshold VFB Rising 8 11 14 %
ΔVFBL PGOOD Lower Threshold VFB Falling –8 –11 –14 %
ΔVFB(HYS) PGOOD Hysteresis VFB Returning 1.5 3 %
VPGL PGOOD Low Voltage IPGOOD = 5mA 0.15 0.4 V
Differential Sensing Amplifi er
ADA Gain l0.9965 1.000 1.0035 V/V
RIN Input Resistance Measured at VOUTSENSE+ Input 80 kΩ
VOS Input Offset Voltage VOUTSENSE+ = VDIFFOUT = 1.5V,
IDIFFOUT = 1mA
2mV
PSRROA Power Supply Rejection Ratio 6V < VIN < 30V 90 dB
ICL Maximum Output Current 3mA
VOUT(MAX) Maximum Output Voltage IDIFFOUT = 300μA l3.775 4 V
GBW Gain Bandwidth Product IDIFFOUT = 1mA 3.5 MHz
Thermal Shutdown
TSD Shutdown Temperature Rising 170 °C
THYST Thermal Hysteresis 15 °C
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = 15V unless otherwise specifi ed.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formulas:
LTC3823GN: TJ = TA + (PD • 80°C/W)
LTC3823UH: TJ = TA + (PD • 34°C/W)
Note 3: The LTC3823 is tested in a feedback loop that servos VFB to
achieve a specifi ed error amplifi er output voltage (ITH).
Note 4: The LTC3823E is guaranteed to meet performance specifi cations
from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3823I is guaranteed over the full
–40°C to 85°C operating temperature range.
ITH VOLTAGE (V)
0
–150
CURRENT SENSE THRESHOLD (mV)
–100
0
50
100
122.5
300
2823 G01
–50
0.5 1.5
150
200
250
VRNG = 2V
1.4V
1V
0.7V
0.5V
ION CURRENT (μA)
10
ON-TIME (ns)
100
1000
10000
20 40 60 80
3823 G02
10010030507090
VON = 0V
VON VOLTAGE (V)
0
ON-TIME (ns)
800
700
600
500
400
300
200
100
0
4
3823 G03
123 53.50.5 1.5 2.5 4.5
IION = 60μA
TYPICAL PERFORMANCE CHARACTERISTICS
LTC3823
5
3823fd
TYPICAL PERFORMANCE CHARACTERISTICS
On-Time vs Temperature
Maximum Current Sense
Threshold vs VRNG Voltage
Maximum Current Sense
Threshold vs Temperature
Error Amplifi er gm vs Temperature Input Current vs Input Voltage Shutdown Current vs Input Voltage
TEMPERATURE (°C)
–50
200
ON-TIME (ns)
205
215
220
225
250
235
050 75
3823 G04
210
240
245
230
–25 25 100 125
IION = 30μA
VON = 0V
VRNG VOLTAGE (V)
0.5
50
MAX CURRENT SENSE THRESHOLD (mV)
100
150
200
250
300
0.75 1 1.25 1.5
3823 G05
1.75 2
TEMPERATURE (°C)
–50
100
MAX CURRENT SENSE THRESHOLD (mV)
105
115
120
125
150
135
050 75
3823 G06
110
140
145
130
–25 25 100 125
VRNG = 1V
TEMPERATURE (°C)
–50
gm (mS)
1.7
1.8
25 75
3823 G07
1.6
–25 0 50 100 125
1.5
INPUT VOLTAGE, VIN (V)
0
1.0
INPUT CURRENT (mA)
1.5
2.0
2.5
5101520
3823 G08
25 30
INPUT VOLTAGE, VIN (V)
0
0
SHUTDOWN CURRENT (μA)
10
20
30
40
60
510 15 20
3823 G09
25 30
50
INTVCC Load Regulation
INTVCC LOAD CURRENT (mA)
0
ΔINTVCC (%)
–0.4
–0.2
0
40
3823 G10
–0.6
–0.8
–0.5
–0.3
–0.1
–0.7
–0.9
–1.0 105 2015 30 35 45
25 50
FCB Pin Current vs Temperature
TEMPERATURE (°C)
–50
–1.50
FCB PIN CURRENT (μA)
–1.45
–1.35
–1.30
–1.25
–1.00
–1.15
050 75
3823 G11
–1.40
–1.10
–1.05
–1.20
–25 25 100 125
Track Up
VOUT
2V/DIV
TRACK/SS
AND VFB
500mV/DIV
250ms/DIV 3823 G12
TRACK/SS
FIGURE 12 CIRCUIT
VFB
VOUT
LTC3823
6
3823fd
TYPICAL PERFORMANCE CHARACTERISTICS
VOUT
2V/DIV
TRACK/SS
AND VFB
500mV/DIV
250ms/DIV 3823 G13
TRACK/SS
VFB
VOUT
FIGURE 12 CIRCUIT
VOUT
100mV/DIV
IL
5A/DIV
STEP
0A TO 10A
20μs/DIV 3823 G14
FIGURE 12 CIRCUIT
Track Down Transient Response Effi ciency vs Load Current
LOAD CURRENT (A)
0.1
50
EFFICIENCY (%)
55
65
70
75
100
85
1
3823 G15
60
90
95
80
10
DISCONTINUOUS MODE
CONTINUOUS MODE
FIGURE 12 CIRCUIT
LOAD CURRENT (A)
0
0
ITH VOLTAGE (mV)
200
600
800
1000
1400
157
38
2
3
G
1
6
400
1200
4910
2368
FIGURE 12 CIRCUIT
DISCONTINUOUS MODE
CONTINUOUS MODE
INPUT VOLTAGE (V)
0
240
FREQUENCY (kHz)
260
280
300
320
340
360
5101520
3823 G17
25
ILOAD = 10A
ILOAD = 1A
FCB = 0V
FIGURE 12 CIRCUIT
ITH Voltage vs Load Current Frequency vs Input Voltage Effi ciency vs Input Voltage
Frequency vs Load Current
INPUT VOLTAGE (V)
0
EFFICIENCY (%)
92
96
100
20
3823 G18
88
84
90
94
98
86
82
80 510 15 25
ILOAD = 10A
ILOAD = 1A
FCB = 5V
FIGURE 12 CIRCUIT
LOAD CURRENT (A)
0
FREQUENCY (kHz)
400
350
300
250
200
150
100
50
0
8
3823 G19
246 107135 9
FIGURE 12 CIRCUIT
DISCONTINUOUS MODE
CONTINUOUS
MODE
Current Limit Foldback ION Current vs VIN
VFB (V)
0
MAXIMUM CURRENT SENSE THRESHOLD (mV)
60
80
100
0.3 0.5
3823 G20
40
20
00.1 0.2 0.4
120
140
160
0.6
VRNG = 1V
INPUT VOLTAGE, VIN (V)
0
80
100
140
15 25
3823 G21
60
40
510 20 30 35
20
0
120
ION CURRENT (μA)
RON = 82k
LTC3823
7
3823fd
PIN FUNCTIONS
(UH/GN)
VRNG (Pin 1/Pin 5): Sense Voltage Range Input. The volt-
age at this pin is ten times the nominal sense voltage at
maximum output current and can be set from 0.5V to 2V
by a resistive divider from INTVCC. The nominal sense
voltage defaults to 50mV when this pin is tied to ground
and 200mV when tied to INTVCC. Do not set this voltage
between 0.5V to ground and 2V to INTVCC.
VFB (Pin 2/Pin 6): Error Amplifi er Feedback Input. This pin
connects the error amplifi er input to an external resistive
divider from VOUT.
ITH (Pin 3/Pin 7): Current Control Threshold and Error
Amplifi er Compensation Point. The current comparator
threshold increases with this control voltage. The voltage
ranges from 0V to 2.4V with 0.75V corresponding to zero
sense voltage (zero current).
SGND (Pin 4/Pin 8): Signal Ground. All small-signal
components and compensation components should
connect to this ground, which in turn, connects to PGND
at one point.
ION (Pin 5/Pin 9): On-Time Current Input. Tie a resistor
from this pin to ground to set the one-shot timer current
and thereby, set the switching frequency.
VDIFFOUT (Pin 6/Pin 10): Output of Remote Sensing Dif-
ferential Amplifi er. Connect this to VFB directly or through
a resistive divider.
VOUTSENSE+ (Pin 8/Pin 11): This is the positive sense pin
for the remote sense differential amplifi er. Connect this pin
to the positive terminal of the output load capacitor.
VOUTSENSE– (Pin 9/Pin 12): This is the negative sense pin
for the remote sense differential amplifi er. Connect this pin
to the negative terminal of the output load capacitor.
NC (Pins 7, 10, UH Package): No Connect.
TRACK/SS (Pin 11/Pin 13): Output Voltage Tracking and
Soft-Start Input. When the IC is confi gured to be the
master of two outputs, a capacitor to ground at this pin
sets the ramp rate for the output voltage. When the IC is
confi gured to be the slave of two outputs, the VFB voltage
of the master IC is reproduced by a resistive divider and
applied to this pin during the soft-start phase. An internal
1.7μA soft-start current is charging this pin during the
soft-start phase.
PLLFLTR (Pin 12/Pin 14): The phase-locked loop’s lowpass
fi lter is tied to this pin. The voltage at this pin defaults to
1.180V when the IC is not synchronized with an external
clock at the PLLIN pin.
PLLIN (Pin 13/Pin 15): External Synchronization Input to
Phase Detector. This pin is internally terminated to SGND
with a 50k resistor.
VIN (Pin 14/Pin 16): Main Input Supply. Decouple this to
PGND with a capacitor (0.1μF to 1μF).
VINSNS (Pin 15, UH Package): VIN Voltage Sense Input.
Normally this pin is tied to VIN. However, in certain ap-
plications when the IC is powered from a separate supply,
VINSNS is tied to the upper MOSFET supply to sense the
VIN voltage. This pin is co-bonded with VIN in the GN
package.
ZVCC (Pin 16/Pin 17): Post-Package Zener Trim Supply.
Under normal conditions this pin should always be con-
nected to INTVCC.
Z1/SSENABLE (Pin 17/Pin 18): Post-Package Zener Trim
Control. This pin is a multifunctional pin used in produc-
tion for post-package trimming and tracking. Ground this
pin under normal soft-start operation. Connecting this
pin to INTVCC will turn off the soft-start current during
tracking.
Z2 (Pin 18/Pin 19): Post-Package Zener Trim Control.
This pin is used in production for post-package trimming.
Ground this pin under normal operation.
INTVCC (Pin 19/Pin 20): Internal 5V Regulated Output. The
control circuits are powered from this voltage. Decouple
this pin to PGND with a minimum of 4.7μF low ESR tan-
talum or ceramic capacitor.
DRVCC (Pin 20, UH Package): Driver Voltage Input. Must
be connected to INTVCC externally. Do not exceed 7V at
this pin. This pin is co-bonded to INTVCC internally in the
GN package.
BG (Pin 21/Pin 21): Bottom Gate Driver Output. This pin
drives the gate of the bottom N-channel MOSFET between
ground and INTVCC.
LTC3823
8
3823fd
PIN FUNCTIONS
(UH/GN)
PGND (Pin 22/Pin 22): Power Ground. Connect this pin
closely to the source of the bottom N-channel MOSFET,
the (–) terminal of CVCC and CIN.
SENSE– (Pin 23/Pin 23): Current Sense Comparator In-
put. The negative input to the current comparator is used
to accurately Kelvin sense the bottom side of the sense
resistor or MOSFET.
SENSE+ (Pin 24/Pin 24): Current Sense Comparator
Input. The positive input to the current comparator is
normally connected to the SW node unless using a sense
resistor.
SW (Pin 25/Pin 25): Switch Node. The (–) terminal of the
bootstrap capacitor, CB, connects here. This pin swings
from a diode drop below ground up to VIN.
TG (Pin 26/Pin 26): Top Gate Drive Output. This pin drives
the top N-channel MOSFET with a voltage swing equal to
INTVCC, superimposed on the switch node voltage SW.
BOOST (Pin 27/Pin 27): Boosted Floating Driver Supply.
The (+) terminal of the bootstrap capacitor, CB, connects
here. This pin swings from a diode voltage drop below
INTVCC up to VIN + INTVCC.
Z0 (Pin 28/Pin 28): Dead Time Control Input. Applying a
DC voltage at this pin will vary the dead time between TG
low and BG high transition. Do not force a voltage higher
than INTVCC on this pin.
FCB (Pin 29/Pin 1): Forced Continuous Input. Connect
this pin to SGND to forced continuous synchronization
operation at low load, to INTVCC to enable discontinuous
mode operation at low load, or to a resistive divider from
a secondary output when using a secondary winding.
RUN (Pin 30/Pin 2): Run Control Input. A voltage above
1.5V turns on the IC. Forcing this pin below 1.5V shuts
down the device.
VON (Pin 31/Pin 3): On-Time Input. Connecting this pin
to the output voltage makes the on-time proportional to
VOUT. The comparator input defaults to 0.6V when the
pin is grounded and defaults to 4.8V when the pin is tied
to INTVCC.
PGOOD (Pin 32/Pin 4): Power Good Output. Open-drain
logic that is pulled to ground when the output voltage is
not within ±11% of the regulation point after the internal
20μs power bad mask timer expires.
SGND (Exposed Pad Pin 33, UH Package): The exposed
pad is signal ground. It must be soldered to PCB ground
for electrical contact and for rated thermal performance.
LTC3823
9
3823fd
FUNCTIONAL DIAGRAM
0.5V
0.6V
2.0V
0.5V
VRNG
–
+
–+
–+
–+
–
+
ION FCB VIN
1
μ
A
RON
VVON
IION
tON = (10pF) R
SQ
20k
ICMP IREV
Q6
3.3
μ
A
RUN
SWITCH
LOGIC
AND
ANTI-
SHOOT
THROUGH
BG
ON
FCNT
F
0.6V
OV
1
240k
Q1
Q2
1.5V
EXTERNAL TO CHIP
ITH RC
CC1
EA
SS
Q4
VDIFFOUT
SGND
R2
(EXT)
R1
(EXT)
RUN
PGND
PGOOD
DRVCC
INTVCC
INTVCC
SW
TG CB
VIN
CIN
BOOST
–
+
–
+
OV
UV
CVCC
VOUT
M2
M1
L1
COUT
DB
ITHB
VOUT
0.6V 4.8V
VON
RSENSE
(OPTIONAL)
SENSE+
SENSE–
SENSE+
SENSE–
BG M2
*CONNECTION W/O
SENSE RESISTOR
SW
PGND
(0.5~2)
–+
FOLDBACK
–
+
0.25V
TRACK/SS
FOLDBACK
DISABLED
AT START-UP
RUN
VFB
PLLIN
PLLFLTR
PLL-SYNC
+
VINSNS
Z0
Z1/SSENABLE
Z2
ZVCC
+
+
5V
REG
1.7
μ
A
CSS
3823 FD
R
R
R
INTVCC
40k
VOUTSENSE–
VOUTSENSE+
40k
40k
40k
–
+
LTC3823
10
3823fd
OPERATION
Main Control Loop
The LTC3823 is a current mode controller for DC/DC
step-down converters. In normal operation, the top
MOSFET is turned on for a fi xed interval determined by
a one-shot timer, OST. When the top MOSFET is turned
off, the bottom MOSFET is turned on until the current
comparator ICMP trips, restarting the one-shot timer and
initiating the next cycle. Inductor current is determined
by sensing the voltage between the SENSE– and SENSE+
pins using a sense resistor or the bottom MOSFET on-
resistance . The voltage on the ITH pin sets the comparator
threshold corresponding to inductor valley current. The
error amplifi er EA adjusts this voltage by comparing the
feedback signal, VFB, to an internal reference voltage. If
the load current increases, it causes a drop in the feedback
voltage relative to the reference. The ITH voltage then rises
until the average inductor current again matches the load
current.
At low load currents, the inductor current can drop to zero
and become negative. This is detected by current reversal
comparator IREV which then shuts off M2, resulting in
discontinuous operation. Both switches will remain off
with the output capacitor supplying the load current until
the ITH voltage rises above the zero current level (0.75V)
to initiate another cycle. Discontinuous mode operation
is disabled by comparator F when the FCB pin is brought
below 0.6V, forcing continuous synchronous operation.
The operating frequency is determined implicitly by the
top MOSFET on-time and the duty cycle required to main-
tain regulation. The one-shot timer generates an on time
that is proportional to the ideal duty cycle, thus holding
frequency approximately constant with changes in VIN.
The nominal frequency can be adjusted with an external
resistor, RON.
For applications with stringent constant frequency re-
quirements, the LTC3823 can be synchronized with an
external clock. By programming the nominal frequency
of the LTC3823 the same as the external clock frequency,
the LTC3823 behaves as a constant frequency part against
the load and supply variations.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±10% window around the regulation point after the
internal 20μs power bad mask timer expires. Furthermore,
in an overvoltage condition, M1 is turned off and M2 is
turned on immediately and held on until the overvoltage
condition clears.
Foldback current limiting is provided if the output is shorted
to ground. As VFB drops, the buffered current threshold
voltage, ITHB, is pulled down and clamped to 0.9V. This
reduces the inductor valley current level to one-tenth of its
maximum value as VFB approaches 0V. Foldback current
limiting is disabled at start-up.
Pulling the RUN pin low forces the controller into its
shutdown state, turning off both M1 and M2. Forcing a
voltage above 1.5V will turn on the device.
INTVCC Power
Power for the top and bottom MOSFET drivers and most of
the internal controller circuitry is derived from the INTVCC
pin. The top MOSFET driver is powered from a fl oating
bootstrap capacitor, CB. This capacitor is recharged from
INTVCC through an external Schottky diode, DB, when the
top MOSFET is turned off. If the input voltage is low and
INTVCC drops below 3V, undervoltage lockout circuitry
prevents the power switches from turning on.
LTC3823
11
3823fd
APPLICATIONS INFORMATION
The basic LTC3823 application circuit is shown in
Figure 12. External component selection is primarily de-
termined by the maximum load current and begins with
the selection of the sense resistance and power MOSFET
switches. The LTC3823 uses either a sense resistor or
the on-resistance of the synchronous power MOSFET for
determining the inductor current. The desired amount of
ripple current and operating frequency largely determines
the inductor value. Finally, CIN is selected for its ability to
handle the large RMS current into the converter and COUT
is chosen with low enough ESR to meet the output voltage
ripple and transient specifi cation.
Maximum Sense Voltage and VRNG Pin
Inductor current is determined by measuring the volt-
age across a sense resistance that appears between the
SENSE– and SENSE+ pins. The maximum sense voltage
is set by the voltage applied to the VRNG pin and is equal
to approximately (0.133)VRNG. The current mode control
loop will not allow the inductor current valleys to exceed
(0.133)VRNG/RSENSE. In practice, one should allow some
margin for variations in the LTC3823 and external com-
ponent values and a good guide for selecting the sense
resistance is:
RV
I
SENSE RNG
OUT MAX
=10 • ()
An external resistive divider from INTVCC can be used
to set the voltage of the VRNG pin between 0.5V and 2V
resulting in nominal sense voltages of 50mV to 200mV.
Additionally, the VRNG pin can be tied to SGND or INTVCC in
which case the nominal sense voltage defaults to 50mV or
200mV, respectively. The maximum allowed sense voltage
is about 1.33 times this nominal value.
Connecting the SENSE+ and SENSE– Pins
The IC can be used with or without a sense resistor. When
using a sense resistor, place it between the source of the
bottom MOSFET, M2, and PGND. Connect the SENSE+ and
SENSE– pins to the top and bottom of the sense resistor.
Using a sense resistor provides a well defi ned current
limit, but adds cost and reduces effi ciency. Alternatively,
one can eliminate the sense resistor and use the bottom
MOSFET as the current sense element by simply connecting
the SENSE+ pin to the SW pin and SENSE– pin to PGND.
This improves effi ciency, but one must carefully choose
the MOSFET on-resistance as discussed below.
Power MOSFET Selection
The LTC3823 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage V(BR)DSS,
threshold voltage V(GS)TH, on-resistance RDS(ON), reverse
transfer capacitance CRSS and maximum current IDS(MAX).
The gate drive voltage is set by the 5V INTVCC supply.
Consequently, logic-level threshold MOSFETs must be used
in LTC3823 applications. If the input voltage is expected
to drop below 5V, then sub-logic level threshold MOSFETs
should be considered.
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its on-resis-
tance. MOSFET on-resistance is typically specifi ed with
a maximum value RDS(ON)(MAX) at 25°C. In this case,
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
RR
DS ON MAX SENSE
T
()( )
=ρ
The ρT term is a normalization factor (unity at 25°C) ac-
counting for the signifi cant variation in on-resistance with
temperature, typically about 0.4%/°C as shown in Figure 1.
For a maximum junction temperature of 100°C, using a
value ρT = 1.3 is reasonable.
The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and the
load current. When the LTC3823 is operating in continuous
mode, the duty cycles for the MOSFETs are:
DV
V
DVV
V
TOP OUT
IN
BOT IN OUT
IN
=
=–
LTC3823
12
3823fd
The resulting power dissipation in the MOSFETs at maxi-
mum output current are:
P
TOP = DTOP IOUT(MAX)2 ρT(TOP) RDS(ON)(MAX)
+ k VIN2 IOUT(MAX) CRSS f
P
BOT = DBOT IOUT(MAX)2 ρT(BOT) RDS(ON)(MAX)
Both MOSFETs have I2R losses and the top MOSFET in-
cludes an additional term for transition losses, which are
largest at high input voltages. The constant k = 1.7A–1 can be
used to estimate the amount of transition loss. The bottom
MOSFET losses are greatest when the bottom duty cycle is
near 100%, during a short-circuit or at high input voltage.
Operating Frequency
The choice of operating frequency is a tradeoff between
effi ciency and component size. Low frequency operation
improves effi ciency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
The operating frequency of LTC3823 applications is de-
termined implicitly by the one-shot timer that controls
the on-time, tON, of the top MOSFET switch. The on-time
is set by the current out of the ION pin and the voltage at
the VON pin according to:
tV
IpF
ON VON
ION
=()10
Tying a resistor RON to SGND from the ION pin yields an
on-time inversely proportional to 1/3 VIN. The current out
of the ION pin is:
IV
R
ION IN
ON
=3
For a step-down converter, this results in approximately
constant frequency operation as the input supply varies:
fV
VRpF
H
OUT
VON ON Z
=•()
[]
310
To hold frequency constant during output voltage changes,
tie the VON pin to VOUT. The VON pin has internal clamps
that limit its input to the one-shot timer. If the pin is tied
below 0.6V, the input to the one-shot is clamped at 0.6V.
Similarly, if the pin is tied above 4.8V, the input is clamped
at 4.8V. In high VOUT applications, tie VON to INTVCC. Figures
2a and 2b show how RON relates to switching frequency
for several common output voltages.
JUNCTION TEMPERATURE (°C)
–50
RT NORMALIZED ON-RESISTANCE
1.0
1.5
150
3823 F01
0.5
0050 100
2.0
Figure 1. RDS(ON) vs Temperature
APPLICATIONS INFORMATION
RON (kΩ)
100
100
SWITCHING FREQUENCY (kHz)
1000
1000
3823 F02a
VOUT = 3.3V
VOUT = 1.5V
VOUT = 2.5V
RON (kΩ)
10
100
SWITCHING FREQUENCY (kHz)
1000
100 1000
3823 F02b
VOUT = 3.3V
VOUT = 12V
VOUT = 5V
Figure 2a. Switching Frequency vs RON (VON = 0V) Figure 2b. Switching Frequency vs RON (VON = INTVCC)
LTC3823
13
3823fd
When there is no RON resistor connected to the ION pin,
the on-time tON is theoretically infi nite, which in turn could
damage the converter. To prevent this, the LTC3823 detects
this fault condition and provides a minimum ION current
of 5μA to 10μA.
Changes in the load current magnitude will cause fre-
quency shift. Parasitic resistance in the MOSFET switches
and inductor reduce the effective voltage across the
inductance, resulting in increased duty cycle as the load
current increases. By lengthening the on-time slightly as
current increases, constant frequency operation can be
maintained. This is accomplished with a resistive divider
from the ITH pin to the VON pin and VOUT. The values
required will depend on the parasitic resistances in the
specifi c application. A good starting point is to feed about
25% of the voltage change at the ITH pin to the VON pin
as shown in Figure 3a. Place capacitance on the VON pin
to fi lter out the ITH variations at the switching frequency.
The resistor load on ITH reduces the DC gain of the error
amp and degrades load regulation, which can be avoided
by using the PNP emitter follower of Figure 3b.
MOSFET back off. This time is generally about 280ns.
The minimum off-time limit imposes a maximum duty
cycle of tON/(tON + tOFF(MIN)). If the maximum duty cycle
is reached, due to a dropping input voltage for example,
then the output will drop out of regulation. The minimum
input voltage to avoid dropout is:
VV
tt
t
IN MIN OUT ON OFF MIN
ON
() ()
=+
A plot of maximum duty cycle vs frequency is shown in
Figure 4.
APPLICATIONS INFORMATION
CVON
0.01μF
RVON2
100k
RVON1
30k
CC
VOUT
RC
(3a)
(3b)
VON
ITH
LTC3823
CVON
0.01μF
RVON2
10k
Q1
2N5087
RVON1
3k
10k
CC3823 F03
VOUT
INTVCC RC
VON
ITH
LTC3823
Figure 3. Correcting Frequency Shift with Load Current Changes
Minimum Off-Time and Dropout Operation
The minimum off-time tOFF(MIN) is the smallest amount of
time that the LTC3823 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
2.0
1.5
1.0
0.5
0
0 0.25 0.50 0.75
3823 F04
1.0
DROPOUT
REGION
DUTY CYCLE (VOUT/VIN)
SWITCHING FREQUENCY (MHz)
Figure 4. Maximum Switching Frequency vs Duty Cycle
Inductor Selection
Given the desired input and output voltages, the induc-
tor value and operating frequency determine the ripple
current:
ΔIV
fL
V
V
LOUT OUT
IN
=⎛
⎝
⎜⎞
⎠
⎟−
⎛
⎝
⎜⎞
⎠
⎟
•1
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest effi ciency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, effi ciency and operating frequency.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). The largest ripple current
occurs at the highest VIN. To guarantee that ripple current
LTC3823
14
3823fd
does not exceed a specifi ed maximum, the inductance
should be chosen according to:
LV
fI
V
V
OUT
LMAX
OUT
IN MAX
=⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟−
⎛
⎝
⎜
⎜
⎞
⎠
Δ() ()
1⎟⎟
⎟
Once the value for L is known, the type of inductor must
be selected. High effi ciency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mμ
®
cores. A variety of inductors designed for
high current, low voltage applications are available from
manufacturers such as Sumida, Panasonic, Coiltronics,
Coilcraft and Toko.
Schottky Diode D1 Selection
The Schottky diode D1 shown in Figure 12 conducts dur-
ing the dead time between the conduction of the power
MOSFET switches. It is intended to prevent the body diode
of the bottom MOSFET from turning on and storing charge
during the dead time, which can cause a modest (about
1%) effi ciency loss. The diode can be rated for about one
half to one fi fth of the full load current since it is on for
only a fraction of the duty cycle. In order for the diode
to be effective, the inductance between it and the bottom
MOSFET must be as small as possible, mandating that
these components be placed adjacently. The diode can
be omitted if the effi ciency loss is tolerable.
CIN and COUT Selection
The input capacitance CIN is required to fi lter the square
wave current at the drain of the top MOSFET. Use a low ESR
capacitor sized to handle the maximum RMS current.
II V
V
V
V
RMS OUT MAX OUT
IN
IN
OUT
≅() –1
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT(MAX)/2. This simple worst-case condition is
commonly used for design because even signifi cant de-
viations do not offer much relief. Note that ripple current
ratings from capacitor manufacturers are often based on
only 2000 hours of life which makes it advisable to derate
the capacitor.
The selection of COUT is primarily determined by the
ESR required to minimize voltage ripple and load step
transients. The output ripple ΔVOUT is approximately
bounded by:
ΔΔV I ESR fC
OUT L
OUT
≤+
⎛
⎝
⎜⎞
⎠
⎟
1
8
Since ΔIL increases with input voltage, the output ripple
is highest at maximum input voltage. Typically, once the
ESR requirement is satisfi ed, the capacitance is adequate
for fi ltering and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount pack-
ages. Special polymer capacitors offer very low ESR but
have lower capacitance density than other types. Tantalum
capacitors have the highest capacitance density but it is
important to only use types that have been surge tested
for use in switching power supplies. Aluminum electrolytic
capacitors have signifi cantly higher ESR, but can be used
in cost-sensitive applications providing that consideration
is given to ripple current ratings and long term reliability.
Ceramic capacitors have excellent low ESR characteris-
tics but can have a high voltage coeffi cient and audible
piezoelectric effects. The high Q of ceramic capacitors with
trace inductance can also lead to signifi cant ringing. When
used as input capacitors, care must be taken to ensure that
ringing from inrush currents and switching does not pose
an overvoltage hazard to the power switches and control-
ler. To dampen input voltage transients, add a small 5μF
to 50μF aluminum electrolytic capacitor with an ESR in
the range of 0.5Ω to 2Ω. High performance through-hole
capacitors may also be used, but an additional ceramic
capacitor in parallel is recommended to reduce the effect
of their lead inductance.
Top MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor CB connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
This capacitor is charged through diode DB from INTVCC
when the switch node is low. When the top MOSFET turns
APPLICATIONS INFORMATION
LTC3823
15
3823fd
on, the switch node rises to VIN and the BOOST pin rises
to approximately VIN + INTVCC. The boost capacitor needs
to store about 100 times the gate charge required by the
top MOSFET. In most applications 0.1μF to 0.47μF, X5R
or X7R dielectric capacitor is adequate.
Discontinuous Mode Operation and FCB Pin
The FCB pin determines whether the bottom MOSFET
remains on when current reverses in the inductor. Tying
this pin above its 0.6V threshold enables discontinuous
operation where the bottom MOSFET turns off when in-
ductor current reverses. The load current at which current
reverses and discontinuous operation begins depends on
the amplitude of the inductor ripple current and will vary
with changes in VIN. Tying the FCB pin below the 0.6V
threshold forces continuous synchronous operation, al-
lowing current to reverse at light loads and maintaining
high frequency operation. To prevent forcing current back
into the main power supply, potentially boosting the input
supply to a dangerous voltage level, forced continuous
mode of operation is disabled when the TRACK/SS volt-
age is 20% below the reference voltage during soft-start
or tracking up. Forced continuous mode of operation is
also disabled when the TRACK/SS voltage is below 0.1V
during tracking down operation. During these two periods,
the PGOOD signal is forced low.
In addition to providing a logic input to forced continu-
ous operation, the FCB pin provides a mean to maintain
a fl yback winding output when the primary is operating
in discontinuous mode. The secondary output VOUT2 is
normally set as shown in Figure 5 by the turns ratio N
of the transformer. However, if the controller goes into
discontinuous mode and halts switching due to a light
primary load current, then VOUT2 will droop. An external
resistor divider from VOUT2 to the FCB pin sets a minimum
voltage VOUT2(MIN) below which continuous operation is
forced until VOUT2 has risen above its minimum.
VV
R
R
OUT MIN206 1 4
3
() .=+
⎛
⎝
⎜⎞
⎠
⎟
Fault Conditions: Current Limit and Foldback
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage.
In the LTC3823, the maximum sense voltage is controlled
by the voltage on the VRNG pin. With valley current control,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
IV
RI
LIMIT SNS MAX
DS ON T
L
=+
()
()
ρ
1
2Δ
The current limit value should be checked to ensure that
ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit
generally occurs with the largest VIN at the highest ambi-
ent temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of ILIMIT which heats
the MOSFET switches.
Caution should be used when setting the current limit
based upon the RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET
on-resistance. Data sheets typically specify nominal
and maximum values for RDS(ON), but not a minimum.
A reasonable assumption is that the minimum RDS(ON)
lies the same percentage below the typical value as the
maximum lies above it. Consult the MOSFET manufacturer
for further guidelines.
To further limit current in the event of a short circuit to
ground, the LTC3823 includes foldback current limiting.
If the output falls by more than 60%, then the maximum
sense voltage is progressively lowered to about one tenth
of its full value.
APPLICATIONS INFORMATION
VIN
LTC3823
SGND
FCB
TG
SW
R3
R4
3823 F05
T1
1:N
BG
PGND
+COUT2
1μF VOUT1
VOUT2
VIN
+
CIN
1N4148
•
•
+
COUT
Figure 5. Secondary Output Loop
LTC3823
16
3823fd
INTVCC Regulator
An internal P-channel low dropout regulator produces the
5V supply that powers the drivers and internal circuitry
within the LTC3823. The INTVCC pin can supply up to 50mA
RMS and must be bypassed to ground with a minimum
of 4.7μF low ESR tantalum capacitor or other low ESR
capacitor. Good bypassing is necessary to supply the high
transient currents required by the MOSFET gate drivers.
Applications using large MOSFETs with a high input voltage
and high frequency of operation may cause the LTC3823
to exceed its maximum junction temperature rating or
RMS current rating. Most of the supply current drives the
MOSFET gates. In continuous mode operation, this current
is IGATECHG = f(Qg(TOP) + Qg(BOT)). The junction temperature
can be estimated from the equations given in Note 2 of the
Electrical Characteristics. For example, the GN package is
limited to less than 23mA from a 30V supply:
T
J = 70°C + (23mA)(30V)(80°C/W) = 125°C
For applications where more current is needed than INTVCC
can supply, INTVCC can be driver by an external supply
with a voltage higher than 5.35V. However, the INTVCC pin
should not exceed its absolute maximum voltage of 7V.
External Gate Drive Buffers
The LTC3823 drivers are adequate for driving up to about
50nC into MOSFET switches with RMS currents of 50mA.
Applications with larger MOSFET switches or operating
at frequencies requiring greater RMS currents will benefi t
from using external gate drive buffers such as the LTC1693.
Alternately, the external buffer circuit shown in Figure 6
can be used.
Soft-Start and Tracking
The LTC3823 has the ability to either soft start by itself with
a capacitor or track the output of another supply. When
the device is confi gured to soft start by itself, a capacitor
should be connected to the TRACK/SS pin. The LTC3823
is put in a low quiescent current shutdown state (30μA)
if the RUN pin voltage is below 1.5V. The TRACK/SS
pin is actively pulled to ground in this shutdown state.
Once the RUN pin voltage is above 1.5V, the LTC3823 is
powered up. A soft-start current of 1.7μA then starts to
charge the soft-start capacitor CSS. Pin Z1/SSENABLE must
be grounded for soft-start operation. Note that soft-start
is achieved not by limiting the maximum output current
of the controller but by controlling the ramp rate of the
output voltage. Current foldback is disabled during this
soft-start phase. During the soft-start phase, the LTC3823
is ramping the reference voltage until it is 20% below the
voltage set by the VREFIN pin. The forced continuous mode
is also disabled and PGOOD signal is forced low during this
phase. The total soft-start time can be calculated as:
t
SOFTSTART = 0.5V • CSS/1.7μA
When the device is confi gured to track another supply,
the feedback voltage of the other supply is duplicated by
a resistor divider and applied to the TRACK/SS pin. Pin
Z1/SSENABLE should be tied to INTVCC to turn off the soft-
start current in this mode. Therefore, the voltage ramp rate
on this pin is determined by the ramp rate of the other
supply output voltage.
Output Voltage Tracking
The LTC3823 allows the user to program how its output
ramps up and down by means of the TRACK/SS pin.
Through this pin, the output can be set up to either co-
incidentally or ratiometrically track with another supply’s
output, as shown in Figure 7. In the following discussions,
VOUT1 refers to the master LTC3823’s output and VOUT2
refers to the slave LTC3823’s output.
To implement the coincident tracking in Figure 7a, connect
an additional resistive divider to VOUT1 and connect its
midpoint to the TRACK/SS pin of the slave IC. The ratio of
this divider should be selected the same as that of the slave
IC’s feedback divider shown in Figure 8. In this tracking
APPLICATIONS INFORMATION
Q1
FMMT619
GATE
OF M1
TG
BOOST
SW
Q2
FMMT720
Q3
FMMT619
GATE
OF M2
BG
3823 F06
INTVCC
PGND
Q4
FMMT720
10Ω 10Ω
Figure 6. Optional External Gate Driver
LTC3823
17
3823fd
mode, VOUT1 must be set higher than VOUT2. To implement
the ratiometric tracking, the ratio of the divider should be
exactly the same as the master IC’s feedback divider. Note
that the pin Z1/SSENABLE of the slave IC should be tied to
INTVCC so that the internal soft-start current is disabled
in both tracking modes or it will introduce a small error
on the tracking voltage depending on the absolute values
of the tracking resistive divider.
By selecting different resistors, the LTC3823 can achieve
different modes of tracking including the two in Figure 7.
So which mode should be programmed? While either
mode in Figure 7 satisfi es most practical applications,
there do exist some tradeoffs. The ratiometric mode saves
a pair of resistors, but the coincident mode offers better
output regulation. This can be better understood with the
help of Figure 9. At the input stage of the slave IC’s error
amplifi er, two common anode diodes are used to clamp
the equivalent reference voltage and an additional diode
is used to match the shifted common mode voltage. The
top two current sources are of the same amplitude. In the
coincident mode, the TRACK/SS voltage is substantially
higher than 0.6V at steady state and effectively turns off
D1. D2 and D3 will therefore conduct the same current
and offer tight matching between VFB2 and the internal
precision 0.6V reference. In the ratiometric mode, however,
TRACK/SS equals 0.6V at steady state. D1 will divert part
of the bias current to make VFB2 slightly lower than 0.6V.
Although this error is minimized by the exponential I-V
characteristic of the diode, it does impose a fi nite amount
of output voltage deviation. Furthermore, when the master
IC’s output experiences dynamic excursion (under load
transient, for example), the slave IC output will be affected
as well. For better output regulation, use the coincident
tracking mode instead of ratiometric.
APPLICATIONS INFORMATION
TIME
(7a) Coincident Tracking
VOUT1
VOUT2
OUTPUT VOLTAGE
TIME 3823 F07
(7b) Ratiometric Tracking
VOUT1
VOUT2
OUTPUT VOLTAGE
Figure 7. Two Different Modes of Output Voltage Tracking
R3 R1
R4 R2
R3
VOUT2
R4
(8a) Coincident Tracking Setup
TO
VFB1
PIN
TO
TRACK/SS2
PIN
TO
VFB2
PIN
VOUT1
R1
R2
R3
VOUT2
R4
3823 F08
(8b) Ratiometric Tracking Setup
TO
VFB1
PIN
TO
TRACK/SS2
PIN
TO
VFB2
PIN
VOUT1
Figure 8. Setup for Coincident and Ratiometric Tracking
–
+
II
D1
TRACK/SS2
0.6V
VFB2
D2
D3
3823 F09
EA2
Figure 9. Equivalent Input Current of Error Amplifi er
LTC3823
18
3823fd
Differential Amplifi er
This amplifi er provides true differential output voltage
sensing. Sensing both the positive and negative terminals
of the output voltage benefi ts regulation in high current
applications and/or applications having electrical intercon-
nection losses. Precision feedback resistors are integrated
in the IC with the amplifi er already confi gured as a unity-gain
differential amplifi er. It has a GBW product of 3.5MHz and
an open-loop gain of >120dB. The amplifi er can source
>2mA of current, and can be used in applications with
up to 3.3V output voltage. The amplifi er is not capable of
sinking signifi cant current, and must be resistively loaded.
A load of 20kΩ or less is recommended for stability. The
amplifi er is not designed to drive capacitive loads.
Phase-Locked Loop and Frequency Synchronization
The LTC3823 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range
of the voltage controlled oscillator is ±30% around the
center frequency, fO. The center frequency is the operat-
ing frequency discussed in the previous section. The
LTC3823 incorporates a pulse detection circuit that will
detect a clock on the PLLIN pin. In turn, it will turn on the
phase-locked loop function. The pulse width of the clock
has to be greater than 400ns and the amplitude of the
clock should be greater than 2V.
During the start-up phase, phase-locked loop function is
disabled. When LTC3823 is not in synchronization mode,
PLLFLTR pin voltage is set to around 1.18V. Frequency
synchronization is accomplished by changing the internal
on-time current according to the voltage on the PLLFLTR
pin.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the ex-
ternal and internal pulses. This type of phase detector will
not lock up on input frequencies close to the harmonics
of the VCO center frequency. The PLL hold-in range, ΔfH,
is equal to the capture range, ΔfC:
ΔfH = ΔfC = ±0.3 fO
The output of the phase detector is a complementary pair of
current sources charging or discharging the external fi lter
network on the PLLFLTR pin. A simplifi ed block diagram
is shown in Figure 10.
If the external frequency (fPLLIN) is greater than the oscil-
lator frequency fO, current is sourced continuously, pull-
ing up the PLLFLTR pin. When the external frequency is
less than fO, current is sunk continuously, pulling down
the PLLFLTR pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. Thus the voltage on the PLLFLTR
pin is adjusted until the phase and frequency of the external
and internal oscillators are identical. At this stable operating
point the phase comparator output is open and the fi lter
capacitor CLP holds the voltage. The LTC3823 PLLIN pin
must be driven from a low impedance source such as a
logic gate located close to the pin.
The loop fi lter components (CLP, RLP) smooth out the cur-
rent pulses from the phase detector and provide a stable
input to the voltage controlled oscillator. The fi lter compo-
nents CLP and RLP determine how fast the loop acquires
lock. Typically RLP =10k and CLP is 0.01μF to 0.1μF.
Dead Time Control
To further optimize the effi ciency, the LTC3823 gives us-
ers some control over the dead time of the Top gate low
and Bottom gate high transition. By applying a DC voltage
on the Z0 pin, the TG low BG high dead time can be pro-
grammed. Because the dead time is a strong function of
APPLICATIONS INFORMATION
DIGITAL
PHASE/
FREQUENCY
DETECTOR
PLLIN
PLLFLTR
2.4V CLP
3823 F10
RLP
VCO
Figure 10. Phase-Locked Loop Block Diagram
LTC3823
19
3823fd
the load current and the type of MOSFET used, users need
to be careful to optimize the dead time for their particular
applications. Figure 11 shows the relation between the TG
Low BG High dead time by varying the Z0 voltages. For
an application using LTC3823 with load current of 5A and
IR7811W MOSFETs, the dead time could be optimized. To
make sure that there is no shoot-through under all condi-
tions, a dead time of 70ns is selected. This corresponds to
a DC voltage about 2.4V on Z0 pin. This voltage can easily
be generated with a resistor divider off INTVCC.
APPLICATIONS INFORMATION
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the
input voltage, load current, driver strength and MOSFET
capacitance, among other factors. The loss is signifi -
cant at input voltages above 20V and can be estimated
from:
Transition Loss ≅ (1.7A–1) VIN2 IOUT CRSS f
3. INTVCC current. This is the sum of the MOSFET driver
and control currents.
4. CIN loss. The input capacitor has the diffi cult job of
fi ltering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss
and suffi cient capacitance to prevent the RMS current
from causing additional upstream losses in fuses or
batteries.
Other losses, including COUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
When making adjustments to improve effi ciency, the input
current is the best indicator of changes in effi ciency. If you
make a change and the input current decreases, then the
effi ciency has increased. If there is no change in input
current, then there is no change in effi ciency.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ΔILOAD (ESR), where ESR is the effective series
resistance of COUT. ΔILOAD also begins to charge or dis-
charge COUT generating a feedback error signal used by the
regulator to return VOUT to its steady-state value. During
this recovery time, VOUT can be monitored for overshoot
or ringing that would indicate a stability problem. The ITH
pin external components shown in Figure 12 will provide
adequate compensation for most applications. For a
detailed explanation of switching control loop theory see
Application Note 76.
Z0 VOLTAGE (V)
0
TG LOW TO BG HIGH DEADTIME (ns)
120
160
200
4
3823 F11
80
40
100
140
180
60
20
010.5 21.5 3 3.5 4.5
2.5 5
IOUT = 2A
FIGURE 12 CIRCUIT
Figure 11. TG Low BG High Dead Time vs Z0 Voltage
Effi ciency Considerations
The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3823 circuits:
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
effi ciency to drop at high output currents. In continuous
mode the average output current fl ows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same RDS(ON), then
the resistance of one MOSFET can simply be summed
with the resistances of L and the board traces to obtain
the DC I2R loss. For example, if RDS(ON) = 0.01Ω and
RL = 0.005Ω, the loss will range from 15mW to 1.5W
as the output current varies from 1A to 10A.
LTC3823
20
3823fd
APPLICATIONS INFORMATION
Design Example
As a design example, take a supply with the following
specifi cations: VIN = 5V to 28V (15V nominal), VOUT =
2.5V ±5%, IOUT(MAX) = 10A, f = 320kHz. First, calculate
the timing resistor with VON = VOUT:
RV
VkHzpF k
ON =
()( )()
=
25
3 2 5 320 10 104
.
.Ω
and choose the inductor for about 40% ripple current at
the maximum VIN:
LV
kHz A
V
V
=
()()()
−
⎛
⎝
⎜⎞
⎠
⎟=
25
320 0 4 10 125
2817
.
.
..77µH
Selecting a standard value of 1.2μH results in a maximum
ripple current of:
Δμ
IV
kHz H
V
VA
L=
()()
⎛
⎝
⎜⎞
⎠
⎟=
25
320 1 2 125
2859
.
.–..
Next, choose the synchronous MOSFET switch. Choosing
a Si7892ADP (RDS(ON) = 0.005Ω (NOM) 0.006Ω (MAX),
θJA = 50°C/W) yields a nominal sense voltage of:
V
SNS(NOM) = (7A)(1.3)(0.005Ω) = 45mV
Tying VRNG to 0.75V will set the current sense voltage range
for a nominal value of 75mV with current limit occurring
at 100mV. To check if the current limit is acceptable, as-
sume a junction temperature of about 80°C above a 70°C
ambient with ρ150°C = 1.5:
ImV AA
LIMIT ≥
()( )
+
()
=
100
15 0006
1
259 14
.. .
Ω
and double check the assumed TJ in the MOSFET:
PVV
VAW
BOT =
()()( )
=
2825
2814 15 0006 16
2
–. .. .Ω
T
J = 70°C + (1.6W)(50°C/W) = 150°C
Because the top MOSFET is on for such a short time,
an Si7342DP RDS(ON)(MAX) = 0.010Ω, CRSS = 120pF,
θJA = 53°C/W will be suffi cient. Checking its power dissipa-
tion at current limit with ρ100°C = 1.4:
PV
VA
V
TOP =
()()
Ω
()
+
()( )
25
2814 1 4 0 010
17 28
2
2
...
.114 120 320
025 072 097
ApFkHz
WWW
()( )( )
=+=...
T
J = 70°C + (0.97W)(53°C/W) = 121°C
The junction temperature will be signifi cantly less at
nominal current, but this analysis shows that careful at-
tention to heat sinking on the board will be necessary in
this circuit.
CIN is chosen for an RMS current rating of about 3A at
85°C. The output capacitors are chosen for a low ESR
of 0.013Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
ΔVOUT(RIPPLE) = ΔIL(MAX) (ESR)
= (5.9A) (0.013Ω) = 77mV
However, a 0A to 10A load step will cause an output
change of up to:
ΔVOUT(STEP) = ΔILOAD (ESR) = (10A) (0.013Ω) = 130mV
An optional 22μF ceramic output capacitor is included
to minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 12.
PC Board Layout Checklist
When laying out a PC board follow one of two suggested
approaches. The simple PC board layout requires a ded-
icated ground plane layer. Also, for higher currents, it is
recommended to use a multilayer board to help with heat
sinking power components.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
LTC3823
21
3823fd
• Place CIN, COUT, MOSFETs, D1 and inductor all in one
compact area. It may help to have some components
on the bottom side of the board.
• Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3823.
Use several bigger vias for power components.
• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
• Use planes for VIN and VOUT to maintain good voltage
fi ltering and to keep power losses low.
• Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
component. You can connect the copper areas to any
DC net (VIN, VOUT, GND or to any other DC rail in your
system).
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera-
tion of the controller.
3823 F12
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
FCB
RUN
VON
PGOOD
VRNG
VFB
ITH
SGND
ION
VDIFFOUT
VOUTSENSE+
VOUTSENSE–
TRACK/SS
PLLFLTR
GND
PGOOD VRNG
INTVCC
VITH
ION
DIFFOUT
FB
TRACK/SS
RUN
Z0
BOOST
TG
SW
SENSE+
SENSE–
PGND
BG
INTVCC
Z2
Z1/SSENABLE
ZVCC
VIN
PLLIN
LTC3823GN
R6
7.5k
R5
42.5k
RON
100k
R2
16.2k
R1
5.11k
RC
1.5k
RPG
100k
CC2
100pF
CC1
6800pF
C4
220pF
CSS
0.1μF
1000pF
10k
CVCC
4.7μF
DB
CMDSH-3 D1
B320A
+COUT3
47μF
X5R
s3
COUT1
220μF
4V
VOUT
2.5V
10A
VIN
5V TO 28V
+
CIN
10μF
50V
s3
CB
0.22μF
R7
23.2k
R8
27.1k
M1
Si7342DP
L1
1.2μH
M2
Si7892ADP
PLLIN
+
0.01μF
Figure 12. Design Example: 2.5V/7A at 320kHz
• Segregate the signal and power grounds. All small-
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to
the source of M2.
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
• Connect the input capacitor(s) CIN close to the power
MOSFETs. This capacitor carries the MOSFET AC
current.
• Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Connect the INTVCC decoupling capacitor CVCC closely
to the INTVCC and PGND pins.
• Connect the top driver boost capacitor CB closely to
the BOOST and SW pins.
• Connect the VIN pin decoupling capacitor CIN closely
to the VIN and PGND pins.
APPLICATIONS INFORMATION
LTC3823
22
3823fd
TYPICAL APPLICATION
CP
1000pF
VOUTSENSE–
VRNG
VFB
ITH
SGND
ION
VDIFFOUT
NC
VOUTSENSE+
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
SENSE+
SENSE–
PGND
BG
DRVCC
INTVCC
Z2
Z1/SSENABLE
NC TRACK/SS PLLFLTR PLLIN VIN VINSNS ZVCC
PGOOD VON
32
RON
66.5k
1%
RC
1.5k
1%
R4
5.11k
1%
R5
5.11k
1%
RBOOST
0Ω
RRUN
100k
R1
23.2k
1%
RPG
100k
R2
26.7k
1%
C6
220pF
CC2
100pF
CPL
0.01μF
CSS
0.1μF
RVIN
10Ω
CVIN
0.1μF
CVCC
10μF
6.3V
Q2
Si4874
Q1
Si4884
R6
11k
R3
39k
E4
PGOOD
E1
INTVCC
INTVCC
VIN
E2
RUN
E10
TRACK/SS
E12
GND
E13
GND
E11
PLLIN
CC1
6800pF
31 30 29 28 27 26
DB
CMDSH-3-LTC
C5
0.22μF
91011 1213141516
RUN FCB
LTC3823UH
Z0 BOOST TG SW
RPL
10k
D1
B320A
L1
1μH
IHLP-2525CZ-01
C11
47μF
6.3V
s3
C12
10μF
6.3V
R7
100Ω
1%
C2
10μF
16V
s3
R8
100Ω
1%
E9
VOUTSENSE–
E6
VOUTSENSE+
E8
GND
E5
GND
E7
VOUT
1.2V/10A
E3
VIN
4.5V TO 16V
E14
VOUT
E15
GND
3823 TA02
Design Example: 1.2V/10A at 450kHz with Light Load Discontinuous Mode Operation
LTC3823
23
3823fd
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
PACKAGE DESCRIPTION
.386 – .393*
(9.804 – 9.982)
GN28 (SSOP) 0204
12
3456789101112
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
20212223242526272819 1817
13 14
1615
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.0075 – .0098
(0.19 – 0.25)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.033
(0.838)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
LTC3823
24
3823fd
PACKAGE DESCRIPTION
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
5.00 p 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 p 0.10
31
1
2
32
BOTTOM VIEW—EXPOSED PAD
3.50 REF
(4-SIDES)
3.45 p 0.10
3.45 p 0.10
0.75 p 0.05 R = 0.115
TYP
0.25 p 0.05
(UH32) QFN 0406 REV D
0.50 BSC
0.200 REF
0.00 – 0.05
0.70 p0.05
3.50 REF
(4 SIDES)
4.10 p0.05
5.50 p0.05
0.25 p 0.05
PACKAGE OUTLINE
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 s 45° CHAMFER
R = 0.05
TYP
3.45 p 0.05
3.45 p 0.05
LTC3823
25
3823fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
D 10/09 Text Change to Title
Patent Numbers Added
I-Grade Parts Added to Order Information
Text Changes to Notes 2, 3, 4
Text Changes to Pin Functions
Text Changes to Applications Information Section
Updated Related Parts
1
1
2
4
8
16
24
(Revision history begins at Rev D)
LTC3823
26
3823fd
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
LT 1209 REV D • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
CP
1000pF
VOUTSENSE–
VRNG
VFB
ITH
SGND
ION
VDIFFOUT
NC
VOUTSENSE+
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
SENSE+
SENSE–
PGND
BG
DRVCC
INTVCC
Z2
Z1/SSENABLE
NC TRACK/SS PLLFLTR PLLIN VIN VINSNS ZVCC
PGOOD VON
32
RON
90k
1%
RC
1.5k
1%
R4
5.11k
1%
R5
10.2k
1%
RBOOST 0Ω
RRUN
100k
R1
23.2k
1%
RPG
100k
R2
27.1k
1%
C6
220pF
CC2
100pF
CPL
0.01μF
CSS
0.1μF
RVIN
10Ω
CVIN
0.1μF
CVCC
10μF
6.3V
C9
47μF
6.3V
s3
Q2
Si4874
Q1
Si4884
R6
11k
R3
39k
E4
PGOOD
E1
INTVCC
INTVCC
VIN
E2
RUN
E10
TRACK/SS
E12
GND
300kHz
E13
GND
E11
PLLIN
CC1
6800pF
31 30 29 28 27 26
DB
CMDSH-3-LTC
C5
0.22μF
91011 1213141516
RUN FCB
LTC3823UH
Z0 BOOST TG SW
RPL
10k
D1
B320A
L1
1μH
IHLP-2525CZ-01
C7
180μF
+
R7
100Ω
1%
C2
10μF
16V
s3
R8
100Ω
1% E9
VOUTSENSE–
E6
VOUTSENSE+
E8
GND
E5
GND
E7
VOUT
1.8V/10A
E3
VIN
4.5V TO 16V
E14
VOUT
E15
GND
3823 TA03
Design Example: 1.8V/10A with Synchronization
PART NUMBER DESCRIPTION COMMENTS
LTC3854 Small Footprint Wide VIN Range Synchronous Step-Down
DC/DC Controller
Fixed 400kHz Operating Frequency, 4.5V ≤ VIN ≤ 38V,
0.8V ≤ VOUT ≤ 5.25V, 2mm × 3mm QFN-12
LTC3851A/
LTC3851A-1
No RSENSE Wide VIN Range Synchronous Step-Down DC/DC
Controller
Phase-Lockable Fixed Operating Frequency 250kHz to 750kHz,
4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5.25V, MSOP-16E, 3mm × 3mm
QFN-16, SSOP-16
LTC3878 No RSENSE Constant On-Time Synchronous Step-Down DC/DC
Controller
Very Fast Transient Response, tON(MIN) = 43ns, 4V ≤ VIN ≤ 38V,
0.8V ≤ VOUT ≤ 0.9VIN, SSOP-16
LTC3879 No RSENSE Constant On-Time Synchronous Step-Down DC/DC
Controller
Very Fast Transient Response, tON(MIN)= 43ns, 4V ≤ VIN ≤ 38V,
0.6V ≤ VOUT ≤ 0.9VIN, MSOP-16E, 3mm × 3mm QFN-16
LTC3850/LTC3850-1/
LTC3850-2
Dual 2-Phase, High Effi ciency Synchronous Step-Down DC/DC
Controllers, RSENSE or DCR Current Sensing and Tracking
Phase-Lockable Fixed Operating Frequency 250kHz to 780kHz,
4V ≤ VIN ≤ 30V, 0.8V ≤ VOUT ≤ 5.25V
LTC3855 Dual, Multiphase Synchronous Step-Down DC/DC with
Differential Remote Sense
Phase-Lockable Fixed Operating Frequency 250kHz to 770kHz,
4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 12.5V
LTM4600HV 10A DC/DC μModule
®
Complete Power Supply High Effi ciency, Compact Size, Ultrafast Transient Response,
4.5V ≤ VIN ≤ 28V, 0.8V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.8mm
LTM4601AHV 12A DC/DC μModule Complete Power Supply High Effi ciency, Compact Size, Ultrafast Transient Response,
4.5V ≤ VIN ≤ 28V, 0.8V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.8mm
LTC3610 12A, 1MHz, Monolithic Synchronous Step-Down DC/DC
Converter
High Effi ciency, Adjustable Constant On-Time, 4V ≤ VIN ≤ 24V,
VOUT(MIN) 0.6V, 9mm × 9mm QFN-64
LTC3611 10A, 1MHz, Monolithic Synchronous Step-Down DC/DC
Converter
High Effi ciency, Adjustable Constant On-Time, 4V ≤ VIN ≤ 32V,
VOUT(MIN) 0.6V, 9mm × 9mm QFN-64
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