LTM2882
1
2882fc
Typical applicaTion
DescripTion
Dual Isolated RS232
µModule Transceiver + Power
The LTM
®
2882 is a complete galvanically isolated dual
RS232 µModule
®
transceiver. No external components are
required. A single 3.3V or 5V supply powers both sides
of the interface through an integrated, isolated DC/DC
converter. A logic supply pin allows easy interfacing with
different logic levels from 1.62V to 5.5V, independent of
the main supply.
Coupled inductors and an isolation power transformer
provide 2500VRMS of isolation between the line transceiver
and the logic interface. This device is ideal for systems
with different grounds, allowing for large common mode
voltages. Uninterrupted communication is guaranteed for
common mode transients greater than 30kV/μs.
This part is compatible with the TIA/EIA-232-F standard.
Driver outputs are protected from overload and can be
shorted to ground or up to ±15V without damage. An
auxiliary isolated digital channel is available. This channel
allows configuration for half-duplex operation by control-
ling the DE pin.
Enhanced ESD protection allows this part to withstand up
to ±10kV (human body model) on the transceiver interface
pins to isolated supplies and across the isolation barrier
to logic supplies without latchup or damage.
Isolated Dual RS232 µModule Transceiver
FeaTures
applicaTions
n UL Rated Dual RS232 Transceiver: 2500VRMS
UL Recognized
®
File #E15178
n Isolated DC Power: 5V at Up to 200mA
n No External Components Required
n 1.62V to 5.5V Logic Supply for Flexible Digital
Interfacing
n High Speed Operation
1Mbps for 250pF/3kΩ Load
250kbps for 1nF/3kΩ Load
100kbps for 2.5nF/3kΩ TIA/EIA-232-F Load
n 3.3V (LTM2882-3) or 5V (LTM2882-5) Operation
n No Damage or Latchup to ±10kV HBM ESD on
Isolated RS232 Interface or Across Isolation Barrier
n High Common Mode Transient Immunity: 30kV/μs
n Common Mode Working Voltage: 560VPEAK
n True RS232 Compliant Output Levels
n Low Profile (15mm × 11.25mm) Surface Mount
BGA and LGA Packages
n Isolated RS232 Interface
n Industrial Communication
n Test and Measurement Equipment
n Breaking RS232 Ground Loops
1Mbps Operation
2882 TA01a
ON
DIN
T1IN
R1OUT
T2IN
R2OUT
DOUT
T1OUT
R1IN
T2OUT
R2IN
LTM2882
3.3V (LTM2882-3)
5V (LTM2882-5)
VLVCC
GND GND2
ISOLATION BARRIER
ONOFF
VCC2
DE
5V
AVAILABLE CURRENT:
150mA (LTM2882-5)
100mA (LTM2882-3)
400ns/DIV
DRIVER OUTPUTS TIED TO RECEIVER INPUTS
TOUT LOAD = 250pF + RIN
ROUT LOAD = 150pF
10V/DIV
5V/DIV TIN
T1OUT/R1IN
T2OUT/R2IN
5V/DIV
2882 TA01b
R1OUT
R2OUT
L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
LTM2882
2
2882fc
pin conFiguraTionabsoluTe MaxiMuM raTings
VCC to GND .................................................. –0.3V to 6V
VL to GND .................................................... –0.3V to 6V
VCC2 to GND2 ............................................... –0.3V to 6V
Logic Inputs
T1IN, T2IN, ON, DIN to GND ........–0.3V to (VL + 0.3V)
DE to GND2.............................–0.3V to (VCC2 + 0.3V)
Logic Outputs
R1OUT, R2OUT to GND ...............–0.3V to (VL + 0.3V)
DOUT to GND2 ........................–0.3V to (VCC2 + 0.3V)
Driver Output Voltage
T1OUT, T2OUT to GND2 ...........................–15V to 15V
Receiver Input Voltage
R1IN, R2IN to GND2 ............................... –25V to 25V
Operating Temperature Range (Note 4)
LTM2882C .........................................0°C ≤ TA ≤ 70°C
LTM2882I ..................................... –40°C ≤ TA ≤ 85°C
LTM2882H ...................................–40°C ≤ TA ≤ 105°C
LTM2882MP ...................................... –55°C to 105°C
Maximum Internal Operating Temperature ............ 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Package Body Reflow Temperature .............. 245°C
(Note 1)
VCC
GND
GND2
A
B
C
D
E
F
G
H
I
J
K
L
12345678
LGA PACKAGE
32-PIN (15mm × 11.25mm × 2.8mm)
TJMAX = 125°C,
θJA = 29°C/W, θJCtop = 27.9°C/W,
θJCbottom = 18°C/W, θJB = 22.7°C/W,
WEIGHT = 1.1g
BGA PACKAGE
32-PIN (15mm × 11.25mm × 3.42mm)
TJMAX = 125°C,
θJA = 30°C/W, θJCtop = 27.8°C/W,
θJCbottom = 19.3°C/W, θJB = 24°C/W,
WEIGHT = 1.1g
TOP VIEW
VCC2
VL
ONDINT1IN
R1OUT
T2IN
DE
DOUTT1OUTR1IN
T2OUT
R2IN
R2OUT
LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTM2882CY-3#PBF LTM2882CY-3#PBF LTM2882Y-3 32-Pin (15mm × 11.25mm × 3.42mm) BGA 0°C to 70°C
LTM2882IY-3#PBF LTM2882IY-3#PBF LTM2882Y-3 32-Pin (15mm × 11.25mm × 3.42mm) BGA –40°C to 85°C
LTM2882HY-3#PBF LTM2882HY-3#PBF LTM2882Y-3 32-Pin (15mm × 11.25mm × 3.42mm) BGA –40°C to 105°C
LTM2882MPY-3#PBF LTM2882MPY-3#PBF LTM2882Y-3 32-Pin (15mm × 11.25mm × 3.42mm) BGA –55°C to 105°C
LTM2882CY-5#PBF LTM2882CY-5#PBF LTM2882Y-5 32-Pin (15mm × 11.25mm × 3.42mm) BGA 0°C to 70°C
LTM2882IY-5#PBF LTM2882IY-5#PBF LTM2882Y-5 32-Pin (15mm × 11.25mm × 3.42mm) BGA –40°C to 85°C
LTM2882HY-5#PBF LTM2882HY-5#PBF LTM2882Y-5 32-Pin (15mm × 11.25mm × 3.42mm) BGA –40°C to 105°C
LTM2882MPY-5#PBF LTM2882MPY-5#PBF LTM2882Y-5 32-Pin (15mm × 11.25mm × 3.42mm) BGA –55°C to 105°C
LTM2882CV-3#PBF LTM2882CV-3#PBF LTM2882V-3 32-Pin (15mm × 11.25mm × 2.8mm) LGA 0°C to 70°C
LTM2882IV-3#PBF LTM2882IV-3#PBF LTM2882V-3 32-Pin (15mm × 11.25mm × 2.8mm) LGA –40°C to 85°C
LTM2882CV-5#PBF LTM2882CV-5#PBF LTM2882V-5 32-Pin (15mm × 11.25mm × 2.8mm) LGA 0°C to 70°C
LTM2882IV-5#PBF LTM2882IV-5#PBF LTM2882V-5 32-Pin (15mm × 11.25mm × 2.8mm) LGA –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
orDer inForMaTion
LTM2882
3
2882fc
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. LTM2882-3 VCC = 3.3V, LTM2882-5 VCC = 5.0V, VL = VCC, and GND =
GND2 = 0V, ON = VL unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supplies
VCC Input Supply Range LTM2882-3 l3.0 3.3 3.6 V
LTM2882-5 l4.5 5.0 5.5 V
VLLogic Supply Range l1.62 5.5 V
ICC Input Supply Current ON = 0V l0 10 µA
LTM2882-3, No Load l24 30 mA
LTM2882-5, No Load l17 21 mA
VCC2 Regulated Output Voltage, Loaded LTM2882-3 DE = 0V, ILOAD = 100mA l4.7 5.0 V
LTM2882-3, H/MP-Grade, ILOAD = 90mA l4.75 V
LTM2882-5 DE = 0V, ILOAD = 150mA l4.7 5.0 V
VCC2(NOLOAD) Regulated Output Voltage, No Load DE = 0, No Load 4.8 5.0 5.35 V
Efficiency ICC2 = 100mA, LTM2882-5 (Note 2) 65 %
ICC2 Output Supply Short-Circuit Current l250 mA
Driver
VOLD Driver Output Voltage Low RL = 3kΩ l–5 –5.7 V
VOHD Driver Output Voltage High RL = 3kΩ l5 6.2 V
IOSD Driver Short-Circuit Current VT1OUT, VT2OUT = 0V, VCC2 = 5.5V l±35 ±70 mA
IOZD Driver Three-State (High Impedance)
Output Current
DE = 0V, VT1OUT, VT2OUT = ±15V l±0.1 ±10 µA
Receiver
VIR Receiver Input Threshold Input Low l0.8 1.3 V
Input High
Input High, H/MP-Grade
l
l
1.7 2.5
2.7
V
V
VHYSR Receiver Input Hysteresis l0.1 0.4 1.0 V
RIN Receiver Input Resistance –15V ≤ (VR1IN, VR2IN) ≤ 15V l3 5 7 kΩ
Logic
VITH Logic Input Threshold Voltage ON, T1IN, T2IN, DIN = 1.62V ≤ VL < 2.35V l0.25•VL0.75•VLV
ON, T1IN, T2IN, DIN = 2.35V ≤ VL ≤ 5.5V l0.4 0.67•VLV
DE l0.4 0.67•VCC2 V
IINL Logic Input Current l±1 µA
VHYS Logic Input Hysteresis T1IN, T2IN, DIN (Note 2) 150 mV
VOH Logic Output High Voltage R1OUT, R2OUT
ILOAD = –1mA (Sourcing), 1.62V ≤ VL < 3.0V
ILOAD = –4mA (Sourcing), 3.0V ≤ VL ≤ 5.5V
l
l
VL – 0.4
VL – 0.4
V
V
DOUT, ILOAD = –4mA (Sourcing) lVCC2 – 0.4 V
VOL Logic Output Low Voltage R1OUT, R2OUT
ILOAD = 1mA (Sinking), 1.62V ≤ VL < 3.0V
ILOAD = 4mA (Sinking), 3.0V ≤ VL ≤ 5.5V
l
l
0.4
0.4
V
V
DOUT, ILOAD = 4mA (Sinking) l0.4 V
ESD (HBM) (Note 2)
RS232 Driver and Receiver Protection (T1OUT, T2OUT, R1IN, R2IN) to (VCC2, GND2) ±10 kV
(T1OUT, T2OUT, R1IN, R2IN) to (VCC, VL, GND) ±10 kV
Isolation Boundary (VCC2, GND2) to (VCC, VL, GND) ±10 kV
LTM2882
4
2882fc
swiTching characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. LTM2882-3 VCC = 3.3V, LTM2882-5 VCC = 5.0V, VL = VCC, and GND =
GND2 = 0V, ON = VL unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Maximum Data Rate
(T1IN to T1OUT, T2IN to T2OUT)
RL = 3kΩ, CL = 2.5nF (Note 3) l100 kbps
RL = 3kΩ, CL = 1nF (Note 3) l250 kbps
RL = 3kΩ, CL = 250pF (Note 3) l1000 kbps
Maximum Data Rate (DIN to DOUT) CL = 15pF (Note 3) l10 Mbps
Driver
Driver Slew Rate (6V/tTHL or tTLH) RL = 3kΩ, CL = 50pF (Figure 1) l150 V/µs
tPHLD, tPLHD Driver Propagation Delay RL = 3kΩ, CL = 50pF (Figure 1) l0.2 0.5 µs
tSKEWD Driver Skew |tPHLD – tPLHD| RL = 3kΩ, CL = 50pF (Figure 1) 40 ns
tPZHD, tPZLD Driver Output Enable Time DE = ↑ , RL = 3kΩ, CL = 50pF (Figure 2) l0.6 2 µs
tPHZD, tPLZD Driver Output Disable Time DE = ↓ , RL = 3kΩ, CL = 50pF (Figure 2) l0.3 2 µs
Receiver
tPHLR, tPLHR Receiver Propagation Delay CL = 150pF (Figure 3) l0.2 0.4 µs
tSKEWR Receiver Skew |tPHLR – tPLHR| CL = 150pF (Figure 3) 40 ns
tRR, tFR Receiver Rise or Fall Time CL = 150pF (Figure 3) l60 200 ns
Auxiliary Channel
tPHLL, tPLHL Propagation Delay CL = 15pF, tR and tF < 4ns (Figure 4) l60 100 ns
tRL, tFL Rise or Fall Time CL = 150pF (Figure 4) l60 200 ns
Power Supply
Power-Up Time ON = ↑ to VCC2(MIN) l0.2 2 ms
isolaTion characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. LTM2882-3 VCC = 3.3V, LTM2882-5 VCC = 5.0V, VL = VCC, and GND =
GND2 = 0V, ON = VL unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VISO Rated Dielectric Insulation Voltage 1 Minute, Derived from 1 Second Test 2500 VRMS
1 Second (Note 5) ±4400 V
Common Mode Transient Immunity VL = ON = 3.3V, VCM = 1kV, ∆t = 33ns (Note 2) 30 kV/µs
VIORM Maximum Working Insulation Voltage (Notes 2, 5) 560
400
VPEAK
VRMS
Partial Discharge VPR = 1050 VPEAK (Notes 2, 5) 5 pC
Input to Output Resistance (Notes 2, 5) 109Ω
Input to Output Capacitance (Notes 2, 5) 6 pF
Creepage Distance (Notes 2, 5) 9.48 mm
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Guaranteed by design and not subject to production test.
Note 3: Maximum Data Rate is guaranteed by other measured parameters
and is not tested directly.
Note 4: This device includes over-temperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above specified maximum operating junction
temperature may result in device degradation or failure.
Note 5: Tests performed from GND to GND2, all pins shorted each side of
isolation barrier.
LTM2882
5
2882fc
Typical perForMance characTerisTics
VCC Supply Current vs Load
Capacitance (Dual Transceiver)
VCC Supply Current vs Data Rate
(Dual Transceiver)
Driver Short-Circuit Current
vs Temperature
Receiver Input Threshold
vs Temperature
VCC Supply Current
vs Temperature
VCC Supply Current
vs Temperature
TA = 25°C, LTM2882-3 VCC = 3.3V, LTM2882-5
VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted.
TEMPERATURE (°C)
–50
VCC CURRENT (mA)
30
25
15
20
10 500 100
2882 G01
12525–25 75
NO LOAD
VCC = 3.3V
LTM2882-3
VCC = 5.0V
LTM2882-5
TEMPERATURE (°C)
–50
VCC CURRENT (mA)
70
60
40
35
45
55
65
50
30 500 100
2882 G02
12525–25 75
T1OUT AND T2OUT
BAUD = 100kbps
RL = 3k, CL = 2.5nF
VCC = 3.3V
LTM2882-3
VCC = 5.0V
LTM2882-5
LOAD CAPACITANCE (nF)
0
VCC CURRENT (mA)
100
250kbps, LTM2882-3
100kbps, LTM2882-3
19.2kbps, LTM2882-3
19.2kbps, LTM2882-5
250kbps, LTM2882-5 100kbps, LTM2882-5
80
40
50
30
70
90
60
20 1 2
2882 G03
2.50.5 1.5
DATA RATE (kbps)
0
VCC CURRENT (mA)
140
100
40
80
120
60
20 400 800
2882 G04
1000200 600
5.0V CL = 1nF
5.0V CL = 250pF
3.3V CL = 1nF
3.3V CL = 250pF
TEMPERATURE (°C)
–50
THRESHOLD VOLTAGE (V)
3.0
2.0
0.5
1.5
2.5
1.0
0500 100
2882 G05
125
INPUT LOW
25–25 75
INPUT HIGH
LOAD CAPACITANCE (nF)
0
SLEW RATE (V/µs)
70
50
10
20
40
60
30
042
2882 G06
531
FALLING
RISING
TEMPERATURE (°C)
–50
SHORT-CIRCUIT CURRENT (mA)
50
40
25
20
15
35
45
30
10 0 50 75 100
2882 G07
125–25 25
SOURCING
SINKING
Driver Slew Rate
vs Load Capacitance
Receiver Output Voltage
vs Load Current
LOAD CURRENT(mA)
0
OUTPUT VOLTAGE (V)
6
1
2
4
5
3
084
2882 G09
1062
VL = 5.5V
VL = 3.3V
VL = 1.62V
Driver Disabled Leakage Current
vs Temperature at ±15V
TEMPERATURE (°C)
–50
LEAKAGE CURRENT (nA)
1000
10
0.01
1
100
0.1
0.001 0 50 75 100
2882 G08
125–25 25
VTOUT = ±15V
LTM2882
6
2882fc
Typical perForMance characTerisTics
Driver Outputs Exiting Shutdown Driver Outputs Enable/Disable
Logic Input Threshold
vs VL Supply Voltage
TA = 25°C, LTM2882-3 VCC = 3.3V, LTM2882-5
VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted.
VL SUPPLY VOLTAGE (V)
0
THRESHOLD VOLTAGE (V)
3.5
2.5
0.5
1.0
2.0
3.0
1.5
04 52
2882 G10
631
INPUT HIGH
INPUT LOW
100µs/DIV
5V/DIV
T1OUT
T1OUT
ON
T2OUT
T2OUT
2882 G12
DE = VCC2
DE = DOUT,
DIN = VL
2µs/DIV
5V/DIV
2V/DIV
T1OUT
T2OUT
2882 G13
DE
Operating Through 35kV/µs
Common Mode Transients
50ns/DIV
500V/DIV
2V/DIV
T1IN
R1OUT
*
* MULTIPLE SWEEPS OF
COMMON MODE TRANSIENTS
2V/DIV
2882 G14
T1OUT = R1IN
VCC2 Output Voltage
vs Load Current
LOAD CURRENT (mA)
0
VCC2 VOLTAGE (V)
5.2
5.0
4.6
4.7
4.9
5.1
4.8
4.5 15050 250
2882 G11
300
3.0V
100 200
VCC = 3.0V TO 3.6V, LTM2882-3
VCC = 4.5V TO 5.5V, LTM2882-5
5.5V
5.0V
4.5V 3.6V
3.3V
LTM2882
7
2882fc
VCC2 Load Step Response
100µs/DIV
50mA/DIV
200mV/DIV
2882 G18
VCC2 Ripple and Noise
VCC2 Power Efficiency
10µs/DIV
100mV/DIV
2882 G17
T1IN = 250kbps
T1OUT, T2OUT, RL = 3k
LOAD CURRENT (mA)
0
EFFICIENCY (%)
POWER LOSS (W)
70
60
20
30
50
40
10
1.2
1.0
0.2
0.4
0.8
0.6
0
200 250100
2882 G16
30015050
LTM2882-3
LTM2882-5
TA = 25°C
Typical perForMance characTerisTics
TA = 25°C, LTM2882-3 VCC = 3.3V, LTM2882-5
VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted.
VCC2 Surplus Current
vs Temperature
TEMPERATURE (°C)
–50
VCC2 CURRENT (mA)
300
200
50
150
250
100
0500 100
2882 G15
12525–25 75
T1OUT AND T2OUT
BAUD = 100kbps
RL = 3k, CL = 2.5nF
VCC2 = 4.8V
VCC = 3.3V
LTM2882-3
VCC = 5.0V
LTM2882-5
LTM2882
8
2882fc
TesT circuiTs
Figure 3. Receiver Timing Measurement
Figure 4. Auxiliary Channel Timing Measurement
2882 F03
RIN
ROUT
CLtPHLR tPLHR
tFR tRR
10% ½VL
90%
90%
10%
1.5V
3V
VOL
VOH
–3V
RIN
ROUT
tr, tf ≤ 40ns
2882 F04
DIN
DOUT
CLtPLHL tPHLL
tRL tFL
90%
10%
10%
90%
½VL
½VCC2
VL
VOH
VOL
0V
DIN
DOUT
Figure 1. Driver Slew Rate and Timing Measurement
Figure 2. Driver Enable/Disable Times
2882 F01
RL
TIN
TOUT
CLtPLHD tPHLD
tTHL tTLH
3V 0V
–3V
½VL
VL
VOLD
VOHD
0V
TIN
TOUT
tr, tf ≤ 40ns
2882 F02
RL
DE
TOUT
tr, tf ≤ 40ns
0 OR VL
CL
tPZHD
tPZLD
tPHZD
tPLZD
VOLD – 0.5V
VOHD – 0.5V
½VCC2
VCC2
VOHD
VOLD
0V
0V
0V
TOUT
TOUT
DE
–5V
5V
LTM2882
9
2882fc
LOGIC SIDE
R2OUT (Pin A1): Channel 2 RS232 Inverting Receiver
Output. Controlled through isolation barrier from receiver
input R2IN. Under the condition of an isolation communi-
cation failure R2OUT is in a high impedance state.
T2IN (Pin A2): Channel 2 RS232 Inverting Driver Input.
A logic low on this input generates a high on isolated
output T2OUT. A logic high on this input generates a low
on isolated output T2OUT. Do not float.
R1OUT (Pin A3): Channel 1 RS232 Inverting Receiver
Output. Controlled through isolation barrier from receiver
input R1IN. Under the condition of an isolation communi-
cation failure R1OUT is in a high impedance state.
T1IN (Pin A4): Channel 1 RS232 Inverting Driver Input.
A logic low on this input generates a high on isolated
output T1OUT. A logic high on this input generates a low
on isolated output T1OUT. Do not float.
DIN (Pin A5): General Purpose Non-Inverting Logic Input.
A logic high on DIN generates a logic high on isolated
output DOUT. A logic low on DIN generates a logic low
on isolated output DOUT. Do not float.
ON (Pin A6): Enable. Enables power and data communica-
tion through the isolation barrier. If ON is high the part is
enabled and power and communications are functional to
the isolated side. If ON is low the logic side is held in reset
and the isolated side is unpowered. Do not float.
VL (Pin A7): Logic Supply. Interface supply voltage for pins
DIN, R2OUT, T2IN, R1OUT, T1IN, and ON. Operating voltage
is 1.62V to 5.5V. Internally bypassed to GND with 2.2µF.
VCC (Pins A8, B7-B8): Supply Voltage. Operating volt-
age is 3.0V to 3.6V for LTM2882-3, and 4.5V to 5.5V for
LTM2882-5. Internally bypassed to GND with 2.2µF.
GND (Pins B1-B6): Circuit Ground.
ISOLATED SIDE
GND2 (Pins K1-K7): Isolated Side Circuit Ground. These
pads should be connected to the isolated ground and/or
cable shield.
VCC2 (Pins K8, L7-L8): Isolated Supply Voltage Output. In-
ternally generated from VCC by an isolated DC/DC converter
and regulated to 5V. Supply voltage for pins R1IN, R2IN,
DE, and DOUT. Internally bypassed to GND2 with 2.2µF.
R2IN (Pin L1): Channel 2 RS232 Inverting Receiver Input.
A low on isolated input R2IN generates a logic high on
R2OUT. A high on isolated input R2IN generates a logic
low on R2OUT. Impedance is nominally 5kΩ in receive
mode or unpowered.
T2OUT (Pin L2): Channel 2 RS232 Inverting Driver
Output. Controlled through isolation barrier from driver
input T2IN. High impedance when the driver is disabled
(DE pin is low).
R1IN (Pin L3): Channel 1 RS232 Inverting Receiver Input.
A low on isolated input R1IN generates a logic high on
R1OUT. A high on isolated input R1IN generates a logic
low on R1OUT. Impedance is nominally 5kΩ in receive
mode or unpowered.
T1OUT (Pin L4): Channel 1 RS232 Inverting Driver
Output. Controlled through isolation barrier from driver
input T1IN. High impedance when the driver is disabled
(DE pin is low).
DOUT (Pin L5): General Purpose Non-Inverting Logic
Output. Logic output connected through isolation barrier
to DIN.
DE (Pin L6): Driver Output Enable. A low input forces
both RS232 driver outputs, T1OUT and T2OUT, into a high
impedance state. A high input enables both RS232 driver
outputs. Do not float.
pin FuncTions
LTM2882
10
2882fc
block DiagraM
2882 BD
2.2µF
2.2µF
VCC VCC2
GND2
DE
DOUT
T1OUT
R1IN
T2OUT
R2IN
VL2.2µF
GND
ON
DIN
T1IN
T2IN
R2OUT
R1OUT
DC/DC
CONVERTER
ISOLATED
COMMUNI-
CATIONS
INTERFACE
ISOLATED
COMMUNI-
CATIONS
INTERFACE
5V
REG
VDD
VEE
VDD
VDD
VEE
VEE
5k
5k
LTM2882
11
2882fc
Figure 5. VCC and VL Are Independent
2882 F05
ON
DIN
T1IN
R1OUT
T2IN
R2OUT
DE
DOUT
T1OUT
R1IN
T2OUT
R2IN
LTM2882
ANY VOLTAGE FROM
1.62V TO 5.5V
3.0V TO 3.6V LTM2882-3
4.5V TO 5.5V LTM2882-5
EXTERNAL
DEVICE
VLVCC VCC2
GND
ISOLATION BARRIER
GND2
applicaTions inForMaTion
Overview
The LTM2882 µModule transceiver provides a galvanically-
isolated robust RS232 interface, powered by an integrated,
regulated DC/DC converter, complete with decoupling
capacitors. The LTM2882 is ideal for use in networks
where grounds can take on different voltages. Isolation in
the LTM2882 blocks high voltage differences, eliminates
ground loops and is extremely tolerant of common mode
transients between grounds. Error-free operation is main-
tained through common mode events greater than 30kV/
μs providing excellent noise isolation.
µModule Technology
The LTM2882 utilizes isolator µModule technology to
translate signals and power across an isolation barrier.
Signals on either side of the barrier are encoded into
pulses and translated across the isolation boundary using
coreless transformers formed in the µModule substrate.
This system, complete with data refresh, error checking,
safe shutdown on fail, and extremely high common mode
immunity, provides a robust solution for bidirectional signal
isolation. The µModule technology provides the means
to combine the isolated signaling with our advanced dual
RS232 transceiver and powerful isolated DC/DC converter
in one small package.
DC/DC Converter
The LTM2882 contains a fully integrated isolated DC/DC
converter, including the transformer, so that no external
components are necessary. The logic side contains a full-
bridge driver, running at about 2MHz, and is AC-coupled
to a single transformer primary. A series DC blocking
capacitor prevents transformer saturation due to driver
duty cycle imbalance. The transformer scales the primary
voltage, and is rectified by a full-wave voltage doubler.
This topology eliminates transformer saturation caused
by secondary imbalances.
The DC/DC converter is connected to a low dropout regulator
(LDO) to provide a regulated low noise 5V output, VCC2.
An integrated boost converter generates a 7V VDD supply
and a charge pumped –6.3V VEE supply. VDD and VEE power
the output stage of the RS232 drivers and are regulated
to levels that guarantee greater than ±5V output swing.
The internal power solution is sufficient to support the
transceiver interface at its maximum specified load and
data rate, and has the capacity to provide additional 5V
power on the isolated side VCC2 and GND2 pins. VCC and
VCC2 are each bypassed internally with 2.2µF ceramic
capacitors.
VL Logic Supply
A separate logic supply pin VL allows the LTM2882 to in-
terface with any logic signal from 1.62V to 5.5V as shown
in Figure 5. Simply connect the desired logic supply to VL.
There is no interdependency between VCC and VL; they
may simultaneously operate at any voltage within their
specified operating ranges and sequence in any order. VL
is bypassed internally by a 2.2µF capacitor.
Hot Plugging Safely
Caution must be exercised in applications where power
is plugged into the LTM2882’s power supplies, VCC or VL,
due to the integrated ceramic decoupling capacitors. The
parasitic cable inductance along with the high Q char-
acteristics of ceramic capacitors can cause substantial
ringing which could exceed the maximum voltage ratings
and damage the LTM2882. Refer to Linear Technology Ap-
plication Note 88, entitled “Ceramic Input Capacitors Can
Cause Overvoltage Transients” for a detailed discussion
and mitigation of this phenomenon.
LTM2882
12
2882fc
Channel Timing Uncertainty
Multiple channels are supported across the isolation bound-
ary by encoding and decoding of the inputs and outputs.
The technique used assigns T1IN/R1IN the highest priority
such that there is no jitter on the associated output chan-
nels T1OUT/R1OUT, only delay. This preemptive scheme
will produce a certain amount of uncertainty on T2IN/
R2IN to T2OUT/R2OUT and DIN to DOUT. The resulting
pulse width uncertainty on these low priority channels is
typically ±6ns, but may vary up to about 40ns.
Half-Duplex Operation
The DE pin serves as a low-latency driver enable for half-
duplex operation. The DE pin can be easily driven from
the logic side by using the uncommitted auxiliary digital
channel, DIN to DOUT. Each driver is enabled and disabled
in less than 2µs, while each receiver remains continuously
active. This mode of operation is illustrated in Figure 6.
applicaTions inForMaTion
Figure 6. Half-Duplex Configuration Using DOUT to Drive DE
2882 F06
ON
DIN
T1IN
R1OUT
T2IN
R2OUT
DE
DOUT
T1OUT
R1IN
T2OUT
R2IN
LTM2882
3.3V (LTM2882-3)
5V (LTM2882-5)
VLVCC VCC2
GND GND2
ISOLATION BARRIER
TX
RX
Driver Overvoltage and Overcurrent Protection
The driver outputs are protected from short-circuits to
any voltage within the absolute maximum range of ±15V
relative to GND2. The maximum current is limited to no
more than 70mA to maintain a safe power dissipation and
prevent damaging the LTM2882.
Receiver Overvoltage and Open Circuit
The receiver inputs are protected from common mode
voltages of ±25V relative to GND2.
Each receiver input has a nominal input impedance of 5kΩ
relative to GND2. An open circuit condition will generate a
logic high on each receiver’s respective output pin.
RF, Magnetic Field Immunity
The LTM2882 has been independently evaluated and has
successfully passed the RF and magnetic field immunity
testing requirements per European Standard EN 55024,
in accordance with the following test standards:
EN 61000-4-3 Radiated, Radio-Frequency,
Electromagnetic Field Immunity
EN 61000-4-8 Power Frequency
Magnetic Field Immunity
EN 61000-4-9 Pulsed Magnetic Field Immunity
Tests were performed using an unshielded test card de-
signed per the data sheet PCB layout recommendations.
Specific limits per test are detailed in Table 1.
Table 1
TEST FREQUENCY FIELD STRENGTH
EN 61000-4-3, Annex D 80MHz to 1GHz 10V/m
1.4MHz to 2GHz 3V/m
2GHz to 2.7GHz 1V/m
EN 61000-4-8, Level 4 50Hz and 60Hz 30A/m
EN 61000-4-8, Level 5 60Hz 100A/m*
EN 61000-4-9, Level 5 Pulse 1000A/m
*Non IEC Method
LTM2882
13
2882fc
applicaTions inForMaTion
PCB Layout
The high integration of the LTM2882 makes PCB layout
very simple. However, to optimize its electrical isolation
characteristics, EMI, and thermal performance, some
layout considerations are necessary.
• UnderheavilyloadedconditionsVCC and GND current
can exceed 300mA. Sufficient copper must be used
on the PCB to insure resistive losses do not cause the
supply voltage to drop below the minimum allowed
level. Similarly, the VCC2 and GND2 conductors must
be sized to support any external load current. These
heavy copper traces will also help to reduce thermal
stress and improve the thermal conductivity.
• InputandOutputdecouplingisnotrequired,sincethese
components are integrated within the package. An ad-
ditional bulk capacitor with a value of 6.8µF to 22µF is
recommended. The high ESR of this capacitor reduces
board resonances and minimizes voltage spikes caused
by hot plugging of the supply voltage. For EMI sensitive
applications, an additional low ESL ceramic capacitor of
1µF to 4.7µF, placed as close to the power and ground
terminals as possible, is recommended. Alternatively, a
number of smaller value parallel capacitors may be used
to reduce ESL and achieve the same net capacitance.
• DonotplacecopperonthePCBbetweentheinnercol-
umns of pads. This area must remain open to withstand
the rated isolation voltage.
• The use of solid ground planes for GND and GND2
is recommended for non-EMI critical applications to
optimize signal fidelity, thermal performance, and to
minimize RF emissions due to uncoupled PCB trace
conduction. The drawback of using ground planes,
where EMI is of concern, is the creation of a dipole
antenna structure which can radiate differential voltages
formed between GND and GND2. If ground planes are
used it is recommended to minimize their area, and
use contiguous planes as any openings or splits can
exacerbate RF emissions.
• Forlargegroundplanesasmallcapacitance(≤330pF)
from GND to GND2, either discrete or embedded within
the substrate, provides a low impedance current return
path for the module parasitic capacitance, minimizing
any high frequency differential voltages and substantially
reducing radiated emissions. Discrete capacitance will
not be as effective due to parasitic ESL. In addition, volt-
age rating, leakage, and clearance must be considered
for component selection. Embedding the capacitance
within the PCB substrate provides a near ideal capacitor
and eliminates component selection issues; however,
the PCB must be 4 layers. Care must be exercised in
applying either technique to insure the voltage rating
of the barrier is not compromised.
The PCB layout in Figures 7a to 7e show the low EMI
demo board for the LTM2882. The demo board uses a
combination of EMI mitigation techniques, including both
embedded PCB bridge capacitance and discrete GND to
GND2 capacitors. Two safety rated type Y2 capacitors
are used in series, manufactured by Murata, part number
GA342QR7GF471KW01L. The embedded capacitor ef-
fectively suppresses emissions above 400MHz, whereas
the discrete capacitors are more effective below 400MHz.
EMI performance is shown in Figure 8, measured using
a Gigahertz Transverse Electromagnetic (GTEM) cell and
method detailed in IEC 61000-4-20, “Testing and Mea-
surement Techniques – Emission and Immunity Testing
in Transverse Electromagnetic Waveguides.”
LTM2882
14
2882fc
applicaTions inForMaTion
TECHNOLOGY
Figure 7a. Low EMI Demo Board Layout
Figure 7b. Low EMI Demo Board Layout (DC1747A), Top Layer
Figure 7c. Low EMI Demo Board Layout (DC1747A), Inner Layer 1
LTM2882
15
2882fc
applicaTions inForMaTion
Figure 7d. Low EMI Demo Board Layout (DC1747A), Inner Layer 2
Figure 7e. Low EMI Demo Board Layout (DC1747A), Bottom Layer
FREQUENCY (MHz)
0
dBµV/m
60
50
40
30
20
–20
–10
0
–30 400200 600
2882 F08
1000300100 500 700 900800
10
DETECTOR = QuasiPeak
RBW = 120kHz
VBW = 300kHz
SWEEP TIME = 17sec
DC1747A-A
DC1747A-B
CISPR 22 CLASS 8 LIMIT
Figure 8. Low EMI Demo Board Emissions
LTM2882
16
2882fc
Typical applicaTions
Figure 9. Single Line Dual Half-Duplex
Isolated Transceiver
2882 F09
ON
DIN
T1IN
R1OUT
T2IN
R2OUT
DE
DOUT
T1OUT
R1IN
T2OUT
R2IN
LTM2882
3.3V (LTM2882-3)
5V (LTM2882-5)
VLVCC
GND GND2
3.3k
ISOLATION BARRIER
TX
RX
3.3k
Figure 13. Isolated Multirail Power Supply
with Switched Outputs
Figure 10. Driving Larger Capacitive Loads
Figure 11. 1.8V Microprocessor Interface
2882 F10
ON
DIN
T1IN
R1OUT
T2IN
R2OUT
DE
DOUT
T1OUT
R1IN
T2OUT
R2IN
LTM2882
3.3V (LTM2882-3)
5V (LTM2882-5) VLVCC
GND GND2
ISOLATION BARRIER
3k CL
DATA RATE
(kbps)
100 5
250 2
1000 0.5
CL (nF)
2882 F11
ON
DIN
T1IN
R1OUT
T2IN
R2OUT
DE
DOUT
T1OUT
R1IN
T2OUT
R2IN
LTM2882
µP
VLVCC
GND
1.8V
3.3V (LTM2882-3)
5V (LTM2882-5)
ISOLATION BARRIER
GND2
Figure 12. Isolated 5V Power Supply
2882 F12
ON
DIN
T1IN
R1OUT
T2IN
R2OUT
DE
DOUT
T1OUT
R1IN
T2OUT
R2IN
LTM2882
VLVCC VCC2
GND
3.3V (LTM2882-3)
5V (LTM2882-5) 5V
REGULATED
150mA (LTM2882-5)
100mA (LTM2882-3)
ISOLATION BARRIER
GND2
ONOFF
2882 F13
ON
DIN
T1IN
R1OUT
T2IN
R2OUT
DE
DOUT
T1OUT
R1IN
T2OUT
R2IN
LTM2882
3.3V (LTM2882-3)
5V (LTM2882-5)
5V
REGULATED
7V
SWITCHED
RETURN
–6.3V
SWITCHED
VLVCC VCC2
GND GND2
ISOLATION BARRIER
ONOFF
LTM2882
17
2882fc
package DescripTion
BGA Package
32-Lead (15mm × 11.25mm × 3.42mm)
(Reference LTC DWG # 05-08-1851 Rev B)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
BALL DESIGNATION PER JESD MS-028 AND JEP95
5. PRIMARY DATUM -Z- IS SEATING PLANE
4
3
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
PACKAGE TOP VIEW
4
PIN “A1”
CORNER
X
Y
aaa Z
aaa Z
PACKAGE BOTTOM VIEW
3
SEE NOTES
SUGGESTED PCB LAYOUT
TOP VIEW
BGA 32 0110 REV B
LTMXXXXXX
µModule
TRAY PIN 1
BEVEL
PACKAGE IN TRAY LOADING ORIENTATION
COMPONENT
PIN “A1”
DETAIL A
PIN 1
0.000
0.635
0.635
1.905
1.905
3.175
3.175
4.445
4.445
6.350
6.350
5.080
5.080
0.000
DETAIL A
Øb (32 PLACES)
F
G
H
L
J
K
E
A
B
C
D
2 14 35678
DETAIL B
SUBSTRATE
0.27 – 0.37
2.45 – 2.55
// bbb Z
D
A
A1
b1
ccc Z
DETAIL B
PACKAGE SIDE VIEW
MOLD
CAP
Z
MX YZddd
MZeee
0.630 ±0.025 Ø 32x
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
aaa
bbb
ccc
ddd
eee
MIN
3.22
0.50
2.72
0.73
0.60
NOM
3.42
0.60
2.82
0.78
0.63
15.0
11.25
1.27
12.70
8.89
MAX
3.62
0.70
2.92
0.83
0.66
0.15
0.10
0.20
0.30
0.15
NOTES
DIMENSIONS
TOTAL NUMBER OF BALLS: 32
E
b
e
e
b
A2
F
G
LTM2882
18
2882fc
package DescripTion
LGA Package
32-Lead (15mm × 11.25mm × 2.82mm)
(Reference LTC DWG # 05-08-1773 Rev Ø)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
LAND DESIGNATION PER JESD MO-222
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. THE TOTAL NUMBER OF PADS: 32
4
3
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
DETAIL B
DETAIL B
SUBSTRATE
MOLD
CAP
0.290 – 0.350
2.400 – 2.600
bbb Z
Z
PACKAGE TOP VIEW
11.25
BSC
15.00
BSC
4
PAD “A1”
CORNER
X
Y
aaa Z
aaa Z
PACKAGE BOTTOM VIEW
3
PADS
SEE NOTES
SUGGESTED PCB LAYOUT
TOP VIEW
LGA 32 0308 REV Ø
LTMXXXXXX
µModule
TRAY PIN 1
BEVEL
PACKAGE IN TRAY LOADING ORIENTATION
COMPONENT
PIN “A1”
8.89
BSC
1.27
BSC
PAD 1
0.635
0.635
1.905
1.905
3.175
3.175
4.445
4.445
6.350
6.350
5.080
5.080
0.000
SYMBOL
aaa
bbb
eee
TOLERANCE
0.10
0.10
0.05
DETAIL A
0.630 ±0.025 Ø 32x
SYXeee
DETAIL C
0.630 ±0.025 Ø 32x
SYXeee
F
G
H
L
J
K
E
A
B
C
D
2 14 3567
2.69 – 2.95
DETAIL A
12.70
BSC
8
DETAIL c
LTM2882
19
2882fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 3/10 Changes to Features
Add BGA Package to Pin Configuration, Order Information and Package Description Sections
Changes to LGA Package in Pin Configuration Section
Update to Pin Functions
Update to RF, Magnetic Field Immunity Section
“PCB Layout Isolation Considerations” Section Replaced
1
2, 15
2
9
12
13
B 3/11 H-Grade parts added. Reflected throughout the data sheet. 1-20
C 1/12 MP-Grade parts added. Reflected throughout the data sheet. 1-24
LTM2882
20
2882fc
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2010
LT 0112 REV C • PRINTED IN USA
relaTeD parTs
Typical applicaTions
PART NUMBER DESCRIPTION COMMENTS
LTM2881 Isolated RS485/RS422 µModule Transceiver with
Low EMI Integrated DC/DC Converter
20Mbps, ±15kV HBM ESD, 2500VRMS Isolation with 1W Power
LTC2870/LTC2871 RS232/RS485 Multiprotocol Transceivers with
Integrated Termination
20Mbps RS485 and 500kbps RS232, ±26kV ESD, 3V to 5V Operation
LTC2804 1Mbps RS232 Transceiver Dual Channel, Full-Duplex, ±10kV HBM ESD
LTC1535 Isolated RS485 Transceiver 2500 VRMS Isolation with External Transformer Driver
Figure 16. Isolated Gate Drive with Overcurrent Detection
Figure 14. Isolated RS232 Interface with Handshaking Figure 15. Isolated Dual Inverting Level Translator
2882 F14
ON
DIN
T1IN
R2OUT
T2IN
R2OUT
DE
DOUT
T1OUT
R1IN
T2OUT
R2IN
LTM2882
µC PERIPHERAL
VLVCC
RX
TX
RTS
CTS
TXD
RXD
PY
PZ
VCC2
GND GND2
3.3V (LTM2882-3)
5V (LTM2882-5)
ISOLATION BARRIER
2882 F15
ON
DIN
T1IN
R1OUT
T2IN
R2OUT
DE
DOUT
T1OUT
R1IN
T2OUT
R2IN
LTM2882
VLVCC
GND
3.3V (LTM2882-3)
5V (LTM2882-5)
GND2
1.62V TO 5.5V
ISOLATION BARRIER
ONOFF
VL
0V
VL
0V
–25V TO 0V
3V TO 25V
–25V TO 0V
3V TO 25V
2882 F16
ON
DIN
T1IN
R1OUT
T2IN
R2OUT
DE
DOUT
T1OUT
R1IN
T2OUT
R2IN
LTM2882
VLVCC VCC2
GND GND2
+VS
3k
IRLML2402
IRLML6402
470pF
1k
1k
3.3V (LTM2882-3)
5V (LTM2882-5)
ISOLATION BARRIER
RESET
FAULT
PWMA
PWMB
RILIM = 0.6/MAX CURRENT47pF
CMPT2369-LTV
3k
LOGIC
LEVEL
FETS