Filterless High Efficiency
Mono 3 W Class-D Audio Amplifier
SSM2311
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
FEATURES
Filterless Class-D amplifier with Σ-Δ modulation
No sync necessary when using multiple Analog Devices, Inc.,
Class-D amplifiers
3 W into 3 Ω load and 1.4 W into 8 Ω load at 5.0 V supply with
less than 10% total harmonic distortion (THD)
90% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
Better than 98 dB signal-to-noise ratio (SNR)
Single-supply operation from 2.5 V to 5.5 V
20 nA ultralow shutdown current
Short-circuit and thermal protection
Available in 9-ball, 1.5 mm × 1.5 mm WLCSP
Pop-and-click suppression
Built-in resistors reduce board component count
Default fixed 18 dB or user-adjustable gain setting
APPLICATIONS
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
GENERAL DESCRIPTION
The SSM2311 is a fully integrated, high efficiency, Class-D audio
amplifier. It is designed to maximize performance for mobile
phone applications. The application circuit requires a minimum
of external components and operates from a single 2.5 V to 5.5 V
supply. It is capable of delivering 3 W of continuous output power
with less than 1% THD + N driving a 3 Ω load from a 5.0 V supply.
The SSM2311 features a high efficiency, low noise modulation
scheme that does not require any external LC output filters. The
modulation continues to provide high efficiency even at low output
power. It operates with 90% efficiency at 1.4 W into 8 Ω or 85%
efficiency at 3 W into 3 Ω from a 5.0 V supply and has an SNR that
is better than 98 dB. Spread-spectrum pulse density modulation
is used to provide lower EMI-radiated emissions compared with
other Class-D architectures.
The SSM2311 has a micropower shutdown mode with a typical
shutdown current of 20 nA. Shutdown is enabled by applying a
logic low to the SD pin.
The device also includes pop-and-click suppression circuitry. This
minimizes voltage glitches at the output during turn-on and turn-
off, thus reducing audible noise on activation and deactivation.
The fully differential input of the SSM2311 provides excellent
rejection of common-mode noise on the input. Input coupling
capacitors can be omitted if the dc input common-mode voltage
is approximately VDD/2.
The default gain of SSM2311 is 18 dB, but users can reduce the gain
by using a pair of external resistors (see the Gain section).
The SSM2311 is specified over the industrial temperature range
(−40°C to +85°C). It has built-in thermal shutdown and output
short-circuit protection. It is available in a 9-ball, 1.5 mm × 1.5 mm
wafer level chip scale package (WLCSP).
FUNCTIONAL BLOCK DIAGRAM
SHUTDOWN
FET
DRIVER
MODULATOR
0.1µF
VDD
GND
OSCILLATOR POP-AND-CLICK
SUPPRESSION
OUT+
OUT–
BIAS
IN+
VBATT
2.5V TO 5.0V
IN–
10µF
22nF
1
300k
300k
37.5k
37.5k
1
INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V
DD
/2.
22nF
1
SD
A
UDIO IN–
A
UDIO IN+
SSM2311
06161-001
R
EXT
R
EXT
GAIN = 300k
(37.5k + R
EXT
)
Figure 1.
SSM2311
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Typical Application Circuits ......................................................... 13
Application Notes ........................................................................... 15
Overview ..................................................................................... 15
Gain.............................................................................................. 15
Pop-and-Click Suppression ...................................................... 15
Layout .......................................................................................... 15
Input Capacitor Selection.......................................................... 16
Proper Power Supply Decoupling ............................................ 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
1/08—Revision 0: Initial Version
SSM2311
Rev. 0 | Page 3 of 20
SPECIFICATIONS
VDD = 5.0 V, TA = 25oC, RL = 8 Ω, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
DEVICE CHARACTERISTICS
Output Power PORL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 1.2 W
R
L = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 0.615 W
R
L = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 1.53 W
R
L = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 0.77 W
R
L = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 2 W
R
L = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 1.4 W
R
L = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 2.3 W
R
L = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 1.6 W
R
L = 3 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 3 W
R
L = 3 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 1.8 W
R
L = 3 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 3.3 W
R
L = 3 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 2.5 W
Efficiency η POUT = 1.4 W, 8 Ω, VDD = 5.0 V 89 %
Total Harmonic Distortion + Noise THD + N PO = 3 W into 3 Ω, f = 1 kHz, VDD = 5.0 V 0.5 %
P
O = 1 W into 8 Ω, f = 1 kHz, VDD = 5.0 V 0.2 %
Input Common-Mode Voltage Range VCM 1.0 VDD1.0 V
Common-Mode Rejection Ratio CMRRGSM VCM = 2.5 V ± 100 mV at 217 Hz input referred 60 dB
Average Switching Frequency fSW 800 kHz
Differential Output Offset Voltage VOOS G = 18 dB 2.0 12.0 mV
POWER SUPPLY
Supply Voltage Range VDD Guaranteed from PSRR test 2.5 5.0 V
Power Supply Rejection Ratio PSRR VDD = 2.5 V to 5.0 V, dc input floating/ground 70 85 dB
PSRRGSM VRIPPLE = 100 mV at 217 Hz, inputs ac GND,
CIN = 0.1 μF
60 dB
Supply Current ISY VIN = 0 V, no load, VDD = 5.0 V 5.5 mA
V
IN = 0 V, no load, VDD = 3.6 V 4.5 mA
V
IN = 0 V, no load, VDD = 2.5 V 4.0 mA
Shutdown Current ISD SD = GND 20 nA
GAIN CONTROL
Closed-Loop Gain Av 18 dB
Differential Input Impedance ZIN SD = VDD 37.5
SHUTDOWN CONTROL
Input Voltage High VIH ISY ≥ 1 mA 1.2 V
Input Voltage Low VIL ISY ≤ 300 nA 0.5 V
Turn-On Time tWU SD rising edge from GND to VDD 30 ms
Turn-Off Time tSD SD falling edge from VDD to GND 5 μs
Output Impedance ZOUT SD = GND >100
NOISE PERFORMANCE
Output Voltage Noise en VDD = 3.6 V, f = 20 Hz to 20 kHz, inputs are
ac grounded, AV = 18 dB, A weighting
35 μV
Signal-to-Noise Ratio SNR POUT = 1.4 W, RL = 8 Ω 98 dB
SSM2311
Rev. 0 | Page 4 of 20
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 2.
Parameter Rating
Supply Voltage 6 V
Input Voltage VDD
Common-Mode Input Voltage VDD
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type PCB θJA θJB Unit
9-Ball, 1.5 mm × 1.5 mm WLCSP 1S0P1162 38.5 °C/W
2S0P176 21 °C/W
1 Referencing the JEDEC thermal standard.
ESD CAUTION
SSM2311
Rev. 0 | Page 5 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SSM2311
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
06161-002
BALL A1
CORNER
A
321
B
C
Figure 2. SSM2311 WLCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
2C SD Shutdown Input. Active low digital input.
1A IN+ Noninverting Input.
1C IN− Inverting Input.
3C OUT− Inverting Output.
1B VDD Power Supply.
2A, 3B GND Ground.
3A OUT+ Noninverting Output.
2B PVDD Power Supply.
SSM2311
Rev. 0 | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
100
0.001
0.0001 10
OUTPUT POWER (W)
THD + N (%)
0.001 0.01 0.1 1
0.01
0.1
1
10
R
L
= 8, 33µH
GAIN = 18dB
V
DD
= 2.5V
V
DD
= 3.6V
V
DD
= 5V
06161-027
Figure 3. THD + N vs. Output Power into 8 Ω, AV = 18 dB
100
10
1
0.1
0.01
0.001
0.0001 10
OUTPUT POWER (W)
THD + N (%)
V
DD
= 2.5V
V
DD
= 5V
0.001 0.01 0.1 1
V
DD
= 3.6V
R
L
= 8, 33µH
GAIN = 6dB
06161-028
Figure 4. THD + N vs. Output Power into 8 Ω, AV = 6 dB
100
0.001
0.0001 10
OUTPUT POWER (W)
THD + N (%)
0.001 0.01 0.1 1
0.01
0.1
1
10
GAIN = 18dB
R
L
= 4, 33µH
V
DD
= 5V
V
DD
= 3.6V
V
DD
= 2.5V
06161-029
Figure 5. THD + N vs. Output Power into 4 Ω, AV = 18 dB
100
0.001
0.0001 10
OUTPUT POWER (W)
THD + N (%)
0.001 0.01 0.1 1
0.01
0.1
1
10
GAIN = 6dB
R
L
= 4, 33µH
VDD = 2.5V
VDD = 3.6V
VDD = 5V
06161-030
Figure 6. THD + N vs. Output Power into 4 Ω, AV = 6 dB
1
100
0.001
0.0001 10
OUTPUT POWER (W)
THD + N (%)
10
0.1
0.01
0.001 0.10.01 1
GAIN = 18dB
R
L
= 3, 33µH
V
DD
= 2.5V
V
DD
= 3.6V
V
DD
= 5V
06161-031
Figure 7. THD + N vs. Output Power into 3 Ω, AV = 18 dB
100
0.001
0.0001 10
OUTPUT POWER (W)
THD + N (%)
0.001 0.01 0.1 1
0.001
0.1
1
10
RL = 3, 33µH
GAIN = 6dB
V
DD
= 3.6V
V
DD
= 5V
V
DD
= 2.5V
06161-032
Figure 8. THD + N vs. Output Power into 3 Ω, AV = 6 dB
SSM2311
Rev. 0 | Page 7 of 20
FREQUENCY (Hz)
100
0.001
10 100k
THD + N (%)
100 1k 10k
0.01
0.1
1
10
V
DD
= 5V
GAIN = 18dB
R
L
= 8, 33µH
1W
0.5W
0.25W
06161-033
Figure 9. THD + N vs. Frequency, VDD = 5.0 V, RL = 8 Ω, AV = 18 dB
100
0.001
10 100k
FREQUENCY (Hz)
THD + N (%)
100 1k 10k
0.01
0.1
1
10
V
DD
= 5V
GAIN = 18dB
R
L
= 4, 33µH
1W
0.5W
2W
06161-034
Figure 10. THD + N vs. Frequency, VDD = 5.0 V, RL = 4 Ω, AV = 18 dB
100
0.001
10 100k
FREQUENCY (Hz)
THD + N (%)
100 1k 10k
0.01
0.1
1
10
V
DD
= 5V
GAIN = 18dB
R
L
= 3, 33µH
1.5W
0.75W
3W
06161-035
Figure 11. THD + N vs. Frequency, VDD = 5.0 V, RL = 3 Ω, AV = 18 dB
100
0.001
10 100k
FREQUENCY (Hz)
THD + N (%)
100 1k 10k
0.01
0.1
1
10
V
DD
= 3.6V
GAIN = 18dB
R
L
= 8, 33µH
0.5W
0.25W
0.125W
06161-036
Figure 12. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω, AV = 18 dB
100
0.001
10 100k
FREQUENCY (Hz)
THD + N (%)
100 1k 10k
0.01
0.1
1
10
V
DD
= 3.6V
GAIN = 18dB
R
L
= 4, 33µH
0.5W
0.25W
1W
06161-037
Figure 13. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω, AV = 18 dB
100
0.001
10 100k
FREQUENCY (Hz)
THD + N (%)
100 1k 10k
0.01
0.1
1
10
V
DD
= 3.6V
GAIN = 18dB
R
L
= 3, 33µH
0.38W
0.75W
1.5W
06161-038
Figure 14. THD + N vs. Frequency, VDD = 3.6 V, RL = 3 Ω, AV = 18 dB
SSM2311
Rev. 0 | Page 8 of 20
100
0.001
10 100k
FREQUENCY (Hz)
THD + N (%)
100 1k 10k
0.01
0.1
1
10
V
DD
= 2.5V
GAIN = 18dB
R
L
= 8, 33µH
0.125W
0.075W
0.25W
06161-039
Figure 15. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 Ω, AV = 18 dB
100
0.001
10 100k
FREQUENCY (Hz)
THD + N (%)
100 1k 10k
0.01
0.1
1
10
V
DD
= 2.5V
GAIN = 18dB
R
L
= 4, 33µH
0.125W 0.25W
0.5W
06161-040
Figure 16. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω, AV = 18 dB
100
0.001
10 100k
FREQUENCY (Hz)
THD + N (%)
100 1k 10k
0.01
0.1
1
10
V
DD
= 2.5V
GAIN = 18dB
R
L
= 3, 33µH
0.75W
0.38W
0.2W
06161-041
Figure 17. THD + N vs. Frequency, VDD = 2.5 V, RL = 3 Ω, AV = 18 dB
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.9
3.4
3.2
2.5 5.5
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
3.0 3.5 4.0 4.5 5.0
06161-042
NO LOAD
Figure 18. Supply Current vs. Supply Voltage, No Load
12
0
00
SHUTDOWN VOLTAGE (V)
SHUTDOWN CURRENT (mA)
.8
10
8
6
4
2
0.10.20.30.40.50.60.7
V
DD
= 2.5V
V
DD
= 5V
V
DD
= 3.6V
06161-043
Figure 19. Shutdown Current vs. Shutdown Voltage
2.0
0
2.5 5.0
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
3.0 3.5 4.0 4.5
f = 1kHz
GAIN = 18dB
R
L
= 8, 33µH
10%
1%
06161-044
Figure 20. Maximum Output Power vs. Supply Voltage, RL = 8 Ω, AV = 18 dB
SSM2311
Rev. 0 | Page 9 of 20
3.5
0
2.5 5.0
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
3.0
2.5
2.0
1.5
1.0
0.5
3.0 3.5 4.0 4.5
f = 1kHz
GAIN = 18dB
R
L
= 4, 33µH
10%
1%
06161-045
Figure 21. Maximum Output Power vs. Supply Voltage, RL = 4 Ω, AV = 18 dB
4.5
0
2.5 5.0
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
3.0 3.5 4.0 4.5
10% 1%
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
f = 1kHz
GAIN = 18dB
R
L
= 3, 33µH
06161-046
Figure 22. Maximum Output Power vs. Supply Voltage, RL = 3 Ω, AV = 18 dB
2.0
2.5 5.0
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
3.0 3.5 4.0 4.5
10%
1%
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
f = 1kHz
GAIN = 6dB
R
L
= 8, 33µH
06161-047
Figure 23. Maximum Output Power vs. Supply Voltage, RL = 8 Ω, AV = 6 dB
3.5
0
2.5 5.0
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
3
2.5
2.0
1.5
1.0
0.5
3.0 3.5 4.0 4.5
f = 1kHz
GAIN = 6dB
R
L
= 4, 33µH
10% 1%
06161-048
Figure 24. Maximum Output Power vs. Supply Voltage, RL = 4 Ω, AV = 6 dB
4.5
0
2.5 5.0
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
3.0 3.5 4.0 4.5
10% 1%
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
f = 1kHz
GAIN = 6dB
R
L
= 3, 33µH
06161-049
Figure 25. Maximum Output Power vs. Supply Voltage, RL = 3 Ω, AV = 6 dB
100
0
02
OUTPUT POWER (W)
EFFICIENCY (%)
.0
90
80
70
60
50
40
30
20
10
0.20.40.60.81.01.21.41.61.8
R
L
= 8, 33µH
V
DD
= 2.5V
V
DD
= 3.6V V
DD
= 5V
06161-050
Figure 26. Efficiency vs. Output Power into 8 Ω
SSM2311
Rev. 0 | Page 10 of 20
OUTPUT POWER (W)
EFFICIENCY (%)
100
0
02
.4
0.30
0.25
0.20
0.15
0.10
0.05
0
0
OUTPUT POWER (W)
POWER DISSIPATION (W)
06161-073
90
80
70
60
50
40
30
20
10
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
V
DD
= 2.5V
V
DD
= 3.6V
V
DD
= 5V
R
L
= 4, 33µH
R
L
= 4, 33µH
Figure 27. Efficiency vs. Output Power into 4 Ω
100
0
OUTPUT POWER (W)
EFFICIENCY (%)
90
80
70
60
50
40
30
20
10
R
L
= 3, 33µH
V
DD
= 2.5V
V
DD
= 3.6V
V
DD
= 5V
06161-051
0
3.6
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
Figure 28. Efficiency vs. Output Power into 3 Ω
0.14
0.12
0.10
0.08
0.06
0.04
OUTPUT POWER (W)
POWER DISSIPATION (W)
06161-074
0
1.5
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
R
L
= 8, 33µH
V
DD
= 5V
Figure 29. Power Dissipation vs. Output Power into 8 Ω at VDD = 5.0 V
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
V
DD
= 5V
06161-052
Figure 30. Power Dissipation vs. Output Power into 4 Ω at VDD = 5.0 V
0.6
0.5
0.4
0.3
0.2
0.1
0
0
OUTPUT POWER (W)
POWER DISSIPATION (W)
3.20.20.40.60.81.01.21.41.61.82.02.22.42.62.83.0
RL = 3, 33µH
VDD = 5V
0
6161-053
Figure 31. Power Dissipation vs. Output Power into 3 Ω at VDD = 5.0 V
0.10
0
0
OUTPUT POWER (W)
POWER DISSIPATION (W)
0.9
0.08
0.06
0.04
0.02
0.10.20.30.40.50.60.70.8
R
L
= 8, 33µH
V
DD
= 3.6V
0
6161-054
Figure 32. Power Dissipation vs. Output Power into 8 Ω at VDD = 3.6 V
SSM2311
Rev. 0 | Page 11 of 20
0.24
0.22
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
0
OUTPUT POWER (W)
POWER DISSIPATION (W)
1.70.10.20.30.40.50.60.70.80.91.01.11.21.31.41.51.6
06161-055
V
DD
= 3.6V
R
L
= 4, 33µH
Figure 33. Power Dissipation vs. Output Power into 4 Ω at VDD = 3.6 V
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
02
.0
OUTPUT POWER (W)
POWER DISSIPATION (W)
06161-072
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
V
DD
= 3.6V
R
L
= 3, 33µH
Figure 34. Power Dissipation vs. Output Power into 3 Ω at VDD = 3.6 V
350
0
0
OUTPUT POWER (W)
I
SY
(mA)
1.6
300
250
200
150
100
50
0.20.40.60.81.01.21.4
R
L
= 8, 33µH
V
DD
= 5V
V
DD
= 3.6V
V
DD
= 2.5V
06161-056
Figure 35. Supply Current vs. Output Power into 8 Ω
600
0
0
OUTPUT POWER (W)
I
SY
(mA)
2.4
500
400
300
200
100
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2
R
L
= 4, 33µH
V
DD
= 5V
V
DD
= 3.6V
V
DD
= 2.5V
06161-057
Figure 36. Supply Current vs. Output Power into 4 Ω
800
0
0
OUTPUT POWER (W)
I
SY
(mA)
700
600
500
400
300
200
100
V
DD
= 3.6V
V
DD
= 5V
R
L
= 3, 33µH
0.20.40.60.81.01.21.41.61.82.02.22.42.62.83.03.23.4
V
DD
= 2.5V
06161-058
Figure 37. Supply Current vs. Output Power into 3 Ω
0
–100
10
FREQUENCY (Hz)
PSRR (dB)
100k100 1k 10k
–10
–20
–30
–40
–50
–60
–70
–80
–90
06161-059
Figure 38. Power Supply Rejection Ratio vs. Frequency
SSM2311
Rev. 0 | Page 12 of 20
0
–80
10
FREQUENCY (Hz)
CMRR (dB)
100k100 1k 10k
R
L
= 8, 33µH
–10
–20
–30
–40
–50
–60
–70
06161-060
7
–2
–10
TIME (ms)
VOLTAGE (V)
90
6
5
4
3
2
1
0
–1
0 1020304050607080
SD INPUT
OUTPUT
06161-062
Figure 39. Common-Mode Rejection Ratio vs. Frequency Figure 41. Turn-On Response
0
–140
10
FREQUENCY (Hz)
CROSSTALK (dB)
100k100 1k 10k
–20
–40
–60
–80
–100
–120
V
DD
= 3.6V
V
RIPPLE
= 1V rms
R
L
= 8, 33µH
06161-061
7
–2
–20
TIME (ms)
VOLTAGE (V)
180
6
5
4
3
2
1
0
–1
0 20 40 60 80 100 120 140 160
OUTPUT
SD INPUT
06161-063
Figure 40. Crosstalk vs. Frequency Figure 42. Turn-Off Response
SSM2311
Rev. 0 | Page 13 of 20
TYPICAL APPLICATION CIRCUITS
SHUTDOWN
FET
DRIVER
MODULATOR
0.1µF
VDD
GND
OSCILLATOR POP/CLICK
SUPPRESSION
OUT+
OUT–
BIAS
IN+
VBATT
2.5V TO 5.0V
IN–
10µF
22nF
1
300k
300k
37.5k
37.5k
1
INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V
DD
/2.
22nF
1
SD
AUDIO IN–
A
UDIO IN+
SSM2311
06161-019
Figure 43. Differential Input Configuration
SHUTDOWN
FET
DRIVER
MODULATOR
0.1µF
VDD
GND
OSCILLATOR POP/CLICK
SUPPRESSION
OUT+
OUT–
BIAS
IN+
VBATT
2.5V TO 5.0V
IN
10µF
22nF
1
300k
300k
37.5k
37.5k
1
INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V
DD
/2.
22nF
1
SD
AUDIO IN+
SSM2311
06161-020
Figure 44. Single-Ended Input Configuration
SSM2311
Rev. 0 | Page 14 of 20
SHUTDOWN
FET
DRIVER
MODULATOR
0.1µF
VDD
GND
OSCILLATOR POP/CLICK
SUPPRESSION
OUT+
OUT–
BIAS
IN+
VBATT
2.5V TO 5.0V
IN
10µF
22nF
1
300k
300k
37.5k
37.5k
1
INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V
DD
/2.
22nF
1
SD
A
UDIO IN–
A
UDIO IN+
SSM2311
06161-021
R
EXT
R
EXT
GAIN = 300k
(37.5k + R
EXT
)
Figure 45. Differential Input Configuration, User-Adjustable Gain
SHUTDOWN
FET
DRIVER
MODULATOR
0.1µF
VDD
GND
OSCILLATOR POP/CLICK
SUPPRESSION
OUT+
OUT–
BIAS
IN+
VBATT
2.5V TO 5.0V
IN–
10µF
22nF
1
300k
300k
37.5k
37.5k
1
INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V
DD
/2.
22nF
1
SD
A
UDIO IN+
SSM2311
06161-022
R
EXT
R
EXT
GAIN = 300k
(37.5k + R
EXT
)
Figure 46. Single-Ended Input Configuration, User-Adjustable Gain
SSM2311
Rev. 0 | Page 15 of 20
APPLICATION NOTES
OVERVIEW
The SSM2311 mono Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external components
count, conserving board space and thus reducing the systems cost.
The SSM2311 does not require an output filter, but instead relies
on the inherent inductance of the speaker coil and the natural
filtering of the speaker and the human ear to fully recover the audio
component of the square-wave output. While many Class-D ampli-
fiers use some variation of pulse-width modulation (PWM), the
SSM2311 uses Σ-Δ modulation to determine the switching
pattern of the output devices. This provides a number of important
benefits. Σ-Δ modulators do not produce a sharp peak with
many harmonics in the AM frequency band, as pulse-width
modulators often do. Σ-Δ modulation provides the benefits of
reducing the amplitude of spectral components at high frequencies;
that is, reducing EMI emission that might otherwise be radiated
by speakers and long cable traces. Due to the inherent spread-
spectrum nature of Σ-Δ modulation, the need for oscillator
synchronization is eliminated for designs incorporating
multiple SSM2311 amplifiers.
The SSM2311 also offers protection circuits for overcurrent and
temperature protection.
GAIN
The SSM2311 has a default gain of 18 dB, but can be reduced by
using a pair of external resistors with a value calculated as follows:
External Gain Settings = 300k/(37.5k + Rext)
POP-AND-CLICK SUPPRESSION
Voltage transients at the output of audio amplifiers can occur when
shutdown is activated or deactivated. Voltage transients as low
as 10 mV can be heard as an audio pop in the speaker. Clicks
and pops can also be classified as undesirable audible transients
generated by the amplifier system and therefore as not coming
from the system input signal. Such transients can be generated
when the amplifier system changes its operating mode. For example,
the following can be sources of audible transients: system power-up/
power-down, mute/unmute, input source change, and sample rate
change. The SSM2311 has a pop-and-click suppression architecture
that reduces these output transients, resulting in noiseless activation
and deactivation.
LAYOUT
As output power continues to increase, care needs to be taken to
lay out PCB traces and wires properly between the amplifier,
load, and power supply. A good practice is to use short, wide
PCB tracks to decrease voltage drops and minimize inductance.
Ensure that track widths are at least 200 mil for every inch of
track length for lowest DCR, and use 1 oz or 2 oz of copper PCB
traces to further reduce IR drops and inductance. A poor layout
increases voltage drops, consequently affecting efficiency. Use
large traces for the power supply inputs and amplifier outputs to
minimize losses due to parasitic trace resistance.
Proper grounding guidelines help to improve audio
performance, minimize crosstalk between channels, and
prevent switching noise from coupling into the audio signal. To
maintain high output swing and high peak output power, the
PCB traces that connect the output pins to the load and supply
pins should be as wide as possible to maintain the minimum
trace resistances. It is also recommended to use a large-area
ground plane for minimum impedances.
In addition, good PCB layouts isolate critical analog paths from
sources of high interference. High frequency circuits (analog
and digital) should be separated from low frequency ones.
Properly designed multilayer printed circuit boards can reduce
EMI emission and increase immunity to the RF field by a factor of
10 or more compared with double-sided boards. A multilayer
board allows a complete layer to be used for the ground plane,
whereas the ground plane side of a double-sided board is often
disrupted with signal crossover. If the system has separate analog
and digital ground and power planes, the analog ground plane
should be underneath the analog power plane, and, similarly, the
digital ground plane should be underneath the digital power
plane. There should be no overlap between analog and digital
ground planes or analog and digital power planes.
06161-076
70
60
50
40
30
20
10
0
–10
30 100 1000
LEVEL (dB/µV)
FREQUENCY (MHz)
Figure 47. EMI Emissions from SSM2311
SSM2311
Rev. 0 | Page 16 of 20
INPUT CAPACITOR SELECTION
The SSM2311 does not require input coupling capacitors if the
input signal is biased from 1.0 V to VDD − 1.0 V. Input capacitors
are required if the input signal is not biased within this recom-
mended input dc common-mode voltage range, if high-pass
filtering is needed (Figure 43), or if using a single-ended source
(Figure 44). If high-pass filtering is needed at the input, the input
capacitor along with the input resistor of the SSM2311 forms a
high-pass filter whose corner frequency is determined by the
following equation:
fC = 1/(2π × RIN × CIN)
The input capacitor can significantly affect the performance of
the circuit. Not using input capacitors degrades both the output
offset of the amplifier and the PSRR performance.
PROPER POWER SUPPLY DECOUPLING
To ensure high efficiency, low THD, and high PSRR, proper power
supply decoupling is necessary. Noise transients on the power
supply lines are short-duration voltage spikes. Although the actual
switching frequency can range from 10 kHz to 100 kHz, these
spikes can contain frequency components that extend into the
hundreds of megahertz. The power supply input needs to be
decoupled with a good quality low ESL, low ESR capacitor—usually
of around 4.7 μF. This capacitor bypasses low frequency noises
to the ground plane. For high frequency transients noises, use a
0.1 μF capacitor as close as possible to the VDD pin of the device.
Placing the decoupling capacitor as close as possible to the SSM2311
helps maintain efficiency performance.
SSM2311
Rev. 0 | Page 17 of 20
OUTLINE DIMENSIONS
SEATING
PLANE
0.50 BSC
BALL PITCH
1.575
1.515
1.455
1.750
1.690
1.630
0.28
0.24
0.20
0.35
0.32
0.29
0.65
0.59
0.53
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
A
123
B
C
BALL 1
IDENTIFIER
091306-B
Figure 48. 9-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-9-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
SSM2311CBZ-R21−40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-1 A1G
SSM2311CBZ-REEL1−40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-1 A1G
SSM2311CBZ-REEL71−40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-1 A1G
SSM2311-EVALZ1 Evaluation Board
SSM2311-MINI-EVALZ1 Evaluation Board, 7 mm × 7 mm
1 Z = RoHS Compliant Part.
SSM2311
Rev. 0 | Page 18 of 20
NOTES
SSM2311
Rev. 0 | Page 19 of 20
NOTES