1. General description
The SJA1105 is an IEEE 802.3-compliant 5-por t automotive Ethernet switch. Each of the
five ports can be individually configured to operate in MII, RMII and RGMII modes. This
arrangement provides the flexibility to connect a mix of switches, microprocessors and
PHY devices such as the TJA1100 BroadR-Reach PHY from NXP Semiconductors
(Ref. 1 and Ref. 2) and other commercially available Fast Ethernet and Gigabit Ethernet
PHYs. The high-speed interface makes it easy to cascade multiple SJA1105s for
scalability. It can be used in various automotive scenarios such as gateway applications,
body domain controllers or for interconne cting multiple ECUs in a daisy chain. Audio
Video Bridging (AVB) support (Ref. 3) fully leverages info tainment an d ad vanced driver
assistance systems.
The SJA1105 comes in two pin-compatible variants. The SJA1105EL supports Etherne t
and AVB. The SJA1105TEL includes additional functionality to support Time-Triggered
Ethernet (TTEthernet) and Time-Sensitive Networking (TSN).
2. Features and benefits
2.1 General features
5-port store and forward architecture
Each port individually configurable for MII and RMII operation at 10 Mbit/s or
100 Mbit/s and RGMII operation at 10 Mbit/s, 100 Mbit/s or 1000 Mbit/s
Interface-dependent selectable I/O supply voltages; 1.2 V core voltage
Small footprint: LFBGA159 (12 mm 12 mm) package
Automotive Grade 2 ambient operating temperature: 40 C to +105 C
Automotive product qualification in accordance with AEC-Q100
2.2 Ethernet switching and AVB features
IEEE 802.3 compliant
128 kB frame buffer
1024 entry MAC address learning table
Address learning space can be configured for static and learned addresses
2 kB frame length handling
IEEE 802.1Q defined tag support
4096 VLANs
Egress tagging/untagging on a per-VLAN ba sis pe r po rt
QoS handling based on IEEE 802.1Q
Per-port priority remapping and 8 configurable egress queues per port
SJA1105
5-port automotive Ethernet switch
Rev. 1 — 7 November 2016 Product data sheet
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Product data sheet Rev. 1 — 7 November 2016 2 of 34
NXP Semiconductors SJA1105
5-port automotive Ethernet switch
Ingress rate-limiting on a per- port and per-priority basis for Unicast/Multicast and
Broadcast traffic
Frame replication and retagging of traffic
Frame mirroring for enhanced diagnostics
Hardware support for IEEE 802.1AS and IEEE 802.1Qav for AVB traffic support
Ingress and egress timestamping per port
Ten IEEE 802.1Qav credit-based shapers available; shapers can be freely allocated to
any priority que ue on a pe r po rt basis
Support for AVB SR Class A, Class B and Class C traffic
IEEE 1588v 2 on e- step sy nc forwa r din g in ha rd wa re
IEEE 802.1X support for setting port reachability and disabling address learning
Broadcast storm protection
Statistics for dropped frames and buffer load
2.3 TT and TSN features (SJA1105TEL only)
IEEE 802.1Qbv time-aware traffic
IEEE 802.1Qci per-stream policing (pre-standard)
Support for ring-based redundan cy (for time-triggered traffic only)
1024 deterministic Ethernet flows with per-flow based:
Time-triggered traffic transmission
Ingress policing and reception window check
Active and redundant routes
Statistics
2.4 Interface features
MII/RMII interfaces supporting all standard Ethernet PHY technologies such as (but
not limited to) Fast Ethernet (IEEE 100BASE-TX), IEEE 100BASE-T1 and optical
PHYs
RGMII for interfacing with Gigabit Ethernet (1000BASE-T) PHYs (Gigabit Ethernet;
Ref. 4)
MAC and PHY modes for interfacing (MII/RMII/RGMII) directly with another switch or
host processor
Programmable drive strength for all interfaces
SPI at up to 25 MHz for host processor access
2.5 Other features
25 MHz system clock input from crystal oscillator or AC-coupled single-ended clock
25 MHz reference clock output
Device reset input from host processor
IEEE 1149.1 compliant JTAG interface for TAP controller access and boundary scan
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Product data sheet Rev. 1 — 7 November 2016 3 of 34
NXP Semiconductors SJA1105
5-port automotive Ethernet switch
3. Ordering information
4. Block diagram
Tabl e 1. Ordering information
Type number Package
Name Description Version
SJA1105EL LFBGA159 plastic low profile fine-pitc h ball grid array package; 159 balls SOT1427-1
SJA1105TEL
Fig 1. Block diagram of SJA1105EL
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SJA1105 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 7 November 2016 4 of 34
NXP Semiconductors SJA1105
5-port automotive Ethernet switch
Fig 2. Block diagram of SJA1105TEL
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SJA1105 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 7 November 2016 5 of 34
NXP Semiconductors SJA1105
5-port automotive Ethernet switch
5. Pinning information
5.1 Pinning
Fig 3. Pin configuration diagram
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Product data sheet Rev. 1 — 7 November 2016 6 of 34
NXP Semiconductors SJA1105
5-port automotive Ethernet switch
5.2 Pin description
[1] xMII I/O pins will be floating until the configuration has been loaded.
[2] I: digital input; O: digital output; P: power supply.
[1] P: power supply; G: ground.
Table 2. Pin description - xMII interface[1]
Symbol Pin Type[2] Description
MII interface:
0 1 2 3 4
VDDIO_
MIIx D4
E4
G4
D5
D7
D8
D10
D11
E11
G11
H11
K11
L8
L10
L11
P 3.3 V/2.5 V I/O supply voltage
TX_CLK/
REF_CLK/
TXC
D1 A7 C14 K14 N9 I/O
I/O
O
TX_CLK: MII interface transmit clock (also configurable as output)
REF_CLK: RMII interface reference clock (also configurable as input)
TXC: RGMII interface transmit clock
TX_EN/
TX_CTL D2 B7 C13 K13 P9 O TX_EN: MII/RMII interface transmit enable input
TX_CTL: RGMII interface transmi t control ou tput
TX_ER A3 A10 F14 N14 P6 O MII/RMII interface transmit coding error outpu t
TXD0 A2 B9 E13 M13 P7 O MII/RMII/RGMII interface transmit data output, bit 0
TXD1 B1 A9 E14 M14 N7 O MII/RMII/RGMII interface transmit data output, bit 1
TXD2 C2 B8 D13 L13 P8 O MII/RGMII interface transmit data output, bit 2
TXD3 C1 A8 D14 L14 N8 O MII/RGMII interface transmit data output, bit 3
RX_CLK/
RXC E2 B6 B14 J13 P10 I/O
IRX_CLK: MII interface receive clock (also configurable as output)
RXC: RGMII interface receive clock
RX_ER H2 B3 B10 F13 P13 I MII/RMII interface receive error input
RX_DV/
CRS_DV/
RX_CTL
G1 A4 A11 G14 N12 I RX_DV: MII interface receive data valid input
CRS_DV: RMII interface carrier sense/data valid input
RX_CTL: RGMII interface receive control input
RXD0 E1 A6 A13 J14 N10 I MII/RMII/RGMII interface receive data input, bit 0
RXD1 F2 B5 B12 H13 P11 I MII/RMII/RGMII interface receive data input, bit 1
RXD2 F1 A5 A12 H14 N11 I MII/RGMII interface receive data input, bit 2
RXD3 G2 B4 B11 G13 P12 I MII/RGMII interface receive data input, bit 3
Tabl e 3. Pin descriptio n - core supply and ground
Symbol Pin Type[1] Description
VDD_CORE D6, D9, F4, F11, J4, J11, L6, L9 P 1.2 V core supply voltage
VSS A1, A14, B13, E5, E6, E7, E8, E9, E10, F5, F6, F7, F8, F9, F10,
G5, G6, G7, G8, G9, G10, H5, H6, H7, H8, H9, H10, J5, J6, J7,
J8, J9, J10, K4, K5, K6, K7, K8, K9, K10, L7, N2, N13, P1, P14
G supply ground
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Product data sheet Rev. 1 — 7 November 2016 7 of 34
NXP Semiconductors SJA1105
5-port automotive Ethernet switch
[1] I: digital input; O: digital output; P: power supply, G: ground.
[2] Pins RST_N and TRST_N must be held LOW simultaneously to reset the device.
[3] JTAG pins have internal pull-ups.
Table 4. Pin description - general
Symbol Pin Type[1] Description
RST_N[2] P3 I reset input (active LOW)
PTP_CLK N4 O PTP clock
VDDIO_HOST L5 P host interface supply voltage
i.c. L4 G internally connected; must be connected to ground
Clock generation (CGU)
VDDA_OSC K1 P oscillator supply voltage
VSSA_OSC L2 G oscillator supply ground
VDDA_PLL J1 P PLL supply voltage
VSSA_PLL J2 G PLL supply ground
VDDIO_CLO H4 P clock output supply voltage (CLK_OUT)
CLK_OUT H1 O clock output
OSC_IN K2 I oscillator inpu t
OSC_OUT L1 O oscillator output
SPI interface
SCK P5 I SPI clock
SDI N5 I SPI data input
SDO P4 O SPI data output
SS_N N6 I SPI slave select (active LOW)
JTAG interface[3]
TRST_N M1 I test reset (active LOW)
TDI M2 I test data in
TCK N1 I test clock
TMS P2 I test mode state
TDO N3 O test data out
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Product data sheet Rev. 1 — 7 November 2016 8 of 34
NXP Semiconductors SJA1105
5-port automotive Ethernet switch
6. Functional description
The SJA1105 is designed to provide a cost-optimized and flexible solution for automotive
Ethernet switches. Each port can be independently configured for MII, RMII or RGMII
operation. Switch configuration is performed via an SPI interface. A typical system
diagram is shown in Figure 5.
6.1 Functional overview
The SJA1105 contains the following functional modules (see the block diagrams in
Figure 1 and Figure 2):
6.1.1 Auxiliary Configuration Unit (ACU)
This module contains the pin configuration and status registers. The host can configure
the I/O pads of the chip (pull-up/-down, speed etc.) and monitor the product configuration
and temperature sensor status via these registers.
6.1.2 Clock Generation Unit (CGU)
This module contains the oscillator and PLLs used to generate clocks for all internal
blocks and a number of interface output clocks.
6.1.3 Reset Generation Unit (RGU)
This block ensures that the device transitions to a pre-defined state after power-up or an
externally asserted reset.
Fig 5. System diagram showing the SJA1105 Ethern et switch con nected to PHYs and a
host processor
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SJA1105 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 7 November 2016 9 of 34
NXP Semiconductors SJA1105
5-port automotive Ethernet switch
6.1.4 Serial Peripheral Interface (SPI)
The host controller manag es access to the internal con figuration and pr ogramming sp ace
via the SPI.
6.1.5 Status and Control Unit (SCU)
This block contains the switch core status and configuration registers. The host processor
accesses these registers via the SPI.
6.1.6 Configuration Stream Decoder/Configuration Controller (CSD/CC)
This block handles the distribution of the configuration stream from the host processor to
the other modules and performs a CRC check on the configuration blo cks.
6.1.7 xMII
This block is a wrapper and multiplexer for the MII interface options. The device supports
MII, RMII and RGMII.
6.1.8 Dynamic Memory Management (DMM)/Frame Memory Controller (FMC)/
Frame Buffer Management (FBM)
These blocks deal with the storage and handling of frames in the memory buffer. The
DMM provides memory handles for ingress frames and holds meta information related to
the frames. The DMM releases frame handles for frames that are transmitted or dropped.
The FMC converts frame handles into virtual memory addresses and the FBM optimizes
the use of on-chip frame memory based on frame size.
6.1.9 Receive MAC (RXM)
The RXM loads the data from the xMII interface block and che cks the IF G, the preamble,
the SOF delimiter, the CRC and the frame length. It provides timestamps for clock
synchronization frames, extracts fram e metadata such as MAC addresses and VLAN
information a nd drops run t and oversized frames. The RXM co llects memory handles fr om
the DMM and transfers frame data to the FMC block for writing to memory.
6.1.10 Input Queue (IQ)
The IQ arranges the frame processing order so that the switching fabric behaves in a
deterministic manner. If two ports each receive the last byte of a complete frame in the
same clock cycle, the lower port ID is processed first.
6.1.11 VLAN Lookup (VLAN_LU)
The forwarding limit ations an d t agging/unt agging options are determined in the VLAN_LU
block.
6.1.12 Address Lookup (L2ADDR_LU)
The forwarding information for frames based on the destination MAC address in
combination with the VLAN ID are determin ed in this block. The lookup table is ad dressed
using an 8-bit hash value computed from the destination MAC address and the VLAN ID.
Up to four entries are supported per hash value. The table holds dyna mically learned as
well as statically configured entries. Dynamically learned entries can be configured to
time-out. The address lookup pr ocess can be configured to use shared or independent
address learning.
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Product data sheet Rev. 1 — 7 November 2016 10 of 34
NXP Semiconductors SJA1105
5-port automotive Ethernet switch
6.1.13 Policing (L2_POLICE)
Ingress policing rules are enfor ced in the L2_POLICE block. The transmission rate can be
limited for any of the eight priority levels and for bro adcast traffic at each port.
Non-compliant traffic is dropped and is indicated by associated flags and counters.
6.1.14 Forwarding (L2_FORW)
The L2_FORW block forwards frames to the destination ports. It maintains a vector of
reachable port s for unica st traf fic for e ach ingress port. In ad dition, it maint ains a ve ctor of
destination ports for broadcast traffic and for unknown multicast traffic. This block also
maintains a me mory partition account for tr affic received per port an d drops frames if there
is insufficient sp a ce. This block a lso ha ndles prio rity remap ping and e gress queu e priority
mapping.
6.1.15 Transmit MAC (TXM)
This block handles frame output via the xMII interface. It supports eight priority queues
and implement s strict-priority scheduling. The AVB block can interrupt the scheduling from
specific priority queues in case shapers are allocated to queues. When a frame is
selected for transmission, this block gets the frame data from th e FMC using the memory
handle of the frame. It passes the free memory handle back to the DMM once the frame
has been transmitted. It also inserts VLAN tags into packet headers. It can be configured
to perform the IEEE 1588v2 transparent clock update for synchronization frames.
6.1.16 Audio Video Bridging (AVB)
This block implements credit-based traffic shaping and interrupts transmission from
priority queues in the TXM when necessary to ensure that shaping occurs. It also captures
high-resolution timestamps for IEEE 802.1AS and IEEE 1588v2 operation. The host
processor can adjust the IEEE 1588v2 hardware clock via this block.
6.1.17 Loopback Port (LBP)
This block uses an internal p ort to replicate a frame intern ally and change the VLAN t ag to
support ingress and egre ss retagging of traffic. The replicated fra me-handling infor mation
is fed back to the IQ which processes the frame in the same way as a frame from a
regular traffic port.
6.1.18 Virtual Link Lookup (VL_LU); SJA1105TEL only
The VL_LU block performs a lookup of time -triggered and rate-constrained traffic based
on the configured Virtual Link Multicast addresses, the VLAN ID and the VLAN priority
identifying time-triggered or rate-constrained traffic.
6.1.19 Virtual Link Policing (VL_POLICE); SJA1105TEL only
The VL_POLICE block executes policing functions based on the time-triggered Ethernet
or rate-constrained traf fic rule set. Policing mechanisms ca n be configured individua lly per
flow (i.e. per virtual link). Time-triggered Ethernet policin g verifies that a frame rece ived by
the switch was sent at the correct point in time by the neighboring node. Non-compliant
frames are dropped and are indicated by associated flags and counters.
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6.1.20 Virtual Link Forwarding (VL_FORW); SJA1105TEL only
The VL_FORW block forwards time-trigger ed or rate-constrained traffic to the destination
ports. T ime-trigge red traffic is stored in this module until the runn ing traffic sche dule fires a
transmit trigger for the respective Virtual Link. Rate-constrained traffic is immediately
routed to the destin ation p orts. All time-triggered frames are drop ped if synchr oni zatio n is
lost.
6.1.21 Clock Synchronization Subsystem (CSS) and Schedule Engine (SCH);
SJA1105TEL only
This block implements the clock synchronization protocol and executes the message
schedules.
6.2 Media Independent Interfaces (xMII)
The SJA1105 xMII interfaces can be configured to support a wide variety of PHYs and
host controllers. Each port can be configured for MAC-to-PHY or MAC-to-MAC
communication. The following configu rations are supported:
MII: 25 MHz clock for 100 Mbit/s or 2.5 MHz for 10 Mbit/s operation, 14 interface signals,
full duplex only, 3.3 V (Ref. 5)
RMII: 50 MHz clock for 100 Mbit/s and 10 Mbit/s operation, 8 interface signals (reference
clock can be an input to both devices or may be driven from MAC to PHY), full duplex
only, 3.3 V specification (Ref. 6)
RGMII: 125 MHz clock (both edges) fo r 1000 Mbit/s, 25 MHz for 100 Mbit/s or 2.5 MHz for
10 Mbit/s operation, 12 interface signals; full duplex only, 2.5 V (Ref. 4)
Depending on how the switch is configured, the following interface signals are available at
each of the five ports:
Tabl e 5. MII pin multiplexing
MII (14 interface signals) RMII (8 int er face signals) RGMII (12 interface signals)
TX_CLK REF_CLK TXC
TX_EN TX_EN TX_CTL
TX_ER TX_ER -
TXD0 TXD0 TXD0
TXD1 TXD1 TXD1
TXD2 - TXD2
TXD3 - TXD3
RX_CLK - RXC
RX_ER RX_ER -
RX_DV CRS_DV RX_CTL
RXD0 RXD0 RXD0
RXD1 RXD1 RXD1
RXD2 - RXD2
RXD3 - RXD3
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5-port automotive Ethernet switch
6.2.1 MII signaling and encoding
Figure 6 shows the PHY-MAC and MAC-M A C co nne cti ons in an MII interface. Data is
exchanged via 4-bit wide data nibbles TXD[3:0] and RXD[3:0]. Data transmission is
synchronous with the transmit (T X_CLK) and receive (RX_CLK) clocks. For the PHY-MAC
interface, both clock signals are provided by the PHY and are typically derived from an
external crystal running at a nominal 25 MHz (100 ppm) or from the CLK_ OUT signal on
the switch. When the Ethernet Switch is configured for MAC-MAC communication, the
switch provides the cloc ks an d acts like a PHY.
A HIGH level on TX_EN initiates data transmission; a HIGH level on RX_DV signals data
reception.
6.2.2 RMII signaling and encoding
RMII data is exchanged via 2-bit data signals TXD[1:0] and RXD[1:0] as shown in
Figure 7. Transmit and receive signals are synchronous with the shared reference clock,
REF_CLK.
In the PHY-MAC configuration, the REF_CLK shared r eference clock can be gen erated by
the Ethernet switch. In the MAC-MAC configuration, the external MAC can supply the
reference clock.
To achieve the same data rate as MII, the interface is clocked at a nominal 50 MHz
(50 ppm) for 100 Mbit/s and 10 Mbit/s operation.
a. PHY-MAC interface b. MAC-MAC interface
Fig 6. MII interface connections
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Product data sheet Rev. 1 — 7 November 2016 13 of 34
NXP Semiconductors SJA1105
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6.2.3 RGMII signaling and encoding
The PHY-MAC and MAC-MAC connections in an RGMII-configured interface are shown in
Figure 8. The RGMII protocol is intended to be an alternative to the IEEE 802.3z GMII
standard (not supported on the SJA1105). The objective is to reduce the number of pins
needed to connect the MAC and PHY in a cost-effective and technology-independent
way. RGMII has the added advantage over RMII in that it supports Gigabit operation.
In order to achieve a reduced pin count, the number of data signals and associated
control signals is reduced . Control signals are multiplexed tog ether and transmitted dat a is
synchronized with both clock edges (double data rate).
RGMII is a symmetrical interface. For 1000 Mbit/s, 100 Mbit/s a nd 10 Mbit/s operation, the
clocks operate at 1 25 MHz, 25 MHz and 2.5 MHz (50 ppm) respectively. The TXC signal
is always generated by the MAC. The PHY genera tes th e RXC. Note that RGMII requir es
an external delay of between 1.5 ns and 2 ns on TXC and RXC.
a. PHY-MAC interface b. MAC-MAC interface
Fig 7. RMII interface connections
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5-port automotive Ethernet switch
6.3 SPI interface
The SJA1105 provides an SPI bus slave as the host control interface. The host can
control/configure the SJA1105 by accessing the configuration address space and the
programming address space.
This interface act s as a slave in a synchronou s serial data link that conforms with the SPI
standard as de fined in the SPI Block Guide from Motorola ( Ref. 7) . The interface operates
in SPI Tran sf er mode 1 (C POL = 0, CPHA = 1).
An example SPI timing diagram is shown in Figure 9. Data is captured on the falling edge
of the clock and transmitte d on the rising edge. Both master and slave mu st operate in the
same mode.
When CGU registe rs ar e re ad , a 64 ns de lay must be ins er te d be twe e n the con tr ol and
data phases to allow the device to retrieve the data. Alternatively, the access can be
performed at a frequency below 17.8 MHz. In addition, a read-af ter-write time of >130 ns
between an SPI write and re ad tran sactio n to the same re gister must be guarantee d. See
the SJA1105 software user manuals (Ref. 8) for further details on the data format.
The number of SPI clock cycle s must be b etween 64 an d 2080 and be a m ultiple of 32 . In
order to ensure support for a wide a range of microcontrolle rs, the SPI interface can
operate at a supply voltage of 3.3 V, 2.5 V or 1.8 V (determined by the voltage connected
to VDDIO_HOST; see Section 11).
Fig 9. SPI transfer timing (example)
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7. Limiting values
[1] According to AEC-Q100-002.
[2] According to AEC-Q100-011.
8. Thermal characteristics
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDDA(osc) oscillator analog supp ly
voltage on pin VDDA_OSC 0.5 +1.6 V
VDDA(PLL) PLL analog supply voltage on pin VDDA_PLL 0.5 +1.6 V
VDDC core supply voltage on pins VDD_CORE 0.5 +1.6 V
VDD(host) host supply voltage on pin VDDIO_HOST 0.5 +5 V
VDD(clk) clock supply voltage on pin VDDIO_CLO 0.5 +5 V
VDD(MII) MII supply voltage on pins VDDIO_MIIx 0.5 +5 V
VESD electrostatic discharge voltage Human Body Model (HBM); 100 pF, 1.5 k[1] 2000 +2000 V
Charged Device Model (CDM) [2]
corner balls 750 +750 V
other balls 500 +500 V
Tjjunction temperature 40 +125 C
Tstg storage temperature 55 +150 C
Table 7. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient 4-layer board (JESD51-9) 29 K/W
Rth(j-lead) thermal resistance from junction to lead 4-layer board (JESD51-9) 15 K/W
j-top thermal characterization parameter from junc tion to top
of package 4-layer board (JESD51-9) 0.33 K/W
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5-port automotive Ethernet switch
9. Static characteristics
Table 8. Static characteristics
Tj=
40
C to +125
C; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into
the IC.
Symbol Parameter Conditions Min Typ Max Unit
Supply voltages; see Figure 15
Clock and host interface supply (pins VDDIO_CLO and VDDIO_HOST)
VDD(clk) clock supply voltage 3.3 V signaling 3.00 3.30 3.60 V
2.5 V signaling 2.30 2.50 2.70 V
1.8 V signaling 1.65 1.80 1.95 V
VDD(host) host supply voltage 3.3 V signaling 3.00 3.30 3.60 V
2.5 V signaling 2.30 2.50 2.70 V
1.8 V signaling 1.65 1.80 1.95 V
MII interface supply (pins VDDIO_MII0 to VDDIO_MII4)
VDD(MII) MII supply voltage MII/RMII 3.00 3.30 3.60 V
RGMII 2.30 2.50 2.70 V
Core, oscillator and PLL suppl y (pins VDD_CORE, VDDA_OSC and VDDA_PLL)
VDDC core supply voltage see Figure 15 1.14 1.20 1.30 V
VDDA(osc) oscillator analo g supply voltage 1.10 1.20 1.30 V
VDDA(PLL) PLL analog supply voltage 1.10 1.20 1.30 V
Supply currents
Clock and host interface supply (pins VDDIO_CLO and VDDIO_HOST)
IDD(host) host supply current VDD(HOST) =3.30V - - 2.8 mA
IDD(clk) clock supply current VVDD(CLK) =3.30V - - 3.5 mA
MII interface supply (pins VDDIO_MII0 to VDDIO_MII4)
IDD(MII) MII supply current port set to RGMII, 1 Gbit/s
CL =18pF - - 65.5 mA
25 % load PRBS - 14.3 - mA
100 % load PRBS - 31.8 - mA
port set to RMII, 100 Mbit/s
CL =25pF - - 15.5 mA
25 % load PRBS - 6.8 - mA
100 % load PRBS - 8.5 - mA
port set to MII, 100 Mbit/s
CL =25pF - - 11.5 mA
25 % load PRBS - 0.7 - mA
100 % load PRBS - 2.4 - mA
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Core, oscillator and PLL suppl y (pins VDD_CORE, VDDA_OSC and VDDA_PLL)
IDDC core supply current worst case - - 110 mA
all ports set to RGMII,
1Gbit/s
25 % PRBS - 37.7 - mA
100 % PRBS - 54.3 - mA
all ports set to MII/RMII, 100 Mbit/s
25 % PRBS - 31.0 - mA
100 % PRBS - 33.2 - mA
IDDA(PLL) PLL analog supply current PLL0 enabled; see Ref. 8 --1.2mA
PLL0 and PLL1 enabled; see
Ref. 8 --2.4mA
IDDA(osc) oscillator analog su pply current - 350 - A
Istartup(osc) oscillator start-up current 0.2 1.0 2.5 mA
Power-On Reset (POR)
Vtrip(POR) power-on reset trip voltage HIGH level 0.65 0.76 1.01 V
LOW level 0.60 0.72 0.91 V
pin RST_N[1]
Vhys(i) input hysteresis voltage 0.1
VVDD(HOST)
-- V
VIH HIGH-level input voltage 3.3 V signaling 2.0 - VVDD(HOST)
+ 0.5 V
2.5 V signaling 1.7 - VVDD(HOST)
+ 0.5 V
1.8 V signaling 0.65
VVDD(HOST)
-V
VDD(HOST)
+ 0.5 V
VIL LOW-level input voltage 3.3 V signaling 0.5 - +0.8 V
2.5 V signaling 0.5 - +0.7 V
1.8 V signaling 0.5 - +0.35
VVDD(HOST)
V
Rpu(weak) weak pull-up resistance 40 50 57 k
Ciinput capacitance - - 8.0 pF
Oscillator (p ins OSC_IN and OSC_OUT)
Crystal oscillator mode
Ciinput capacitance on pin OSC_IN - - 3.5 pF
Cshunt shunt capacitance - - 7.0 pF
CL(ext) external load capacitance on pin OSC_IN [2] -8- pF
on pin OSC_OUT [2] -8- pF
Clock mode
Cdec decoupling capacitance - 100 - pF
Vi(OSC_IN) input voltage on pin OSC_IN RMS value 0.20 - VDDA(OSC) V
Table 8. Static characteristics …continued
Tj=
40
C to +125
C; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into
the IC.
Symbol Parameter Conditions Min Typ Max Unit
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[1] Pins RST_N and TRST_N must be held LOW simultaneously to reset the device.
[2] Value is crystal dependent.
[3] Supply voltage on I/O pin x.
I/O pins (VDDIO_MII0 to VDDIO_MII4, SPI, JTAG, CLK_OUT, PTP_CLK)
VIH HIGH-level input voltage 3.3 V signaling (supported for
MII/RMII operation) 2.0 - VDDx + 0.5[3] V
2.5 V signaling (supported for
RGMII operation) 1.7 - VDDx[3] + 0.5 V
1.8 V signaling (not supported
for MII, RMII or RGMII) 0.65
VDDx[3] -V
DDx[3] + 0.5 V
VIL LOW-level input voltage 3.3 V signaling 0.5 - +0.8 V
2.5 V signaling 0.5 - +0.7 V
1.8 V signaling 0.5 - +0.35
VDDx[3] V
Vhys(i) input hysteresis voltage 0.1
VDDx[3] -- V
Rpu(weak) weak pull-up resistance VIO = 0 V 40.0 50.0 57.0 k
Rpd(weak) weak pull-down resistance VIO = VDDx 40.0 50.0 57.0 k
IOSH HIGH-level short-circuit output
current --111.7 mA
IOSL LOW-level short-circuit output
current --110.2mA
Ciinput capacitance - - 5.0 pF
Zooutput impedance 40.0 - 67.5
Table 8. Static characteristics …continued
Tj=
40
C to +125
C; all voltages are defined with respect to ground unless otherwise specified; positive currents flow into
the IC.
Symbol Parameter Conditions Min Typ Max Unit
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10. Dynamic characteristics
Table 9. Dynamic characteristics