PIC16LC65B-04I/PQ - MICROCHIP TECHNOLOGY

 1998-2013 Microchip Technology Inc. DS30605D-page 1

PIC16C63A/65B/73B/74B

Devices included in thi s data sheet:

PIC16CXX Microcont roller Cor e Feat ures:

• High performance RISC CPU

• Only 35 single word instructions to learn

• All single cycle instructions except for program

branches which are two cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• 4 K x 14 words of Program Memory,

192 x 8 bytes of Data Memory (RAM)

• Interrupt capability

• Eight-level deep hardware stac k

• Direct, indirect and relative addressing modes

• Pow er-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST)

• Watchdog Timer (WDT) with its own on -chip RC

oscillator for reliable operat ion

• Programmable code protection

• Power-saving SLEEP mode

• Selectable oscillator op tions

• Low power, high speed CMOS EPROM

technology

• Wide operating voltage range: 2.5V to 5.5V

• High Sink/Source Current 25/25 mA

• Commercial, Industrial and Automotive

temperature ranges

• Low power consumption:

- < 5 mA @ 5V, 4 MHz

-23 A typical @ 3V, 32 kHz

-< 1.2 A typical standby current

PIC16C7X Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler

can be increm ent ed duri ng SLEEP via extern al

crystal/clock

• Timer2: 8-bit time r/counter with 8-bit period

• Capture , Comp a r e, PWM mo dul es

- Capture is 16-bit, max. resolution is 200 ns

- Compare is 16-bit, max. resolution is 200 ns

- PWM max. resolution is 10-bit

• 8-bit multichannel Analog-to-Digital converter

• Synchronous Serial Port (SSP) with SPITM

and I2CTM

• Universal Synchronous Asynchronous Receiver

Transmitter (USART/SCI)

• Parallel Slave Port (PSP), 8-bits wide with

external RD, WR and CS controls

• Brown-ou t dete cti on circ uitry for Brown-out Reset

(BOR)

Pin Diagram:

• PIC16C63A • PIC16C73B

• PIC16C65B • PIC16C74B

Devices I/O

Pins A/D

Chan. PSP Interrupts

PIC16C63A 22 - No 10

PIC16C65B 33 - Yes 11

PIC16C73B 22 5 No 11

PIC16C74B 33 8 Yes 12

PDIP, Windowed CERDIP

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0/INT

VDD

VSS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

MCLR/VPP

RA0/AN0

RA1/AN1

RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

RA5/SS/AN4

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

VDD

VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RD0/PSP0

RD1/PSP1

PIC16C65B

PIC16C74B

8-Bit CMOS Microcontrollers with A/ D C o nverter

PIC16C63A/65B/73B/74B

DS30605D-page 2  1998-2013 Microchip Technology Inc.

MCLR/VPP

RA0/AN0

RA1/AN1

RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

RA5/SS/AN4

VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0/INT

VDD

VSS

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

• 1

SDIP, SOIC, Windowed CERDIP

RB3

RB2

RB1

RB0/INT

VDD

VSS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7/RX/DT

RA4/T0CKI

RA5/SS/AN4

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

VDD

VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

MCLR/VPP

RB7

RB6

RB5

RB4

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1 6

PIC16C65B

RC0/T1OSO/T1CKI

OSC2/CLKOUT

OSC1/CLKIN

VSS

VDD

RE2/CS/AN7

RE1/WR/AN6

RE0/RD/AN5

RA5/SS/AN4

RA4/T0CKI

RC7/RX/DT

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

VSS

VDD

RB0/INT

RB1

RB2

RB3

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI/CCP2

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

MCLR/VPP

RB7

RB6

RB5

RB4

NC 44

MQFP

PLCC

PIC16C74B

TQFP

RC1/T1OSI/CCP2

PIC16C65B

PIC16C74B

PIC16C63A

PIC16C73B

Key Features

PIC® Mid-Range MCU Family Reference

Manual (DS33023) PIC16C63A PIC16C65B PIC16C73B PIC16C74B

Program Memory (EPROM) x 14 4 K 4 K 4 K 4 K

Data Memory (Bytes) x 8 192 192 192 192

Pins 28 40 28 40

Parallel Slave Port — Yes — Yes

Capture/Compare/PWM Modules 2 2 2 2

Timer Modules 3 3 3 3

A/D Channels — — 5 8

Serial Communication SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART

In-Circuit Serial Programming Yes Yes Yes Yes

Brown-out Reset Yes Yes Yes Yes

Interrupt Sources 10 11 11 12

Packages 28-pin SDIP, SOIC,

SSOP,

Windowed CERDIP

40-pin PDIP;

44-pin PLCC,

MQFP, TQFP,

Windowed CERDIP

28-pin SDIP, SOIC,

SSOP,

Windowed CERDIP

40-pin PDIP;

44-pin PLCC,

MQFP, TQFP,

Windowed CERDIP

 1998-2013 Microchip Technology Inc. DS30605D-page 3

PIC16C63A/65B/73B/74B

Table of Contents

1.0 General Description......... .... ......... .. .... .... .. ......... .. .... .... .. ......... .... .. .... .... ....... .... .. .... .... ................................................................... 5

2.0 PIC1 6 C 6 3 A/65B/73 B/74B Device Varieties.............. ........... .......... ..................... ........... .......... .................................................... 7

3.0 Architectural Overview ................................................................................................................................................................. 9

4.0 Memory Organization................................................................................................................................................................. 15

5.0 I /O Po rts........... ........... .......... ........... .......... ........... .......... ........... .......... ........... ........................................................................... 29

6.0 Timer0 Module ........................................................................................................................................................................... 39

7.0 Timer1 Module ........................................................................................................................................................................... 43

8.0 Timer2 Module ........................................................................................................................................................................... 47

9.0 Capture/Compare/PWM Modules .......... .... ......... .... .... .... ......... .... .... .... ......... .... .... .... ......... .... .... ................................................ 49

10.0 Synchronous Serial Port (SS P) Mo dule ..................................................................................................................................... 55

11.0 Addr essable Universal Synchronous Asynchronous Receiv er Transmitter (USA RT )................................................................ 65

12.0 Analog-t o-Digital Converter (A/D) Module ................................................................................................................................. 79

13.0 Specia l Features of the CPU........ .......... ........... .......... ........... .......... ........... .......... ..................................................................... 85

14.0 Instruction Set Summary............................................................................................................................................................ 99

15.0 Development Support............................................................................................................................................................... 107

16.0 Electrical Characterist ics.......................................................................................................................................................... 113

17.0 DC and AC Characteristics Graphs and Tables........................... .... ........... .... .... .... ........... .... .... .... ... ....................................... 139

18.0 Packagin g In fo rmation.......................... ........... .......... ........... ..................... .......... ........... .......................................................... 153

Appendix A: Revision History ............................................................ .... ............... .... ...... .......... ..................................................... 165

Appendix B: Device Differences...................................... .... ......... .... .... .... ......... .... .... .... .. ........... .................................................... 165

Appendix C: Device Migrations - PIC16C63/65A/73A/74A PIC16C63A/65B/73B/74B ............................................................. 166

Appendix D: Migration from Baseline to Mid-Range Devices............. .... .... ......... .. .... .... ......... .. .... .... .... .......................................... 168

On-Line Support............................................... .... ......... .... .... .... ......... .... .... .... ......... .... .... ................................................................... 175

Reader Response.............................................................................................................................................................................. 176

Product Identification System ............................................................................................................................................................ 177

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PIC16C63A/65B/73B/74B

DS30605D-page 4  1998-2013 Microchip Technology Inc.

NOTES:

 1998-2013 Microchip Technology Inc. DS30605D-page 5

PIC16C63A/65B/73B/74B

1.0 GENERAL DESCRIP T ION

The PIC16C63A/65B/73B/74B devices are low cost,

high performance, CMOS, fully-static, 8-bit micro-

controllers in the PIC16CXX mid-range family.

All PIC® microcontrollers employ an advanced RISC

arch itecture. The PI C16CXX mic rocontroll er family has

enhanced core features, eight-level deep stack and

multiple internal and external interrupt sources. The

separate instruction and data buses of the Harvard

architecture allow a 14-bit wide instruction word with

the separate 8-bit wide data. The two stage instruction

pipeline allows all instructions to execute in a single

cycle, except for program branches, which require two

cycles. A total of 35 instructions (reduced instruction

set) are available. Additionally, a large register set

gives some of the architectural innovations used to

ach i eve a very high performance.

The PIC16C63A/73B devices have 22 I/O pins. The

PIC16C65B/74B devices have 33 I/O pins. Each

device has 192 bytes of RAM. In addition, several

periphera l features are available, including: three timer/

counters, two Capture/Compare/PWM modules, and

two serial ports. The Synchronous Serial Port (SSP)

can be configured as either a 3-wire Serial Peripheral

Interface (SPI) or the two-wire Inter-Integrated Circuit

(I2C) bus. The Universal Synchronous Asynchronous

Receiver Transmitter (USART) is also known as the

Serial Communications Interface or SCI. Also, a 5-

channel high speed 8-bit A/D is provided on the

PIC16C73B, while the PIC16C74B offers 8 channels.

The 8-bit resolution is ideally suited for applications

requiring low cost analog interface, e.g., thermostat

control, pressure sensing, etc.

The PIC16C63A/65B/73B/74B devices have special

featur es to red uce extern al com ponent s, th us redu cing

cost, enhancing system reliability and reducing power

consumption. There are four oscillator options, of which

the single pin RC oscillator provides a low cost solution,

the LP oscillator minimizes power consumption, XT is

a standard crystal, and the HS is for high speed crys-

tals. The SLEEP (power-down) feature provides a

power-saving mode. The user can wake-up the chip

from SLEEP through several external and internal

interrupts and RESETS.

A highly reliable Watchdog Timer (WDT), with its own

on-chip RC oscillator, provides protection against soft-

ware lockup, and also provides one way of waking the

device from SLEEP.

A UV erasable CERDIP packaged version is ideal for

code development, while the cost effective One-Time-

Programm able (OTP) versi on is suit able for productio n

in any volume .

The PIC16C63A/65B/73B/74B devices fit nicely in

many applications ranging from security and remote

sensors to appliance control and automotive. The

EPROM technology makes customization of applica-

tion programs (transmitter codes, motor speeds,

receiver frequencies, etc.) extremely fast and con-

venient . The smal l foo tprint p acka ges ma ke this micro-

controller series perfect for all applications with space

limitations. Low cost, low power, high performance,

ease of use and I/O flexibility make the PIC16C63A/

65B/73B/74B devices very versatile, even in areas

where no microcontroller use has been considered

before (e.g., timer functions, serial communication,

capture an d compare, PWM functions and coprocessor

applications).

1.1 Family and Upward Compatibility

Users fami liar with the PIC16C5X microcontroller fam-

ily will realize that this is an enhanced version of the

PIC16C5X a rch ite ctu re. Please refer to Appe ndi x A f or

a detailed list of enhancements. Code written for the

PIC16C5X c an be e as ily po rted to the PIC16CXX fam-

ily of devic es (Appe ndi x B).

1.2 Development Support

PIC® devices are supported by the complete line of

Microchip Development tools.

Please refer to Section 15.0 for more details about

Microchip’s development tools.

PIC16C63A/65B/73B/74B

DS30605D-page 6  1998-2013 Microchip Technology Inc.

NOTES:

 1998-2013 Microchip Technology Inc. DS30605D-page 7

PIC16C63A/65B/73B/74B

2.0 PIC16C63A/65B/73B/74B DEVICE

VARIETIES

A variety of frequency ranges and packaging options

are avail able. Depending on application and production

requirem ents, the p roper device o ption can be s elected

using the information in the PIC16C63A/65B/73B/74B

Product Ide ntif ic atio n Sys tem sec tio n at the end of thi s

data sheet. When placing orders, please use that page

of the data sheet to specify the correct part number.

For the PIC16C7X family, there are two device “types”

as indicated in the device number:

1. C, as in PIC16C74. These devices have

EPROM type memory and operate over the

standard voltage range.

2. LC, as in PIC16LC74. These devices have

EPROM type memory and operate over an

extended voltage range.

2.1 UV Erasable Devices

The UV erasable version, offered in win dowed CERDIP

packages, is optimal for prototype development and

pilot programs. This version can be erased and

reprogrammed to any of the oscillator modes.

Microchip's PICSTART Plus and PRO MATEII

programmers both support programming of the

PIC16C63A/65B/73B/74B.

2.2 One-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for

customers who need the flexibility for frequent code

updates and small volume applications.

The OT P devices , packaged i n plasti c packages , per-

mit the user to program them once. In addition to the

program memory, the configuration bits must also be

programmed.

2.3 Quick-Turnaround-Production

(QT P ) D e vices

Microchip offers a QTP Programming Service for fac-

tory produc tion or ders. Th is servi ce is ma de availa ble

for users who choose not to program a medium to high

quantity of units and whose code patterns have stabi-

lized. The devices ar e identical to the OT P d evi ce s but

with all EPROM locations and configuration options

already programmed by the factory. Certain code and

prototype verification procedures apply before produc-

tion shipm ents are availabl e. Plea se co ntact your local

Microchip Technology sales office for more details.

2.4 Serialized Quick-Turnaround

Production (SQTPSM) Devices

Microchip offers a unique programming service where

a few user-defined locations in each device are pro-

grammed with diffe rent serial numbers. The serial num-

bers may be random, pseudo-random or sequential.

Serial programming allows each device to have a

unique number, which can serve as an entry code,

password or ID number.

PIC16C63A/65B/73B/74B

DS30605D-page 8  1998-2013 Microchip Technology Inc.

NOTES:

 1998-2013 Microchip Technology Inc. DS30605D-page 9

PIC16C63A/65B/73B/74B

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16CXX family can be

attributed to a number of architectural features com-

monly found in RISC microprocessors. To begin with,

the PIC16CXX uses a Harvard architecture, in which

program and data are accessed from separate memo-

ries using separate buses. This improves bandwidth

over traditional von Neumann architecture, in which

program and data are fetched from the same memory

using the same bus. Separating program and data

buses fu r the r all ow s inst r uct i on s t o be si ze d diffe ren t ly

than the 8-bit wide data word. Instruction opcodes are

14-bits wide, making it possible to have all single word

instructions. A 14-bit wide program memory access

bus fetches a 14-bit instruction in a single cycle. A

two-stage pipeline overlaps fetch and execution of

instructions (Example 3-1). Consequently, most

instructions execute in a single cycle (200 ns @

20 MHz) except for program branches.

All devices covered by this data sheet contain

4K x 14-bit program memory and 192 x 8-bit data

memory.

The PIC16CXX can directly, or indirectly, address its

isters, including the program counter, are mapped in

the data memory. The PIC16CXX has an orthogonal

(symmetrical) instruction set that makes it possible to

carry out any operation on any register using any

addressing mode. This symmetrical nature and lack of

‘speci al opti mal s ituat ions ’ make prog rammi ng wi th the

PIC16CXX simp le yet ef ficient. In addition, the lea rning

curve is reduced significantly.

PIC16CXX devices contain an 8-bit ALU and working

It performs arithmetic and Boolean functions between

the data in the working register and any register file.

The ALU is 8-bits wide and capable of addition, sub-

traction, shift and logical operations. Unless otherwise

mentioned, arithmetic operations are two's comple-

ment in nature. In two-operand instructions, typically

one operand is the working register (W register). The

other operand is a file register or an immediate con-

stant. In single operand instructions, the operand is

either the W register or a file register.

The W registe r is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affe ct the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bit s in the ST ATUS register . The C and D C bits

operate as a borrow bit and a digit borrow out bit,

respect ively, in subtract ion. Se e the SUBLW and SUBWF

instructions for examples.

PIC16C63A/65B/73B/74B

DS30605D-page 10  1998-2013 Microchip Technology Inc.

FIGURE 3-1: PIC16C63A/6 5 B/73B/74B BLOCK DIAGRAM

EPROM

Program

Memory

13 Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level S tack

(13-bit) RAM

File

Registers

Direct Addr 7

RAM Addr (1) 9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR VDD, V SS

PORTA

PORTB

PORTC

PORTD(3)

PORTE(3)

RA4/T0CKI

RA5/SS/AN4(2)

RB0/INT

RB7:RB1

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

RC7/RX/DT

RD6/PSP6

RE0/RD/AN5(2,3)

RE1/WR/AN6(2,3)

RE2/CS/AN7(2,3)

Brown-out

Reset

Note 1: Higher order bits are from the STATUS register.

2: A/D is not available on the PIC16C63A/65B.

3: PSP and Ports D and E are not available on PIC16C63A/73B.

USART

CCP1 CCP2 Synchronous

A/D(2)

Timer0 Timer1 Timer2

Serial Port

RA3/AN3/VREF(2)

RA2/AN2(2)

RA1/AN1(2)

RA0/AN0(2)

Parallel Slave Port

(3)

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

RD5/PSP5

RD0/PSP0

RD7/PSP7

 1998-2013 Microchip Technology Inc. DS30605D-page 11

PIC16C63A/65B/73B/74B

TABLE 3-1: PIC16C63A/73B PINOUT DESCRIPTION

Pin Name DIP

Pin# SOIC

Pin# I/O/P

Type Buffer

Type Description

OSC1/CLKIN 9 9 I ST/CMOS(3) Oscillator crystal input/external clock source input.

OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, t he OSC2 pin outputs

CLKOUT which has 1/4 the frequency of OSC1, and denotes

the instruction cycle rate.

MCLR/VPP 1 1 I/P ST Master clear (RESET) input or programming voltage input.

This pin is an active low RESET to the device.

PORTA is a bi-directional I/O port.

RA0/AN0(4) 2 2 I/O T T L RA0 can also be analog input 0(4).

RA1/AN1(4) 3 3 I/O T T L RA1 can also be analog input 1(4).

RA2/AN2(4) 4 4 I/O T T L RA2 can also be analog input 2(4).

RA3/AN3/VREF(4) 5 5 I/O T TL RA3 can also be analog input 3 or analog reference

voltage(4).

RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer 0 module.

Output is open drain type.

RA5/SS/AN4(4) 7 7 I/O TTL RA5 can also be analog input 4(4) or the slave select for

the synchronous serial port.

PORTB is a bi-directional I/O port. PORTB can be software

programmed for internal weak pull-up on all input s.

RB0/INT 21 21 I/O TTL/ST(1) RB0 can also be the external interrupt pin.

RB1 22 22 I/O TTL

RB2 23 23 I/O TTL

RB3 24 24 I/O TTL

RB4 25 25 I/O TTL Interrupt-on-change pin.

RB5 26 26 I/O TTL Interrupt-on-change pin.

RB6 27 27 I/O TTL/ST(2) Interrupt-on-change pin. Serial programming clock.

RB7 28 28 I/O TTL/ST(2) Interrupt-on-change pin. Serial programming data.

PORTC is a bi-directional I/O port.

RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1

clock input.

RC1/T1OSI/CCP2 12 12 I /O S T RC1 can also be the Tim er1 oscillator input or Capture2

input/Compare2 output/PWM2 output.

RC2/CCP1 13 13 I /O S T RC2 can also be the Capture1 input/Compare1

output/PWM1 output.

RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output

for both SPI and I2C modes.

RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or

data I/O (I2C mode).

RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).

RC6/TX/CK 17 17 I /O ST RC6 can also be the USART Asynchronous Transmit

or Synchronous Clock.

RC7/RX/DT 18 18 I /O ST RC7 can also be the USART Asynchronous Receive

or Synchronous Data.

VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins.

VDD 20 20 P — Positive supply for logic and I/O pins.

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

4: A/D module is not available in the PIC16C63A.

PIC16C63A/65B/73B/74B

DS30605D-page 12  1998-2013 Microchip Technology Inc.

TABLE 3-2: PIC16C65B/74B PINOUT DESCRIPTION

Pin Name DIP

Pin# PLCC

Pin#

TQFP

MQFP

Pin#

I/O/P

Type Buffer

Type Description

OSC1/CLKIN 13 14 30 I ST/CMOS(4) Oscillator crystal input/external clock source input.

OSC2/CLKO UT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, OSC2 pin outputs

CLKOUT which has 1/4 the frequency of OSC1, and

denotes the instruction cycle rate.

MCLR/VPP 1 2 18 I/P ST Master clear (RESET) input or programming voltage input.

This pin is an active low RESET to the device.

PORTA is a bi-directional I/O port.

RA0/AN0(5) 2 3 19 I/O TTL RA0 can also be analog input 0(5).

RA1/AN1(5) 3 4 20 I/O TTL RA1 can also be analog input 1(5).

RA2/AN2(5) 4 5 21 I/O TTL RA2 can also be analog input 2(5).

RA3/AN3/VREF(5) 5 6 22 I/O TTL RA3 can also be analog input 3 or analog reference

voltage(5).

RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/

counter. Output is open drain type.

RA5/SS/AN4(5) 7 8 24 I/O TTL RA5 can also be analog input 4(5) or the slave select for

the synchronous serial port.

PORTB is a bi-directional I/O port. PORTB can be software

programmed for internal weak pull-up on all inputs.

RB0/INT 33 36 8 I/O TTL/ST(1) RB0 can also be the external interrupt pin.

RB1 34 37 9 I/O TTL

RB2 35 38 10 I/O TTL

RB3 36 39 11 I/O TTL

RB4 37 41 14 I /O TTL Interrupt-on-change pin.

RB5 38 42 15 I /O TTL Interrupt-on-change pin.

RB6 39 43 16 I/O TTL/ST(2) Interrupt-on-change pin. Serial programming clock.

RB7 40 44 17 I/O TTL/ST(2) Interrupt-on-change pin. Serial programming data.

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel

Slave Port mode (for interfacing to a microprocesso r bus).

4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

5: A/D is not available on the PIC16C65B.

 1998-2013 Microchip Technology Inc. DS30605D-page 13

PIC16C63A/65B/73B/74B

PORTC is a bi-directional I/O port.

RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a

Timer1 clock input.

RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or Capture2

input/Compare2 output/PWM2 output.

RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/

PWM1 output.

RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchronous serial clock input/

output for both SPI and I2C modes.

RC4/SDI/SDA 23 25 42 I/O S T RC4 can also be the SPI Data In (SPI mode) or

data I/O (I2C mode).

RC5/SDO 24 26 43 I /O ST RC5 can also be the SPI Data Out

(SPI mode).

RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or

Synchronous Clock.

RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or

Synchronous Data.

PORTD is a bi-directional I/O port or parallel slave port

when interfacing to a microprocessor bus.

RD0/PSP0 19 21 38 I/O ST/TTL(3)

RD1/PSP1 20 22 39 I/O ST/TTL(3)

RD2/PSP2 21 23 40 I/O ST/TTL(3)

RD3/PSP3 22 24 41 I/O ST/TTL(3)

RD4/PSP4 27 30 2 I/O ST/TTL(3)

RD5/PSP5 28 31 3 I/O ST/TTL(3)

RD6/PSP6 29 32 4 I/O ST/TTL(3)

RD7/PSP7 30 33 5 I/O ST/TTL(3)

PORTE is a bi-directional I/O port.

RE0/RD/AN5(5) 8925I/OST/TTL

(3) RE0 can also be read control for the parallel slave port,

or analog input 5(5).

RE1/WR/AN6(5) 91026I/OST/TTL

(3) RE1 can also be write control for the p arallel slave port,

or analog input 6(5).

RE2/CS/AN7(5) 10 11 27 I/O ST/TTL(3) RE2 can also be select control for the parallel slave

port, or analog input 7(5).

VSS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins.

VDD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins.

NC — 1,17,28,

40 12,13,

33,34 — These pins are not internally connected. These pins should

be left unconnected.

TABLE 3-2: PIC16C65B/74B PINOUT DESCRIPTION (CONTINUED)

Pin Name DIP

Pin# PLCC

Pin#

TQFP

MQFP

Pin#

I/O/P

Type Buffer

Type Description

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel

Slave Port mode (for interfacing to a microprocesso r bus).

4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

5: A/D is not available on the PIC16C65B.

PIC16C63A/65B/73B/74B

DS30605D-page 14  1998-2013 Microchip Technology Inc.

3.1 Clocking Scheme/Instruction

Cycle

The clock input (from OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-

gram counter (PC) is incremented every Q1, the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The instruc-

tion is decoded and executed during the following Q1

through Q4. The clocks and instruction execution flow

is shown in Figure 3-2.

3.2 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 a nd Q4). The ins truc tio n fe tch and ex ecu te are

pipelined such that fetch takes one instruction cycle,

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO),

then tw o cycles are req uired to com plete the ins truction

(Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the ex ecution cycle , the fetched instruction i s latched

into the “Instruction Register" (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q 3 and Q4 c ycles. Dat a mem ory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal

phase

clock

Note: All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruc tion is

“flushed” from the pipeline, while the new instruction is being fetched and then executed.

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. CALL SUB_1 Fetch 3 Execute 3

4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush

5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1

 1998-2013 Microchip Technology Inc. DS30605D-page 15

PIC16C63A/65B/73B/74B

4.0 MEMORY ORGANIZATION

4.1 Program Memory Organization

The PIC16C63A/65B/73B/74B has a 13-bit program

counter capable of addressing an 8K x 14 program

memory space. All devices covered by this data sheet

have 4K x 14 bits of program memory. The address

range is 0000h - 0FFFh for all devices.

Accessing a location above 0FFFh will cause a wrap-

around.

The RESET ve ctor is at 0000h and the interrupt vector

is at 0004h.

FIGURE 4-1: PI C16C6 3A/6 5B/73B/74 B

PROGRAM MEMORY MAP

AND STACK

4.2 Data Memory Organization

The data memory is partitioned into multiple banks

which contain the General Purpose Registers (GPR)

and the Special Function Registers (SFR). Bits RP1

and RP0 are the bank select bits.

RP1:RP0 (STATUS<6:5>)

= 00  Bank0

= 01  Bank1

= 10  Bank2

= 11  Bank3

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the SFRs.

Above the SFRs are GPRs, implemented as static

RAM.

All implem en ted bank s con t ai n SFR s. Fre que ntly used

SFRs from one bank may be mirrored in another bank

for code reduction and quicker access.

4.2.1 GENERAL PURPOSE REGISTER

FILE

The registe r file can be accesse d eith er directly, or ind i-

rectly, through the File Select Register (FSR)

(Section 4.5).

PC<12:0>

0000h

0004h

0005h

07FFh

0800h

0FFFh

1000h

1FFFh

Stack Level 1

Stack Level 8

RESET Vector

Interrupt Vector

On-chip Prog ram

Memory (Page 1)

Memory (Page 0)

CALL,RETURN

RETFIE,RETLW

User Memory

Space

Note: Maintain the IRP and RP1 bits clear in

these devices.

PIC16C63A/65B/73B/74B

DS30605D-page 16  1998-2013 Microchip Technology Inc.

FIGURE 4-2: REGI S T ER FI LE M AP 4.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the

desired operation of the device. These registers are

implemented as static RAM.

The Special Function Registers can be classified into

two sets (core and peripheral). Those registers associ-

ated wi th the “co re” functi ons are descri bed in th is sec-

tion, and those related to the operation of the peripheral

features are described in the section of that peripheral

feature.

INDF(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PORTC

PORTD(2)

PORTE(2)

PCLATH

INTCON

PIR1

PIR2

TMR1L

TMR1H

T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA

TXREG

RCREG

CCPR2L

CCPR2H

CCP2CON

ADRES(3)

ADCON0(3)

INDF(1)

OPTION_REG

PCL

STATUS

FSR

TRISA

TRISB

TRISC

TRISD(2)

TRISE(2)

PCLATH

INTCON

PIE1

PIE2

PCON

PR2

SSPADD

SSPSTAT

TXSTA

SPBRG

ADCON1(3)

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h A0h

General

Purpose

General

Purpose

7Fh FFh

Bank 0 Bank 1

File

Address File

Address

nimplemented data memory locations, read as ’0’.

Note 1: Not a physical register.

2: These registers are not implemented on the

PIC16C63A/73B, read as '0'.

3: These registers are not implemented on the

PIC16C63A/65B, read as '0'.

 1998-2013 Microchip Technology Inc. DS30605D-page 17

PIC16C63A/65B/73B/74B

TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on

all other

RESETS(3)

Bank 0

00h INDF(4) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

02h PCL(4) Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

03h STATUS(4) IRP(2) RP1(2) RP0 TO PD ZDCC0001 1xxx 000q quuu

04h FSR(4) Indirect data memory address pointer xxxx xxxx uuuu uuuu

05h PORTA —— PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000

06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu

07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu

08h PORTD(5) PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu

09h PORTE(5) — — — — —RE2RE1RE0---- -xxx ---- -uuu

0Ah PCLATH(1,4) — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

0Bh INTCON(4) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(5) ADIF(6) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

0Dh PIR2 — — — – — — —CCP2IF---- ---0 ---- ---0

0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

11h TMR2 Timer2 module’s register 0000 0000 0000 0000

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

13h SSPBUF Synchrono us Se rial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu

16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu

17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x

19h TXREG USART Transmit D ata registe r 0000 0000 0000 0000

1Ah RCREG USART Receive Data register 0000 0000 0000 0000

1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu

1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu

1Dh CCP2CON —— CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

1Eh ADRES(6) A/D Result register xxxx xxxx uuuu uuuu

1Fh ADCON0(6) ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 0000 00-0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>.

2: The IRP and RP1 bits are reserved; always maintain these bits clear .

3: Other (non power-up) RESETS include external RESET through M C LR and Watchdog Timer Reset.

4: These registers can be addressed from either bank.

5: PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and

registers clear .

6: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear.

PIC16C63A/65B/73B/74B

DS30605D-page 18  1998-2013 Microchip Technology Inc.

Bank 1

80h INDF(4) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

82h PCL(4) Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

83h STATUS(4) IRP(2) RP1(2) RP0 TO PD ZDCC0001 1xxx 000q quuu

84h FSR(4) Indirect data memory address pointer xxxx xxxx uuuu uuuu

85h TRISA —— PORTA Data Direction Register --11 1111 --11 1111

86h TRISB PORTB Data Direction register 1111 1111 1111 1111

87h TRISC PORTC Data Direction register 1111 1111 1111 1111

88h TRISD(5) PORTD Data Direction register 1111 1111 1111 1111

89h TRISE(5) IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111

8Ah PCLATH(1,4) — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

8Bh INTCON(4) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

8Ch PIE1 PSPIE(5) ADIE(6) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0

8Eh PCON — — — — — —PORBOR ---- --qq ---- --uu

8Fh —Unimplemented — —

90h —Unimplemented — —

91h —Unimplemented — —

92h PR2 Timer2 Period register 1111 1111 1111 1111

93h SSPADD Synchronous Seria l Port (I2C mode) Address register 0000 0000 0000 0000

94h SSPSTAT ——D/A PSR/WUA BF --00 0000 --00 0000

95h —Unimplemented — —

96h —Unimplemented — —

97h —Unimplemented — —

98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator register 0000 0000 0000 0000

9Ah —Unimplemented — —

9Bh —Unimplemented — —

9Ch —Unimplemented — —

9Dh —Unimplemented — —

9Eh —Unimplemented — —

9Fh ADCON1(6) — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on

all other

RESETS(3)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>.

2: The IRP and RP1 bits are reserved; always maintain these bits clear .

3: Other (non power-up) RESETS include external RESET through M C LR and Watchdog Timer Reset.

4: These registers can be addressed from either bank.

5: PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and

registers clear .

6: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear.

 1998-2013 Microchip Technology Inc. DS30605D-page 19

PIC16C63A/65B/73B/74B

4.2.2.1 STATUS Register

The STATUS register, shown in Register 4-1, contains

the ar ithmetic st atus of th e ALU, the RESET st atus and

the bank select bits for data memory.

The STATUS register can be the destination for any

instru ction, as with a ny other r egister. If the STA TU S reg-

ister is the destination for an instruction that affects the Z,

DC or C bits, th en the write to the se three bit s is disabled.

These bits are set or cleared according to the device

logic. F u rt her mo r e, th e TO and PD bits are not writabl e.

Therefore, the result of an instruction with the STATUS

For example, CLRF STATUS will clear the upper three

bits and set t he Z bit. This leaves the STATUS register

as 000u u1uu (where u = unch ang ed).

It is recommended that only BCF, BSF, SWAPF and

MOVWF instructions be used to alter the STATUS regis-

ter. These instruct ion s do not af fect the Z, C or DC bits

in the STATUS register . For oth er inst ructions which d o

not affect status bits, see the "Instruction Set Sum-

mary."

Note 1: These devices do not use bits IRP and

RP1 (STATUS<7:6>), maintain these bits

clear t o e nsure upwa rd compatibility wi th

future products.

2: The C and DC b its operat e as borrow and

digit bo rrow bits, respectively, in subtrac-

tion. See the SUBLW and SUBWF instruc-

tions for examples.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP(1) RP1(1) RP0 TO PD ZDC C(2)

bit 7 bit 0

bit 7 IRP(1): Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

bit 6-5 RP1(1):RP0: Regi ster Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh)

10 = Bank 2 (100h - 17Fh)

01 = Bank 1 (80h - FFh)

00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes

bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instru ction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carry /borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instruct ions) (for borrow the po larity

is reversed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0 C(2): Carry/borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the most significant bit of the result occurred

0 = No carry-o ut from the most sig ni f icant bit of the result oc cur r ed

Note 1: Maintain the IRP and RP1 bits clear.

2: For borrow and digit borrow, the polarity is reversed. A subtraction is executed by

adding the tw o’s complement of the second opera nd . For rota te (RRF,RLF) instruc-

tions, this bit is loaded with either the high or low order bit of the source register.

Legend:

R = Readable bit W = Writable bit U = Unim plemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16C63A/65B/73B/74B

DS30605D-page 20  1998-2013 Microchip Technology Inc.

4.2.2.2 OPTION Register

The OPTION_REG register is a readable and writable

the TMR0/WDT prescaler, the external INT Interrupt,

TMR0 and the weak pull-ups on PORT B.

Note: To achieve a 1:1 prescaler assignment for

the TMR0 register, assign the prescaler to

the watchdog timer.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disa bled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin

0 = Interrupt on falling edge of RB0/INT pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin

0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS2:PS0: Presca ler Ra te Sele ct bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

 1998-2013 Microchip Technology Inc. DS30605D-page 21

PIC16C63A/65B/73B/74B

4.2.2.3 INTCON Register

The INTCON register is a readable and writable regis-

ter, which contains various enable and flag bits for the

TMR0 register ov erflow, RB Port change and external

RB0/INT pin interrupts.

Note: Interru pt fl ag bit s are set when an interru pt

conditi on occ urs , re gardless of the state of

its corresponding enable bit, or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

bit 7 bit 0

bit 7 GIE: Global Interrupt Enab le bit

1 = Enables all unmasked interrupts

0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5 T0IE: TMR0 Overf low Interr upt Enable bit

1 = Enables the TMR0 interru pt

0 = Disables the TMR0 interrupt

bit 4 INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/IN T ex terna l inte rrupt

0 = Disables the RB0/INT external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)

0 = TMR0 register did not overflow

bit 1 INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)

0 = The RB0/INT external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bi t

1 = At least one of the RB7:RB4 pins changed state(1)

0 = None of the RB7:RB4 pins have changed state

Note 1: A mismatch condition will exist until PORTB is read. After reading PORTB, the RBIF

flag bit can be cleared.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16C63A/65B/73B/74B

DS30605D-page 22  1998-2013 Microchip Technology Inc.

4.2.2.4 PIE1 Regi st er

This register contains the individual enable bits for the

peripheral interrupts.

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

bit 7 PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit

1 = Enables the PSP read/write interrupt

0 = Disables the PSP read/write interrupt

bit 6 ADIE(2): A/D Converter Interrupt Enab le bit

1 = Enables the A/D interrupt

0 = Disables the A/D interrupt

bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt

0 = Disables the USART receive interrupt

bit 4 TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt

0 = Disables the USART transmit interrupt

bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt

0 = Disables the SSP interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

Note 1: PIC16C63A/73B devices do not have a parallel slave port imple m ented; always

maintain this bit clear.

2: PIC16C63A/65B devices do not have an A/D implem ented; always maintain this bit

clear.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 1998-2013 Microchip Technology Inc. DS30605D-page 23

PIC16C63A/65B/73B/74B

4.2.2.5 PIR1 Register

This register contains the individual flag bits for the

peripheral interrupts.

Note: Interru pt fl ag bit s are set when an interru pt

conditi on occ urs , re gardless of the state of

its corresponding enable bit, or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

bit 7 PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit

1 = A read or a write operation has taken place (must be cleared in software)

0 = No read or write has occurred

bit 6 ADIF(2): A/D Converter Interrupt Flag bit

1 = An A/D conversion completed (must be cleared in software)

0 = The A/D conversion is not complete

bit 5 RCIF: USART Receive Interrupt Flag bit

1 = The USART receive buffer is full (clear by reading RCREG)

0 = The USART receive buffer is empty

bit 4 TXIF: USART Transmit Interrupt Flag bit

1 = The USART transmit buffer is empty (clear by writing to TXREG)

0 = The USART transmit buffer is full

bit 3 SSPIF: Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive

bit 2 CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register captur e occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mo de:

Unused in this mode

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)

0 = TMR1 register did not overflow

Note 1: PIC16C 63A/7 3B devi ces do not have a p arallel slav e port imple mented. T his b it loc a-

tion is reserved on these devices.

2: PIC16C63A/65B devices do not have an A/D implemented. This bit location is

reserved on these devices.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16C63A/65B/73B/74B

DS30605D-page 24  1998-2013 Microchip Technology Inc.

4.2.2.6 PIE2 Regi st er

This register contains the individual enable bit for the

CCP2 periph eral interru pt.

4.2.2.7 PIR2 Register

This regi ster contains the CCP2 interrupt flag bit.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — CCP2IE

bit 7 bit 0

bit 7-1 Unimplemented: Read as '0'

bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt

0 = Disables the CCP2 interrupt

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

Note: Interru pt fl ag bits are set whe n an in terru pt

conditi on occ urs , re gardless of the st a te of

its corresponding enable bit, or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — CCP2IF

bit 7 bit 0

bit 7-1 Unimplemented: Read as '0'

bit 0 CCP2IF: CCP2 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mo de:

Unused

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 1998-2013 Microchip Technology Inc. DS30605D-page 25

PIC16C63A/65B/73B/74B

4.2.2.8 PCON Register

The Power Control (PCON) register contains flag bits

to allow differentiation between a Power-on Reset

(POR), a Brown-out Reset (BOR), a Watchdog Reset

(WDT) and an external MCLR Reset.

Note: BOR is un known on P OR. It must be set by

the user and checked on subsequent

RESETS to see if BOR is cl ear, indic ating

a brown- out has occurred. T he BOR statu s

bit is a “don' t ca re” and is not predi ctable if

the brown-out circuit is disabled (by clear-

ing the BODEN bit in the configuration

word).

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q

— — — — — —PORBOR

bit 7 bit 0

bit 7-2 Unimplemented: Read as '0'

bit 1 POR: Power-on Reset Status bit

1 = No Power-on Reset occu rred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit

1 = No Brown-out Rese t occu rred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occu rs)

Legend:

R = Readable bit W = Writable bit U = Unim plemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16C63A/65B/73B/74B

DS30605D-page 26  1998-2013 Microchip Technology Inc.

4.3 PCL and PCLATH

The progra m counter (PC) is 13-bits wid e. The low byte

comes from the PCL register, which is a readable and

writable register. The upper bits (PC<12:8>) are not

readable, but are indirectly writable through the

PCLATH register. On any RESET, the upper bits of the

PC will b e clea red. Fig ure 4-3 sho ws the tw o sit uation s

for the l oading of th e PC. The up per ex ample in th e fig-

ure shows how the PC is loaded on a write to PCL

(PCLATH<4:0>  PCH). The lowe r ex am pl e i n th e fi g-

ure shows how the PC is loaded during a CALL or GOTO

instruction (PCLATH<4:3>  PCH).

FIGURE 4-3: LOADING OF PC IN

DIFFERENT SITUATIONS

4.3.1 COMPU TED GO TO

A comput ed GOTO is a ccom pli shed by adding an offset

to the program counter (ADDWF PCL). When doing a

table read using a computed GOTO method, care

should be ex ercise d if th e t able loca tion c rosse s a PCL

memory boundary (each 256 byte block). Refer to the

application note “Implementing a T able Read" (AN556).

4.3.2 STACK

The PIC16CXX family has an 8-level deep x 13-bit wide

hardware stack. The stack space is not part of either

program or data space and the stack pointer is not

readable or writ able. The PC i s PUSHed on to the st ack

when a CALL instruction is executed, or an interrupt

causes a bran ch . The st ac k is POPed in the ev en t of a

RETURN,RETLW or a RETFIE instruction execution.

PCLATH is not affected by a PUSH or POP operation.

The st ack operates as a circular buf fer . This means that

after the st ack h as be en PU SHed ei ght ti mes, th e nin th

push ov erwrit es the v alue tha t was stor ed fro m the first

push. The tenth push overw ri tes the second push (and

so on).

4.4 Program Memory Paging

PIC16CXX de vices are capable o f addressing a contin-

uous 8K word block of program memory . The CALL and

GOTO instructions provide only 11 bits of address to

allow branching within any 2K program memory page.

When ex ec utin g a CALL or GOTO ins truc tio n, t he upper

2 bits of the address are provided by PCLATH<4:3>.

When doi ng a CALL or GOTO inst r uct ion , th e us er m us t

ensure that the page select bits are programmed, so

that the de sired prog ram memory p age is a ddressed. If

a return from a CALL instruction (or interrupt) is exe-

cuted, the entire 13-bit PC is popped from the stack.

Therefore, manipulation of the PCLATH<4:3> bits are

not require d for the return instructions (whi ch POPs the

address from the stack).

Example 4-1 shows the calling of a subroutine in

page 1 of the prog ram memory. This e xample assu mes

that PCLATH is saved and restored by the Interrupt

Service Routi ne (if interrupts are used).

EXAMPLE 4-1: CALL OF A SUBROUTINE

IN PAGE 1 FROM PAGE 0

ORG 0x500

BSF PCLATH,3 ;Select page 1 (800h-FFFh)

CALL SUB1_P1 ;Call subroutine in

: ;page 1 (800h-FFFh)

ORG 0x900 ;page 1 (800h-FFFh)

SUB1_P1

: ;called subroutine

: ;page 1 (800h-FFFh)

RETURN ;return to Call subroutine

;in page 0 (000h-7FFh)

12 8 7 0

5PCLATH<4:0>

PCLATH

Instruction with

ALU

GOTO,CALL

Opcode < 10:0 >

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as

Destination

Note 1: There are no status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW, and RETFIE

instructions, or the vectoring to an inter-

rupt address.

Note 1: The contents of PCLATH are unchanged

after a return or RETFIE instruction is

executed. The user must set up PCLATH

for any subsequent CALL’s o r GOTO’s

2: PCLATH<4> is not used in these PIC®

devices. The use of PCLATH<4> as a

general purpose read/write bit is not rec-

ommended, since this may affect upward

compatibility with future products.

 1998-2013 Microchip Technology Inc. DS30605D-page 27

PIC16C63A/65B/73B/74B

4.5 Indirect Addressing, INDF and

FSR Registers

The INDF register is no t a physica l register. Addressin g

the INDF register will caus e indirect addressing.

Indirect addressing is poss ible by using the INDF reg-

ister. Any instruction using the INDF register actually

acces ses the register pointed to by the File Sele ct Reg-

ister, FSR. Reading the INDF register itself indirectly

(FSR = '0') will read 00h. Writing to the INDF register

indirec tly res ul t s in a no-operation (although status bits

may be affec ted). An ef fectiv e 9-bit add ress is o btaine d

by conc atenat ing the 8 -bit F SR regi ster and the IRP bit

(STATUS <7>), as shown in Fig ure 4-4.

A simple program to clear RAM locations 20h-2Fh

using indirect addressing is shown in Example 4-2.

EXAMPLE 4-2: INDIRECT ADDRESS ING

movlw 0x20 ;initialize pointer

movwf FSR ;to RAM

NEXT clrf INDF ;clear INDF register

incf FSR,F ;inc pointer

btfss FSR,4 ;all done?

goto NEXT ;no clear next

CONTINUE

: ;yes continue

FIGURE 4-4: DIRE CT/INDI RECT ADDRESS ING

Note: Maintain the IRP and RP1 bits clear.

Note 1: For register file map detail, see Figure 4-2.

2: Shaded portions are not implemented; maintain the IRP and RP1 bits clear.

Data

Memory

Indirect AddressingDirect Addressing

bank select location select

RP1:RP0 6 0

from opcode IRP FSR register

bank select location select

00 01 10 11

Bank 0 Bank 1 Bank 2 Bank 3

not used

FFh

80h

7Fh

00h

17Fh

100h

1FFh

180h

PIC16C63A/65B/73B/74B

DS30605D-page 28  1998-2013 Microchip Technology Inc.

NOTES:

 1998-2013 Microchip Technology Inc. DS30605D-page 29

PIC16C63A/65B/73B/74B

5.0 I/O PORTS

Some pins for these I/O ports are multiplex ed with an

alternate function for the peripheral features on the

device. In general, when a peripheral is enabled, that

pin may not be used as a general purpose I/O pin.

5.1 PORTA and TRISA Registers

PORTA is a 6-bit latch.

The RA4/T0CKI pin is a Schmitt Trigger input and an

open drain output. All other RA port pins have TTL

input lev els and ful l CMOS output drivers. All pi ns have

data direction bits (TRIS registers), which can config-

ure these pins as output or input.

Setting a TRISA register bit puts the corresponding out-

put dr iver in a hi-impe dance mo de. Clea ring a b it in th e

TRISA register puts the co ntents of the output latch on

the selected pin(s).

Reading the PORTA register reads the status of the

pins, where as wri tin g to i t wi ll write to th e port latch. All

write operations are read-modify-write operations.

Therefore , a write to a port implies that the port pins are

read, the value is modified and then written to the port

data l atch.

Pin RA4 is multiplexed with the Timer0 module clock

input to become the RA4/T0CKI pin.

On the PIC16C73B/74B, PORTA pins are multiplexed

with analog inputs and analog VREF input. The opera-

tion of each pin is selected by clearing/setting the con-

trol bits in the ADCON1 register (A/D Control

Register1).

The TRISA register controls the direction of the RA

pins, ev en w h en th ey are be ing us ed as ana log inputs.

The user mu st ensure the bit s in the TRISA regi ster are

maintained set when using them as analog inputs.

EXAMPLE 5-1: INITIALIZING PORTA

(PIC16C73B/74B)

BCF STATUS, RP0 ;

CLRF PORTA ; Initialize PORTA by

; clearing output

; data latches

BSF STATUS, RP0 ; Select Bank 1

MOVLW 0x06 ; Configure all pins

MOVWF ADCON1 ; as digital inputs

MOVLW 0xCF ; Value used to

; initialize data

; direction

MOVWF TRISA ; Set RA<3:0> as inputs

; RA<5:4> as outputs

; TRISA<7:6> are always

; read as '0'.

FIGURE 5-1: BLOCK DIAGRAM OF

RA3:RA0 AND RA5 PINS

FIGURE 5-2: BLOCK DIAGRAM OF

RA4/T0CKI PIN

Note: On all RESETS, pi ns with analog fun ctions

are con figured a s analog a nd digit al inputs .

Data

Bus

Port

TRIS

Data Latch

TRIS Latch

RD TRIS

RD Port

VSS

VDD

I/O pin(1)

Note 1: I/O pins have protection diodes to VDD and VSS.

Analog

Input

mode

TTL

Input

Buffer

To A/D Converter

Data

Bus

Port

TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

Schmitt

Trigger

Input

Buffer

VSS

I/O pi n

TMR0 Clock Input

(1)

Note 1: I/O pins have protection diodes to VDD and VSS.

PIC16C63A/65B/73B/74B

DS30605D-page 30  1998-2013 Microchip Technology Inc.

TABLE 5-1: PORTA FUNCTIONS

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit# Buffer Function

RA0/AN0(1) bit0 TTL Digital input/output or analog input.

RA1/AN1(1) bit1 TTL Digital input/output or analog input.

RA2/AN2(1) bit2 TTL Digital input/output or analog input.

RA3/AN3/VREF(1) bit3 TTL Digital input/output or analog input or VREF.

RA4/T0CKI bit4 ST Digital input/output or ex ternal clock input for Timer0.

Output is open drai n type.

RA5/SS/AN4(1) bit5 TTL Input/output or slave select input for synchronous serial port or analog input.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: The A/D is not implemented on the PIC16C63A/65B. Pins will operate as digital I/O only. ADCON1 is not

implemented; maintain this register clear.

Add r e s s Name Bi t 7 B it 6 Bit 5 Bit 4 Bit 3 B i t 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

RESETS

05h PORTA —— RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000

85h TRISA —— PORTA Data Direction Register --11 1111 --11 1111

9Fh ADCON1(1) — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.

Note 1: The A/D is not implemented on the PIC16C63A/65B. Pins will operate as digital I/O only. ADCON1 is not implemented;

maintain this register clear.

 1998-2013 Microchip Technology Inc. DS30605D-page 31

PIC16C63A/65B/73B/74B

5.2 PORTB and TRISB Registers

PORTB is an 8-bit wide, bi-directional port. The corre-

sponding data direction register is TRISB. Setting a bit

in the TRISB register puts the corresponding output

driver in a hi-impedance input mode. Clearing a bit in

the TRISB regi ster puts the c ontents of the output latc h

on the selected pin(s).

Each of th e POR TB pins has a we ak inte rnal pul l-up. A

single control bit can turn on all the pull-ups. This is per-

formed by clearing bit RBPU (OPTION_REG<7>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are dis-

abled on a Power-on Reset.

FIGURE 5-3: BLOCK DIAGRAM OF

RB3:RB0 PINS

Four of PORTB’s pins, RB7:RB4, have an

interrupt-on-change feature. Only pins configured as

inputs can cause this interrupt to occur (i.e., any

RB7:R B4 pin conf igu r ed as an outp ut is exclud ed fro m

the interrupt-on-change comparison). The input pin s (of

RB7:RB4) are compared with the value latched on the

last read of PORTB. The “mismatch” outputs of

RB7:RB4 are OR’d together to generate the RB Port

Change Interrupt with flag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The

user, in the Interrupt Service Routine, can clear the

interr upt in the foll owin g man ner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear flag bit RBIF.

A mism at c h c ond it i on wi ll cont i n ue to s et f lag bi t RB IF.

Reading PORTB will end the mismatch condition, and

allow flag bit RBIF to be cleared.

This interrupt-on-mismatch feature, together with soft-

ware configurable pull-ups on these four pins, allow

easy interface to a keypad and make it possible for

wake-up on key depression. Refer to the Embedded

Control Handbook, “Implementing Wake-up on Key

Stroke” (AN552).

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

RB0/IN T is an ext ernal i nterrupt input pin a nd is confi g-

ured using the INTEDG bit (OPTION_REG<6>).

RB0/INT is discussed in detail in Section 13.5.1.

FIGURE 5-4: BLOCK DIAGRAM OF

RB7:RB4 PINS

Data Latch

RBPU(2)

VDD

Data Bus

WR Port

WR TRIS

RD TRIS

RD Port

Weak

Pull-up

RD Port

RB0/INT

I/O pin(1)

TTL

Input

Buffer

Schmitt Trigger

Buffer

TRIS Latch

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS

bit(s) and clear the RBPU bit (OPTION_REG<7>).

Data Latch

From other

RBPU(2)

VDD

I/O pin (1)

Data Bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pi ns

Weak

Pull-up

RD Port

Latch

TTL

Input

Buffer ST

Buffer

RB7:RB6 in Serial Programming mode Q3

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the a ppropri ate TRIS

bit(s) and clear the RBPU bit (OPTION_REG<7>).

PIC16C63A/65B/73B/74B

DS30605D-page 32  1998-2013 Microchip Technology Inc.

TABLE 5-3: PORTB FUNCTIONS

TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit# Buffer Function

RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software

programmable weak pull-up.

RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.

RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.

RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.

RB4 bit4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak

pull-up.

RB5 bit5 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak

pull-up.

RB6 bit6 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak

pull-up. Serial programming clock.

RB7 bit7 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak

pull-up. Serial programming data.

Legend: TTL = TTL input, ST = Schmitt Tr igger input

Note 1: Th is buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a S chmit t Trigger input when used in Serial Programming mode.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

RESETS

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu

86h TRISB PORTB Data Dir ect ion register 1111 1111 1111 1111

81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

 1998-2013 Microchip Technology Inc. DS30605D-page 33

PIC16C63A/65B/73B/74B

5.3 PORTC and TRISC Registers

PORTC is an 8-bit bi-directional port. Each pin is indi-

vidually configurable as an input or output through the

TRISC register. PORTC is multiplexed with several

peripheral functions (Table 5-5). PORTC pins have

Schmitt Trigger input buffers.

When enabling peripheral functions, care should be

taken in defining TRIS bit s fo r each POR T C pi n. Som e

peripheral s override the TRIS bit to make a pin an ou t-

put, while other peripherals override the TRIS bit to

make a pin an input. Since the TRIS bit override is in

effect while the peripheral is enabled, read-modify-write

instr uctions (BSF, BCF, XORWF) with TRISC as des-

tination should be avoi ded. The user should refer to the

corresponding peripheral section for the correct TRIS

bit settings.

FIGURE 5-5: PORTC BLOCK DIAGRAM

TABLE 5-5: PORTC FUNCTIONS

TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

PORT/PERIPHERAL Select(2)

Data Bus

Port

TRIS

Data Latch

TRIS Latch

RD TRIS Schmitt

Trigger

Peripheral Data Out 0

VDD

VSS

Port

Peripheral

OE(3)

Peripheral Input

I/O p in (1)

Note 1: I/O pins have diode protection to VDD and VSS.

2: Port/Peripheral select signal selects between port

data and peripheral output.

3: Peripheral OE (output enable) is only activated if

peripheral select is active.

Name Bit# Buffer Type Function

RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input.

RC1/T1OSI/CCP2 bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/Compare2

output/PWM2 output.

RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output.

RC3/SCK/SCL bit3 ST RC3 can also be the Synchronous Serial Clock for both SPI and I2C modes.

RC4/SDI/SDA bit4 ST RC 4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode).

RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port Data output.

RC6/TX/CK bit6 ST Input/output port pin or USART Asynchronous Transmit, or USART

Synchronous Clock.

RC7/RX/DT bit7 ST Input/output port pin or USART Asynchronous Receive, or USART

Synchronous Data.

Legend: ST = Schmitt Trigger input

Addr e s s Na m e Bit 7 Bit 6 B i t 5 Bit 4 Bit 3 Bit 2 Bit 1 B it 0 Value on:

POR,

BOR

Value on

all other

RESETS

07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu

87h TRISC PORT C Data Direction register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged

PIC16C63A/65B/73B/74B

DS30605D-page 34  1998-2013 Microchip Technology Inc.

5.4 PORTD and TRISD Registers

PORTD is an 8-bit port with Schmitt Trigger input buff-

ers. Each pin is individually configured as an input or

output.

PORTD can be configured as an 8-bit wide micropro-

cessor port (parallel slave port) by setting control bit

PSPMODE (TRISE<4>). In this mod e, the input buffe rs

are TTL.

FIGURE 5-6: PORTD BLOCK DIAGRAM

TABLE 5-7: PORTD FUNCTIONS

TABLE 5-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Note: The PIC16C63A and PIC16C73B do not

provide PORTD. The PORTD and TRISD

registers are not implemented.

Data

Bus

Port

TRIS

RD Po rt

Data Latch

TRIS Latch

RD TRIS

Schmitt

Trigger

Input

Buffer

I/O pin(1)

Note 1: I/O pins have protection diodes to VDD and VSS.

Name Bit# Buffer Type Function

RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or par allel slave port bit0

RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or par allel slave port bit1

RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or par allel slave port bit2

RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or par allel slave port bit3

RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or par allel slave port bit4

RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or par allel slave port bit5

RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or par allel slave port bit6

RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or par allel slave port bit7

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port mode.

Addr e s s Na m e Bit 7 Bit 6 B i t 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

RESETS

08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu

88h TRISD PORTD Data Direction register 1111 1111 1111 1111

89h TRISE IBF OBF IBOV PSPMODE —PORTE Data Direction bits 0000 -111 0000 -111

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD.

 1998-2013 Microchip Technology Inc. DS30605D-page 35

PIC16C63A/65B/73B/74B

5.5 PORTE and TRISE Register

PORTE has three pins: RE0/RD/AN5, RE1/WR/AN6

and RE2/C S/ A N7, w hich are individually conf ig ured as

inputs or outputs. These pins have Schmitt Trigger

input buffers.

I/O PORTE becomes control inputs for the micropro-

cessor port when bit PSPMOD E (TRISE<4>) is set. In

this mode, the user must make sure that the

TRISE<2:0> bits are set (pins are configured as digital

input s) an d t hat reg ister ADCON1 is con figured for di g-

ital I/O. In this mode, the input buffers are TTL.

trols the parallel slave port operation.

PORTE pins may be multiplexed with analog inputs

(PIC16C74B only). The operation of these pins is

selected by control bits in the ADCON1 register. When

select ed as an anal og input, thes e pins will re ad as '0's.

TRISE controls the direction of the RE pins, even when

they are being used as analog inputs. The user must

make sure to keep the pins configured as inputs when

using them as analog inputs.

FIGURE 5-7: PORTE BLOCK DIAGRAM

TABLE 5-9: PORTE FUNCTIONS

Note 1: The PIC16C63A and PIC16C73B do not

prov ide PORTE. The PORTE and TRISE

registers are not implemented.

2: The PIC16 C63A/65B does not p rovide an

A/D module. A/D functions are not imple-

mented.

Note: On a Pow er-on Reset, these pins are con-

figured as analog inputs and read as ‘0’s.

Data

Bus

Port

TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

Schmitt

Trigger

Input

Buffer

I/O pin(1)

Note 1: I/O pins have protection diodes to VDD and VSS.

Name Bit# Buffer Ty pe Function

RE0/RD/AN5 bit0 ST/TTL(1) Input/output port pin or read control input in Parallel Slave Port mode or analog

input: RD

1 = Idle

0 = Read operation. Contents of PORTD register is output to PORTD

I/O pins (if chip selected).

RE1/WR/AN6 bit1 ST/TTL(1) Input/output port pin or write control input in Parallel Slave Port mode or analog

input: WR

1 = Idle

0 = Writ e operation. Value of PORTD I/O pins is latched into PORTD

RE2/CS/AN7 bit2 ST/TTL(1) Input/output port pin or chip select control input in Parallel Slave Port mode or

analog input:

1 = Device is not selected

0 = Device is selected

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.

PIC16C63A/65B/73B/74B

DS30605D-page 36  1998-2013 Microchip Technology Inc.

TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1

IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0

bit 7 bit 0

bit 7 IBF: Input Buffer Full Status bit

1 = A word has been received and is waiting to be read by the CPU

0 = No word has been received

bit 6 OBF: Output Buffer Full Status bit

1 = The output buffer still holds a pr eviously written word

0 = The output buffer has been read

bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)

1 = A write occurred when a previously input word has not been read (must be cleared in

software)

0 = No overflow occurred

bit 4 PSPMODE: Parallel Slave Port Mode Select bit

1 = Parallel Slave Port mode

0 = General purpose I/O mode

bit 3 Unimplemented: Read as '0'

bit 2 TRISE2: Direction Control bit for pin RE2/CS/AN7

1 = Input

0 = Output

bit 1 TRISE1: Direction Control bit for pin RE1/WR/AN6

1 = Input

0 = Output

bit 0 TRISE0: Direction Control bit for pin RE0/RD/AN5

1 = Input

0 = Output

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

RESETS

09h PORTE — — — — —RE2RE1RE0---- -xxx ---- -uuu

89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTE.

 1998-2013 Microchip Technology Inc. DS30605D-page 37

PIC16C63A/65B/73B/74B

5.6 Par allel Slave Port (PSP)

PORTD operates as an 8-bit wide Parallel Slave Port

(PSP), or microprocessor port when control bit PSP-

MODE (TRISE<4>) is set. In Slave mode, it is asyn-

chronously readable and writable by the external world,

through RD control input pin RE0/RD/AN5 and WR

control input pi n RE1/WR/AN6.

It can directl y int erface to an 8-bit mic rop roc es sor dat a

bus. The extern al mic roproc essor c an rea d or write th e

PORTD latch as an 8-bit latch. Setting bit PSPMODE

enables port pin RE0/RD/AN5 to be the RD input,

RE1/WR/AN6 to be the WR input and RE2/CS/AN7 to

be th e C S (chip select) input. For this functionality, the

corresponding data direction bits of the TRISE register

(TRISE<2:0>) must be configured as inputs (set) and

the A/D port configuration bits PCFG2:PCFG0

(ADCON1<2 :0>) must be set, w hich w i ll c on fig ure pins

RE2: RE0 as digital I/O.

There are actually two 8-bit latches, one for data out

(from the PIC® MCU) and one for data input. The user

writes 8-bit data to PORTD data latch and reads data

from the port pin latch (note that they have the same

address). In this mode, the TRISD register is ignored

since the external device is controlling the direction of

data flow.

A write to the PSP occ urs w hen both the CS and WR

lines are first detected low. When either the CS or WR

lines become high (level triggered), then the Input

Buffer Full (IBF) status flag bit (TRISE<7>) is set on the

Q4 clock cycle, following the next Q2 cycle, to signal

the write is compl ete (Fi gure 5-9 ). The in terru pt flag bit

PSPIF (PIR1<7>) is also set on the same Q4 clock

cycl e. IBF can o nly be cl eared by readi ng the PORTD

input latch. The Input Buffer Overflow (IBOV) status

flag bit (TRISE<5>) is set if a second write to the PSP

is attem pted when the previou s byte has no t been read

out of the buffer.

A read from t he PSP occurs when both the CS and RD

lines are first detected low. The Output Buffer Full

(OBF) status flag bit (TRISE<6>) is cleared immedi-

ately (Figure 5-10), indicating that the PORTD latch is

waitin g to be read by the ext ernal bus. Whe n eithe r the

CS or RD pin be co me s hi gh ( lev el trigg ere d), the inter-

rupt flag bit PSPIF is set on the Q4 clock cycle, follow-

ing the next Q2 cycle, indicating that the read is

complete. OBF remains low until data is written to

PORTD by the user firmware.

When not in PSP mode, the IBF and OBF b its are held

clear. However, if flag bit IBOV was previously set, it

must be cleared in firmware.

An interrupt is generated and latched into flag bit

PSPIF when a read or write operation is completed.

PSPIF must be cleared by the us er in fi rmware and th e

interrupt can be disabled by clearing the interrupt

enable bit PSPIE (PIE1<7>).

FIGURE 5-8: PORTD AND PORTE

BLOCK DIAGRAM

(PARALLEL SLAVE

PORT)

Note: The PIC16C63A and PIC16C73B do not

provi de a para llel slav e por t. T he PO RTD,

PORTE, TRISD and TRISE registers are

not implem ented.

Data Bus

Port

RDx

Port

One bit of PORTD

Set Interrupt Flag

PSPI F (PIR1<7>)

Read

Chip Select

Write

TTL

Note 1: I/O pins have protection diodes to VDD and VSS.

PIC16C63A/65B/73B/74B

DS30605D-page 38  1998-2013 Microchip Technology Inc.

FIGURE 5-9: PARALLEL SLAVE PORT WRITE WAVEFORMS

FIGURE 5-10: PARALLEL SLAVE PORT READ WAV EFORMS

TABLE 5-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

IBF

OBF

PSPIF

PORTD<7:0>

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

IBF

PSPIF

OBF

PORTD<7:0>

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

RESETS

08h PORTD Port data lat ch when written, Port pins when read xxxx xxxx uuuu uuuu

09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu

0Bh, 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111

0Ch PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend: x = unknown, u = unchanged, - = unim plement ed, read as '0'. Shaded cells are not used by the Parallel Slave Port.

 1998-2013 Microchip Technology Inc. DS30605D-page 39

PIC16C63A/65B/73B/74B

6.0 TIMER0 MODULE

The T imer0 modul e timer/counter has the following fea-

tures:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock

Figure 6- 1 is a block diagram of th e Ti mer0 module and

the prescaler shared with the WDT.

Additional information on the Timer0 module is

available in the PIC® Mid-Range MCU Family Refer-

ence Manual (DS33023).

Timer mode is selected by clearing bit T0CS

(OPTION_REG<5>). In Timer mode, the Timer0

module will increment every instruction cycle (without

prescaler). If the TMR0 register is written, the incre-

ment is inhibited for the following two instruction c ycles.

The user can work around this by writing an adjusted

value to the TMR0 register.

Counter mode is selected by setting bit T0CS

(OPTION_REG<5>). In counter mode, Timer0 will

inc remen t, e ith er on ev ery r isin g, o r fal lin g ed ge of pin

RA4/T0CKI. The incrementing edge is determined by

the Timer0 Source Edge Select bit T0SE

(OPTION_REG<4>). Clearing bit T0 SE selects the ris-

ing edge. Restrictions on the external clock input are

discussed in detail in Section 6.2.

The prescaler is mutually exclusively shared between

the Timer0 module and the watchdog timer. The

prescaler is not readable or writable. Section 6.3

details the operation of the prescaler.

6.1 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister overflows from FFh to 00h. This overflow sets bit

T0IF (INTCON<2>). The interrupt can be masked by

clearing bit T0IE (INTCON<5>). Bit T0IF must be

cleared in softw are by the T imer0 mo dule Interrupt Ser-

vice Routine before re-enabling this interrupt. The

TMR0 interrupt cannot awaken the processor from

SLEEP, since the timer is shut-off during SLEEP.

FIGURE 6-1: BLOCK DIAGRAM OF THE T IMER0/WDT PRESCALER

RA4/T0CKI

T0SE

CLKOUT (= FOSC/4)

SYNC

Cycles TMR 0 re g

8-bit Prescaler

8 - to - 1MUX

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).

PSA

WDT Enable bit

Data Bus

Set Flag bi t T0 IF

on Overflow

PSA

T0CS

PRESCALER

PIC16C63A/65B/73B/74B

DS30605D-page 40  1998-2013 Microchip Technology Inc.

6.2 Using Timer0 with an External

Clock

The synchronization of T0CKI with the internal phase

clocks is accomplished by sampling the synchronized

input on the Q2 and Q4 cycles of the internal phase

clocks. Therefore, it is necessary for T0CKI to be high

for at least 2 TOSC (and a small RC delay of 20 ns) and

low for a t least 2 TOSC (and a small RC delay of 20 ns).

Refer to the electrical specification for the desired

device.

6.3 Prescaler

There is only one prescal er av ai lable which is mutually

exclus ively shar ed between th e T imer0 mod ule and the

watch dog tim er. A prescal er ass ignme nt for the Timer0

module means that there is no p rescaler fo r the W atch-

dog Timer, and vice-versa. This prescaler is not read-

able or writable (see Figure 6-1).

The PSA and PS2:PS0 bits (OPTION_REG<3:0>)

determine the prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

wri ting to th e TMR0 re gister (e.g., CLRF 1, MOVWF 1,

BSF 1,x....etc.) will clear the prescal er . When assigned

to WDT, a CLRWDT instruction will clear the prescaler

along with the Watchdog Timer. The prescaler is not

readable or writable.

Note: Writing to TMR0, when the prescaler is

assign ed to T imer0 , will clear th e prescaler

count, but will not change the prescaler

assignment.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 RBPU

bit 6 INTEDG

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

Note: To avoid an unintended device RESET, the instructio n sequence shown in the PIC® Mid-Range MCU Family

Reference Manual (DS33023, Section 11.6) must be executed when changing the prescaler assignment

from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.

 1998-2013 Microchip Technology Inc. DS30605D-page 41

PIC16C63A/65B/73B/74B

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

RESETS

01h TMR0 Timer0 Module’s register xxxx xxxx uuuu uuuu

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer 0.

PIC16C63A/65B/73B/74B

DS30605D-page 42  1998-2013 Microchip Technology Inc.

NOTES:

 1998-2013 Microchip Technology Inc. DS30605D-page 43

PIC16C63A/65B/73B/74B

7.0 TIMER1 MODULE

The Timer1 module is a 16 -bi t tim er/c ou nter cons is tin g

of two 8-bit registers (TMR1H and TMR1L), which are

readable and writable. The TMR1 Register pair

(TMR1H:TMR1L) increments from 0000h to FFFFh

and roll s over to 0000h. The TMR1 Interrupt, if enabled,

is generated on overflow, which is latched in interrupt

flag bit TMR1IF (PIR1<0>). This interrupt can be

enabled/disabled by setting/clearing TMR1 interrupt

enable bit TMR1 IE (PIE1<0> ).

Timer1 can operate in one of two modes:

•As a timer

•As a counter

The operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>).

In Timer mode, Timer1 increments every instruction

cycle. In Counter mode, it increments on every rising

edge of the external clock input.

Timer1 can be enabled/disabled by setting/clearing

control bit TMR 1 ON (T1CO N<0>).

Timer1 also has an internal “RESET input”. This

RESET can be generated by either of the two CCP

modules (Section 9.0) using the special event trigger.

When the Timer1 oscillator is enabled (T1OSCEN is

set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI

pins become inputs. That is, the TRISC<1:0> value is

ignored, and these pins read as ‘0’.

Additional information on timer modules is available in

the PIC® Mid-range MCU Family Reference Manual

(DS33023).

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 bit 0

bit 7-6 Unimplemented: Read as '0 '

bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11 = 1:8 Presca le val ue

10 = 1:4 Presca le val ue

01 = 1:2 Presca le val ue

00 = 1:1 Presca le val ue

bit 3 T1OSCEN: Ti mer1 Oscillator Enable Control bit

1 = Oscillator is enabled

0 = Oscillator is shut-off (The oscillator inverter is turned off to eliminate power drain)

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1:

1 = Do not synchronize external clock input

0 = Synchronize extern al clock input

TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1 TMR1CS: Timer1 Clock Source Select bit

1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)

0 = Internal clock (F OSC/4)

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 = Stops Timer1

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16C63A/65B/73B/74B

DS30605D-page 44  1998-2013 Microchip Technology Inc.

7.1 Timer1 Operation in Timer Mode

Timer mode is selected by clearing the TMR1CS

(T1CON<1>) bit. In this mode, the input clock to the

timer is FOSC/4. The synchronize control bit T1SYNC

(T1CON<2>) has no effect since the internal clock is

always in sync.

7.2 T imer1 Operation i n Synchronized

Counter Mode

Counter mode is selected by setting bit TMR1CS. In

this mode, the timer increments on every rising edge of

clock input on pin RC1/T1OSI/CCP2, when bit

T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when

bit T1OSCEN is cleared.

If T1SYNC is cleared, then the external clock input is

synchronized with internal phase clocks. The synchro-

nization is done after the prescaler stage. The

prescaler stage is an asynchronous ripple counter.

In this configuration during SLEEP mode, Timer1 will

not increment even if the external clock is present,

since the synchronization circuit is shut-off. The

prescaler, however, will continue to increment.

FIGURE 7-1: TIMER1 BLOCK DIAGRAM

TMR1H TMR1L

T1OSC T1SYNC

TMR1CS

T1CKPS1:T1CKPS0 SLEEP Input

T1OSCEN

Enable

Oscillator(1)

FOSC/4

Internal

Clock

TMR1ON

On/Off

Prescaler

1, 2, 4, 8 Synchronize

det

Synchronized

Clock Input

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2(2)

Note 1: When the T1OSCEN bit is cleared, the inverter is turned off . This eliminates power drain.

2: For the PIC16C65B/73B/74B, the Schmitt Trigger is not implemented in External Clock mode.

Set Flag bit

TMR1IF on

Overflow TMR1

(2)

 1998-2013 Microchip Technology Inc. DS30605D-page 45

PIC16C63A/65B/73B/74B

7.3 Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYN C (T1CON<2>) is set, the external

clock input is not synchron ized. The timer continues to

increment asynchronous to the internal phase clocks.

The timer will continue to run during SLEEP and can

generate an interrupt-on-overflow, which will wake-up

the processor. However, special precautions in soft-

ware are needed to read/write the timer (Section 7.3.1).

In Asynchronous Counter mode, Timer1 can not be

used as a time-base for capture or compare opera-

tions.

7.3.1 READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will guarantee a

valid read (taken care of in hardware). However, the

user shoul d keep i n mind that r eadi ng the 16-bit time r

in two 8-bit values itself poses certain problems, since

the timer may overflow between the reads.

For write s, it is re comm ended that the us er simply stop

the timer and write the desired values. A write conten-

tion may occur by writing to the timer registers, while

the register is incrementing. This may produce an

unpredictable v alue in the timer register.

Reading the 16-bit value requires some care. Exam-

ples 12-2 and 12-3 in the PIC® Mi d-Range MCU Family

Reference Manual (DS33023) show how to read and

write Timer1 when i t is runni ng in Async hronou s mod e.

7.4 Timer1 Oscillator

A crystal oscillator circuit is built-in between pins T1OSI

(input) and T1OSO (amplifier output). It is enabled by

setting control b it T1OSCEN (T1CON<3>). The o scilla-

tor is a low power oscillator rated up to 200 kHz. It will

continue to run during SLEEP. It is primarily intended

for use with a 32 kHz crystal. Table 7-1 shows the

capacitor selection for the Timer1 oscillator.

The Timer1 oscillator is identical to the LP oscillator.

The user m us t prov id e a so ftware time delay to en su re

proper oscillator start-up.

T ABLE 7-1: CAP ACITOR SELECTION FOR

THE TIMER1 OSCILLATOR

7.5 Resetting Timer1 using a CCP

Trigger Output

If the CCP 1 or CCP2 mo dule is config ured in C omp are

mode to generate a “special event trigger”

(CCP1M3:CCP1M0 = 1011), this signal will reset

Timer1.

Timer1 must be configured for either timer or Synchro-

nized Counter mode to take advantage of this feature.

If Timer1 is running in Asynchronous Counter mode,

this RESET operation may not work.

In the even t that a write to T imer1 coi ncides with a spe-

cial event trigger from CCP1 or CCP2, the write will

take precedence.

In this mode of ope ration, the CCPRxH: CCPRx L regis -

ter pair effectively becomes the period register for

Timer1.

7.6 Resetting of Timer1 Register Pair

(TMR1H, TMR1L)

TMR1H an d TMR1 L regist ers are not reset to 00h on a

POR, or any other RESET, except by the CCP1 and

CCP2 spe cial ev ent trig gers .

T1CON register is reset to 00h on a Power-on Reset or a

Brown-out Reset, which shuts off the ti mer and leaves a

1:1 pre scale. In all other resets, the regist er is unaffected.

7.7 Timer1 Prescaler

The prescaler counter is cleared on writes to the

TMR1H or TMR1L registers.

Osc Type Freq C1 C2

LP 32 kHz 33 pF 33 pF

100 k Hz 15 pF 15 pF

200 k Hz 15 pF 15 pF

These values are for design guidance only.

Crystals Tested:

32.768 kHz Eps on C-001R32. 768K- A ± 20 PP M

100 kHz Epson C-2 100.00 KC-P ± 20 PPM

200 kHz STD XTL 200.000 kHz ± 20 PPM

Note 1: Higher capacitance increases the stability

of oscil lator, but also inc reases th e start-u p

time.

2: Since each resonat or/crystal has its own

charact eristics , the user sho uld cons ult the

resonator/crystal manufacturer for appro-

priate values of external components.

Note: The special event triggers from the CCP1

and CCP2 modules will not set interrupt

flag bit TMR1IF (PIR1<0>).

PIC16C63A/65B/73B/74B

DS30605D-page 46  1998-2013 Microchip Technology Inc.

TABLE 7-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Va lue o n

all other

RESETS

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.

2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.

 1998-2013 Microchip Technology Inc. DS30605D-page 47

PIC16C63A/65B/73B/74B

8.0 TIMER2 MODULE

Timer2 is an 8-bit timer with a prescaler and a

postscaler. It can be used as the PWM time-base for

the PWM mo de of the CCP m od ule (s). The T MR2 re g-

ister is readable and writable, and is cleared on any

device RESET.

The input clock (FOSC/4) has a prescale option of 1:1,

1:4, or 1:16, selected by control bits

T2CKPS1:T2CKPS0 (T2CON<1: 0>).

The Timer2 module has an 8-bit period register, PR2.

Timer2 increments from 00h until it matches PR2 and

then resets to 00h on the next increment cycle. PR2 is

a readable and writable register. The PR2 register is

initiali zed to FFh upon RESET.

The match output of TMR2 goes through a 4-bit

postscaler (which gives a 1:1 to 1:16 scaling inclusive)

to generate a TMR2 interrupt (latched in flag bit

TMR2IF, (PIR1<1>)).

Timer2 can b e s hu t-off by cl ea ring c ont rol bit TMR2ON

(T2CON<2>) to minimize power consumption.

Additional information on timer modules is available in

the PIC® Mid-Range MCU Family Reference Manual

(DS33023).

8.1 Timer2 Prescaler and Postscaler

The prescaler and postscaler counters are cleared

when any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register

• any device RESET (POR, BOR, MCLR Reset, or

WDT Reset)

TMR2 is not cleared when T2CON is written.

8.2 Output of TMR2

The output of TMR2 (before the post scaler) is fed to the

SSP module, which optionally uses it to generate the

shift clock.

FIGURE 8-1: TIMER2 BLOCK DIAGRAM

Comparator

TMR2

Sets Flag

TMR2 reg

Output(1)

RESET

Postscaler

Prescaler

PR2 reg

FOSC/4

1:1 1:16

1:1, 1:4, 1:16

bit TMR2IF

Note 1:TMR2 register output can be software selected by the

SSP module as a baud clock.

T2OUTPS3:

T2OUTPS0

T2CKPS1:

T2CKPS0

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 bit 0

bit 7 Unimplemented: Read as '0'

bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

0000 = 1:1 Postscale

0001 = 1:2 Postscale

0010 = 1:3 Postscale

•

1111 = 1:16 Postscale

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00 = Prescaler is 1

01 = Prescaler is 4

1x = Prescaler is 16

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16C63A/65B/73B/74B

DS30605D-page 48  1998-2013 Microchip Technology Inc.

TABLE 8-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

RESETS

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF(2)RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

8Ch PIE1 PSPIE(1) ADIE(2)RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

11h TMR2 Timer2 Module’s registe r 0000 0000 0000 0000

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

92h PR2 Timer2 Peri o d regist er 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.

2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.

 1998-2013 Microchip Technology Inc. DS30605D-page 49

PIC16C63A/65B/73B/74B

9.0 CAPTURE/COMPARE/PWM

MODULES

Each Capture/Compare/PWM (CCP) module contains

a 16-bit register which can operate as a:

• 16-bit Capture register

• 16-bit Compare register

• PWM Master/Slave Duty Cycle register

Both the CCP1 and CCP2 modules are identical in

operatio n, with th e except ion being the operati on of the

specia l event trigger. Table 9-1 and Table 9-2 show the

resources and interactions of the CCP module(s). In

the following sections, the operation of a CCP module

is describe d with respec t to CCP1. CCP2 opera tes the

same as CCP1, except where noted.

CCP1 Module:

Capture/Compare/PWM Register1 (CCPR1) is com-

prised of two 8-bit registers: CCPR1L (low byte) and

CCPR1H (high byte). The CCP1CON register controls

the operation of CCP1. The special event trigger is

generated by a compare match and will reset Timer1.

CCP2 Module:

Capture/Compare/PWM Register2 (CCPR2) is com-

prised of two 8-bit registers: CCPR2L (low byte) and

CCPR2H (high byte). The CCP2CON register controls

the operation of CCP2. The special event trigger is

generated by a compare match and will reset Timer1

and start an A/D conversion (if the A/D module is

enabled).

Additional information on CCP modules is available in

the PIC® Mid-Range MCU Family Reference Manual

(DS33023) and in “Using the CCP Modules” (AN594).

TABLE 9-1: CCP MODE - TIMER

RESOURCES REQUIR ED

TABLE 9-2: INTERACTION OF TWO CCP MODULES

CCP Mode Timer Resource

Capture

Compare

PWM

Timer1

Timer2

CCPx Mode CCPy Mode Interaction

Capture Capture Same TMR1 time-base.

Capture Compare The compare should be configured for the special event trigger, which clears TMR1.

Compare Compare The compare(s) should be configured for the special event trigger, which clears TMR1.

PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt).

PWM Capture None.

PWM Compare None.

PIC16C63A/65B/73B/74B

DS30605D-page 50  1998-2013 Microchip Technology Inc.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0

bit 7 bit 0

bit 7-6 Unimplemented: Read as '0'

bit 5-4 CCPxX:CCPxY: PWM Least Significant bits

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.

bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits

0000 = Capture/Compare/PWM disabled (resets CCPx module)

0100 = Capture mode, every falling edge

0101 = Capture mode, every rising edge

0110 = Capture mode, every 4th rising edge

0111 = Capture mode, every 16th rising edge

1000 = Compare mode, set output on match (CCPxIF bit is set)

1001 = Compare mode, clear output on match (CCPxIF bit is set)

1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is

unaffected)

1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected);

CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module

is enabled)

11xx =PWM mode

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 1998-2013 Microchip Technology Inc. DS30605D-page 51

PIC16C63A/65B/73B/74B

9.1 Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the

16-bit value of the TMR1 r egister wh en an eve nt occurs

on pin RC2/CCP1. An event is defined as one of the fol-

lowing and is configured using CCPxCON<3:0>:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

An event is selected by control bits CCP1M3:CCP1M0

(CCP1CON<3:0>). When a capture is made, the inter-

rupt request flag bit CCP1IF (PIR1<2>) is set. The

interrupt flag must be cleared in software. If another

capture occurs before the value in register CCPR1 is

read, the previous captured value is overwritten by the

new captured value.

9.1.1 CCP PIN CONFIGURATION

In Capt ure m od e, th e R C2/CCP1 pin should be confi g-

ured as an input by setting the TRISC<2> bit.

FIGURE 9-1: CAPTURE MODE

OPERATION BLOCK

DIAGRAM

9.1.2 TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode for the CCP module to use the

capture feature. In Asynchronous Counter mode, the

capture operation may not work.

9.1.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCP1IE (PIE1<2>) clear to avoid false interrupts and

should clear the flag bit CCP1IF following any such

change in ope rati ng mod e.

9.1.4 CCP PRESCALER

There are four prescaler settings, specified by bits

CCP1M3:CCP1M0. Whenever the CCP module is

turned off, or the CCP module is not in Capture mode,

the prescaler counter is cleared. Any RESET will clear

the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleare d, therefore , the first cap ture may be from

a non-zero prescaler. Example 9-1 shows the recom-

mended method for switching between capture pres-

calers. This example also clears the prescaler counter

and will not generate the “false” interrupt.

EXAMPLE 9-1: CHANGING BETWEEN

CAPTURE PRESCALERS

CLRF CCP1CON ; Turn CCP module off

MOVLW NEW_CAPT_PS ; Load the W reg with

; the new prescaler

; move value and CCP ON

MOVWF CCP1CON ; Load CCP1CON with this

; value

Note: If the RC2/CCP1 pin is configured as an

output, a write to the port can cause a

capture co ndition.

CCPR1H CCPR1L

TMR1H TMR1L

Set Flag bit CCP1IF

(PIR1<2>)

Capture

Enable

Q’s CCP1CON<3:0>

RC2/CCP1

Prescaler

 1, 4, 16

and

Edge Detect

PIC16C63A/65B/73B/74B

DS30605D-page 52  1998-2013 Microchip Technology Inc.

9.2 Compare Mode

In C ompare mo de, t he 16 -bit CC PR1 r egist er va lue is

constantly compared against the TMR1 register pair

value. Whe n a match occu rs, the RC2/CC P1 pin is:

• Driven high

•Driven low

• Remains unchanged

The action on the pin is based on the value of control

bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the

same time, interrupt flag bit CCP1IF is set.

FIGURE 9-2: COMPARE MODE

OPERATION BLOCK

DIAGRAM

9.2.1 CCP PIN CONFIGURATION

The user must configure the RC2/CCP1 pin as an out-

put by clearing the TRISC<2> bit.

9.2.2 TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

9.2.3 SOFTWARE INTERRUPT MODE

When Generate Sof tware Interrupt mode is cho sen, the

CCP1 pin is not affected. The CCPIF bit is set, causing

a CCP interrupt (if enabled).

9.2.4 SPECIAL EVENT TRIGGER

In this mod e, an internal hardware trigger is gene rated,

which may be used to initiate an action.

The special event trigger output of CCP1 resets the

TMR1 regi ste r pai r. This allo ws the C CPR 1 re gis ter t o

ef fectively b e a 16-bit progra mmable pe riod registe r for

Timer1.

The special event trigger output of CCP2 resets the

TMR1 re gist e r p ai r and starts an A/D conversion (if the

A/D module is enabled).

9.3 PWM Mode (PWM)

In Pulse Width Modulation mode, the CCPx pin pro-

duces up to a 10-bit resolu tion PWM output. Since the

CCP1 pin is multiplexed with the PORTC data latch, the

TRISC<2> bit must be cleared to make the CCP1 pin

an output.

Figure 9-3 shows a simplified block diagram of the

CCP module in PWM mode.

For a ste p-by-step proc edure on how to set up the CC P

module for PWM operation, see Section 9.3.3.

FIGURE 9-3: SIMPLIFIED PWM BLOCK

DIAGRAM

Note: Clearing the CCP1CON register will force

the RC2/CCP1 co mpare outp ut latch to the

default low level. This is not the PORTC

I/O data latch.

CCPR1H CCPR1L

TMR1H TMR1L

Comparator

Output

Logic

Special Event Trigger

Set Flag bit CCP1IF

(PIR1<2>)

Match

RC2/CCP1

TRISC<2>

CCP1CON<3:0>

Mode Select

Output Enable

Special event trigger will:

reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),

and set bit GO/DONE (ADCON0<2>).

Note: The special event trigger from the

CCP1a nd CCP2 modul es w ill not set int er-

rupt flag bit TMR1IF (PIR1<0>).

Note: Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default

low level. This is not the PORTC I/O data

latch.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

Duty Cycle Registers CCP1CON<5:4>

Clear Tim er,

CCP1 pin and

latch D.C.

TRISC<2>

RC2/CCP1

Note 1: 8-bit timer is concatenated with 2-bit internal Q clock,

or 2 bits of the prescale, to create 10-bit time-base.

 1998-2013 Microchip Technology Inc. DS30605D-page 53

PIC16C63A/65B/73B/74B

A PWM output (Figure 9-4) has a time-base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(1/period).

FIGURE 9-4: PW M OUTPUT

9.3.1 PWM PERIOD

The PWM period is specified by writing to the PR2

following formula:

PWM period = [(PR2) + 1] • 4 • TOSC •

(TMR2 prescale value)

PWM frequency is defined as 1 / [PWM period].

When TM R2 is equa l to PR2, t he followi ng three ev ents

occur on the next increment cycle:

• TMR2 is cl eare d

• The CCP1 pin is set (exception: if PWM duty

cycl e = 0%, the CCP1 pin will not be set)

• The PWM dut y cycl e is latched from CCPR1L i nto

CCPR1H

9.3.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available: the CCPR1L contains

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The following equation is

used to calculate the PWM duty cycle in time:

PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •

TOSC • (TMR2 prescale value)

CCPR1L and CCP1CON<5:4> can be written to a t any

time, but the duty cycle value is not latched into

CCPR1H until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are

used to dou ble buf fer th e PWM duty cycle. Thi s doubl e

buffering is essential for glitchless PWM operati on.

When t he CCP R1H an d 2-bit latch match T MR2, con-

catenate d with an in terna l 2-b it Q clock , or 2 bits of the

TMR2 prescaler, the CCP1 pin is clear ed.

Maximum PWM resolution (bits) for a given PWM

frequency:

9.3.3 SET-UP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Set the PWM period by writing to the PR2 register .

2. Set the PWM duty cycle by writing to the

CCPR1L register and CCP1CON<5:4> bits.

3. Make the CCP1 pin an output by clearing the

TRISC<2> bit.

4. Set the TMR2 prescale value and enable T imer2

by writing to T2CON.

5. Configure the CCP1 module for PWM opera tion.

TABLE 9-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz

Note: The Timer2 post s cal er (see Se cti on 8.1) i s

not used in the determination of the PWM

frequenc y . T he posts caler could b e used to

have a servo update rate at a different fre-

quency than the PWM output.

Period

Duty Cycle

TMR2 = P R 2

TMR2 = Duty Cycle

TMR2 = PR2(Timer2 RESET)

(Timer2 RESET)

Note: If the PWM duty cycle value is longer than

the PWM period, the CCP1 pin will not be

cleared.

log(FPWM

log(2)

FOSC )

bits

Resolution

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescaler (1, 4, 16) 16 4 1 1 1 1

PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum Resolution (bi ts) 10 10 10 8 7 5.5

PIC16C63A/65B/73B/74B

DS30605D-page 54  1998-2013 Microchip Technology Inc.

TABLE 9-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

TABLE 9-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

RESETS

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0

8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0

87h TRISC PORTC Data Direction register 1111 1111 1111 1111

0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu

16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu

17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

1Bh CCPR2L Capture/Compare/PWM register2 (LSB) xxxx xxxx uuuu uuuu

1Ch CCPR2H Capture/Compare/PWM register2 (MSB) xxxx xxxx uuuu uuuu

1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.

Note 1: The PSP is not implemented on the PIC16C63A/73B; always maintain these bits clear.

2: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits clear.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

RESETS

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0

8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0

87h TRISC PORTC Data Direction register 1111 1111 1111 1111

11h TMR2 Timer2 Module’s register 0000 0000 0000 0000

92h PR2 Timer2 Module’s Period register 1111 1111 1111 1111

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

15h CCPR1 L Captur e/Co mpar e/P WM reg i ster 1 (LSB ) xxxx xxxx uuuu uuuu

16h CCPR1 H Captur e/C o mpar e/PW M reg ister 1 (MS B) xxxx xxxx uuuu uuuu

17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

1Bh CCPR2L Capture/C o mpar e/PW M reg ister 2 (LS B) xxxx xxxx uuuu uuuu

1Ch CCPR2H Captur e/Compare/PWM reg i ster 2 (MSB ) xxxx xxxx uuuu uuuu

1Dh CCP2CON —— CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.

2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.

 1998-2013 Microchip Technology Inc. DS30605D-page 55

PIC16C63A/65B/73B/74B

10.0 SYNCHRONOUS SERIAL PORT

(SSP) MODULE

10.1 SSP Module Overview

The Synchronous Serial Port (SSP) module is a serial

interface useful for communicating with other periph-

eral or microcontroller devices. These peripheral

devices may be Serial EEPROMs, shift registers, dis-

play d riv ers, A/D converters, et c. The SSP module can

operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I2C)

An overview of I2C operations and additional informa-

tion on the SSP module can be found in the PIC®

Mid-Range MCU Family Reference Manual

(DS33023).

Refer to Application Note AN578, “Use of the SSP

Module in the I2C Multi-Master Environment.”

10.2 SPI Mode

This section contains register definitions and opera-

tional characteristics of the SPI module.

SPI mode allows 8 bits of data to be synchronously

transmitted and received simultaneously. To accom-

plish communication, typically three pins are used:

• Serial Data Out (SDO) RC5/SDO

• Serial Data In (SDI) RC4/SDI/SDA

• Serial Clock (SCK) RC3/SCK/SCL

Additionally, a fourth pin may be used when in a Slave

mode of operation:

• Slave Select (SS) RA5/SS/AN4

When initializing the SPI, several options need to be

specif ied. This is done by progra mming the ap propriate

control bits in the SSPCON register (SSPCON<5:0>)

and SSPSTAT<7:6>. These control bits allow the fol-

lowing to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Clock edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

FIGURE 10-1: SSP BLOCK DIAGRAM

(SPI MODE)

To enable the serial port, SSP enable bit, SSPEN

(SSPCON<5>) must be set. To reset or reconfigure SPI

mode, clear bit SSPEN, re-initialize the SSPCON reg-

ister, and then set bit SSPEN. Th is con fig ures the SDI,

SDO, SCK, and SS pins as serial po rt pins. For the pins

to behave as the serial port function, they must have

their data direction bits (in the TRISC register) appro-

priately programmed. That is:

• SDI must have TRISC<4> set

• SDO must have TRISC<5> cl eared

• SCK (Master mode) must have TRISC<3> cleared

• SCK (Slave mode) must have TRISC<3> set

•SS

must have TRI SA<5> set

• ADCON1 must configure RA5 as a digital I/O pin.

.Note 1: When the SPI is in Slave mode with SS

pin control enabled (SSPCON<3:0> =

0100), the SP I modul e will reset if the SS

pin is set to VDD.

2: If the SPI is used in Slave mode with

CKE = '1', th en the SS pin contro l must be

enabled.

Read Write

Internal

Data Bus

RC4/SDI/SDA

RC5/SDO

RA5/SS/AN4

RC3/SCK/

SSPSR reg

SSPBUF reg

SSPM3:SSPM0

bit0 Shift

Clock

SS Control

Enable

Edge

Select

Clock Select

TMR2 Output

TCY

Prescaler

4, 16, 64

TRISC<3>

Edge

Select

SCL

PIC16C63A/65B/73B/74B

DS30605D-page 56  1998-2013 Microchip Technology Inc.

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A PSR/WUA BF

bit 7 bit 0

bit 7 SMP: SPI Data Input Sample Phase

SPI Master mode:

1 = Input data sampled at end of data output time

0 = Input data sampled at middle of data output time (Microwire®)

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

I2 C mode:

This bit must be maintained clear

bit 6 CKE: SPI Clock Edge Select (see Figure 10-2, Fi gure 10-3, and Figure 10-4)

SPI mode:

CKP = 0:

1 = Data transmitted on rising edge of SCK (Microwire alternate)

0 = Data transmitted on falling edge of SCK

CKP = 1:

1 = Data transmitted on falling edge of SCK (Microwire default)

0 = Data transmitted on rising edge of SCK

I2 C mode:

This bit must be maintained clear

bit 5 D/A: Data/Address bit (I2C mode only)

1 = Indicates that the last byte received or transmitted was data

0 = Indicates that the last byte received or transmitted was address

bit 4 P: ST OP bit (I2C m ode only). T his bit i s cleared wh en the SSP m odule is d isabled, or when the

START bit is detected last. SSPEN is cleared.

1 = Indicates that a STOP bit has been detected last (this bit is '0' on RESET)

0 = STOP bit was not de tected last

bit 3 S: START bit (I2C mode only). This bit is cleared when the SSP module is disabled, or when

the STOP bit is detected last. SSPEN is cleared.

1 = Indicates that a START bit has been detected last (this bit is '0' on R ESET)

0 = START bit was not detected last

bit 2 R/W: Read/W rite bit information (I2C mode only). This bit holds the R/W bit information follow-

ing the last ad dress match. Thi s bit is only vali d from the address match to the next START bit,

STOP bit, or ACK bit.

1 =Read

0 =Write

bit 1 UA: Update Address (10-bit I2C mode only)

1 = Indicates that the user needs to update the address in the SSPADD register

0 = Address does not need to be updated

bit 0 BF: Buffer Full Status bit

Receive (SPI and I2 C modes):

1 =Receive complete, SSPBUF is full

0 =Receive not complete, SSPBUF is empty

Transmit (I2 C mode only):

1 = Transmit in progress, SSPBUF is full

0 = Transmit complete, SSPBUF is empty

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 1998-2013 Microchip Technology Inc. DS30605D-page 57

PIC16C63A/65B/73B/74B

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

bit 7 bit 0

bit 7 WCOL: Write Collision Flag bit

1 = The SSPBUF register was written while still transmitting the previous word (must be

cleared in software)

0 = No collision

bit 6 SSPOV: Synchronous Serial Port Overflow Flag bit

In SPI mode:

1 = A new byte was received while the SSPBUF register is still holding the previous unread

data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave

mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting

overflo w. In Master m ode , th e overflow bit is no t s et si nc e e ac h n ew rec epti on (an d trans -

mission) is initiated by writing to the SSPBUF register.

0 = No overflow

In I2 C mode:

1 = A byte was received while the SSPBUF register is still holding the previous unread byte.

SSPOV is a "don’t care" in transmit mode. SSPOV must be cleared in softw are in either

mode.

0 = No overflow

bit 5 SSPEN: Synchronous Serial Port Enable bit. When enabled, the SSP pins must be properly

configured as input or output.

In SPI mode:

1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins

0 = Disables serial port and configures these pins as I/O port pins

In I2 C mode:

1 = Enables the serial port and configures the SDA and SCL pins as serial port pins

0 = Disables serial port and configures these pins as I/O port pins

bit 4 CKP: Clock Polarity Select bit

In SPI mode:

1 = Idle state for clock is a high level (Microwire default)

0 = Idle state for clock is a low level (Microwire alternate)

In I2 C mode:

SCK release control

1 = Enable clock

0 = Holds clock low (clock stretch). (Used to ensure data setup time.)

bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0000 = SPI Master mo de, clock = FOSC/4

0001 = SPI Master mo de, clock = FOSC/16

0010 = SPI Master mo de, clock = FOSC/64

0011 = SPI Master mode, clock = TMR2 output/2

0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.

0101 = SPI Slave m ode, c lo ck = SCK p in. SS pin control disabl ed. SS ca n be used as I/O pi n.

0110 = I2C Slave mode, 7-bit address

0111 = I2C Slave mode, 10-bit address

1011 = I2C firmware controlled Master mode (Slave idle)

1110 = I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled

1111 = I2C Slave mode, 10- bit address with START and STOP bit interrupts enabled

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16C63A/65B/73B/74B

DS30605D-page 58  1998-2013 Microchip Technology Inc.

FIGURE 10-2: SPI MODE TIMING, MASTER MODE

FIGURE 10-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0)

SCK (CKP = 0,

SDI (SMP = 0)

SSPIF

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

SDI (SMP = 1)

SCK (CKP = 0,

SCK (CKP = 1,

SDO

bit7

bit7 bit0

bit0

CKE = 0)

CKE = 1)

CKE = 0)

CKE = 1)

SCK (CKP = 0)

SDI (SMP = 0)

SSPIF

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

SCK (CKP = 1)

SDO

bit7 bit0

SS (optional)

 1998-2013 Microchip Technology Inc. DS30605D-page 59

PIC16C63A/65B/73B/74B

FIGURE 10-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1)

TABLE 10-1: REGISTERS ASSOCIATED WITH SPI OPERATION

SCK (CKP = 0)

SDI (SMP = 0)

SSPIF

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

SCK (CKP = 1)

SDO

bit7 bit0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

RESETS

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

87h TRISC PORTC Data Direction register 1111 1111 1111 1111

13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit register xxxx xxxx uuuu uuuu

14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

85h TRISA —— PORTA Data Direction register --11 1111 --11 1111

94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, - = unim plement ed, read as '0'. Shaded cells are not used by the SSP in SPI mode.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.

2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.

PIC16C63A/65B/73B/74B

DS30605D-page 60  1998-2013 Microchip Technology Inc.

10.3 SSP I 2C Operation

The SSP module in I2C mode full y implemen ts all s lave

functions, except general call support, and provides

interrupts on START and STOP bits in hardware to

facilitate firmware implementation of the master func-

tions. Th e SSP mod ule imple ment s the st andard m ode

specifications as well as 7-bit and 10-bit addressing.

Two pins are used for data transfer , the RC3/SCK/SCL

pin, which is the clock (SCL), and the RC4/SDI/SDA

pin, which is the data (SDA). The user must configure

these pins as inputs or outputs through the

TRISC<4:3 > bit s. External pull -up resisto rs for the SCL

and SDA pins must be provided in the application cir-

cuit for proper operation of the I2C module.

The SSP mod ule fun ctions a re enabl ed by settin g SSP

enable bit SSPEN (SSPCON<5>).

FIGURE 10-5: SSP BLOCK DIAGRAM

(I2C MODE)

The SSP module has five registers for I2C operation.

These are the:

• SSP Control Register (SSPCON)

• SSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buff er (SSPBUF)

• SSP Shift Register (SSPSR) - not directly accessible

• SSP Address Register (SSPADD)

The SSPCON register al lows control of the I 2C opera-

tion. Four mode selection bits (SSPCON<3:0>) allow

one of the following I2C modes to be selected:

•I

2C Slave mode (7-bit address)

•I

2C Slave mode (10-bit address)

•I

2C Slave mode (7-bit address), with START and

STOP bit interrupts enabled to support firmware

Master mode

•I

2C Slave mode (10-bit ad dress), with ST ART and

STOP bit interrupts enabled to support firmware

Master mode

•I

2C START and STOP bit interrupts enabled to

support firmware Master mode, Slav e is idle

Selection of any I2C mode with the SSPEN bit set,

forces the SCL and SDA pins to be open drain, pro-

vided these pins are programmed to inputs by setting

the appropriate TRISC bits.

Additional information on SSP I2C operation can be

found in the PIC® Mid-Range MCU Family Reference

Manual (DS33023).

10.3.1 SLAVE MODE

In Slave mod e, the SCL and SDA pin s must be config-

ured as input s (TRISC<4 :3> set). The SSP module will

override the input state with the output data when

required (sl ave-tran smit ter).

When an address is matched or the data transfer after

an add ress m atc h is r ece ived , the hard ware aut omati -

cally generates the acknowledge (ACK) pulse, and

then loads the SSPBUF register with the received

value currently in the SSPSR register.

There are certain conditions that will cause the SSP

module not to give this ACK pul se. They in clude (eith er

or both):

a) The buffer full bit BF (SSPSTAT<0>) was set

before the transfer was received.

b) The overflow bit SSPOV (SSP CON<6>) was set

before the transfer was received.

In this case, the SSPSR register value is not loaded

into the SSPBUF, but bit SSPIF (PIR1<3>) is set.

Table 10-2 shows what happens when a data transfer

byte is received, given the status of bits BF and

SSPOV. The shaded cells show the condition where

user so ftw are d id no t pr operly clear th e ove rflo w cond i-

tion. Flag bit BF is cleared by reading the SSPBUF

The SCL clock input must have minimum high and low

times for proper operation. The high and low times of

the I2C specification, as well as the requirement of the

SSP module, is shown in timing parameter #100 and

parameter #101.

Read Write

Match Detect

SSPADD reg

START and

STOP bit Detect

SSPBUF reg

Internal

Data Bus

Addr Match

Set, Reset

S, P bits

(SSPSTAT reg)

RC3/SCK/SCL

RC4/SDI/

Shift

Clock

MSb LSb

SDA

SSPSR reg

 1998-2013 Microchip Technology Inc. DS30605D-page 61

PIC16C63A/65B/73B/74B

10.3.1.1 Addressing

Once the SSP module has been enabled, it waits for a

START cond ition to oc cur. Following the START condi-

tion, 8-bits are shifted into the SSPSR register. All

incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addres ses match, and the BF

and SSPOV bits are clear, the following events occur:

a) The SSPSR register value is loaded into the

SSPBUF register.

b) The buffer full bit, BF is set.

c) An ACK pulse is generated.

d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set

(interrupt is genera ted if e nabled ) - on the fallin g

edge of the ninth SCL pulse.

In 10-bit address mode, two address bytes need to be

received by the slave (Figure 10-7). The five Most Sig-

nificant bits (MSbs) of the first address byte specify if

this i s a 10-bit address. Bit R/W (SSPSTAT<2>) must

specif y a w rite so the slave d ev ice w ill rece ive the sec-

ond address byte. For a 10-bit address, the first byte

would e qua l ‘1111 0 A9 A8 0’, whe re A9 and A8 are

the two MSbs of the address. The sequence of events

for 10-bit address is as follows, with steps 7 - 9 for

slave-transmitter:

1. Receive first (high) byte of ad dress (bits SSPIF,

BF, and bit UA (SSPSTAT<1>) are set).

2. Update the SSPADD register with second (low)

byte of Address (clears bit UA and releases the

SCL line).

3. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

4. Receive second (low) byte of address (bits

SSPIF, BF, and UA are set).

5. Update the SSPADD registe r with the f irst (high)

byte of a ddre ss , if match releases SCL li ne, this

will clear bit UA.

6. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

7. Receive Repeated START condition.

8. Receive first (high) byte of address (bits SSPIF

and BF are set).

9. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

TABLE 10-2: DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data

Transfer is Received SSPSR  SSPBUF Generate ACK

Pulse

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

BF SSPOV

0 0 Yes Yes Yes

1 0 No No Yes, SSPOV is set

1 1 No No Yes

0 1 No No Yes

Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition.

PIC16C63A/65B/73B/74B

DS30605D-page 62  1998-2013 Microchip Technology Inc.

10.3.1.2 Reception

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

the SSPBUF register.

When the address byte overflow condition exists , then

no acknowledge (ACK) pulse is given. An overflow con-

dition is define d as any situa tion w here a rec eive d byte

in SSPBUF is overwritten by the next received byte

before it has been read. An overflow has occurred

when:

a) The Buffer Full flag bit, BF(SSPSTAT<0>) was

set, indicating that the byte in SSPBUF was

waiting to be read when another byte was

received. This sets the SSPOV flag.

b) The overflow flag , SSPOV (SSPCON1<6> ) wa s

set.

An SSP interrupt is generated for each data transfer

byte. F lag bit SSPIF (PIR1<3>) must be cle ared in soft-

ware. The SSPSTAT register is used to determine the

status of the byte.

FIGURE 10-6: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

D3D4

D6D7

A7 A6 A5 A4 A3 A2 A1SDA

SCL 123456789123456789123

Bus Master

terminates

transfer

Bit SSPOV is set because the SSPBUF register is still full

Cleared in software

SSPBUF register is read

ACK Receiving Data

Receiving Data D0

D3D4

D6D7

ACK

R/W=0

Receiving Ad dr ess

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

SSPOV (SSPCON<6>)

ACK

ACK is not sent

 1998-2013 Microchip Technology Inc. DS30605D-page 63

PIC16C63A/65B/73B/74B

10.3.1.3 Transmission

When the R/W bit of the incoming addres s byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the n inth bit and pin RC3/SC K/SCL is held

low. The transmit data must be loaded into the

SSPBUF register, which also loads the SSPSR regis-

ter. Then pin RC3/SC K/SCL s ho uld be ena ble d by s et-

ting bit CKP (SSPCON<4>). The master must monitor

the SCL p in p rior to asserting anothe r clock pulse. The

slave devices may be holding off the master by stretch-

ing the clock. The eight data bits are shifted out on the

falling edge of the SCL input. This ensures that the

SDA signal is valid during the SCL high time

(Figure 10-7).

An SSP interrupt is generated for each data transfer

byte. Flag bit SSPIF must be cleared in software, and

the SSPSTAT register is used to determine the status

of the byte. Flag bit SSPIF is set on the falling edge of

the ninth clock pulse.

As a slave-transmitter, the ACK pulse from the

master-receiver is latched on the rising edge of the

ninth SCL input pulse. If the SDA line was high (not

ACK), then the data transfer is complete. When the

ACK is latched by the slave, the slave logic is reset

(reset s SSPSTA T register) a nd the slave then mon itors

for anoth er occurrence o f the ST AR T bit. If th e SDA line

was low (ACK), the transmit data must be loaded into

the SSPBUF register , which also loads the SSPSR reg-

ister. Then pin RC3/SCK/SCL should be enabled by

setting bit CKP.

FIGURE 10-7: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

CKP (SSPCON<4>)

A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

Transmitting DataR/W = 1Receiving Address

123456789 123456789 P

Cleared in softwa re

SSPBUF is written in software From SSP Interrupt

Service Routine

Set bit after writing to SSPBUF

SData in

sampled SCL held low

while CPU

responds to SSPIF

(the SSPBUF must be written to

before the CKP bit can be set)

PIC16C63A/65B/73B/74B

DS30605D-page 64  1998-2013 Microchip Technology Inc.

10.3.2 MASTER MODE

Master mode of operation is supported in firmware

using interrupt generation on the detection of the

START and STOP conditions. The STOP (P) and

START (S) bit s are c leared fro m a RESET, or when th e

SSP module is disabled. The STOP (P) and START (S)

bits will toggle based on the START and STOP condi-

tions. Control of the I2C bus may be taken when the P

bit is set, o r the bus is i dle and both the S and P bits are

clear.

In Master mode, the SCL and SDA lines are manipu-

lated by cleari ng the c orresp onding TRISC<4 :3> bit(s ).

The output level is always low, irrespective of the

value(s ) i n PO R T C <4:3 >. So w h en tran sm itti ng da t a, a

'1' data bit must have the TRISC<4> bit set (input) and

a '0' data bit must have the TRISC <4 > bit c lea red (o ut-

put). The same scenario is true for the SCL line with the

TRISC <3> bit.

The following events will cause SSP Interrupt Flag bit,

SSPIF, to be set (an SSP Interrupt will occur, if

enabled):

• START condition

• STOP condition

• Data transfer byte transmitted/received

Master mode of operation can be done with either the

Slave mode idle (SSPM3:SSPM0 = 1011), or with the

slave active. When both Master and Slave modes are

enabled, the software needs to differentiate the

source(s) of the interrupt.

10.3.3 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the START and STOP conditions allows

the determination of when the bus is free. The STOP

(P) and START (S) bits are cleared from a RESET or

when the SSP module is disabled. The STOP (P) and

START (S) bits will toggle based on the START and

STOP conditions. Control of the I2C bus may be taken

when bit P (SSPSTAT<4>) is set, or the bus is idl e an d

both the S and P bits clear. When the bus is busy,

enabling the SSP Interrupt will generate the interrupt

when the STOP condition occurs.

In Multi-Ma ster operation, the SDA line must be moni-

tored to see if the signal level is the expected output

level. This check only needs to be done when a high

level is output. If a high level is e xpect ed and a low leve l

is present, the device needs to release the SDA and

SCL lines (set TRISC<4:3>). There are two stages

where this arbitration can be lost, these are:

• Address Transfer

• Data Transfer

When the slav e log ic is enab led, th e sla ve co ntinue s to

receive . If arbitrati on was l ost during the addres s trans-

fer stage, communication to the device may be in

progress. If addressed, an ACK pulse will be gener-

ated. If arbitration was lost during the data transfer

stage, the device will need to re-transfer the data at a

later time.

TABLE 10-3: REGISTERS ASSOCIATED WITH I2C OPERATION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

RESETS

0Bh, 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

13h SSPBUF S ync hronous Ser ial Port Receive Buffer/Transmit register xxxx xxxx uuuu uuuu

93h SSPADD Synchronous Serial Port (I2C mode) Address register 0000 0000 0000 0000

14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

94h SSPSTAT SMP(3) CKE(3) D/A PSR/WUA BF 0000 0000 0000 0000

87h T RI SC PO RTC Data Direction register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.

Shaded cells are not used by SSP module in I2C mode.

Note 1: PSPIF and PSPIE are reserved on the PIC16C63A/73B; always maintain these bits clear.

2: ADIF and ADIE are reserved on the PIC16C63A/65B; always maintain these bits clear.

3: Maintain these bits clear in I2C mode.

 1998-2013 Microchip Technology Inc. DS30605D-page 65

PIC16C63A/65B/73B/74B

11.0 ADDRESSABLE UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (USART)

The Universal Synchronous Asynchronous Receiver

Transmitter (USART) module is one of the two serial

I/O mo dules . (USA RT is al so kno wn as a S erial Com-

munications Interface or SCI.) The USART can be con-

figured as a full duplex asynchronous system that can

communicate with periph eral devices, such as CR T ter-

minals and perso nal co mputers, or it can be confi gured

as a half duplex synchro nou s s y ste m th at c an com m u-

nicate with peri pheral devic es, such a s A/D or D/A inte-

grated circuits, Serial EEPROMs etc.

The USART can be configured in the following modes:

• Asynchronous (full duplex)

• Synchronous - Master (half duplex)

• Synchronous - Slave (half duplex)

Bits SPEN (RCSTA<7>) and TRISC<7:6> have to be

set in order to configure pins RC6/TX/CK and

RC7/RX/DT as the universal synchronous asynchro-

nous receiver transmitter.

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0

CSRC TX9 TXEN SYNC — BRGH TRMT TX9D

bit 7 bit 0

bit 7 CSRC: Clock Source S ele ct bit

Asynchronous mode:

Don’t care

Synchronous mode:

1 =Master mode (Clock generated internally from BRG)

0 = Slave mode (Clock from external source)

bit 6 TX9: 9-bit Transmit Enable bit

1 = Selects 9-bit transmission

0 = Selects 8-bit transmission

bit 5 TXEN: Transmi t Enable bit

1 = Transmit enabled

0 = Transmit disabled

Note: SREN/CREN overrides TXEN in SYNC mode.

bit 4 SYNC: USART Mode Select bit

1 =Synchronous mode

0 =Asynchronous mode

bit 3 Unimplemented: Read as '0'

bit 2 BRGH: High Baud Rate Select bit

Asynchronous mode:

1 =High speed

0 =Low speed

Synchronous mode:

Unused in this mode

bit 1 TRMT: Transmit Shift Register Status bit

1 = TSR empty

0 = TSR full

bit 0 TX9D: 9th bit of Transmit Data. Can be parity bit.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16C63A/65B/73B/74B

DS30605D-page 66  1998-2013 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R-0 R-x

SPEN RX9 SREN CREN — FERR OERR RX9D

bit 7 bit 0

bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)

0 = Serial por t disabled

bit 6 RX9: 9-bit Receive Enable bit

1 = Selects 9-bit reception

0 = Selects 8-bit reception

bit 5 SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode - Master:

1 = Enables single receive

0 = Disables single receive

This bit is cleared after reception is complete.

Synchronous mode - Slave:

Don’t care

bit 4 CREN: Continuous Recei ve Enab le bit

Asynchronous mode:

1 = Enables continuous receive

0 = Disables continuous receive

Synchronous mode:

1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0 = Disables continuous receive

bit 3 Unimplemented: Read as '0'

bit 2 FERR: Framing Error bit

1 = Framin g error (can be updated by reading RCREG register and receive next valid byte)

0 = No framing error

bit 1 OERR: Overrun Error bit

1 = Overrun error (can be cleared by clearing bit CREN)

0 = No overrun error

bit 0 RX9D: 9th bit of Received Data. (Can be parity bit. Calculated by firmware.)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 1998-2013 Microchip Technology Inc. DS30605D-page 67

PIC16C63A/65B/73B/74B

11.1 USART Baud Rate Generator

(BRG)

The BRG supports both the Asynchronous and Syn-

chronous modes of the USART. It is a dedicated 8-bit

baud rate generator. The SPBRG register controls the

period of a free running 8-bit timer. In Asynchronous

mode, bit BRGH (TXSTA<2>) also controls the baud

rate. In Synchronous mode, bit BRGH is ignored.

Table 11-1 shows the formula for computation of the

baud rat e for dif feren t USART modes, wh ich only a pply

in Master mode (internal clock).

Given the desired b aud rate an d Fosc, the n earest inte-

ger value for the SPBRG register can be calculated

using the formula in Table 11-1. From this, the error in

baud rate can be determined.

It may be advantageous to use the high baud rate

(BRGH = 1) even for slower baud clocks. This is

becaus e the FOSC/(16(X + 1 )) eq uat ion can reduce th e

baud rate error in some cases.

Writing a new value to the SPBRG register causes the

BRG timer to be reset (or cleared). This ensures the

BRG does not wait for a timer overflow before output-

ting the new bau d rate.

11.1.1 SAMPLING

The dat a on the RC7/RX/D T pin is sa mpled three time s

near the cen ter of each bit ti me by a majo rity detect c ir-

cuit to de termine if a hig h or a low level is present at the

RX pin.

TABLE 11-1: BAUD RATE FORMULA

TABLE 11-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Sp eed)

(Asynchronous) Baud Rate = FOSC/(64(SPBRG+1))

(Synchronou s) Baud Rate = FOSC/(4(SPBRG+1)) Baud Rate = FOSC/(16(SPBRG+1))

N/A

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

RESETS

98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010

18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x

99h SPBRG Baud Rate Generator register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.

PIC16C63A/65B/73B/74B

DS30605D-page 68  1998-2013 Microchip Technology Inc.

11.2 USART Asynchronous Mode

In this mode, the USART uses standard non-

return-to-zero (NRZ) format (one START bit, eight or

nine data bits, and one STOP bit). The most common

data format is 8 bits. An on-chip, dedicated, 8-bit baud

rate generator can be used to derive standard baud

rate frequ en cie s from the osc illato r. The USART tran s-

mits and receive s the LSb first. The USART ’s transmit-

ter and receiver are functionally independent, but use

the same data format and baud rate. The baud rate

generator produces a cl oc k, either x16 or x6 4 o f th e b it

shift rate, depending on bit BRGH (TXSTA<2>). Parity

is not supported by the hardware, but can be imple-

mented in software (and stored as the ninth data bit).

Asynchronous mode is stopped during SLEEP.

Asynchronous mode is selected by clearing bit SYNC

(TXSTA<4>).

The USART Asynchronous module consists of the fol-

lowing im portant elements:

• Baud Rate Generator

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

11.2.1 USART ASYNCHRONOUS

TRANSMITTER

The USART transmitter block diagram is shown in

Figure 11-1. The hea rt of the transmitte r is th e t r ansm it

(serial) shi ft register (TSR). The shift reg ister obta ins its

data from the read/write transmit buffer, TXREG. The

TXREG register is loaded with data in software. The

TSR register is not loaded until the STOP bit has been

transmitted from the previous load. As soon as the

STOP bit is transmitted, the TSR is loaded with new

data from the TXREG register (if available). Once the

TXREG register transfers the data to the TSR register

(occurs in one TCY) , th e T XREG r egi ster is empty and

the USART Transmit Flag bit TXIF (PIR1<4>) is set.

This in terrupt ca n be e nabled/di sabled by settin g/clear-

ing the USART Transmit Enable bit TXIE (PIE1<4>).

The flag bit TXIF will be set, regardless of the state of

enable bit TXIE and cannot be cleared in software. It

will re set only when new data is loaded in to the TXREG

TXREG register, another bit TRMT (TXSTA<1>) shows

the status of the TSR register. Status bit TRMT is a read

only bit, which is set when the TSR register is empty. No

interrupt logic i s tied to this bit, so the user h as to poll this

bit in order to determine if the TSR register is empty.

Transmission is enabled by setting enable bit TXEN

(TXSTA<5>). The actual transmission will not occur

until the TXREG register has been loaded with data

and the baud rate generator (BRG) has produced a

shift clock (Figure 11-2). The transmission can also be

started by first loading the TXREG register and then

setting enable bit TXEN. Normally, when transmission

is first started, the TSR register is empty. At that point,

transfer to the TXREG register will result in an immedi-

ate transfer to TSR, resulting in an empty TXREG. A

back-to-back transfer is thus possible (Figure 11-3).

Clearing enable bit TXEN during a transmission will

cause the tra nsm is s ion to be ab orte d and will rese t th e

transmitter. As a result, the RC6/TX/CK pin will revert

to hi-impedance.

In order to select 9-bit transmission, transmit bit TX9

(TXSTA<6>) should be set and the ninth bit should be

written to TX9D (TXSTA<0>). The ninth bit must be

written before writing the 8-bit data to the TXREG reg-

ister. This is because a data write to the TXREG regis-

ter can resu lt in an immediate tra nsfer of the dat a to the

TSR register (if the TSR is empty). In such a case, an

incorrect ninth data bit may be loaded in the TSR

FIGURE 11-1: USART TRANSMIT BLOCK DIAGRAM

Note 1: The TSR register is not mapped in data

memory, so it is not available to the user.

2: Flag bit T XIF is set whe n enable bit TXEN

is set. TXIF is cle ared by loadi ng TXRE G.

TXIF

TXIE

Interrupt

TXEN Baud Rate CLK

SPBRG

Baud Rate Generator TX9D

MSb LSb

Data Bus

TXREG register

TSR register

(8) 0

TX9

TRMT SPEN

RC6/TX/CK pin

Pin Buffer

and Control



 1998-2013 Microchip Technology Inc. DS30605D-page 69

PIC16C63A/65B/73B/74B

Steps to follow when setting up an Asynchronous

Transmission:

1. Initiali ze th e SPBRG re giste r for the ap prop ria te

baud rate. If a high speed baud rate is desired,

set bit BRGH. (Section 11.1)

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

3. If interrupts are desired, set interrupt enable bits

TXIE (PIE1<4>), PEIE (INTCON<6>), and GIE

(INTCON<7>), as required.

4. If 9-bit transmission is desired, then set transmit

bit TX9.

5. Enable the transmission by setting bit TXEN,

which will also set flag bit TXIF.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Load data to the TXREG register (starts trans-

mission).

FIGURE 11-2: ASYNCHRONOUS MASTER TRANSMISSION

FIGURE 11-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)

TABLE 11-3: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

RESETS

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF(2)RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x

19h TXREG USART Transmit Register 0000 0000 0000 0000

8Ch PIE1 PSPIE(1) ADIE(2)RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: u = unchanged, x = unknown, - = unimplemented locations read as '0'.

Shaded cells are not used for asynchronous transmission.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.

2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.

Word 1 STOP Bit

Word 1

Transmit Shift Reg

START Bit Bit 0 Bit 1 Bit 7/8

Write to TXREG Word 1

BRG output

(shift clock)

RC6/TX/CK (pin)

TXIF bit

(Transmit buffer

reg. empty fl ag)

TRMT bi t

(Transmit shift

reg. empty flag)

Transmit Shift Reg.

Write to TXREG

BRG output

(shift clock)

RC6/TX/CK (pin)

TXIF bit

(interrupt reg. flag)

TRMT bit

(Transmit shift

reg. empty flag)

Word 1 Word 2

START Bit STOP Bit START Bit

Transmit Shift Reg.

Word 1 Word 2

Bit 0 Bit 1 Bit 7/8 Bit 0

Note: This timing diagram shows two consecutive transmissions.

PIC16C63A/65B/73B/74B

DS30605D-page 70  1998-2013 Microchip Technology Inc.

11.2.2 USART ASYNCHRONOUS

RECEIVER

The receiver block diagram is shown in Figure 11-4.

The data is received on th e RC 7/RX/D T p in an d dri ve s

the data recovery block. The data recovery block is

actuall y a h igh sp ee d s hifter operati ng at x 16 tim es th e

baud rate , whereas the main receive serial shif ter oper-

ates at the bit rate or at FOSC.

Once Asynchronous mode is selected, reception is

enabled by setti ng bit CRE N (RCSTA<4>).

The heart of the receive r is the receive (s erial) shif t reg-

ister (RSR). After sampling the STO P bit, the received

data in the RSR is tra nsferred to the R CREG re gister (if

it is empt y). If the transfer is comp lete, USART Receive

Flag bit RCIF (PIR1<5>) is set. This interrupt can be

enabled/disabled by setting/clearing the USART

Receive Enable bit RCIE (PIE1<5> ).

Flag bit R CIF is a read onl y bi t, whic h is cle are d by the

hardware. It is cleared when the RCREG register has

been read and is empty. The RCREG is a double buff-

ered register, i.e., it is a two-deep FIFO. It is possible

for two bytes of data to be receiv ed and transferred to

the RCREG FIFO and a third byte to begin shifting to

the RSR register. On the detection of the STOP bit of

the third byte, if the RCREG register is still full, then

overrun error bit OERR (RCSTA<1>) will be set. The

word in the RSR will be lost. Th e RCREG register can

be read twice to retrieve the two bytes in the FIFO.

Overr un bi t OER R has t o be cleare d in s oftwar e. This

is done b y resetting the rec ei ve lo gic (CR EN i s cl eare d

and then set). If bit OERR is set, transfers from the

RSR register to the RCREG register are inhibited, and

no further dat a will be rece ived; therefore, it is es sential

to clear error bit OERR if it is set. Framing error bit

FERR (RCSTA<2>) is set if a STOP bit is detected as

clear. Bit FERR and the 9th rece ive bi t are buf fer ed th e

same way as the receive data. Reading the RCREG

will load bits RX9D and FERR with new values, there-

fore, it is essential for the user to read the RCSTA reg-

ister befo re reading the RCREG register , in order not to

lose the old FERR and RX9D information.

FIGURE 11 -4: USART RECEIVE BLOCK DIAGRAM

x64 Baud Rate CLK

SPBRG

Baud Rate Generator

RC7/RX/DT

Pin Buffer

and Control

SPEN

Data

Recovery

CREN OERR FERR

RSR Register

MSb LSb

RX9D RCREG Register FIFO

Interrupt RCIF

RCIE

Data Bus

 64

 16

or STOP START

(8) 710

RX9



FOSC

 1998-2013 Microchip Technology Inc. DS30605D-page 71

PIC16C63A/65B/73B/74B

Steps to follow when setting up an Asynchronous

Reception:

1. Initiali ze th e SPBRG re giste r for the ap prop ria te

baud rate. If a high speed baud rate is desired,

set bit BRGH. (Section 11.1).

2. Enable the asynchronous serial port by clearing

bit SYNC, and setting bi t SPEN.

3. If interrupts are desired, set interrupt enable bits

RCIE (PIE1<5>), PEIE (INTCON<6>), and GIE

(INTCON<7>), as required.

4. If 9-bit reception is desired, then set bit RX9.

5. Enable the reception by setting bit CREN.

6. Flag bit RCIF wi ll b e se t w he n rec ept ion is com -

plete an d an interru pt will be generate d if enabl e

bit RCIE was set.

7. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during rec e ption.

8. Read the 8-bit received data by reading the

RCREG register.

9. If any error occurred, clear the error by clearing

enable bit CREN.

FIGURE 11 -5: ASYNCHRONOUS RECE PTION

TABLE 11-4: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

START

bit bit7/8

bit1bit0 bit7/8 bit0STOP

bit

START

bit START

bit

bit7/8 STOP

bit

RX (pin)

reg

Rcv buffer reg

Rcv shift

Read Rcv

buffer reg

RCREG

RCIF

(interrupt flag)

OERR bit

CREN

Word 1

RCREG Word 2

RCREG

STOP

bit

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the

third word, causing the OERR (overrun) bit to be set. An overrun error indicates an error in user’s firmware.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

RESETS

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x

1Ah RCREG USART Receive register 0000 0000 0000 0000

8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010

99h SP BRG Baud Rate Generator regist er 0000 0000 0000 0000

Legend: u = unchanged, x = unknown, - = unimplemented locations read as '0'.

Shaded cells are not used for asynchronous reception.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76; always maintain these bit s clear.

2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.

PIC16C63A/65B/73B/74B

DS30605D-page 72  1998-2013 Microchip Technology Inc.

11.2.3 USART SYNCHRONOUS MASTER

MODE

In Sync hronous Ma ster mode, the data is trans mitted in

a half-duplex manner, i.e., transmission and reception

do not o ccur a t the s ame ti me. Wh en tran smitti ng dat a,

the reception is inhibited and vice versa. Synchronous

mode is entered by setting bit SYNC (TXSTA<4>). In

addition , enable bit SPEN (RCSTA<7>) is set in order

to configure the RC6/TX/CK and RC7/RX/DT I/O pins

to CK (clock) and DT (data) lines, respectively. The

Master mode ind icates t hat the process or transmit s th e

master clock on the CK line. The Master mode is

entered by setting bit CSRC (TXSTA<7>).

11.2.4 USART SYNCHRONOUS MASTER

TRANSMISSION

The USART transmitter block diagram is shown in

Figure 11-1. The hea rt of the transmitte r is th e t r ansm it

(serial) shi ft register (TSR). The shift reg ister obta ins its

data from the read/write transmit buffer register,

TXREG. The TXREG register is loaded with data in

softw are. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG (if available). Once the

TXREG register transfers the data to the TSR register

(occurs in one TCYCLE), the TXR EG is em pty an d inter-

rupt flag b it TXIF (PIR1<4>) i s set. The interru pt can be

enabled/disabled by setting/clearing enable bit TXIE

(PIE1<4>). Flag bit TXIF will be set, regardless of the

state of enable bit TXIE and cannot be cleared in soft-

ware. It will re set o nly when ne w dat a i s loa ded i nto th e

TXREG register . While flag bit TXIF indicates the statu s

of th e T XR EG r egi st e r, anot h er b it T RMT (T XS TA< 1> )

shows the status of the TSR register. TRMT is a read

only bit which is set when the TSR is empty. No inter-

rupt logic is tied to this bit, so the user has to poll this

bit in order to determine if the TSR register is empty.

The TSR is not mapped in data memory, so it is not

availa ble to the user.

Transmission is enabled by setting enable bit TXEN

(TXSTA<5>). The actual transmission will not occur

until the TXREG register has been loaded with data.

The first dat a bit will be shi fted out on the next av ailable

rising edge of the clock on the CK line. Data out is sta-

ble around the falling edge of the synchronous clock

(Figure 11-6). The transmission can also be started by

first loading the TXREG register and then setting bit

TXEN (Figure 11-7). This is advantageous when slow

baud rates are selected, since the BRG is kept in

RESET when bits TXEN, CREN and SREN are clear.

Setting enable bit TXEN will start the BRG, creating a

shif t cl ock imm ediate ly. Normally, when transmis sion i s

first started, the TSR register is empty, so a tran sfer to

the TXREG reg is ter wi ll re sult in an immedia te tra ns fer

to TSR resulting in an empty TXREG. Back-to-back

transfers are possible.

Clearing enable bit TXEN, during a transmission, will

cause the tra nsm is s ion to be ab orte d and will rese t th e

transmitter. The DT and CK pins will revert to

hi-impedance. If either bit CREN, or bit SREN is set

during a transmission, the transmission is aborted and

the DT pin re vert s to a hi -impe dance st ate (for a rece p-

tion). The CK pin will remain an output if bit CSRC is set

(internal clock). The transmitter logic, however, is not

reset, although it is disconnected from the pins. In order

to reset the tran sm itte r, the user has to clear bi t TXEN.

If bit SR EN is set (t o interrupt an on-goin g trans mission

and r eceive a single wo rd), then af ter the singl e word is

received, bit SREN will be cleared and the serial port

will revert back to transmitting, since bit TXEN is still

set. The DT line will immediately switch from

Hi-imp edanc e Receiv e mode to tra nsmit and st art driv-

ing. To avoid this, bit TXEN should be cleared.

In order to select 9-bit transmission, the TX9

(TXSTA<6>) bit should be set and the ninth bit should

be written to bit TX9D (TXSTA<0>). The ninth bit must

be written before writing the 8-bit data to the TXREG

result in an immediate transfer of the data to the TSR

the TXREG was writt en befo re writ ing the “new” T X9D,

the “present” value of bit TX9D is loaded.

Steps to follow when setting up a Synchronous Master

Transmission:

1. Initialize the SPBRG re gis ter for the ap prop ria te

baud rate (Section 11.1).

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. If interrupts a re d esired , set in terrupt e nable bit s

TXIE (PIE1<4>), PEIE (INTCON<6>), and GIE

(INTCON<7>), as required.

4. If 9-bit transmission is desired, set bit TX9.

5. Enable the transmission by setting bit TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Start transmission by loading data to the TXREG

 1998-2013 Microchip Technology Inc. DS30605D-page 73

PIC16C63A/65B/73B/74B

TABLE 11-5: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

FIGURE 11 -6: SYNCHRONOUS TRANSMISSION

FIGURE 11 -7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

RESETS

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF(2)RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x

19h TXREG USART Transmit Register 0000 0000 0000 0000

8Ch PIE1 PSPIE(1) ADIE(2)RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG B aud Rate Generator Register 0000 0000 0000 0000

Legend: u = unchanged, x = unknown, - = unimplemented, read as '0'.

Shaded cells are not used for synchronous master transmission.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.

2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.

bit 0 bit 1 bit 7

Word 1

Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4

bit 2 bit 0 bit 1 bit 7

RC7/RX/DT

RC6/TX/CK

Write to

TXREG reg

TXIF bit

(Interrupt Flag)

TRMT

TXEN bit '1' '1'

Note: Sync Master mode; SPBRG = '0'. Continuous transm ission of two 8-bit words.

Word 2

TRMT bit

Write word1 Write word2

RC7/RX/DT pin

RC6/TX/CK pin

Write to

TXREG reg

TXIF bit

TRMT bit

bit0 bit1 bit2 bit6 bit7

TXEN b it

PIC16C63A/65B/73B/74B

DS30605D-page 74  1998-2013 Microchip Technology Inc.

11.2.5 USART SYNCHRONOUS MASTER

RECEPTION

Once Synchronous mode is selected, reception is

enabled by setting either enable bit SREN

(RCST A<5>), or enable bit CREN (RCSTA<4>). Data is

sampled on the RC7/RX/DT pin on the falling edge of

the clock. If enable bit SREN is set, then only a single

word is received. If enable bit CREN is set, the recep-

tion is c ontinuous until CREN is cleared. If bo th bits are

set, CREN takes precedence. After clo cking the last bit,

the r eceived data in t he Re ceive Sh ift Regist er (RSR)

is transferred to the RCREG register (if it is empty).

When the transfer is complete, interrupt flag bit RCIF

(PIR1<5> ) is set. The interrupt from the USART can be

enabled/disabled by setting/clearing enable bit RCIE

(PIE1<5>). Flag bit RCIF is a read only bit, which is

reset by the ha rdware . In thi s c as e, it i s r ese t whe n th e

RCREG register has been read and is empty. The

RCREG is a double buffered register, i.e., it is a

two-dee p FIFO. I t is possi ble for two bytes of data to be

received and transferred to the RCREG FIFO and a

third by te to begi n shiftin g into the RSR register. On the

clocking of the last bit of the third byte, if the RCREG

(RCSTA<1>) is set. The word in the RSR will be lost.

The RCREG register can be read twice to retrieve the

two bytes in the FIFO. Bit OERR has to be cleared in

software (by clearing bit CREN). If bit OERR is set,

transfers from the RSR to the RCREG are inhibited,

and no further data will be received; therefore, it is

essent ial to clear bi t OERR if it is se t. The ninth rec eive

bit is buffered the same way as the receive data. Read-

ing the RCREG register will load bit RX9D with a new

value, therefore it is essential for the user to read the

RCSTA register before reading RCREG in o rder not to

lose the old RX9D information.

Steps to follow when setting up a Synchronous Master

Reception:

1. Initialize the SPBRG re gis ter for the ap prop ria te

baud rate. (Section 11.1)

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN, and CSRC.

3. Ensure bits CREN and SREN are clear.

4. If interrupts a re d esired , set in terrupt e nable bit s

RCIE (PIE1<5>), PEIE (INTCON<6>), and GIE

(INTCON<7>), as required.

5. If 9-bit reception is desired, then set bit RX9.

6. If a single reception is required, set bit SREN.

For continuous rece ption set bit CREN.

7. Interrupt flag bit RCIF w ill be set when reception

is complete and an interrupt will be generated if

enable bit RCIE was set.

8. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during rec e ption.

9. Read the 8-bit received data by reading the

RCREG register.

10. If any error occurred, clear the error by clearing

bit CREN.

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PIC16C63A/65B/73B/74B

TABLE 11-6: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

FIGURE 11 -8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on:

POR,

BOR

Value on

all other

RESETS

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF(2)RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x

1Ah RCREG USART Receive register 0000 0000 0000 0000

8Ch PIE1 PSPIE(1) ADIE(2)RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator register 0000 0000 0000 0000

Legend: u = unchanged, x = unknown, - = unimplemented, read as '0'.

Shaded cells are not used for synchronous master reception.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.

2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.

CREN bit

RC7/RX/DT pin

RC6/TX/CK pin

Write to

bit SREN

SREN bit

RCIF bit

(interrupt)

Read

RXREG

Note: Timing diagram demons trates SYNC Master mode with bit SREN = '1' and bit BRG = '0'.

Q3Q4 Q1Q2Q3 Q4Q1Q2 Q3Q4Q2 Q1Q2 Q3Q4Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3Q4 Q1 Q2Q3Q4Q1Q2 Q3Q4 Q1 Q2Q3Q4

'0'

bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7

'0'

Q1Q2Q3Q4

PIC16C63A/65B/73B/74B

DS30605D-page 76  1998-2013 Microchip Technology Inc.

11.3 USART Synchronous Slave Mode

Synchronous Slave mode dif fers from the Master mode

in the fact that the shift clock is supplied externally at

the RC6/TX/ CK pin (instead of being supplied internally

in Master mode). This allows the device to transfer or

receive data while in SLEEP mode. Slave mode is

entered by clearing bit CSRC (TXSTA<7>).

11.3.1 USART SYNCHRONOUS SLAVE

TRANSMIT

The operation of the Synchronous Master and Slave

modes are identical, except in the case of the SLEEP

mode.

If two words are written to the TXREG and then the

SLEEP instruction is executed, the following will occur:

a) The first word will immediately transfer to the

TSR register and transmit.

b) The second word will remain in TXREG register.

c) Flag bit TXIF will not be set.

d) When the first word has been shif ted out of TSR,

the TXREG register will transfer the second

word to the TSR and flag bit TXIF will now be

set.

e) If interrupt enable bits TXIE and PEIE are set,

the interrupt will wake the chip from SLEEP. If

GIE is set, the program will branch to the inter-

rupt vector (0004h), otherwise execution will

resume from the instruc tion follo wing the SLEEP

instruction.

Steps to follow when setting up a Synchronous Slave

Transmission:

1. Enable the sync hronous s lave serial p ort by set-

ting bits SYNC and SPEN and clearing bit

CSRC.

2. Clear bits CREN and SREN.

3. If interrupts are desired, set interrupt enable bits

TXIE (PIE1<4>), PEIE (INTCON<6>), and GIE

(INTCON<7>), as required.

4. I f 9-bit transmission is desired, set bi t TX9.

5. Enable the transmission by setting enable bit

TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Start transmis sion by loadin g data to the TXREG

11.3.2 USART SYNCHRONOUS SLAVE

RECEPTION

The operation of the synchronous Master and Slave

modes is identical, except in the case of the SLEEP

mode. Also, bit SREN is a “don't care” in Slave mode.

If receive is enabled by setting bit CREN prior to the

SLEEP instruction, a word may be received during

SLEEP. On completely receiving the word, the RSR

interrupt enable bits RCIE and PEIE are set, the inter-

rupt generated will wake the chip from SLEEP. If the

global interrupt is enabled, the program will branch to

the interrupt vector (0004h), otherwise execution will

resume from the instruction following the SLEEP

instruction.

Steps to follow when setting up a Synchronous Slave

Reception:

1. Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

2. If interrupts a re d esired , set in terrupt e nable bit s

RCIE (PIE1<5>), PEIE (INTCON<6>), and GIE

(INTCON<7>), as required.

3. If 9-bit reception is desired, set bit RX9.

4. To enable reception, set enable bit CREN.

5. Flag bit RCIF wi ll b e se t w he n rec ept ion is com -

plete and an interrupt will be generated, if

enable bit RCIE was set.

6. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during rec e ption.

7. Read the 8-bit received data by reading the

RCREG register.

8. If any error occurred, clear the error by clearing

bit CREN.

 1998-2013 Microchip Technology Inc. DS30605D-page 77

PIC16C63A/65B/73B/74B

TABLE 11-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

TABLE 11-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Add r e s s Name Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

RESETS

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF(2)RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x

19h TXREG USART Trans mit register 0000 0000 0000 0000

8Ch PIE1 PSPIE(1) ADIE(2)RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator register 0000 0000 0000 0000

Legend: u = unchanged, x = unknown, - = unimplemented, read as '0'.

Shaded cells are not used for synchronous slave transmission.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.

2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

RESETS

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF(2)RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x

1Ah R CREG USA RT Receive register 0000 0000 0000 0000

8Ch PIE1 PSPIE(1) ADIE(2)RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

99h S PBR G Baud Rate Generator regist er 0000 0000 0000 0000

Legend: u = unchanged, x = unknown, - = unimplemented, read as '0'.

Shaded cells are not used for synchronous slave reception.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.

2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.

PIC16C63A/65B/73B/74B

DS30605D-page 78  1998-2013 Microchip Technology Inc.

NOTES:

 1998-2013 Microchip Technology Inc. DS30605D-page 79

PIC16C63A/65B/73B/74B

12.0 ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

The 8-bit Analog-to-Digit al (A/D) converter mod ule has

five inputs for the PIC16C73B and eight for the

PIC16C74B.

The A/D allo w s co nve rsi on of an analog input signal to

a corresponding 8-bit digital number. The output of the

sample and hold is the input into the converter, which

generates the result via successive approximation. The

analog reference voltage is software selectable to

either the de vice ’s posi tive s upply volt age (VDD), or the

voltage level on the RA3/AN3/VREF pin.

The A/D converter has a unique feature of being able

to operat e while th e device i s in SLEEP mod e. To oper-

ate in SLEEP, the A/D conversion clock must be

derived from the A/D’s internal RC oscillator.

The A/D module has three registers. These registers

are:

• A/D Result Register (ADRES)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

The ADCON0 register, shown in Register 12-1, con-

trols the operation of the A/D module. The ADCON1

tions of the port pins. The port pins can be configured

as analog inputs (RA3 can also be a voltage reference),

or as digital I/O.

Addition al information on usi ng the A/D module can b e

found in the PIC® Mid-Range MCU Family Reference

Manual (DS33023) and in Application Note, AN546.

Note: The PIC16C63A and PIC16C65B do not

include A/D modules. ADCON0, ADCON1

and ADRES registers are not imple-

mented. ADIF and ADIE bits are reserved

and should be maintained clear.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON

bit 7 bit 0

bit 7-6 ADCS1:ADCS0: A/D Conversion Cloc k Select bits

00 =F

OSC/2

01 =F

OSC/8

10 =F

OSC/32

11 =F

RC (clock derived from the internal A/D module RC oscillator)

bit 5-3 CHS2:CHS0: Analog Channel Select bits

000 = channel 0, (RA0/AN0)

001 = channel 1, (RA1/AN1)

010 = channel 2, (RA2/AN2)

011 = channel 3, (RA3/AN3)

100 = channel 4, (RA5/AN4)

101 = channel 5, (RE0/AN5)(1)

110 = channel 6, (RE1/AN6)(1)

111 = channel 7, (RE2/AN7)(1)

bit 2 GO/DONE: A/D Conversion Status bit

If ADON = 1:

1 =A/D conversion in progress (setting this bit starts the A/D conversion)

0 = A/D conversion n ot in progress (this bit is au tom ati ca lly c le ared by h ardware when the A/D

conversion is complete)

bit 1 Unimplemented: Read as '0'

bit 0 ADON: A/D On bit

1 = A/D converter module is operating

0 = A/D converter module is shut-off and consumes no operating current

Note 1: A/D channels 5, 6 and 7 are implem ented on the PIC16C74B only.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16C63A/65B/73B/74B

DS30605D-page 80  1998-2013 Microchip Technology Inc.

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCFG2 PCFG1 PCFG0

bit 7 bit 0

bit 7-3 Unimplemented: Read as '0 '

bit 2-0 PCFG2:PCFG0: A/D Port Configuration Control bits

Note 1: RE0, RE1 and RE2 are implemented on the PIC16C74B only.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

A = Analog input D = Digital I/O

PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 RE0(1) RE1(1) RE2(1) VREF

000 AAAAAAAAVDD

001 AAAAVREF AAARA3

010 AAAAADDDV

011 AAAAVREF DDDRA3

100 AADDADDDV

101 A A D D VREF DDDRA3

11x DDDDDDDDV

 1998-2013 Microchip Technology Inc. DS30605D-page 81

PIC16C63A/65B/73B/74B

The follo wing steps sh ould be followed for doing a n A/D

conversion:

1. Configure the A/D module:

• Configure analog pins, voltage reference,

and digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Selec t A/D conve rsi on clock (ADCON0)

• Turn on A/D module (ADCON0)

2. Configure A/ D interrupt (if desired):

• Clear ADIF bit (PIR1<6>)

• Set ADIE bit (PIE1<6>)

• Set PEIE bit (INTCON<6>)

• Set GIE bit (INTCON<7>)

3. Wait the required acquisition time.

4. Set GO/DONE bit (ADCON0) to start con version.

5. Wait for A/D conversion to complete, by either:

Polling for the GO/DONE bit to be cleared (if

interrupts are disabled);

Waiting for the A/D interrupt.

6. Read A/D result register (ADRES), clear bit

ADIF if required.

7. For next conversion, go to step 1 or step 2 as

required. The A/D conversion time per bit is

defined as TAD. A minimum wait of 2 TAD is

required before next acquisition starts.

FIGURE 12-1: A/D BLOCK DIAGRAM

(Input Voltage)

VIN

VREF

(Reference

Voltage)

VDD

PCFG2:PCFG0

CHS2:CHS0

000 or

010 or

100 or

001 or

011 or

101

RE2/AN7(1)

RE1/AN6(1)

RE0/AN5(1)

RA5/AN4

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

111

110

101

100

011

010

001

000

A/D

Converter

Note 1: Not available on PIC16C73B.

11x

PIC16C63A/65B/73B/74B

DS30605D-page 82  1998-2013 Microchip Technology Inc.

12.1 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 12-2. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedanc e varie s over the devic e volt age

(VDD), Figure 12-2. The source impedance affects the

offset voltage at the analog input (due to pin leakage

current).

The maximum recommended impedance for ana-

log sources is 10 k. After the analo g input channe l is

selected (changed), the acquisition time (TACQ) must

pass before the conversion can be started.

To calculate the minimum acquisition time,

Equation 12-1 may be used. This equation assumes

that 1/2 LSb error is used (512 steps for the A/D). The

1/2 LSb er ror is the ma ximu m error allow ed for the A/D

to meet its specified resolution.

For more information, see the PIC® Mid-Range MCU

Family Refere nce Manual ( DS33023). In g eneral , how -

ever, given a maximum source impedance of 10 k

and a worst ca se temperature of 100 °C, T ACQ will be no

more than 16 sec.

FIGURE 12-2: ANALOG INPUT MODEL

EQUATION 12-1: ACQUISITION TIME

CPIN

Rs ANx

5 pF

VDD

VT = 0.6 V

VT = 0.6 V I leakage

RIC £ 1k

Sampling

Switch

SS RSS

CHOLD

= DAC capacitance

VSS

Sampling Switch

567891011

(k)

VDD

= 51.2 pF

± 500 nA

Legend: CPIN

I leakage

RIC

CHOLD

= input capacitance

= threshold voltage

= lea kage current at the pin due to

= interconnec t resistance

= sampling switch

= sample/hold capacitance (from DAC)

various junctions

TACQ =

Amplifier Settling Time +

Hold Capacitor Charging Time +

Temperature Coefficient

TAMP + TC + TCOFF

TAMP = 5 S

TC = - (51.2 pF)(1 k + RSS + RS) In(1/511)

TCOFF = (Temp -25C)(0.05 S/C)

 1998-2013 Microchip Technology Inc. DS30605D-page 83

PIC16C63A/65B/73B/74B

12.2 Selecting the A/D Conversion

Clock

The A/D conversion time per bit is defined as TAD. The

A/D conversion requires 9.5 TAD per 8-bit conversion.

The source of the A/D conversion clock is software

selectable. The four possible options for TAD are:

•2 T

OSC

•8 TOSC

•32 TOSC

• Internal RC oscillator ( 2 - 6 S)

For correct A/D conversions, the A/D conversion clock

(TAD) must be selected to ensure a minimum TAD time

(parameter #130).

12.3 Configuring Analog Port Pins

The ADCON1, TRISA and TRISE registers control the

operation of the A/D port pins. The port pins that are

desired as analog inputs must have their correspond-

ing TRIS bits set (input). If the TRIS bit is cleared (out-

put), the digital output level (VOH or VOL) will be

converted.

The A/D operation is independent of the state of the

CHS2:CHS0 bits and the TRIS bits.

12.4 A/D Conversions

Clearing the GO/DONE bit during a conversion will

abort the current conversion. The ADRES register will

NOT be updated with the partially completed A/D con-

version sample. That is, the ADRES register will con-

tinue to contain the value of the last completed

conversio n (or th e last v alue wr itten to the AD RES reg-

ister). Af t er the A/D convers ion is a borte d, a 2 TAD wait

is required before the next acquisition is started. After

this 2 TAD wait, an acquisition is automatically started

on the selected channel. The GO/DONE bit can then

be set to start another conversion.

12.5 A/D Operation During SLEEP

The A/D module can operate during SLEEP mode. This

requires that the A/D clock source be set to RC

(ADCS1:ADCS0 = 11). When the RC clock source is

selected, the A/D module waits one instruction cycle

before starting the conversion. This allows the SLEEP

instruction to be executed, which eliminates all digital

switchin g noise fro m the conv ersion. Whe n the conv er-

sion is completed, the GO/DONE bit will be cleared,

and the result loaded into the ADRES register. If the

A/D interrupt is enabled, the device will wake-up from

SLEEP. If the A/D in terrupt is not enabled, th e A/D mod-

ule will then be turned off, although the ADON bit will

remain set.

When the A/D clo ck s ource is anothe r cloc k option (not

RC), a SLEEP instruction will cause the present conv er-

sion t o be aborted and the A /D m odule to b e turn ed of f,

though the ADON bit will remain set.

Turning of f the A/D places the A/D modu le in it s lowes t

current consumption state.

12.6 Effects of a RESET

A device RESET forces all registers to their RESET

state. The A/D module is disabled and any conversion

in progress is aborted. All pins with analog functions

are conf igu red as analog inputs.

The ADRES regi ster will contain unknown data after a

Power-on Reset.

12.7 Use of the CCP Trigger

An A/D convers ion can be st arted by th e “special event

trigger” of the CCP2 module. This requires that the

CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-

grammed as 1011 and that the A/D m od ule is ena ble d

(ADON bit is set). When the trigger occurs, the

GO/DONE bit will be set, s tarting t he A/D conver sion,

and the Timer1 counter will be reset to zero. Timer1 is

reset to autom atical ly rep eat th e A/D ac quisi tion perio d

with min imal so ftware ov erhead (mov ing the ADR ES to

the desired location). The appropriate analog input

channel must b e selecte d and the mi nimum ac quisitio n

done before the “special event trigger” sets the

GO/DONE bit (start s a conversi on).

If the A/D module is not enabled (ADON is cleared),

then the “special event trigger” will be ignored by the

A/D module, but will still reset the Timer1 counter.

Note 1: When reading the port register, all pins

configured as analog input channels will

read as c le ared (a l ow l ev el). Pins config-

ured as digital inputs will convert an ana-

log input. Analog levels on a digitally

configu red i nput will not af fec t the co nver-

sion accuracy.

2: Analog le vels on any pin that is defined a s

a digital input, but not as an analog input,

may cause the input buffer to consume

current that is out of the devices specifi-

cation.

3: The TRISE reg ister is not prov ided on the

PIC16C73B.

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

Note: For the A/D module to operate in SLEEP,

the A/D clock source must be set to RC

(ADCS1:ADCS0 = 11). To perform an A/D

conversion in SLEEP, ensure the SLEEP

instruction immediately follows the instruc-

tion that sets the GO/DON E bit.

PIC16C63A/65B/73B/74B

DS30605D-page 84  1998-2013 Microchip Technology Inc.

TABLE 12-1: SUMMARY OF A/D REGISTERS (PIC16C73B/74B ONLY)

Address Name Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOR

Value on

all other

RESETS

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

0Dh PIR2 — — — — — — — CCP1IF ---- ---0 ---- ---0

8Dh PIE2 — — — — — — — CCP1IE ---- ---0 ---- ---0

1Eh ADRES A/D Result register xxxx xxxx uuuu uuuu

1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 0000 00-0

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

05h PORTA —— RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000

85h TRISA —— PORTA Data Direction register --11 1111 --11 1111

09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu

89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111

Legend: x = unknown, u = unchanged, - = unim plement ed, read as '0'. Shaded cells are not used for A/D conversion.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC6C63A/73B; always maintain these bits clear.

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PIC16C63A/65B/73B/74B

13.0 SPECIAL FEATURES OF THE

CPU

What sets a microcontroller apart from other proces-

sors are special circuits to deal with the needs of real-

time applications. The PIC16CXX family has a host of

such features intended to maximize system reliability,

minimize cost through elimination of external compo-

nent s, provide pow er saving opera ting modes an d offer

code protection. These are:

• Oscillator selection

• RESET

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• SLEEP

• Code protection

• ID locations

• In-Circuit Serial Programming (ICSP)

The PIC16CXX has a Watchdog Timer which can be

shut off only through configuration bits. It runs off its

own RC oscillator for added reliability. There are two

timers th at of fer neces sary de lays on power-up . One i s

the Oscill ator S tart-up T imer (OST), intended to keep the

chip in RESET until the crystal oscillator is stable. The

other is the Power-up Timer (PWRT), which provides a

fixed delay of 72 ms (nominal) on power-up only and is

designed to keep the part in RESET, while the power

supply stabilizes. With these two timers on-chip, most

applications need no exte rnal RESET circuitry.

SLEEP mode is designed to offer a very low current

power-down mode. The user can wake-up from SLEEP

through ex ternal RESET, WDT wake-up or through an

interrupt.

Several oscillator options are also made available to

allow the part to fit the application. The RC oscillator

option saves system cost, while the LP crystal option

saves power. A set of configuration bits are used to

select various options.

13.1 Configuration Bits

The con figurat ion bit s ca n be program med (r ead as '0')

or left unprogrammed (read as '1') to select various

device configurations. These bits are mapped in pro-

gram memory location 2007h.

The user will note that address 2007h is beyond the

user program memory space, and can be accessed

only during programming.

CP1 CP0 CP1 CP0 CP1 CP0 — BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0

bit 13 bit 0

bits 13-8,

5-4 CP1:CP0: Code Protection bits(2)

11 = Code protection off

10 = Upper half of program memory code protected

01 = Upper 3/4th of program memory code protected

00 = All memory is code protected

bit 7 Unimplemented: Read as '1'

bit 6 BODEN: Brown-out Reset Enable bit(1)

1 = BOR enabled

0 = BOR disabled

bit 3 PWRTE: Power-up Tim e r Enable bit(1)

1 = PWRT disabled

0 = PWRT enabled

bit 2 WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0 FOSC1:FOSC0: Oscillator Selection bits

11 = RC osc illator

10 = HS oscillator

01 = X T oscillator

00 = LP oscillator

Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of

PWRTE.

2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.

PIC16C63A/65B/73B/74B

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13.2 Oscillator Configurations

13.2.1 OSCILLATOR TYPES

The PIC16CXX can be operated in four different oscil-

lator modes. The user can program two configuration

bits (FOSC1 and FOSC0) to select one of these four

modes:

• LP Low Power Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC Resistor/Capacitor

13.2.2 CRYSTAL OSCILLATOR/CERAMIC

RESONATORS

In XT, LP, or HS modes, a crystal or ceramic resonator

is connected to the OSC1/CLKIN and OSC2/CLKOUT

pins to establish oscillation (Figure 13-1). The

PIC16CXX os cillator design requires the us e of a par-

allel cut cry stal. Us e o f a se ri es cut crys tal m ay g ive a

frequency out of the crystal manufacturers specifica-

tions. When in XT, LP or HS modes, the device can

have an external clock source to drive the OSC1/

CLKIN pin (Figure 13-2). See the PIC® Mid-Range

MCU Reference Manual (DS33023) for details on

building an external oscillator.

FIGURE 13-1: CRYSTAL/CERAMIC

RESONATOR OPERATION

(HS, XT OR LP

OSC CONFIGURATION)

FIGURE 13-2: EXTERNAL CLOCK INP UT

OPERATION ( HS, X T OR

LP OSC CONF IGURA TION )

XTAL

OSC2

(Note 1)

OSC1

RFSLEEP

To internal

logic

PIC16CXX

See Table 13-1 and Table 13-2 for recommended values of C1

and C2.

Note 1: A series res istor may be requi red fo r AT strip cut cr ys t al s.

OSC1

OSC2

Open

Clock from

ext. system PIC16CXX

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PIC16C63A/65B/73B/74B

TABLE 13-1: CERAMIC RESONATORS

TABLE 13-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

13.2.3 RC OSCILLATOR

For timing insensitive applications, the “RC” device

option offers additiona l cos t sav in gs . The RC osc il lat or

frequenc y is a fun ction of the suppl y vo lt a ge, the re sis -

tor (REXT) and capacitor (C EXT) values, and the operat-

ing temp erature. T he oscillato r frequency will vary from

unit to unit due to normal process variation. The differ-

ence in lead frame capacitance between package

types will also affect the oscillation frequency, espe-

cially for low CEXT values. The user also needs to take

into account variation due to tolerance of external R

and C components used. Figure 13-3 shows how the

R/C combination is connected to the PIC16CXX.

The oscillator frequency, divided by 4, is available on

the OSC2/CLKOUT pin, and can be used for test pur-

poses or to synchronize other logic (see Figure 3-2 for

waveform).

FIGURE 13-3: RC OSCILLATOR MODE

Ranges Tested:

Mode Freq OSC1 OSC2

XT 455 kHz

2.0 MHz

4.0 MHz

68 - 100 pF

15 - 68 pF

68 - 100 pF

15 - 68 pF

HS 8.0 MHz

16.0 MHz 10 - 68 pF

10 - 22 pF 10 - 68 pF

10 - 22 pF

Note: These values are for design guidance only.

See notes following Table 13-1 and Table 13-2.

Resonators Used:

455 kHz Panasonic EFO-A455K04B ± 0.3%

2.0 MHz Murata Erie CSA2.00MG ± 0.5%

4.0 MHz Murata Erie CSA4.00MG ± 0.5%

8.0 MHz Murata Erie CSA8.00MT ± 0.5%

16.0 MHz Murata Erie CSA16.00MX ± 0.5%

Note: Resonators used did not have built-in capacitors.

Osc Type Crystal

Freq Cap. Range

C1 Cap. Range

LP 32 kHz 33 pF 33 pF

200 kHz 15 pF 15 pF

XT 200 kHz 47-68 pF 47-68 pF

1 MHz 15 pF 15 pF

4 MHz 15 pF 15 pF

HS 4 MHz 15 pF 15 pF

8 MHz 15-33 pF 15-33 pF

20 MHz 15-33 pF 15-33 pF

Note: These values are for design guidance only.

See notes following Table 13-1 and Table 13-2.

Cryst als Used:

32 kHz Epson C-001R32.768K-A ± 20 PPM

200 kHz STD XTL 200.000KHz ± 20 PPM

1 MHz ECS ECS-10-13-1 ± 50 PPM

4 MHz ECS ECS-40-20-1 ± 50 PPM

8 MHz EPSON CA-301 8.000M-C ± 30 PPM

20 MHz EP SON CA-3 01 20.000M- C ± 30 PPM

Note 1: Higher cap acita nce increase s the stabi lity

of the oscillator, but also increases the

start-up time.

2: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate values of external compo-

nents.

3: Rs may be required in HS mode, as well

as XT mode, to av oid ove rdrivi ng cryst als

with low drive level specification.

4: Osci llator performance should be verified

at the expected voltage and temperature

extremes in which the application is

expected to operate.

OSC2/CLKOUT

CEXT

VDD

REXT

VSS

PIC16CXX

OSC1

FOSC/4

Internal

Clock

Recommended Values : REXT = 3 kW to 100 kW

CEXT = 20 pf to 30 pF

PIC16C63A/65B/73B/74B

DS30605D-page 88  1998-2013 Microchip Technology Inc.

13.3 RESET

The PIC1 6CXX d ifferentiates bet ween various kinds of

RESET:

• Power-on Reset (POR)

•MCLR

Reset during normal operation

•MCLR

Reset during SLEEP

• WDT Reset (normal operation)

• Brown-out Reset (BOR)

Some registers are not affected in any RESET condi-

tion; the ir stat us is unk nown on POR and un changed i n

any other RESET. Most other registers are reset to a

“RESET state” on POR, o n the MC LR and WDT Reset,

on MCLR Reset during SLEEP, and on BOR. The TO

and PD bits are set or cleared differently in different

RESET situations, as indicated in Table 13-4. These

bits are used in so f t ware to d eterm in e the nature of the

RESET. See Table 13-6 for a full d escriptio n of RESET

states of all regi ste rs.

A simplifie d block diagram of the on-chip RESET circu it

is sh own in F igure 13-4.

The PIC device s have a MCLR noise filter in t he MCLR

Reset path. The filter will detect and ignore small

pulses.

It should be noted that internal RESET sources do not

drive MCLR pin low.

FIGURE 13-4: SIMPLIFI ED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

RESET

MCLR

VDD

OSC1

WDT

Module

VDD Rise

Detect

OST/PWRT

On-chip

RC OSC

WDT

Time-out

Power-on Reset

OST

10-bit Ripple Counter

PWRT

Chip Reset

10-bit Ripple Counter

Reset

Enable OST

Enable PWRT

SLEEP

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

Brown-out

Reset BODEN

(Note 1)

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PIC16C63A/65B/73B/74B

13.4 RESETS

13.4.1 POWER-ON RESET (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (parameters D003 and D004, in

the range of 1.5V - 2.1V). To take advantage of the

POR, jus t ti e th e M CLR pin direct ly (or through a resis-

tor) to VDD. This will elim inate ex ternal RC component s

usually needed to create a POR.

When the device starts normal operation (exits the

RESET condition), device operating parameters (volt-

age, frequency, temperature) must be met to ensure

operation. If these conditions are not met, the device

must be held in RESET until the operating conditions

are met . T he dev ice ma y be held in RESET by k eepin g

MCLR at Vss.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting.”

13.4.2 POWER-UP TIMER (PWRT)

The Power-up Timer provides a fixed 72 ms nominal

time-out on power-up from the POR. The PWRT oper-

ates on an internal RC oscillator. The device is kept in

RESET as long as the PWRT is active. The PWRT’s

time delay allows VDD to rise to an acceptable level. A

configuration bit is provided to enable/disable the

PWRT.

The power-up time delay will vary from chip to chip, due

to VDD, temperature and process variation. See DC

parameters for details (TPWRT, parameter #33).

13.4.3 OSCILLATOR START-UP TIMER

(OST)

The Oscillator Start-up Timer provides a delay of 1024

oscillator cycles (from OSC1 input) after the PWRT

delay, if ena bled. Thi s helps t o ensur e that th e crystal

oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

13.4.4 BROWN-OUT RESET (BOR)

The configuration bit, BODEN, can enable or disable

the Brown-out Reset circuit. If VDD falls below VBOR

(parameter D005, about 4V) for longer than TBOR

(param et er #35, about 100S), the brown-out s itua tio n

will reset the device. If VDD falls below VBOR for less

than TBOR, a RESET may not occur.

Once the brown-out occurs, the device will remain in

Brown-out Reset until VDD rises above VBOR. The

Power-up Timer then keeps the device in RESET for

TPWRT (pa rameter #3 3, about 72 mS). If VDD should fall

below VBOR during TPWRT, the Brown-out Reset pro-

cess will restart when VDD rises above VBOR with the

Power-up Timer Reset. The Power-up Timer is always

enabled when the Brown-out Reset circuit is enabled,

regardless of the state of the PWRT configuration bit.

13.4.5 TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows: the

PWRT delay starts (if enabled) when a POR occurs.

Then, OST starts counting 1024 oscillator cycle s w he n

PWRT ends (LP, XT, HS). When the OST ends, the

device comes out of RESET.

If MCLR is kept low long enough, the time-outs will

expire. Bring ing MCLR high will begin execution imme-

diately . This is useful for testing purposes or to synchro-

nize more than one PIC16CXX device operating in

parallel.

Table 13-5 shows the RESET conditions for the

STATUS, PCON and PC registers, while Table 13-6

shows the RESET conditions for all the regis ters.

13.4.6 POWER CONTROL/STATUS

The Brown -out Reset S t atus bit, BOR , is unknown on a

POR. It must be set by the user and checked on sub-

sequent RESETS to see if bit BOR was cleared, indi-

cating a BOR occurred. The BOR bit is not predictable

if the Brown-out Reset circuitry is disabled.

The Power-on Reset Status bit, POR, is cleared on a

POR and unaffected otherwise. The user must set this

bit following a POR and check it on subsequent

RESETS to see if it has been cleared.

PIC16C63A/65B/73B/74B

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TABLE 13-3: TIME-OUT IN VARIOUS SITUATIONS

TABLE 13-4: STATUS BITS AND THEIR SIGNIFICANCE

Legend: x = don’t care, u = unch ang ed

TABLE 13-5: RESET CONDITION FOR SPECIAL REGISTERS

Oscillator Configuration Power-up Brown-out Wake-up from SLEEP

PWRTE = 0 PWRTE = 1

XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC

RC 72 ms — 72 ms —

POR BOR TO PD

0x11Power-on Reset

0x0xIllegal, TO is set on POR

0xx0Illegal, PD is set on POR

1011Brown-out R ese t

1101WDT Reset

1100WDT Wake-up

11uuMCLR Reset during normal operation

1110MCLR Reset during SLEEP or interrupt wake-up from SLEEP

Condition Program

Counter STATUS

PCON

Power-on Reset 000h 0001 1xxx ---- --0x

MCLR Reset during normal operation 000h 000u uuuu ---- --uu

MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu

WDT R eset 000h 0000 1uuu ---- --uu

WDT Wake-up PC + 1 uuu0 0uuu ---- --uu

Brown-out Reset 000h 000x xuuu ---- --u0

Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'

Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

IRP RP1 RP0 TO PD ZDC C

——————PORBOR

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PIC16C63A/65B/73B/74B

TABLE 13-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Brown-out Reset MCLR Resets

WDT Reset W ake-up v ia WDT or

Interrupt

W 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu

INDF 63A 65B 73B 74B N/A N/A N/A

TMR0 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu

PCL 63A 65B 73B 74B 0000h 0000h PC + 1(2)

STATUS 63A 65B 73B 74B 0001 1xxx 000q quuu(3) uuuq quuu(3)

FSR 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu

PORTA 63A 65B 73B 74B --0x 0000 --0u 0000 --uu uuuu

PORTB 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu

PORTC 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu

PORTD 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu

PORTE 63A 65B 73B 74B ---- -xxx ---- -uuu ---- -uuu

PCLATH 63A 65B 73B 74B ---0 0000 ---0 0000 ---u uuuu

INTCON 63A 65B 73B 74B 0000 000x 0000 000u uuuu uuuu(1)

PIR1

63A 65B 73B 74B -0-- 0000 -0-- 0000 -u-- uuuu(1)

63A 65B 73B 74B -000 0000 -000 0000 -uuu uuuu(1)

63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu(1)

PIR2 63A 65B 73B 74B ---- ---0 ---- ---0 ---- ---u(1)

TMR1L 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu

TMR1H 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu

T1CON 63A 65B 73B 74B --00 0000 --uu uuuu --uu uuuu

TMR2 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu

T2CON 63A 65B 73B 74B -000 0000 -000 0000 -uuu uuuu

SSPBUF 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu

SSPCON 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu

CCPR1L 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1H 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu

CCP1CON 63A 65B 73B 74B --00 0000 --00 0000 --uu uuuu

RCSTA 63A 65B 73B 74B 0000 -00x 0000 -00x uuuu -uuu

TXREG 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu

RCREG 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu

CCPR2L 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu

CCPR2H 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu

CCP2CON 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu

ADRES 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition

Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

3: See Table 13-5 for RESET value for specific condition.

PIC16C63A/65B/73B/74B

DS30605D-page 92  1998-2013 Microchip Technology Inc.

ADCON0 63A 65B 73B 74B 0000 00-0 0000 00-0 uuuu uu-u

OPTION_REG 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu

TRISA 63A 65B 73B 74B --11 1111 --11 1111 --uu uuuu

TRISB 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu

TRISC 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu

TRISD 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu

TRISE 63A 65B 73B 74B 0000 -111 0000 -111 uuuu -uuu

PIE1

63A 65B 73B 74B --00 0000 --00 0000 --uu uuuu

63A 65B 73B 74B 0-00 0000 0-00 0000 u-uu uuuu

63A 65B 73B 74B -000 0000 -000 0000 -uuu uuuu

63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu

PIE2 63A 65B 73B 74B ---- ---0 ---- ---0 ---- ---u

PCON 63A 65B 73B 74B ---- --0q(3) ---- --uu ---- --uu

PR2 63A 65B 73B 74B 1111 1111 1111 1111 1111 1111

SSPADD 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu

SSPSTAT 63A 65B 73B 74B --00 0000 --00 0000 --uu uuuu

TXSTA 63A 65B 73B 74B 0000 -010 0000 -010 uuuu -uuu

SPBRG 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu

ADCON1 63A 65B 73B 74B ---- -000 ---- -000 ---- -uuu

TABLE 13-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset MCLR Resets

WDT Reset W ake-up v ia WDT or

Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition

Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

3: See Table 13-5 for RESET value for specific condition.

 1998-2013 Microchip Technology Inc. DS30605D-page 93

PIC16C63A/65B/73B/74B

13.5 Interrupts

The Interrupt Control register (INTCON) records indi-

vidual interrupt requests in flag bits. It also has individ-

ual and global i nterrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>),

enables (if set) all unmasked interrupts, or disables (if

cleared ) all i nterrupt s. W hen bit GIE i s enab led, a nd an

inter rupt’s flag bit and mask bit are s et, the int errupt will

vector immediately. Individual interrupts can be dis-

abled through their corresponding enable bits in vari-

ous registers. Individual interrupt bits are set,

regardless of the status of the GIE bit. The GIE bit is

cleared on RESET.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine, as well as sets the GIE bit, which

re-enable s inte rrup t s.

The RB0/INT pin interrupt, the RB port change in terrupt

and the TMR0 overflow interrupt flags are contained in

the INTCON register.

The periphe ral interru pt flag s are co nt ained in the spe-

cial fu nctio n registers PIR1 and PIR2. The corres pond-

ing interrupt enable bits are contained in special

function registers PIE1 and PIE2 and the peripheral

inter rupt enabl e bit is cont ain ed in spec ial func tion reg-

ister INTCON.

When an interrupt is responded to, the GIE bit is

cleared to disable any further interrupt, the return

address is pus hed onto t he sta ck, and t he PC is lo aded

with 0004h. Once in the Interrupt Service Routine, the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bit(s) must be

cleared in software before re-enabling interrupts to

avoid recursive interrupts.

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs. The latency

is the sa me for one or two cycle instru cti ons . Indi vi dua l

interrupt flag bits are set, regardless of the status of

their corresponding mask bit, PEIE bit, or the GIE bit.

Note: Indiv idual interrupt fl ag bits are s et, regard-

less of the status of their corresponding

mask bit, or the GIE bit.

Note: If an int errupt occurs while the Globa l Inter-

rupt Enable (GIE) bit is being cleared, the

GIE bit may unintentionally be re-enabled

by the user’ s Interrupt Service Routine (the

RETFIE instruction). The events that

would cause this to occur are:

1. An instructio n clears the G IE bit while a n

interr upt is ac kno wledged.

2. The program branches to the interrupt

vector and executes the Interrupt

Service Routi ne.

3. The Interrupt Se rvice Routine c ompletes

the execu tion of the RETFIE instruction.

This causes the GIE bit to be set

(enables interrupts), and the program

returns to the instruction after the one

which was meant to disable interrupts.

Perform the following to ensure that inter-

rupts are globally disabled:

LOOP BCF INTCON, GIE ; Disable global

; interrupt bit

BTFSC INTCON, GIE ; Global interrupt

; disabled?

GOTO LOOP ; NO, try again

: ; Yes, continue

; with program

; flow

PIC16C63A/65B/73B/74B

DS30605D-page 94  1998-2013 Microchip Technology Inc.

FIGURE 13-5: INTERRUPT LOGIC

13.5.1 INT INTERRUPT

The external interrupt on RB0/INT pin is edge trig-

gere d: eithe r rising if bit INTEDG (OPTIO N_REG<6> )

is set, or falling if the INTEDG bit is clea r. When a valid

edge appears on the RB0/INT pin, flag bit INTF

(INTCON<1>) is set. This interrupt can be disabled by

clearing enable bit INTE (INTCON<4>). Flag bit INTF

must be cleared in software in the Interrupt Service

Routin e before re-enablin g this interrupt. The INT in ter-

rupt can wa ke-up the processor from SLEEP, if bit INTE

was set prior to going into SLEEP. The status of global

interr upt enabl e bit GIE dec ides w hether or no t the pro-

cesso r branche s to the in terrupt ve cto r followin g wak e-

up. See Section 13.8 for details on SLEEP mode.

13.5.2 TMR0 INTERRUPT

An overflow (FFh  00h) in the TMR0 register will set

flag bit T0IF (INTCON<2>). The interrupt can be

enabled/disabled by setting/clearing enable bit T0IE

(INTCON<5>) (see Section 6.0).

13.5.3 PORTB INTERRUPT-ON-CHANGE

An input change on PORTB<7:4> sets flag bit RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit RBIE (INTCON<4>).

(Section 5.2)

PSPIF

PSPIE ADIF

ADIE

RCIF

RCIE

TXIF

TXIE

SSPIF

SSPIE

CCP1IF

CCP1IE

TMR2IF

TMR2IE

TMR1IF

TMR1IE

T0IF

T0IE

INTF

INTE

RBIF

RBIE

GIE

PEIE

Wake-up (If in SLEEP mode)

Interrupt to CPU

CCP2IE

CCP2IF

The following table shows which devices have which interrupts.

Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF CCP2IF

PIC16C63A Yes Yes Yes – – Yes Yes Yes Yes Yes Yes Yes

PIC16C65B Yes Yes Yes Yes – Yes Yes Yes Yes Yes Yes Yes

PIC16C73B Yes Yes Yes – Yes Yes Yes Yes Yes Yes Yes Yes

PIC16C74B Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

Note: If a change on the I/O pin should occur

when th e read o peratio n is b eing ex ecuted

(start of the Q2 cycle), the n the RBIF inter-

rupt flag may not get set.

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PIC16C63A/65B/73B/74B

13.6 Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Users may wish to save key registers dur-

ing an interrupt i.e., W register and STATUS register.

This will have to be implemented in software.

Exampl e 13-1 sto res and resto res the STATUS, W , and

PCLATH registers. The register W_TEMP must be

defined in each bank and must be defined at the same

offset from the bank base address (i.e., if W_TEMP is

defined at 0x20 in bank 0, it must also be defined at

0xA0 in bank 1).

The exam ple:

a) Stores the W register.

b) Stores the STATUS register in bank 0.

c) Stores the PCLATH register.

d) Executes the ISR code.

e) Restores the STATUS register

(and bank select bit).

f) Restores the W and PCLATH registers.

EXAMPLE 13-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM

MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero

SWAPF STATUS,W ;Swap status to be saved into W

CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0

MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register

MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3

MOVWF PCLATH_TEMP ;Save PCLATH into W

(ISR) ;User ISR code goes here

MOVF PCLATH_TEMP, W ;Restore PCLATH

MOVWF PCLATH ;Move W into PCLATH

SWAPF STATUS_TEMP, W ;Swap STATUS_TEMP register into W

;(sets bank to original state)

MOVWF STATUS ;Move W into STATUS register

SWAPF W_TEMP,F ;Swap W_TEMP

SWAPF W_TEMP,W ;Swap W_TEMP into W

13.7 Watchdog Timer (WDT)

The W atchdog T imer is a free running on-chip RC oscil-

lator, which doe s not requ ire any external co mpone nts .

This RC oscillator is separate from the RC oscillator of

the OSC1/CLKIN pin. The WDT will run, even if the

clock on the OS C1 /CLKIN an d OSC2 /C LKO UT pin s of

the device has been stopped, for example, by execu-

tion of a SLEEP instruction.

During normal operation, a WDT time-out generates a

device RESET (W atchdog T imer Reset). If the device is

in SLEEP mode, a WDT time-out causes the device to

wake-up and resume normal operation (Watchdog

Timer Wake-up).

The WDT can be permanently disabled by clearing

configuration bit WDTE (Section 13.1).

13.7.1 WDT PERIOD

The WDT has a nominal time-out period of 18 ms

(parameter #31, TWDT). The time-out periods vary with

temperature, VDD, and process variations. If longer

time-out periods ar e desired, a p rescaler with a division

ratio of up to 1:128 can be as si gned to the WDT und er

software control, by writing to the OPTION register.

Time-out periods up to 128 TWDT can be real iz ed.

The CLRWDT and SLEEP instructions clear the WDT

and the pos tscaler, if assigned to the WD T. In addition,

the SLEEP i nstruction prevent s the W D T from ge nera t-

ing a RESET, but will allo w the WDT to wake the device

from SLEEP mode .

The TO bit in the STATUS register will be cleared upon

a WDT time-ou t.

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13.7.2 WDT PROGRAMMIN G

CONSIDERATIONS

It should also be taken into account that under worst

case conditi ons (VDD = Min., Temperature = Max., and

max. WDT prescaler), it may take several seconds

before a WDT time-out occurs.

FIGURE 13-6: WATC HDOG TIMER BLOCK DIAGRAM

TABLE 13-7: SUMMARY OF WATCHDOG TIMER REGISTERS

Note: When a CLRWDT instruction is executed

and the prescaler is assigned to the WDT,

the presc ale r cou nt will be cleared, but the

prescaler assignment is not changed.

From TMR0 Clock Source

(Figure 6-1)

To TMR0 MUX (Figure 6-1)

Postscaler

WDT Timer

WDT

Enable Bit

PSA

8 - to - 1 MUX PS2:PS0

MUX PSA

WDT

Time-out

Note: PSA and PS2:PS0 are bits in the OPTION register.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2007h Con fig. bits –BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0

81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

Legend: Shaded cells are not used by the Watchdog Timer.

Note 1: See Register 13-1 for operation of these bits.

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13.8 Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP

instruction.

If enabled, the WDT will be cleared but keeps running,

the PD bit (STATUS<3>) is cleared, the TO (STA-

TUS<4>) bit is set, and the oscillator driver is turned off.

The I/O ports maintain the status they had, before the

SLEEP instruction was executed (driving high, low, or

hi-impedance).

For lo west curr ent c onsum pti on in this mo de, plac e all

I/O pins at either VDD or VSS, ensure no external cir-

cuitr y is dr awing cu rrent from the I /O pin, power -down

the A/D, and disable external clocks. Pull all I/O pins

that are hi-impedance inputs, hi gh or low externally, to

avoid s witchi ng curre nts caus ed by fl oating input s. Th e

T0CKI input should also be at VDD or VSS for lowest

current consumption. The contribution from on-chip

pull-ups on PORTB should also be considered.

The MCLR pin must be at a logic high level (VIHMC).

13.8.1 WAKE-UP FROM SLEEP

The device can wake up from SLEEP through one of

the following events:

1. External RESET input on MCLR pin.

2. Watchdog Timer Wake-up (if WDT was

enabled).

3. Interrupt from INT pin, RB port change or a

Peripheral Interrupt.

External MCLR Reset will cause a device RESET. All

other events are considered a continuation of program

execut ion and c aus e a “wak e-u p”. The TO and PD bits

in the STATUS register can be used to determine the

cause of device RESET. The PD bit, which is set on

power-up, is cleared when SLEEP is invoked. The TO

bit is cleared if a WDT time-out occurred (and caused

wake-up).

The follo wing periph eral interrupt s can wake the device

from SLEEP:

1. TMR1 interrupt. T im er1 must be operating a s an

asynchronous counter.

2. SSP (START/STOP) bit detect interrupt.

3. SSP transmi t or receive in Slave mode

(SPI/I2C).

4. CCP Capture mode interrupt.

5. Parallel Slave port read or write

(PIC16C65B/74B only).

6. A/D conversion (when A/D clock source is RC).

7. USART TX or R X (Synchrono us Slave mode) .

Other peri pherals cannot g enerate interrup ts since dur-

ing SLEEP, no on-chip Q cloc ks are present.

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is pre-fetched. For the device to

wake-up thro ugh an int errup t eve nt, the co rres pon din g

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

ins tructi on afte r the SLEEP instruction. If the GIE bit is

set (enabl ed), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address (0004h). In cases where the execution of

the instruction following SLEEP is not desirable, the

user should have a NOP after the SLEEP instruction.

13.8.2 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and inte rrupt fla g bit s et, one of the fo llow ing wil l occu r:

• If the interrupt occurs before the ex ecution of a

SLEEP instru ct ion, the SLEEP instruction will com-

plete as a NOP. Therefore, the WDT and WDT

pos tsc aler will not be cleared, the TO bit will not

be set and PD bit will not be cleared.

• If the interrupt occurs during or after the execu-

tion of a SLEEP instruction, the device will imme-

diately wake up from sleep. The SLEEP

instruction will be completely executed before the

wake-up. Therefore, the WDT and WDT

postsc aler w ill be cleared, the TO bit will be set

and the PD bit will be cleared.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP instr uction ex ecuted , test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

To ensure that the WDT is cleared, a CLRWDT inst ruc-

tion should be executed before a SLEEP instruction.

PIC16C63A/65B/73B/74B

DS30605D-page 98  1998-2013 Microchip Technology Inc.

FIGURE 13-7: WAKE-UP FROM SLEEP THROUGH INTERRUPT

13.9 Program Verification/Code

Protection

If the code protection bit(s) have not been pro-

grammed, the on-chip program memory can be read

out for verification purpos es.

13.10 ID Locat ions

Four memory locatio ns (2000h - 2003h) are designate d

as ID locations where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution, but are read-

able and writable during program/verify. It is recom-

mended that only the four leas t signific ant bits of the ID

location are used.

13.11 In-Circuit Serial Programming

PIC16CXX microcontrollers can be serially pro-

grammed while in the end application circuit. This is

simply don e with two lines fo r clo ck and data, and thre e

other lines for power, ground and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices, and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware or a custom firm-

ware to be programmed.

The device is placed into a Program/Verify mode by

holding the RB6 and RB7 pins low, while raising the

MCLR (VPP) pin from VIL to VIHH (see programming

specification). RB6 becomes the programming clock

and RB7 becomes the programming data. Both RB6

and RB7 are Schmitt Trigger inputs in this mode.

After RESET, to place the device into Programming/

Verify mode, the program counter (PC) is at location

00h. A 6-bit command is then supplied to the device.

Depending on the command, 14 bits of program dat a are

then supplied to or from the device, depending if the

command was a load or a read. For complete details of

serial programming, please refer to the PIC16C6X/7X

Programming Specifications (Literature #DS30228).

FIGURE 13-8: TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF Flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

PC PC+1 PC+2

Inst( PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency(2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2 0004h 0005h

Dummy cycle

TOST(2)

PC+2

Note 1: XT, HS or LP oscillator mode assumed.

2: TOST = 1024Tosc (drawing not to scale). This delay is not present in RC osc mode.

3: GIE = '1' assumed. After wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.

4: CLKOUT is not available in these osc modes, but shown here for timing reference.

Note: Microchip does not recommend code pro-

tecting windowed devices. Devices that

are co de prote cted ma y be eras ed, but n ot

programmed agai n.

External

Connector

Signals

To Normal

Connections

To Normal

Connections

PIC16CXX

VDD

VSS

MCLR/VPP

RB6

RB7

+5V

VPP

CLK

Data I/O

VDD

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14.0 INSTRUCTION SET SUMMARY

Each PIC16CXX instruction is a 14-bit word divided

into an OPCODE, which specifies the instruction type

and one or more operands, which further specify the

operation of the instruction. The PIC16CXX instruction

set summary in Table 14-2 lists byte-oriented, bit-ori-

ented, and literal and control operations. Table 14-1

shows the opcode field descriptions.

For byte-oriented instructio ns, 'f' rep r es ents a file reg-

ister designator and 'd' represents a destination desig-

nator. The file register designator specifies which file

The desti nation designator specifies where the resul t of

the operation is to be placed. If 'd' is zero, the result is

placed in the W register . If 'd' is one, the result is placed

in the file register specified in the instruction.

For bit-oriented instructions, 'b' represents a bit field

designator which sel ec ts the number of the bit af fe cte d

by the oper ation, w hile 'f' represen ts the address of the

file in which the bit is located.

For literal and control operations, 'k' represents an

eight or eleven bit constant or literal value.

TABLE 14-1: OPCODE FIELD

DESCRIPTIONS

The instruction set is highly orthogonal and is grouped

into three basic categories:

•Byte-oriented ope rati ons

•Bit-oriented operations

•Literal and control operations

All instructions are executed within one single instruc-

tion cycle, unless a conditional test is true or the pro-

gram counter is changed as a result of an instruction.

In thi s cas e, t he ex ec u ti o n tak es tw o in s tru ct i o n cy cles

with the second cycle executed as a NOP. One instruc-

tion cycle consists of four oscillator periods. Thus, for

an osc illator frequency of 4 M Hz, th e normal i nstructio n

executi on tim e is 1 s. If a con dition al tes t is tr ue or th e

program counter is changed as a result of an instruc-

tion, the instruction execution time is 2 s.

Table 14-2 lists the instructions recognized by the

MPASMTM assembler.

Figur e 14-1 shows the ge neral fo rmats th at the instruc -

tions can have.

All examples use the following format to represent a

hexadecimal number:

0xhh

where h signifies a hexadecimal digit.

FIGURE 14-1: GENERAL FORMAT FOR

INSTRUCTIONS

Field Description

fRegister file address (0x00 to 0x7F)

WWorking register (accumulator)

bBit address within an 8-bit file r egister

kLiteral field, constant data or label

Don't care location (= 0 or 1)

The assembler will generate code with x = 0. It is the

recommended form of use for compatibility with all

Microchip software tools.

Destination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1

label Label name

TOS Top-of-Stack

PC Program Counter

PCLATH Program Counter High Latch

GIE Global Interrupt Enable bit

WDT Wat chdog Timer/Counter

TO Time-out bit

PD Power-down bit

dest Destination either the W register or the specified

[ ] Options

( ) Contents

Assigned to

< > Register bit field

In the set of

talics

User defined term (font is courier)

Note: To maintain upward compatibility with

future PIC16CXX products, do not use the

OPTION and TRIS instr uctions .

Byte-oriented file register operations

13 8 7 6 0

d = 0 for destination W

OPCODE d f (FILE # )

d = 1 for destination f

f = 7-bit file register address

Bit-oriented file register operations

13 10 9 7 6 0

OPCODE b (BIT # ) f (FIL E #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

13 8 7 0

OPCODE k (l i te ra l )

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal)

k = 11-bit immediate value

General

CALL and GOTO instructions only

PIC16C63A/65B/73B/74B

DS30605D-page 100  1998-2013 Microchip Technology Inc.

TABLE 14-2: PIC16CXX INSTRUCTION SET

Mnemonic,

Operands Description Cycles 14-Bit Opcode Stat us

Affected Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERAT IONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

Add W and f

AND W with f

Clear f

Clear W

Compleme nt f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

1(2)

0111

0101

0001

1001

0011

1011

1010

1111

0100

1000

0000

1101

1100

0010

1110

0110

dfff

lfff

0000

dfff

lfff

0xx0

dfff

ffff

0011

ffff

0000

ffff

C,DC,Z

1,2

1,2,3

1,2

1,2,3

1,2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

00bb

01bb

10bb

11bb

bfff

ffff

1,2

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

Inclusive OR liter a l with W

Move literal to W

Re tu r n from interrupt

Return with literal in W

Return from Subrou tine

Go into standby mode

Subtract W from literal

Exclusive OR literal with W

111x

1001

0kkk

0000

1kkk

1000

00xx

0000

01xx

0000

110x

1010

kkkk

0110

kkkk

0000

kkkk

0000

0110

kkkk

0100

kkkk

1001

kkkk

1000

0011

kkkk

C,DC,Z

TO,PD

C,DC,Z

Note 1: When an I/O register is modified as a function of it self ( e.g., MOVF PORTB, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external

device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if

assigned to the Timer0 Module.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

Note: Additional information on the mid-range instruction set is available in the PICmicroTM Mid-Range MCU

Family Reference Manual (DS33023).

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14.1 Instruction Descriptions

ADDLW Add Literal and W

Syntax: [label] ADDLW k

Operands: 0  k  255

Operation: (W) + k  (W)

Status Affected: C, DC, Z

Description: The contents of the W register are

added to the eight bit literal 'k' and the

result is placed in the W register.

ADDWF Add W and f

Syntax: [label] ADDWF f,d

Operands: 0  f  127

d 

Operation: (W) + (f)  (destination)

Status Affected: C, DC, Z

Description: Add the contents of the W register

with register 'f'. If 'd' is 0, the result is

stored in the W register. If 'd' is 1, the

result is stored back in register 'f'.

ANDLW AND Literal with W

Syntax: [label] ANDLW k

Operands: 0  k  255

Operation: (W) .AND. (k)  (W)

Status Affected: Z

Description: The contents of W register are

AND’ed with the eight bit literal 'k'.

The result is placed in the W register.

ANDWF AND W with f

Syntax: [label] ANDWF f,d

Operands: 0  f  127

d 

Operation: (W) .AND. (f)  (destination)

Status Af fe cted: Z

Description: AND the W register with register 'f'. If

'd' is 0, the result is stored in the W

back in register 'f'.

BCF Bit Clear f

Syntax: [label] BCF f,b

Operands: 0  f  127

0  b  7

Operation: 0  (f<b>)

Status Af fe cted: None

Description: Bit 'b' in register 'f' is cleared.

BSF Bit Set f

Syntax: [label] BSF f,b

Operands: 0  f  127

0  b  7

Operation: 1  (f<b>)

Status Af fe cted: None

Description: Bit 'b' in register 'f' is set.

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BTFSS Bit Test f, Skip if Set

Syntax: [label] BTFSS f,b

Operands: 0  f  127

0  b < 7

Operation: skip if (f<b>) = 1

Status Affected: None

Description: If bit 'b' in register 'f' is '0', the next

instruction is executed.

If bit 'b' is '1', then the next instruction

is discarded and a NOP is executed

instead making this a 2TCY instruction.

BTFSC Bit Test, Skip if Clear

Syntax: [label] BTFSC f,b

Operands: 0  f  127

0  b  7

Operation: skip if (f<b>) = 0

Status Affected: None

Description: If bit 'b' in register 'f' is '1', the next

instruction is executed.

If bit 'b', in register 'f', is '0', the next

instruction is discarded, and a NOP is

executed instead, making this a 2 TCY

instruction.

CALL Ca ll Subroutine

Syntax: [ label ] CALL k

Operands: 0  k  2047

Operation: (PC)+ 1 TOS ,

k  PC<10:0>,

(PCLATH<4:3>)  PC<12:11>

Status Affected: None

Description: Call Subroutine. First, return address

(PC+1) is pushed onto the stack. The

eleven bit immediate address is

loaded into PC bits <10:0>. The upper

bits of the PC are loaded from

PCLATH. CALL is a two-cycle

instruction.

CLRF Clear f

Syntax: [

label

] CLRF f

Operands: 0  f  127

Operation: 00h  (f)

1  Z

Status Af fe cted: Z

Description: The contents of register 'f' are cleared

and the Z bit is set.

CLRW Clear W

Syntax: [ label ] CLRW

Operands: None

Operation: 00h  (W)

1  Z

Status Af fe cted: Z

Description: W register is cleared. Zero bit (Z) is

set.

CLRWDT Clear Watchdog Ti m er

Syntax: [ label ] CLRWDT

Operands: None

Operation: 00h  WDT

0  WDT prescaler,

1  TO

1  PD

Status Af fe cted: TO, PD

Description: CLRWDT instruction resets the Watch-

dog T imer. It also resets the prescaler

of the WDT. Status bits TO and PD

are set.

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COMF Complement f

Syntax: [ label ] COMF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f)  (destination)

Status Affected: Z

Description: The contents of register 'f' are comple-

mented. If 'd' is 0, the result is stored

in W. If 'd' is 1, the result is stored

back in register 'f'.

DECF Decrement f

Syntax: [label] DECF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) - 1  (destination)

Status Affected: Z

Description: Decrement register 'f'. If 'd' is 0, the

result is stored in the W register . If 'd'

is 1, the result is stored back in

DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) - 1  (destination);

skip if result = 0

Status Affected: None

Description: The contents of register 'f' are decre-

mented. If 'd' is 0, the result is placed

in the W register. If 'd' is 1, the result is

placed back in register 'f'.

If the result is 1, the next instruction is

executed. If the result is 0, then a NOP

is executed instead making it a 2 TCY

instruction.

GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0  k  2047

Operation: k  PC<10:0>

PCLATH<4:3>  PC<12:11>

Status Af fe cted: None

Description: GOTO is an unconditional branch. The

eleven bit immediate value is loaded

into PC bits <10:0>. The upper bits of

PC are loaded from PCLATH<4:3>.

GOTO is a two-cycle instruction.

INCF Increment f

Syntax: [ label ] INCF f,d

Operands: 0  f  127

d  [0,1 ]

Operation: (f) + 1  (destination)

Status Af fe cted: Z

Description: The contents of register 'f' are incre-

mented. If 'd' is 0, the result is placed

in the W register . If 'd' is 1, the result is

placed back in register 'f'.

INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) + 1  (destination),

skip if result = 0

Status Af fected: None

Description: The contents of register 'f' are incre-

mented. If 'd' is 0, the result is placed

in the W register. If 'd' is 1, the result is

placed back in register 'f'.

If the result is 1, the next instruction is

executed. If the result is 0, a NOP is

executed instead making it a 2 TCY

instruction.

PIC16C63A/65B/73B/74B

DS30605D-page 104  1998-2013 Microchip Technology Inc.

IORLW Inclusive OR Literal with W

Syntax: [ label ] IORLW k

Operands: 0  k  255

Operation: (W) .OR. k  (W)

Status Affected: Z

Description: The contents of the W register are

OR’ed with the eight bit literal 'k'. The

result is placed in the W register.

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f,d

Operands: 0  f  127

d  [0,1]

Operation: (W) .OR. (f)  (destinati on)

Status Affected: Z

Description: Inclusive OR the W register with regis-

ter 'f'. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

MOVF Move f

Syntax: [ label ] MOVF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f)  (destination )

Status Affected: Z

Description: The contents of register f are m oved

to a destination dependant upon the

status of d. If d = 0, destination is W

file register since status flag Z is

affected.

MOVLW Move Literal to W

Syntax: [ label ] MOVLW k

Operands: 0  k  255

Operation: k  (W)

Status Af fe cted: None

Description: The eight bit literal 'k' is loaded into

W register. The don’t cares will

assemble as 0’s.

MOVWF M ove W to f

Syntax: [ label ] MOVWF f

Operands: 0  f  127

Operation: (W)  (f)

Status Af fe cted: None

Description: Move data from W register to

NOP No Operation

Syntax: [ label ] NOP

Operands: None

Operation: No operation

Status Af fe cted: No ne

Description: No operation.

 1998-2013 Microchip Technology Inc. DS30605D-page 105

PIC16C63A/65B/73B/74B

RETFIE Return from Interrupt

Syntax: [ label ] RETFIE

Operands: None

Operation: TOS  PC,

1  GIE

Status Affected: None

RETLW Return with Literal in W

Syntax: [ label ] RETLW k

Operands: 0  k  255

Operation: k  (W);

TOS  PC

Status Affected: None

Description: The W register is loaded with the eight

bit literal 'k'. The program counter is

loaded from the top of the stack (the

return address). This is a two-cycle

instruction.

RETURN Return from Subroutine

Syntax: [ label ] RETURN

Operands: None

Operation: TOS  PC

Status Affected: None

Description: Return from subroutine. The stack is

POPed and the top of the stack (TOS)

is loaded into the program counter.

This is a two-cycle instruction.

RLF Rotate Left f through Carry

Syntax: [ label ]RLF f,d

Operands: 0  f  127

d  [0,1]

Operation: See description below

Status Af fe cted: C

Description: The contents of register 'f ' are rotated

one bit to the left through the Carry

Flag. If 'd' is 0, the result is placed in

the W register. If 'd' is 1, the result is

stored back in register 'f'.

RRF Rotate Right f through Carry

Syntax: [ label ] RRF f,d

Operands: 0  f  127

d  [0,1]

Operation: See description below

Status Af fe cted: C

Description: The contents of register 'f' are rotated

one bit to the right through the Carry

Flag. If 'd' is 0, the result is placed in

the W register . If 'd' is 1, the result is

placed back in register 'f'.

SLEEP

Syntax: [ label ] SLEEP

Operands: None

Operation: 00h  WDT,

0  WDT pres caler,

1  TO,

0  PD

Status Af fe cted: TO, PD

Description: The power-down status bit, PD is

cleared. T ime-out status bit, TO is

set. Watchdog Timer and its

prescaler are cleared.

The processor is put into SLEEP

mode with the oscillator stopped. See

Section 13.8 for more details.

PIC16C63A/65B/73B/74B

DS30605D-page 106  1998-2013 Microchip Technology Inc.

SUBLW Subtract W from Literal

Syntax: [ label ] SUBLW k

Operands: 0 k 255

Operation: k - (W) W)

Status Affected: C, DC, Z

Description: The W register is subtracted (2’s com-

plement method) from the eight bit lit-

eral 'k'. The result is placed in the W

SUBWF Subtract W from f

Syntax: [ label ] SUBWF f,d

Operands: 0 f 127

d  [0,1]

Operation: (f) - (W) destination)

Status Affected: C, DC, Z

Description: Subtract (2’s complement method) W

result is stored in the W register. If 'd' is

1, the result is stored back in register 'f'.

SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f<3:0>)  (destination<7:4>),

(f<7:4>)  (destination<3:0>)

Status Affected: None

Description: The upper and lower nibbles of regis-

ter 'f' are exchanged. If 'd' is 0, the

result is placed in W register . If 'd' is 1,

the result is placed in register 'f'.

XORLW Exclusive OR Literal with W

Syntax: [label] XORLW k

Operands: 0 k 255

Operation: (W) .XOR. k W)

Status Af fe cted: Z

Description: The contents of the W register are

XOR’ed with the eight bit lit eral 'k'.

The result is placed in the W

XORWF Exclusive OR W with f

Syntax: [label] XORWF f,d

Operands: 0  f  127

d  [0,1]

Operation: (W) .XOR. (f) destination)

Status Af fe cted: Z

Description: Exclusive OR the contents of the W

result is stored in the W register. If 'd'

is 1, the result is stored back in

 1998-2013 Microchip Technology Inc. DS30605D-page 107

PIC16C63A/65B/73B/74B

15.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers are supported with a full

range of hardware and software development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C17 and MPLAB C18 C Compilers

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB ICE 2000 In-Circuit Emulator

- ICEPIC™ In-Circuit Emulator

• In-Circuit Debugger

- MPLAB ICD for PIC16F87X

• Device Progra mmers

-PRO MATE

® II Universal D evi ce Programm er

- PICSTART® Plus Entry-Level Development

Programmer

• Low Cost Demonstration Boards

- PICDEMTM 1 Demonstration Board

- PICDEM 2 Demonstration Board

- PICDEM 3 Demons trati on Boar d

- PICDEM 17 Demonstration Board

-K

EELOQ® Demonstration Board

15.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8-bit microcon-

troller market. The MPLAB IDE is a Windows®-based

application that contains:

• An inter face to debugging tools

- simulator

- programmer (sold sep arately )

- emulator (sold separately)

- in-circuit debugger (sold separately)

• A full-featured editor

• A project manager

• Customizable toolbar and key mapping

• A status bar

• On-line help

The MPLAB IDE allows you to:

• Edit your source files (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PIC emulator an d simulator tools (automatically

updates all project information)

• Debug us ing :

- source files

- absolute listing file

- machine code

The ability to use MPLAB IDE with multiple debugging

tools allows users to easily switch from the cost-

effective simulator to a full-featured emulator with

minimal retraining.

15.2 MPASM Assembler

The MPASM assembler is a full-featured universal

macro assembler for all PIC MCUs.

The MPASM assembler has a command line interface

and a Windows shell. It can be used as a stand-alone

application on a Windows 3.x or greater system, or it

can be us ed through MPLAB ID E. The MP ASM assem-

bler generates relocatable object files for the MPLINK

object linker, Intel® standard HEX files, MAP files to

detail memory usage and symbol reference, an abso-

lute LST file that contains source lines and generated

machine code, and a COD file for debugging.

The MPASM assembler features include:

• Integration into MPLAB IDE projects .

• User-defined macros to streamline assembly

code.

• Condit ion al as sem bl y for mult i-p urpo se sourc e

files.

• Directives that allow complete control over the

assembly process.

15.3 MPLAB C17 and MPLAB C18

C Compilers

The MPLAB C1 7 and MP LAB C18 Code De vel op me nt

Systems are complete ANSI ‘C’ compilers for

Microchip’s PIC17CXXX and PIC18CXXX family of

microc ontrollers, re spectively. These com pilers provide

powerful integration capabilities and ease of use not

found with other comp ilers.

For easier source level debugging, the compilers pro-

vide symbol information that is compatible with the

MPLAB IDE memory display.

PIC16C63A/65B/73B/74B

DS30605D-page 108  1998-2013 Microchip Technology Inc.

15.4 MPLINK Object Linker/

MPLIB Object Librari an

The MPLINK object linker combines relocatable

objects created by the MPASM assembler and the

MPLAB C17 and MPLAB C18 C compilers. It can also

link relocatable objects from pre-compiled libraries,

using directives from a linker script.

The MPLIB object librarian is a librarian for pre-

compiled code to be used with the MPLINK object

linker. When a routine from a library is called from

another source file, only the modules that contain that

routine w ill be linked in with the ap plicatio n. This allo ws

large libraries to be used efficiently in many different

applications. The MPLIB object librarian manages the

creation and modification of library files.

The MPLIN K object linker features include:

• Integration with MPASM assembler and MPLAB

C17 and MPLAB C18 C compilers.

• Allows all m emory areas to be defin ed as sections

to provide l ink -time flex ibi lity.

The MPLIB object librarian features include:

• Easier linking because single libraries can be

included instead of many smaller files.

• Helps keep code maintainable by grouping

related modules together.

• Allows libraries to be created and modules to be

added, listed, replaced, deleted or extracted.

15.5 MPLAB SIM Software Simulator

The MPL AB SIM sof tware sim ulator allow s code de vel-

opment in a PC-hosted environment by simulating the

PIC s eri es m icroc ont roll ers on a n in stru cti on level . On

any given instruction, the data areas can be examined

or modified and stimuli can be applied from a file, or

user-defined key press, to any of the pins. The execu-

tion can be performed in single step, execute until

break, or trace mode.

The MPLAB SIM simulator fully supports symbolic debug-

ging using the MPLAB C17 and the MPLAB C18 C com-

pilers and the MP ASM assembler. The software simulator

offers the flexibility to develop and debug code outside of

the laborat ory envir onment, making it an excellent mu lti-

project software development tool.

15.6 MPLAB ICE High Performance

Universal In-Circuit Emulator with

MPLAB IDE

The MPLAB ICE universal in-circuit emulator is intended

to provide the product development engineer with a

complete microc ontroller design tool set for PIC micro-

controllers (MCUs). Software control of the MPLAB ICE

in-circu it emulator is provided by the MPLAB Integrated

Developm en t Environment (IDE), which al low s edi tin g,

building, downloading and source debugging from a

single environment.

The MPLAB ICE 2000 is a full-featured emulator sys-

tem with enhanced trace, trigger and data monitoring

featur es. Interchangea ble processo r modules al low the

system to be easily reconfigured for emulation of differ-

ent processors. The universal architecture of the

MPLAB ICE in-circuit emulator allows expansion to

support new PIC micro co ntrol le rs.

The MPLAB ICE in-circuit emulator system has been

designed as a real-time emulation system, with

advanced features that are generally found on more

expensive development tools. The PC platform and

Microsoft® Windows environment were chosen to best

make these features available to you, the end user.

15.7 ICEPIC In-Circuit Emulator

The ICEPIC low cost, in-circuit emulator is a solution

for the Microchip Technology PIC16C5X, PIC16C6X,

PIC16C7X and PIC16CXXX families of 8-bit One-

Time-Programmable (OTP) microcontrollers. The mod-

ular sy stem can su pport d ifferen t subset s of PIC16 C5X

or PIC16CXXX products through the use of inter-

changeable personality modules, or daughter boards.

The emulator is capable of emulating without target

applic atio n circ ui try bei ng pres en t.

 1998-2013 Microchip Technology Inc. DS30605D-page 109

PIC16C63A/65B/73B/74B

15.8 MPLAB ICD In-Circuit Debugger

Microc hip's In-Circu it Debugger , M PLAB ICD, is a pow-

erful, low cost, run-time development tool. This tool is

based on the FLASH PIC16F87X and can be used to

develo p for this and other PIC microcontrollers from the

PIC16CXXX family. The MPLAB ICD utilizes the in-cir-

cuit debugging capability built in to the PIC16F87X. This

feature, along with Microchip's In-Circuit Serial

ProgrammingTM protocol, offers cost-effective in-circuit

FLASH debugging from the graphical user interface of

the MPLAB Int egrated Development Environment. This

enables a des ign er to dev el op and deb ug so urc e cod e

by watching variables, single-stepping and setting

break points. Running at full speed enables testing

hardware in real-time.

15.9 PRO MATE II Universal Device

Programmer

The PRO MATE II universal device programmer is a

full-featured programmer, capable of operating in

stand-alone mode, as well as PC-hosted mode. The

PRO MATE II device programmer is CE compliant.

The PRO MATE II device programmer has program-

mable VDD and VPP supplies, which allow it to verify

programmed memory at VDD min and VDD max for max-

imum reliability. It has an LCD display for instructions

and error messages, keys to enter commands and a

modular detachable socket assembly to support various

package types. In stand-alone mode, the PRO MATE II

device programmer can read, verify, or program PIC

devices. It can also set code protection in this mode.

15.10 PICSTART Plus Entry Level

Development Programmer

The PICSTART Plus development programmer is an

easy-to-use, low cost, prototype programmer. It con-

nects to the PC via a COM (RS-232) port. MPLAB

Inte grated D evelopm ent Envir onment software m akes

using the programmer simple and efficient.

The PICSTART Plus development programmer sup-

ports all PIC devices with up to 40 pins. Larger pin

count devices, such as the PIC16C92X and

PIC17C76 X, may be suppor ted with an a dapter socket.

The PICSTART Plus development programmer is CE

compliant.

15.11 PICDEM 1 Low Cost PIC MCU

Demonstration Board

The PICDEM 1 demonstration board is a simple board

which demonstrates the capabilities of several of

Microc hip’ s m icroc ontrol lers. T he mi croco ntrolle rs su p-

ported are: PIC16C5X (PIC16C54 to PIC16C58A),

PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,

PIC17C42, PIC17C43 and PIC17C44. All necessary

hardware and software is included to run basic demo

programs. The user can program the sample microcon-

trollers provided with the PICDEM 1 demonstration

board on a PRO MATE II device programmer, or a

PICSTART Plus development programmer, and easily

test firmware. The user can also connect the

PICDEM 1 demonstration board to the MPLAB ICE in-

circuit emul ator and download th e firmware to the emu-

lator for testing. A prototype area is available for the

user to build some additional hardware and connect it

to the microcontroller socket(s). Some of the features

include an RS-232 interface, a potentiometer for si mu-

lated analog input, push button switches and eight

LEDs connected to PORTB.

15.12 PICDEM 2 Low Cost PIC16CXX

Demonstration Board

The PICDEM 2 demonstration board is a simple dem-

onstration board that supports the PIC16C62,

PIC16C64, PIC16C65, PIC16C73 and PIC16C74

microcontrollers. All the necessary hardware and soft-

ware is included to run the basic demonstration pro-

grams. The user can program the sample

microcontrollers provided with the PICDEM 2 demon-

stration board on a PRO MATE II device programm er,

or a PICSTART Plus development programmer, and

easily test firmware . The MPLAB ICE in-circuit emula-

tor may a lso be used with t he PICDEM 2 demonstratio n

board to test firmware. A prototype area has been pro-

vided to the user for adding additional hardware and

connecting it to the microcontroller socket(s). Some of

the features include a RS-232 interface, push button

switches , a poten tiomet er for simula ted anal og inpu t, a

serial EEPROM to d emonstra te usage o f the I2CTM bus

and separate headers for connection to an LCD

module and a keypad.

PIC16C63A/65B/73B/74B

DS30605D-page 110  1998-2013 Microchip Technology Inc.

15.13 PICDEM 3 Low Cost PIC16CXXX

Demonstration Board

The PICDEM 3 demonstration board is a simple dem-

onstration board that supports the PIC16C923 and

PIC16C924 in the PLCC package. It will also support

future 44-p in PLCC micro controlle rs with an LCD Mo d-

ule. All the necessary hardware and software is

includ ed to r un the basic dem onstrat ion pro grams . The

user can program the sample microcontrollers pro-

vided with the PICDEM 3 demonstration board on a

PRO MATE II device prog rammer , or a PICS T AR T Plus

development programmer with an adapter socket, and

easily test firmware. The MPLAB ICE in-circuit emula-

tor may a lso be used with the PICDEM 3 demonstration

board to test firmware. A prototype area has been pro-

vided t o the use r for ad ding hardwa re and con necting it

to the microcontroller socket(s). Some of the features

include a RS-232 interface, push button switches, a

potentiometer for simulated analog input, a thermistor

and separate headers for connection to an external

LCD module and a keypad. Also provided on the

PICDEM 3 demonstration board is a LCD panel, with 4

commo ns and 1 2 segments, tha t is capable of display-

ing time, temperature and day of the week. The

PICDEM 3 d emons tration board pr ovi des an add itiona l

RS-232 interface and Windows software for showing

the demul tiplexed LC D signals on a PC. A si mple serial

interface allows the user to construct a hardware

demultiplexer for the LCD signals.

15.14 PICDEM 17 Demonstration Board

The P ICDEM 17 de mo ns t r at ion bo a r d is an ev al u ati on

board that demonstrates the capabilities of several

Microchip microcontrollers, including PIC17C752,

PIC17C756A, PIC17C762 and PIC17C766. All neces-

sary hard ware is inc luded to ru n basic d emo progra ms,

which are supplied on a 3.5-inch disk. A programmed

sample is included and the user may erase it and

program it with the other sample programs using the

PRO MATE II device programmer, or the PICSTART

Plus development programmer, and easily debug and

test the sample code. In addition, the PICDEM 17 dem-

onstratio n board supports download ing of programs to

and executing out of external FLASH memory on board.

The PICDEM 17 demonstration board is also usable

with the MPLAB ICE in-circuit emulator, or the

PICMAST ER emulat or and al l of the sample progr ams

can be run and modified using either emulator . Addition-

ally, a generous prototype area is available for user

hardware.

15.15 KEELOQ Evaluati on and

Programming Tools

KEELOQ evaluation and programming tools support

Microchip’s HCS Secure Data Products. The HCS eval-

uation kit includes a LCD display to show changing

codes, a decoder to decode transmissions and a pro-

gramming interface to program test transmitters.

 1998-2013 Microchip Technology Inc. DS30605D-page 111

PIC16C63A/65B/73B/74B

TABLE 15-1: DEVELOPMENT TOOLS FROM MICROCHIP

PIC12CXXX

PIC14000

PIC16C5X

PIC16C6X

PIC16CXXX

PIC16F62X

PIC16C7X

PIC16C7XX

PIC16C8X

PIC16F8XX

PIC16C9XX

PIC17C4X

PIC17C7XX

PIC18CXX2

24CXX/

25CXX/

93CXX

HCSXXX

MCRFXXX

MCP2510

Soft war e Tools

MPLAB® Integrated

Development Environment 

MPLAB® C17 C Compiler 

MPLAB® C18 C Compiler 

MPASMTM Assembler/

MPLINKTM Object Linker 

Emulators

MPLAB® ICE In-Circuit Emulator 

** 

ICEPICTM In -Circu it Emu lat or    

Debugger

MPLAB® ICD In-Circuit

Debugger **

Programmers

PICSTART® Plus Entr y Le vel

Development Programmer 

** 

PRO MATE® II

Universal Device Programmer 

** 

Demo Boards and Eval Kits

PICDEMTM 1 Demonstration

Board 

†

PICDEMTM 2 Demonstration

Board ††

PICDEMTM 3 Demonstration

Board 

PICDEMTM 14A Demonstration

Board 

PICDEMTM 17 Demonstration

Board 

KEELOQ® Evaluation Kit 

KEELOQ® Transponder Kit 

microIDTM Programmer’s Kit 

125 kHz microIDTM

Developer’s Kit 

125 kHz Anticollision microIDTM

Developer’s Kit 

13.56 MHz Anticollision

microIDTM Developer’s Kit 

MCP2510 CAN Developer’s Kit 

* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.

** Contact Microchip Technology Inc. for availability date.

†Development tool is available on select devices.

PIC16C63A/65B/73B/74B

DS30605D-page 112  1998-2013 Microchip Technology Inc.

NOTES:

 1998-2013 Microchip Technology Inc. DS30605D-page 113

PIC16C63A/65B/73B/74B

16.0 ELECTRICAL CHARAC TERISTICS

Abso lute Maximum Ratings(†)

Ambient temperature under bias.............................................................................................................-55°C to +125°C

Storage temperature.............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) ..........................................-0.3V to (VDD + 0.3V)

Volta ge on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V

Volta ge on MC LR with respect to VSS (Note 2).........................................................................................0V to +13.25V

Voltage on RA4 with respect to VSS............................................................................................................... 0V to +8.5V

Total powe r dissipation (Note 1) ...............................................................................................................................1.0W

Maximum curre nt out of VSS pin ...........................................................................................................................300 mA

Maximum curre nt into VDD pin..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined)...................................................200 mA

Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined)..............................................200 mA

Maximum current sunk by PORTC and PORTD (Note 3) (co mb ine d)....... ..... ............................ ...... ...... ..............200 mA

Maximum current sourced by PORTC and PORTD (Note 3) (combined).............................................................200 mA

Note 1: Power dissipation is calcu la ted as follows : Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL)

2: Voltage spikes b elo w VSS at the MCLR/VPP pin , inducing curren ts greater th an 80 m A, may cause l atc h-u p.

Thus, a s eri es re si sto r o f 50 - 100 sh ould be used wh en apply ing a “low” le vel to the MCLR/VPP pi n rather

than pulling this pin directly to VSS.

3: PORTD and PORTE not available on the PIC16C63A/73B.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . This is a stres s rating onl y and funct ional ope rati on of the devi ce at those or any other condi tions above thos e

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC16C63A/65B/73B/74B

DS30605D-page 114  1998-2013 Microchip Technology Inc.

FIGURE 16-1: PIC16C6 3A/6 5B/7 3B/74B VOLTAGE-FREQUENCY GRAPH

FIGURE 16-2: PIC16LC63A/6 5B/73 B/74 B VO LTAGE-FREQUENCY GRAPH

Frequency

Voltage

6.0 V

5.5 V

4.5 V

4.0 V

2.0 V

20 MHz

5.0 V

3.5 V

3.0 V

2.5 V

PIC16CXXX-20

Frequency

Voltage

6.0 V

5.5 V

4.5 V

4.0 V

2.0 V

5.0 V

3.5 V

3.0 V

2.5 V

FMAX = (12.0 MHz/V) (VDDAPPMIN - 2.5 V) + 4 MHz

Note 1: VDDAPPMIN is the minimum voltage of the PIC® device in the application.

4 MHz 10 MHz

Note 2: FMAX has a maximum frequency of 10MHz.

PIC16LCXXX-04

 1998-2013 Microchip Technology Inc. DS30605D-page 115

PIC16C63A/65B/73B/74B

FIGURE 16-3: PIC16C6 3A/6 5B/7 3B/74B VOLTAGE-FREQUENCY GRAPH

Frequency

Voltage

6.0 V

5.5 V

4.5 V

4.0 V

2.0 V

5.0 V

3.5 V

3.0 V

2.5 V

PIC16CXXX-04

4 MHz

PIC16C63A/65B/73B/74B

DS30605D-page 116  1998-2013 Microchip Technology Inc.

16.1 DC Characteristics

PIC16LC63A/65B/73B/74B-04 Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C  TA +70°C for commercial

-40°C  TA +85°C for industrial

‡PIC16C63A/65B/73B/74B-04

‡PIC16C6A/65B/73B/74B-20 Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C  TA +70°C for commercial

-40°C  TA +85°C for industrial

-40°C  TA +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

VDD Supply Voltage

D001 PIC16LCXXX 2.5

VBOR*–

–5.5

5.5 V

VLP, XT, RC osc modes (DC - 4 MHz)

BOR enabled (Note 7)

D001

D001A PIC16CXXX 4.0

4.5

VBOR*

–

5.5

XT, RC and LP osc mode

HS osc mode

BOR enabled (Note 7)

D002* VDR RAM Da ta Retention

Voltage (Note 1) –1.5– V

D003 VPOR VDD Start Voltage to

ensure i nte rna l

Power-on Reset signal

–V

SS – V See section on Power-on Reset for details

D004*

D004A* SVDD VDD Rise Rate to

ensure internal

Power-on Reset signal

0.05

TBD –

––

–V/mS

V/mS PWRT enabled (PWRTE bit clear)

PWR T dis ab led (PWRT E bit set)

See section on Power-o n Reset fo r detail s

D005 VBOR Brown-out Reset

voltage trip point 3.65 – 4.35 V BODEN bit set

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherw ise stated. These parameters are for design guidance only and

are not tested.

‡ When specification value s of st andard dev ices differ from those of extended voltage devices, they are shown in gray.

Note 1: This is the limit to which VDD can be lowered without losing RAM data.

2: The supply current is mainly a function of the operatin g volt age and frequency. Other factors such as I/O pin

loading and switchi ng rate, oscil lator type, internal c ode exe cution p a ttern and temperature als o have a n imp ac t

on the current consumption. The test conditions for all IDD measuremen t s in activ e operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-

sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: For RC osc mo de, curre nt thro ugh REXT is no t inclu ded. The c urren t thro ugh the res is tor ca n be esti ma ted by

the formula Ir = VDD/2REXT (mA) with REXT in kOhm.

5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character-

ization and is for design guidance only. This is not tested.

6: The  current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD measurement.

7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.

8: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC

device be driven with external clock in RC mode.

9: The leakage curre nt on the M C LR/VPP pin is strongly depen dent on the applied volt age lev el. Th e sp ecified lev-

els represen t norm al o perati ng c ondi tion s. H ig her le akage c urrent m ay be m eas ured at di f ferent input voltag es.

10:Negative current is defined as current sourced by the pin.

 1998-2013 Microchip Technology Inc. DS30605D-page 117

PIC16C63A/65B/73B/74B

IDD Supply Current (Notes 2, 5)

D010

D010A

PIC16LCXXX –

–

0.6

22.5

2.0

A

XT, RC osc modes:

FOSC = 4 MHz, VDD = 3.0V (Note 4)

LP osc mode:

FOSC = 32 kHz, VDD = 3.0V, WDT disabled

D010

D013

PIC16CXXX –

–

2.7

XT, RC osc modes:

FOSC = 4 MHz, VDD = 5.5 V (Note 4)

HS osc mode:

FOSC = 20 MHz, VDD = 5.5 V

IPD Power-down Current (Notes 3, 5)

D020

D021

D021A

PIC16LCXXX –

–

7.5

0.9

A

VDD = 3.0V, WDT enabled, -40°C to +85°C

VDD = 3.0V, WDT disabled, 0°C to +70°C

VDD = 3.0V, WDT disabled, -40°C to +85°C

D020

D021

D021A

D021B

PIC16CXXX –

–

10.5

1.5

2.5

A

VDD = 4.0V, WDT enabled, -40°C to +85°C

VDD = 4.0V, WDT disabled, 0°C to +70°C

VDD = 4.0V, WDT disabled, -40°C to +85°C

VDD = 4.0V, WDT dis abled, -40°C to +125 °C

PIC16LC63A/65B/73B/74B-04 Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C  TA +70°C for commercial

-40°C  TA +85°C for industrial

‡PIC16C63A/65B/73B/74B-04

‡PIC16C6A/65B/73B/74B-20 Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C  TA +70°C for commercial

-40°C  TA +85°C for industrial

-40°C  TA +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherw ise stated. These parameters are for design guidance only and

are not tested.

‡ When specification values of st andard dev ices differ from those of extended voltage devices, they are shown in gray.

Note 1: This is the limit to which VDD can be lowered without losing RAM data.

2: The supply current is mainly a function of the operatin g volt age and frequency. Other factors such as I/O pin

loading and switchi ng rate, oscil lator type, internal c ode exe cution p a ttern and temperature als o have a n imp ac t

on the current consumption. The test conditions for all IDD measuremen t s in activ e operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-

sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: For RC osc mo de, curre nt thro ugh REXT is no t inclu ded. The c urren t thro ugh the res is tor ca n be esti ma ted by

the formula Ir = VDD/2REXT (mA) with REXT in kOhm.

5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character-

ization and is for design guidance only. This is not tested.

6: The  current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD measurement.

7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.

8: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC

device be driven with external clock in RC mode.

9: The leakage curre nt on the M C LR/VPP pin is s trong ly d epen dent on the applied vol t age lev el. Th e specified lev-

els represen t norm al o perati ng c ondi tion s. H ig her le akage c urrent m ay be m eas ured at di f ferent input voltag es.

10:Negative current is defined as current sourced by the pin.

PIC16C63A/65B/73B/74B

DS30605D-page 118  1998-2013 Microchip Technology Inc.

Module Differential

Current (Note 6)

D022* IWDT Watchdog Timer – 6.0 20 A WDTE bit set, VDD = 4.0V

D022A* IBOR Brown-out Reset – 100 150 A BODEN bit set, VDD = 5.0

Input Low Voltage

VIL I/O ports

D030

D030A with TTL buffer VSS

VSS –

–0.15 VDD

0.8V V

VFor entire VDD range

4.5V  VDD  5.5V

D031 with Schmitt

Trigger buffer VSS –0.2VDD V

D032 MCLR, OSC1

(in RC mode) Vss – 0.2 VDD V

D033 OSC1 (in XT, HS, and

LP modes) Vss – 0.3 VDD V(Note 8)

PIC16LC63A/65B/73B/74B-04 Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C  TA +70°C for commercial

-40°C  TA +85°C for industrial

‡PIC16C63A/65B/73B/74B-04

‡PIC16C6A/65B/73B/74B-20 Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C  TA +70°C for commercial

-40°C  TA +85°C for industrial

-40°C  TA +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherw ise stated. These parameters are for design guidance only and

are not tested.

‡ When specification value s of st andard dev ices differ from those of extended voltage devices, they are shown in gray.

Note 1: This is the limit to which VDD can be lowered without losing RAM data.

2: The supply current is mainly a function of the operatin g volt age and frequency. Other factors such as I/O pin

loading and switchi ng rate, oscil lator type, internal c ode exe cution p a ttern and temperature als o have a n imp ac t

on the current consumption. The test conditions for all IDD measuremen t s in activ e operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-

sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: For RC osc mo de, curre nt thro ugh REXT is no t inclu ded. The c urren t thro ugh the res is tor ca n be esti ma ted by

the formula Ir = VDD/2REXT (mA) with REXT in kOhm.

5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character-

ization and is for design guidance only. This is not tested.

6: The  current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD measurement.

7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.

8: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC

device be driven with external clock in RC mode.

9: The leakage curre nt on the M C LR/VPP pin is strongly depen dent on the applied volt age lev el. Th e sp ecified lev-

els represen t norm al o perati ng c ondi tion s. H ig her le akage c urrent m ay be m eas ured at di f ferent input voltag es.

10:Negative current is defined as current sourced by the pin.

 1998-2013 Microchip Technology Inc. DS30605D-page 119

PIC16C63A/65B/73B/74B

Input High Voltage

VIH I/O ports

D040 with TTL buffer 2.0 –VDD V4.5V  VDD  5.5V

D040A 0.25 VDD +

0.8V –VDD V For entire VDD range

D041 with Schmitt

Trigger buffer 0.8 VDD –VDD V For entire VDD range

D042 MCLR 0.8 VDD –VDD V

D042A OSC1 (in XT, HS, and

LP modes) 0.7 VDD –VDD V(Note 8)

D043 OSC1 (in RC mode) 0.9 VDD –VDD V

Input Leakage

Current (Note s 9, 10)

D060 IIL I/O ports – – ±1 AVss  VPIN  VDD,

Pin at hi-impedance

D061 MCLR, RA4/T0CKI – – ±5 AVss  VPIN  VDD

D063 OSC1 – – ±5 AVss  VPIN  VDD,

XT, HS and LP osc modes

D070 IPURB PORTB Weak Pull-up

Current 50 250 400 AVDD = 5V, VPIN = VSS

PIC16LC63A/65B/73B/74B-04 Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C  TA +70°C for commercial

-40°C  TA +85°C for industrial

‡PIC16C63A/65B/73B/74B-04

‡PIC16C6A/65B/73B/74B-20 Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C  TA +70°C for commercial

-40°C  TA +85°C for industrial

-40°C  TA +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherw ise stated. These parameters are for design guidance only and

are not tested.

‡ When specification values of st andard dev ices differ from those of extended voltage devices, they are shown in gray.

Note 1: This is the limit to which VDD can be lowered without losing RAM data.

2: The supply current is mainly a function of the operatin g volt age and frequency. Other factors such as I/O pin

loading and switchi ng rate, oscil lator type, internal c ode exe cution p a ttern and temperature als o have a n imp ac t

on the current consumption. The test conditions for all IDD measuremen t s in activ e operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-

sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: For RC osc mo de, curre nt thro ugh REXT is no t inclu ded. The c urren t thro ugh the res is tor ca n be esti ma ted by

the formula Ir = VDD/2REXT (mA) with REXT in kOhm.

5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character-

ization and is for design guidance only. This is not tested.

6: The  current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD measurement.

7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.

8: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC

device be driven with external clock in RC mode.

9: The leakage curre nt on the M C LR/VPP pin is s trong ly d epen dent on the applied vol t age lev el. Th e specified lev-

els represen t norm al o perati ng c ondi tion s. H ig her le akage c urrent m ay be m eas ured at di f ferent input voltag es.

10:Negative current is defined as current sourced by the pin.

PIC16C63A/65B/73B/74B

DS30605D-page 120  1998-2013 Microchip Technology Inc.

Output Low Voltage

D080 VOL I/O ports – – 0.6 V IOL = 8.5 mA, VDD = 4.5V,

-40°C to +85°C

––0.6VIOL = 7.0 mA, VDD = 4.5V,

-40°C to +125°C

D083 OSC2/CLKOUT

(RC osc mode) ––0.6VI

OL = 1.6 mA, VDD = 4.5V,

-40°C to +85°C

––0.6VI

OL = 1.2 mA, VDD = 4.5V,

-40°C to +125°C

Output High Voltage

D090 VOH I/O ports (Note 10) VDD-0.7 – – V IOH = -3.0 mA, VDD = 4. 5V,

-40°C to +85°C

VDD-0.7 – – V IOH = -2.5 mA, VDD = 4.5V,

-40°C to +125°C

D092 OSC2/CLKOUT

(RC osc mode) VDD-0.7 – – V IOH = -1.3 mA, VDD = 4.5V,

-40°C to +85°C

VDD-0.7 – – V IOH = -1.0 mA, VDD = 4.5V,

-40°C to +125°C

D150* VOD Open-Drain

High Voltage – – 8.5 V RA4 pin

PIC16LC63A/65B/73B/74B-04 Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C  TA +70°C for commercial

-40°C  TA +85°C for industrial

‡PIC16C63A/65B/73B/74B-04

‡PIC16C6A/65B/73B/74B-20 Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C  TA +70°C for commercial

-40°C  TA +85°C for industrial

-40°C  TA +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherw ise stated. These parameters are for design guidance only and

are not tested.

‡ When specification value s of st andard dev ices differ from those of extended voltage devices, they are shown in gray.

Note 1: This is the limit to which VDD can be lowered without losing RAM data.

2: The supply current is mainly a function of the operatin g volt age and frequency. Other factors such as I/O pin

loading and switchi ng rate, oscil lator type, internal c ode exe cution p a ttern and temperature als o have a n imp ac t

on the current consumption. The test conditions for all IDD measuremen t s in activ e operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-

sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: For RC osc mo de, curre nt thro ugh REXT is no t inclu ded. The c urren t thro ugh the res is tor ca n be esti ma ted by

the formula Ir = VDD/2REXT (mA) with REXT in kOhm.

5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character-

ization and is for design guidance only. This is not tested.

6: The  current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD measurement.

7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.

8: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC

device be driven with external clock in RC mode.

9: The leakage curre nt on the M C LR/VPP pin is strongly depen dent on the applied volt age lev el. Th e sp ecified lev-

els represen t norm al o perati ng c ondi tion s. H ig her le akage c urrent m ay be m eas ured at di f ferent input voltag es.

10:Negative current is defined as current sourced by the pin.

 1998-2013 Microchip Technology Inc. DS30605D-page 121

PIC16C63A/65B/73B/74B

Capacitive Loading

Specs on

Output Pins

D100 COSC2 OSC2 pin – – 15 pF In XT, HS and LP modes when external

clock is used to drive OSC1

D101 CIO All I/O pin s an d OSC2

(in RC mode) ––50pF

D102 Cb SCL, SDA

(in I2C mode) ––400pF

PIC16LC63A/65B/73B/74B-04 Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C  TA +70°C for commercial

-40°C  TA +85°C for industrial

‡PIC16C63A/65B/73B/74B-04

‡PIC16C6A/65B/73B/74B-20 Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C  TA +70°C for commercial

-40°C  TA +85°C for industrial

-40°C  TA +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherw ise stated. These parameters are for design guidance only and

are not tested.

‡ When specification values of st andard dev ices differ from those of extended voltage devices, they are shown in gray.

Note 1: This is the limit to which VDD can be lowered without losing RAM data.

2: The supply current is mainly a function of the operatin g volt age and frequency. Other factors such as I/O pin

loading and switchi ng rate, oscil lator type, internal c ode exe cution p a ttern and temperature als o have a n imp ac t

on the current consumption. The test conditions for all IDD measuremen t s in activ e operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-

sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: For RC osc mo de, curre nt thro ugh REXT is no t inclu ded. The c urren t thro ugh the res is tor ca n be esti ma ted by

the formula Ir = VDD/2REXT (mA) with REXT in kOhm.

5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character-

ization and is for design guidance only. This is not tested.

6: The  current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD measurement.

7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.

8: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC

device be driven with external clock in RC mode.

9: The leakage curre nt on the M C LR/VPP pin is s trong ly d epen dent on the applied vol t age lev el. Th e specified lev-

els represen t norm al o perati ng c ondi tion s. H ig her le akage c urrent m ay be m eas ured at di f ferent input voltag es.

10:Negative current is defined as current sourced by the pin.

PIC16C63A/65B/73B/74B

DS30605D-page 122  1998-2013 Microchip Technology Inc.

16.2 AC (Timing) Characteristics

16.2.1 TIMING PA RAMETER SYMBOLOGY

The timing parameter symbols have been created following one of the following formats:

1. TppS2pp S 3. TCC:ST (I2C specifications only)

2. TppS 4. Ts (I2C specifications only)

TF Frequency T Time

Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1

ck CLKOUT rd RD

cs CS rw RD or WR

di SDI sc SCK

do SDO ss SS

dt Data in t0 T0CKI

io I/O port t1 T1CKI

mc MCLR wr WR

Uppercase letters and their meanings:

SF Fall P Period

HHigh RRise

I Invalid (Hi-im pe dan ce ) V Valid

L Low Z Hi-impedance

I2C only

AA output access High High

BUF Bus free Low Low

TCC:ST (I2C specifications only)

HD Hold SU Setup

DAT DATA input hold STO STOP condition

STA START condition

 1998-2013 Microchip Technology Inc. DS30605D-page 123

PIC16C63A/65B/73B/74B

16.2.2 TIMING CONDITIONS

The temperature and voltages specified in Table 16-1

apply to all timing specifications unless otherwise

noted. Figure 16-4 specifies the load conditions for the

timing specification s.

TABLE 16-1: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC

FIGURE 16-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

AC CHARACTERISTICS

Standard Operating Conditi ons (unle ss otherwise stated)

Operating temperature 0°C  TA +70°C for commercial

-40°C  TA +85°C for industria l

-40°C  TA +125°C for extended

Operating voltage VDD range as described in DC spec Section 16.1.

LC parts operate for commercial/industrial temperatures only.

VDD/2

VSS

RL= 464

CL= 50 pF for all pins except OSC2/CLKOUT

but including D and E outputs as ports

CL= 15 pF for OSC2 output

Load condition 1 Load condition 2

Note 1: PO RTD and PORTE are not implemented on the PIC16C63A/73B.

PIC16C63A/65B/73B/74B

DS30605D-page 124  1998-2013 Microchip Technology Inc.

16.2.3 TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 16-5: EXTERNAL CLOCK TIMING

TABLE 16-2: EXTERNAL CLOCK TIMING REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

1A FOSC External CLKIN Frequency

(Note 1) DC — 4 MHz RC and XT osc modes

DC — 4 MHz HS osc mode (-04)

DC — 20 MHz HS osc mode (-20)

DC — 200 kHz LP osc mode

Oscilla tor Frequency

(Note 1) DC — 4 MHz RC osc mod e

0.1 — 4 MHz XT osc mode

4 — 20 MHz HS osc mode

5 — 200 kHz LP osc mode

1TOSC External CLKIN Period

(Note 1) 250 — — ns RC and XT osc modes

250 — — ns HS osc mode (-04)

50 — — ns HS osc mode (-20)

5— —sLP osc mode

Oscillator Perio d

(Note 1) 250 — — ns RC osc mode

250 — 10,00 0 ns XT osc mode

250 — 250 ns HS osc mode (-04)

50 — 250 ns HS osc mode (-20)

5— —sLP osc mode

2TCY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC

3* TosL,

TosH External Clock in (OSC1) Hig h or

Low Time 100 — — ns XT oscillator

2.5 — — s LP oscillator

15 — — ns HS oscillator

4* TosR,

TosF External Clock in (OSC1) Rise or

Fall Time — — 2 5 ns XT oscillator

— — 50 ns LP oscillator

— — 15 ns HS oscillator

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and

are not tested.

Note 1: Instructi on cycle pe riod (TCY) equals four times the input oscillator time-base period. All specified values are

based on characteri zatio n data fo r that pa rticular os cillator t ype under st anda rd operating conditio ns with the

device e xecutin g code. Exc eeding th ese spec ified lim its m ay result in an unst able o scillato r operation and/or

higher th an expec ted curren t consumpt ion. All d evices are tested to operate a t “min.” v alues wit h an externa l

clock applied to the OSC1/CLKIN pin. When an external clock input is used, the “Max.” cycle time limit is

“DC” (no clock) for all devices.

344

Q4 Q1 Q2 Q3 Q4 Q1

OSC1

CLKOUT

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PIC16C63A/65B/73B/74B

FIGURE 16-6: CLKOUT AND I/O TIMING

TABLE 16-3: CLKOUT AND I/O TIMING REQUIREMENTS

Note: Refer to Figure 16-4 for load conditions.

OSC1

CLKOUT

I/O Pin

(input)

I/O Pin

(output)

Q4 Q1 Q2 Q3

13 14

20, 21

19 18

old value new value

Param

No. Sym Characteristic Min Typ† Max Units Conditions

10* TosH2ckL OSC1 to CLKOUT — 75 200 ns (Note 1)

11* TosH2ckH OSC1 to CLKOUT — 75 200 ns (Note 1)

12* TckR CLKOUT rise time — 35 100 ns (Note 1)

13* TckF CLKOUT fall time — 35 100 ns (Note 1)

14* TckL2ioV CLKOUT  to Port out valid — — 0.5TCY + 20 ns (Note 1)

15* TioV2ckH Port in valid before CLKOUT  T

OSC + 200 — — ns (Note 1)

16* TckH2ioI Port in hold after CLKOUT  0——ns(Note 1)

17* TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 ns

18* TosH2ioI OSC1 (Q2 cycle) to Port

input invalid (I/O in hold

time)

PIC16CXX 100 — — ns

18A* PIC16LCXX 200 — — ns

19* TioV2osH Port input valid to OSC1(I/O in setup

time) 0——ns

20* TioR Port output rise time PIC16CXX — 10 40 ns

20A* PIC16LCXX — — 80 ns

21* TioF Port output fall time PIC16CXX — 10 40 ns

21A* PIC16LCXX — — 80 ns

22††* Tinp INT pin high or low time TCY ——ns

23††* Trbp RB7:RB4 change INT high or low time TCY ——ns

* These parameters ar e character i zed but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and

are not tested.

††These parameters are asynch ronous events not re lated to any internal cloc k edge.

Note 1: Mea s urements are taken in RC mode where C LKOUT outp ut is 4 x TOSC.

PIC16C63A/65B/73B/74B

DS30605D-page 126  1998-2013 Microchip Technology Inc.

FIGURE 16-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIME R TIMI NG

FIGURE 16-8: BROWN-OUT RESET TIMING

TABLE 16-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT RESET REQUIREMENTS

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

RESET

Watchdog

Timer

Reset

I/O Pins

Note: Refer to Figure 16-4 for load conditions.

VDD BVDD

Param No. Sym Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse Width (low ) 2 — — sVDD = 5V, -40°C to +125°C

31* TWDT Watchdog Timer Time-out

Period (No Prescaler) 71833msV

DD = 5V, -40°C to +125°C

32 TOST Oscillation Start-up Timer

Period — 1024 TOSC ——TOSC = OSC1 period

33* TPWRT Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C

34 TIOZ I/O Hi-impedance from MCLR

Low or WDT Reset ——2.1s

35 TBOR Brown-out Reset Pulse Width 100 — — sVDD  BVDD (D005)

* These parameters ar e character i zed but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and

are not tested.

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PIC16C63A/65B/73B/74B

FIGURE 16-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

TABLE 16-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

40* Tt0H T0CKI High Pulse Width No Pre scaler 0.5TCY + 20 — — ns Mus t also meet

parameter 42

With Prescaler 10 — — ns

41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet

parameter 42

With Prescaler 10 — — ns

42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns

With Prescaler Greater of:

20 or TCY + 40

— — ns N = prescale value

(2, 4, ..., 256)

45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet

parameter 47

Synchronous,

Prescaler = 2,4,8 PIC16CXX 15 — — ns

PIC16LCXX 25 — — ns

Asynchronous PIC16CXX 30 — — ns

PIC16LCXX 50 — — ns

46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet

parameter 47

Synchronous,

Prescaler = 2,4,8 PIC16CXX 15 — — ns

PIC16LCXX 25 — — ns

Asynchronous PIC16CXX 30 — — ns

PIC16LCXX 50 — — ns

47* Tt1P T1CKI input

period Synchronous PIC16CXX Greater of:

30 or TCY + 40

— — ns N = prescale value

(1, 2, 4, 8)

PIC16LCXX Greater of:

50 or TCY + 40

N = prescale value

(1, 2, 4, 8)

Asynchronous PIC16CXX 60 — — ns

PIC16LCXX 100 — — ns

Ft1 Timer1 oscillator input frequency range

(oscillator enabled by setting bit T1OSCEN) DC — 200 kHz

48 TCKEZtmr1 Delay from external clock edge to timer increment 2TOSC —7TOSC —

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherwise st ated. These parameters are for design guidance only and are not tested.

Note: Refer to Figure 16-4 for load conditions.

T0CKI

T1OSO/T1CKI

TMR0 or

TMR1

PIC16C63A/65B/73B/74B

DS30605D-page 128  1998-2013 Microchip Technology Inc.

FIGURE 16-10: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)

TABLE 16-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)

Note: Refer to Figure 16-4 for load conditions.

CCPx

(Capture mode)

50 51

CCPx

53 54

(Compare or PWM mode)

Param

No. Sym Characteristic Min Typ† Max Units Conditions

50* TccL CCP1 and

CCP2

input low tim e

No Prescaler 0.5TCY + 20 — — ns

With Prescaler PIC16CXX 10 — — ns

PIC16LCXX 20 — — ns

51* TccH CCP1 and

CCP2

input high time

No Prescaler 0.5TCY + 20 — — ns

With Prescaler PIC16CXX 10 — — ns

PIC16LCXX 20 — — ns

52* TccP CCP1 and CCP2 input period 3TCY + 40

N— — ns N = prescale

value (1, 4, or 16 )

53* TccR CCP1 and CCP2 out put rise tim e PIC16CXX — 10 25 ns

PIC16LCXX — 25 45 ns

54* TccF CCP1 and CCP2 output fall time PIC16CXX — 10 25 ns

PIC16LCXX — 25 45 ns

* These parameters ar e character i zed but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherw ise stated. These parameters are for design guidance only and

are not tested.

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PIC16C63A/65B/73B/74B

FIGURE 16-11: PARALLEL SLAVE PORT TIMING (PIC16C65 B/74 B)

TABLE 16-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C65B/74B)

Note: Refer to Figure 16-4 for load conditions.

RE2/CS

RE0/RD

RE1/WR

RD7:RD0

Param No. Sym Characteristic Min Typ† Max Units Conditions

62* TdtV2wrH Data in valid before WR or CS (setup time) 20 — — ns

63* TwrH2dtI WR or CS to data in

invalid (hold time) PIC16CXX 20 — — ns

PIC16LCXX 35 — — ns

64 TrdL2dtV RD and CS to data out valid ——80ns

65* TrdH2dtI RD or CS to data out invalid 10 — 30 ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and

are not tested.

PIC16C63A/65B/73B/74B

DS30605D-page 130  1998-2013 Microchip Technology Inc.

FIGURE 16-12 : EXAMPLE SP I MAST E R MODE TIMING (CKE = 0)

TABLE 16-8: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

70 TssL2scH,

TssL2scL SS to SCK or SCK input TCY ——ns

71 TscH SCK input high time

(Slave mode) Continuous 1.25TCY + 30 — — ns

71A Single Byte 40 — — ns (Note 1)

72 TscL SCK input low time

(Slave mode) Continuous 1.25TCY + 30 — — ns

72A Single Byte 40 — — ns (Note 1)

73 TdiV2scH,

TdiV2scL Setup time of SDI data input to SCK edge 100 — — ns

73A TB2BLast clock edge of Byte1 to the 1st clock

edge of Byte2 1.5TCY + 40 — — ns (Note 1)

74 TscH2diL,

TscL2diL Hold time of SDI data input to SCK edge 100 — — ns

75 TdoR SDO dat a outp ut rise time PIC16CXX —1025ns

PIC16LCXX —2045ns

76 TdoF SDO dat a outp ut fall time —1025ns

78 TscR SCK output rise time

(Master mo de) PIC16CXX —1025ns

PIC16LCXX —2045ns

79 TscF SCK output fall time (Master mode) —1025ns

80 TscH2doV,

TscL2doV SD O dat a outp ut val id

after SCK edge PIC16CXX ——50ns

PIC16LCXX — — 100 ns

† Data in “Typ” column is at 5 V, 25°C unles s otherwis e st ated . These pa ram eters are for desig n guidan ce only and

are not tested.

Note 1: Specification 73A is only required if specifications 71A and 72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

73 74

75, 76

MSb LSb

BIT6 - - - - - -1

MSb IN LSb IN

BIT6 - - - -1

Note: Refer to Figure 16-4 for load conditions.

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PIC16C63A/65B/73B/74B

FIGURE 16-13 : EXAMPLE SP I MAST E R MODE TIMING (CKE = 1)

TABLE 16-9: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

75, 76

MSb

MSb IN

BIT6 - - - - - -1

LSb IN

BIT6 - - - -1

LSb

Note: Refer to Figure 16-4 for load conditions.

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

71 TscH SCK input high time

(Slave mode) Continuous 1.25TCY + 30 — — ns

71A Single Byte 40 — — ns (Note 1)

72 TscL SCK input low time

(Slave mode) Continuous 1.25TCY + 30 — — ns

72A Single Byte 40 — — ns (Note 1)

73 TdiV2scH,

TdiV2scL Setup time of SDI data input to SCK edge 100 — — ns

73A TB2BLast clock edge of Byte1 to the 1st cloc k

edge of Byte2 1.5TCY + 40 — — ns (Note 1)

74 TscH2diL,

TscL2diL Hold time of SDI data input to SCK edge 100 — — ns

75 TdoR SDO data output rise

time PIC16CXX — 10 25 ns

PIC16LCXX 20 45 ns

76 TdoF SDO data output fall time — 10 25 ns

78 TscR SCK output rise time

(Master mo de) PIC16CXX — 10 25 ns

PIC16LCXX 20 45 ns

79 TscF SCK output fall time (Master mode) — 10 25 ns

80 TscH2doV,

TscL2doV SD O dat a outp ut val id

after SCK edge PIC16CXX — — 50 ns

PIC16LCXX — 100 ns

81 TdoV2scH,

TdoV2scL SDO data output setup to SCK edge TCY ——ns

† Data in “Typ” colum n is at 5 V, 25°C un les s oth erwi se stated. Thes e parameters are fo r de si gn gui dance only and

are not tested.

Note 1: Specification 73A is only required if specifications 71A and 72A are used.

PIC16C63A/65B/73B/74B

DS30605D-page 132  1998-2013 Microchip Technology Inc.

FIGURE 16-14 : EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

TABLE 16-10: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

70 TssL2scH,

TssL2scL

SS to SCK or SCK input TCY —— ns

71 TscH SCK input high time

(Slave mode) Continuous 1.25TCY + 30 — — ns

71A Single Byte 40 — — ns (Note 1)

72 TscL SCK input lo w time

(Slave mode) Continuous 1.25TCY + 30 — — ns

72A Single Byte 40 — — ns (Note 1)

73 TdiV2scH,

TdiV2scL Setup time of SDI data input to SCK edge 100 — — ns

73A TB2BLast clock edge of Byte1 to the 1st clock

edge of Byte2 1.5TCY + 40 — — ns (Note 1)

74 TscH2diL,

TscL2diL Hold time of SDI data input to SCK edge 100 — — ns

75 TdoR SDO data output rise time PIC16CXX — 10 25 ns

PIC16LCXX 20 45 ns

76 TdoF SDO data output fall time — 10 25 ns

77 TssH2doZ SS to SDO output hi-impedance 10 — 50 ns

78 TscR SCK output rise time

(Master mo de) PIC16CXX — 10 25 ns

PIC16LCXX 20 45 ns

79 TscF SCK output fall time (Master mode) — 10 25 ns

80 TscH2doV,

TscL2doV SD O dat a outp ut val id

after SCK edge PIC16CXX — — 50 ns

PIC16LCXX — 100 ns

83 TscH2ssH,

TscL2ssH SS  after SCK edge 1.5TCY + 40 — — ns

† Data in “Typ” col umn i s at 5 V, 25°C u nle ss o the rw ise s t ated. These parameters are fo r design guidanc e onl y and

are not tested.

Note 1: Specification 73A is only required if specifications 71A and 72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

73 74

75, 76 77

SDI

MSb LSb

BIT6 - - - - - -1

MSb IN BIT6 - - - -1 LSb IN

Note: Refer to Figure 16-4 for load conditions.

 1998-2013 Microchip Technology Inc. DS30605D-page 133

PIC16C63A/65B/73B/74B

FIGURE 16-15 : EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)

TABLE 16-11: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)

Param

No. Symbol Characteristic Min Typ† Max Units Conditions

70 TssL2scH,

TssL2scL SS to SCK or SCK input TCY ——ns

71 TscH SCK input high time

(Slave mode) Continuous 1.25TCY + 30 — — ns

71A Single By te 40 — — ns (Note 1)

72 TscL SCK input low time

(Slave mode) Continuous 1.25TCY + 30 — — ns

72A Single By te 40 — — ns (Note 1)

73A TB2BLast clock edge of Byte1 to the 1st clock

edge of Byte2 1.5TCY + 40 — — ns (Note 1)

74 TscH2diL,

TscL2diL Hold time of SDI data input to SCK edge 100 — — ns

75 TdoR SDO dat a output rise

time PIC16CXX — 10 25 ns

PIC16LCXX 20 45 ns

76 TdoF SDO dat a outp ut fall time —1025ns

77 TssH2doZ SS to SDO output hi-impedance 10 — 50 ns

78 TscR SCK output rise time

(Master mo de) PIC16CXX — 10 25 ns

PIC16LCXX — 20 45 ns

79 TscF SCK output fall time (Master mode) —1025ns

80 TscH2doV,

TscL2doV SD O dat a outp ut val id

after SCK edge PIC16CXX — — 50 ns

PIC16LCXX — — 100 ns

82 TssL2doV SD O dat a outp ut val id

after SS edge PIC16CXX — — 50 ns

PIC16LCXX — — 100 ns

83 TscH2ssH,

TscL2ssH SS  after SCK edge 1.5TCY + 40 — — ns

† Data in “Typ” col um n is a t 5 V, 25 °C un le ss otherwise st ated. These parameters a re for de sign guidance o nly and

are not tested.

Note 1: Specification 73A is only required if specifications 71A and 72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

SDI

75, 76

MSb BIT6 - - - - - -1 LSb

MSb IN BIT6 - - - -1 LSb IN

Note: Refer to Figure 16-4 for load conditions.

PIC16C63A/65B/73B/74B

DS30605D-page 134  1998-2013 Microchip Technology Inc.

FIGURE 16-16 : I2C BUS ST ART/STOP BITS TIMING

TABLE 16-12: I2C BUS START/STOP BITS REQUIREMENTS

FIGURE 16-17 : I2C BUS DATA TIMING

Note: Refer to Figure 16-4 for load conditions.

SCL

SDA

START

Condition STOP

Condition

Param

No. Sym Characteristic Min Typ Max Units Conditions

90* TSU:STA START condition 100 kHz mode 4700 — — ns Only relevant for Repeated

START condition

Setup time 400 kHz mode 600 — —

91* THD:STA START condition 100 kHz mode 4000 — — ns After this period the first clock

pulse is generated

Hold time 400 kHz mode 600 — —

92* TSU:STO STOP condition 100 kHz mode 4700 — — ns

Setup time 400 kHz mode 600 — —

93 THD:STO STOP condition 100 kHz mode 4000 — — ns

Hold time 400 kHz mode 600 — —

* These parameters are characterized but not tested.

Note: Refer to Figure 16-4 for load conditions.

91 92

100

101

103

106 107

109 109 110

102

SCL

SDA

Out

 1998-2013 Microchip Technology Inc. DS30605D-page 135

PIC16C63A/65B/73B/74B

TABLE 16-13: I2C BUS DATA REQUIREMENTS

Param.

No. Sym Characteristic Min Max Units Conditions

100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a

minimum of 1.5 MHz

400 kHz mode 0.6 — s Device must operate at a

minimum of 10 MHz

SSP Module 1.5TCY —

101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a

minimum of 1.5 MHz

400 kHz mode 1.3 — s Device must operate at a

minimum of 10 MHz

SSP Module 1.5TCY —

102* TRSDA and SCL rise

time 100 kHz mode — 1000 ns

400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from

10-400 pF

103* TFSDA and SCL fall

time 100 kHz mode — 300 ns

400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from

10-400 pF

90* TSU:STA START condition

setup time 100 kHz mode 4.7 — s Only relevant for Repeated

START condition

400 kHz mode 0.6 — s

91* THD:STA START condition

hold time 100 kHz mode 4.0 — s After this period the first

clock pulse is generated

400 kHz mode 0.6 — s

106* THD:DAT Data input hold time 100 kHz mode 0 — ns

400 kHz mode 0 0.9 s

107* TSU:DAT Data input setup

time 100 kHz mode 250 — ns (Note 2)

400 kHz mode 100 — ns

92* TSU:STO STOP condition

setup time 100 kHz mode 4.7 — s

400 kHz mode 0.6 — s

109* TAA Output valid from

clock 100 kHz mode — 3500 ns (Note 1)

400 kHz mode — — ns

110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free

before a new transmission

can start

400 kHz mode 1.3 — s

Cb Bus capacitive loading — 400 pF

* These parameters are characterized but not tested.

Note 1: As a transm itter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: A fast mode (400 kHz) I2C bus device can be used in a standard mode (100 k Hz) I2C bus system, but the

requirement Tsu: DAT 250 ns must then be met. This will automatically be the case if the device does not

stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it

must out put the nex t dat a bit to the SD A line TR max.+ts u;DAT = 1000 + 250 = 12 50 ns (accordin g to the st an-

dard mode I2C bus specification) before the SCL line is released.

PIC16C63A/65B/73B/74B

DS30605D-page 136  1998-2013 Microchip Technology Inc.

FIGURE 16-18: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

TABLE 16-14: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

FIGURE 16-19: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

TABLE 16-15: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Note: Refer to Figure 16-4 for load conditions.

121 121

120 122

RC6/TX/CK

RC7/RX/DT

Param

No. Sym Characteristic Min Typ† Max Units Conditions

120* TckH2dtV SYNC XMIT (MASTER &

SLAVE)

Clock high to data out valid

PIC16CXX — — 80 ns

PIC16LCXX — — 100 ns

121* Tckrf Clock out rise time and fall

time (Master mode) PIC16CXX — — 45 ns

PIC16LCXX — — 50 ns

122* Tdtrf Data out rise time and fall time PIC16CXX — — 45 ns

PIC16LCXX — — 50 ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless otherw ise stated. These parameters are for design guidance only and

are not tested.

Note: Refer to Figure 16-4 for load conditions.

125

126

RC6/TX/CK

RC7/RX/DT

Param

No. Sym Characteristic Min Typ† Max Units Conditions

125* TdtV2ckL SYNC RCV (MASTER & SLAVE)

Data setup before CK  (DT setup

time) 15 — — ns

126* TckL2dtl Data hold after CK  (DT hold time) 15 — — ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unles s ot herwise stated. These p ara me ters are for design guidance onl y and

are not tested.

 1998-2013 Microchip Technology Inc. DS30605D-page 137

PIC16C63A/65B/73B/74B

TABLE 16-16: A/D CONVERTER CHARACTERISTICS:

PIC16C73B/74B-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)

PIC16C73B/74B-20 (COMMERCIAL, INDUSTRIAL, EXTENDED)

PIC16LC73B/74B-04 (COMMERCIAL, INDUSTRIAL)

Param

No. Sym Characteristic Min Typ† Max Units Conditions

A01 NRReso lution PIC16CXX — — 8 bits bi t VREF = VDD = 5.12 V,

VSS  VAIN  VREF

PIC16LCXX — — 8 bits bit VREF = VDD = 2.5 V

A02 EABS Total A bsolute error — — < ± 1 LSb VREF = VDD = 5.12 V,

Vss  VAIN  VREF

A03 EIL Integral linearity error — — < ± 1 LSb VREF = VDD = 5.12 V,

Vss  VAIN  VREF

A04 EDL Differential linearity error — — < ± 1 LSb VREF = VDD = 5.12 V,

Vss  VAIN  VREF

A05 EFS Full scale error — — < ± 1 LSb VREF = VDD = 5.12 V,

Vss  VAIN  VREF

A06 EOFF Offset error — — < ± 1 LSb VREF = VDD = 5.12 V,

Vss  VAIN  VREF

A10 — Monotonicity (Note 3) — guaranteed — — Vss  V AIN  VREF

A20 VREF Reference volt ag e 2.5V — VDD + 0.3 V

A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V

A30 ZAIN Recommended impedance of

analog voltage source ——10.0k

A40 IAD A/D conversion

current (VDD)PIC16CXX — 180 — AAverag e current

cons umption when A/D

is on (Note 1)

PIC16LCXX — 90 — A

A50 IREF VREF input current (Note 2) 10

—

1000

A

During VAIN acquisition

Based on differentia l of

VHOLD to VAIN to charge

CHOLD, see Section 12.1

During A/D Conversion

cycle

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5 V, 25C unless ot herwi se st ated. Th ese p arame ters are for de sign gu idanc e only an d

are not tested.

Note 1: When A/D is off, it will not cons ume any current other than minor leakage current. The power-down current

spec includes any such leakage from the A/D module.

2: VREF current is from the RA3 pin or the VDD pin, whichever is selected as a reference input.

3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

PIC16C63A/65B/73B/74B

DS30605D-page 138  1998-2013 Microchip Technology Inc.

FIGURE 16-20: A/D CONVERSION TIMING

TABLE 16-17: A/D CONVERSION REQUIREMENTS

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(TOSC/2)(1)

7 6543210

Note 1: If t he A/D cl ock source is selected as RC, a time of TCY is added before the A/D clock st arts. This allows the SLEEP

instruction to be executed.

1 TCY

134

Param

No. Sym Characteristic Min Typ† Max Units Conditions

130 TAD A/D clock period PIC16CXX 1.6 — — sTOSC based, VREF  3.0 V

PIC16LCXX 2.0 — — sT

OSC based ,

2.5V  VREF  5.5 V

PIC16CXX 2.0 4.0 6.0 s A/D RC mode

PIC16LCXX 3.0 6.0 9.0 s A/D RC mode

131 TCNV Conversion time (not including S/H

time) (Note 1) 11 — 11 TAD

132 TACQ Acquisition time 5* — — s Th e minimum time is the

amplifier settling time. This

may be used if the “new”

input voltage has not

change d by mo re than 1 LSb

(i.e., 20.0mV @ 5.12V) from

the la st sampled voltage (as

stated on CHOLD).

134 TGO Q4 to A/D clock start — TOSC/2 — — If the A/D clock source is

select ed as RC, a tim e of TCY

is added before the A/D clock

start s. Thi s allows the SLEEP

instruction to be executed.

135 TSWC Switching from convert  sample time 1.5 — — TAD

* These parameters ar e character i zed but not tested.

† Data in “Typ” column is at 5V, 25C unles s ot herw i se s t ate d. These parameters are fo r des ign gui dan ce only and

are not tested.

Note 1: ADRES register may be read on the following TCY cycle.

2: See Section 12.1 for minimum conditions.

 1998-2013 Microchip Technology Inc. DS30605D-page 139

PIC16C63A/65B/73B/74B

17.0 DC AND AC

CHARACTERISTICS GRAPHS

AND TABLES

The graphs and tables provided in this section are for

design guidance and are not teste d nor gu aran tee d. In

some graphs or tables the data presented is outside

specified operating range (e.g., outside specified VDD

range). This is for information only and devices are

ensured to operate properly only within the specified

range.

The data presented in this section is a statistical sum-

mary of data collected on units from different lots over

a period of time.

Note: Standard de viation is denote d by sig ma ().

•Typ or Typical represents the mean of the

distribution at 25°C.

•Max or Maximum represent s the mean + 3 over

the temperature range of -40°C to 85°C.

•Min or Minimum represents the mean - 3 over

the temperature range of -40°C to 85°C.

PIC16C63A/65B/73B/74B

DS30605D-page 140  1998-2013 Microchip Technology Inc.

FIGURE 17-1: TYPICAL IDD vs. FOSC OVER VDD – HS MODE

FIGURE 17-2: MAXIMUM IDD vs. FOSC OVER VDD – HS MODE

4 6 8 101214161820

FOSC (MHz)

IDD (mA)

5.0 V

5.5 V

4.5 V

4.0 V

3.5 V

3.0 V

2.5 V

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

4 6 8 10 12 14 16 18 20

FOSC (MHz)

IDD (mA)

5.0 V

5.5 V

4.5 V

4.0 V

3.5 V

3.0 V

2.5 V

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

 1998-2013 Microchip Technology Inc. DS30605D-page 141

PIC16C63A/65B/73B/74B

FIGURE 17-3: TYPICAL IDD vs. FOSC OVER VDD – LP MODE

FIGURE 17-4: MAXIMUM IDD vs. FOSC OVER VDD – LP MODE

100

30 40 50 60 70 80 90 100

FOSC (kHz)

IDD (µA)

5.5 V

5.0 V

4.5 V

4.0 V

3.5 V

3.0 V

2.5 V

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

100

120

140

160

30 40 50 60 70 80 90 100

FOSC (kHz)

IDD (µA)

5.5 V

5.0 V

4.5 V

4.0 V

3.5 V

3.0 V

2.5 V

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

PIC16C63A/65B/73B/74B

DS30605D-page 142  1998-2013 Microchip Technology Inc.

FIGURE 17-5: TYPICAL IDD vs. FOSC OVER VDD – XT MODE

FIGURE 17-6: MAXIMUM IDD vs. FOSC OVER VDD – XT MODE

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

0.00.51.01.52.02.53.03.54.0

FOSC (MH z)

IDD (mA)

5.5 V

5.0 V

4.5 V

4.0 V

3.5 V

3.0 V

2.5 V

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0.00.51.01.52.02.53.03.54.0

FOSC (MH z)

IDD (mA)

5.5 V

5.0 V

4.5 V

4.0 V

3.5 V

3.0 V

2.5 V

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

 1998-2013 Microchip Technology Inc. DS30605D-page 143

PIC16C63A/65B/73B/74B

FIGURE 17-7: AVERAGE FOSC vs. VDD FOR VARIOUS RESISTANCES – RC MODE; C = 20 PF

FIGURE 17-8: AVERAGE FOSC vs. VDD FOR VARIOUS RESISTANCES – RC MODE; C = 100 PF

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

2.53.03.54.04.55.05.5

VDD (V)

FOSC (MHz)

3.3 k

5.1 k

10 k

100 k

Not recomm ended for oper at ion over 4 MHz

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

0.0

0.5

1.0

1.5

2.0

2.5

2.53.03.54.04.55.05.5

VDD (V)

FOSC (MHz)

3.3 k

5.1 k

10 k

100 k

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

PIC16C63A/65B/73B/74B

DS30605D-page 144  1998-2013 Microchip Technology Inc.

FIGURE 17-9: AVERAGE FOSC vs. VDD FOR VARIOUS RESISTANCES – RC MODE; C = 300 PF

FIGURE 17-10 : VTH vs. VDD OVER TEMPERAT URE – TTL INPUT

100

200

300

400

500

600

700

800

900

1,000

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

FOSC (kHz)

3.3 k

5.1 k

10 k

100 k

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

VTH (V)

Max (-40°C)

Min (125°C)

Typ (2 5° C )

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

 1998-2013 Microchip Technology Inc. DS30605D-page 145

PIC16C63A/65B/73B/74B

FIGURE 17-11: VIL, VIH vs. VDD OVER TEMPERATURE – SCHMITT TRIGGER INPUT (I2C)

FIGURE 17-12 : VIL, VIH vs. VDD OVER TEMPERATURE – SCHMITT TRIGGER INPUT

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

VIN (V)

VIH Typ (25°C)

VIL Typ (25°C)

VIL Max (125°C)

VIL Min (-40°C)

VIH Max (125°C)

VIH Min (-40°C)

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

VIN (V)

VIH Typ (25°C)

VIL Typ (25°C)

VIL Max (125°C)

VIL Min (-40°C)

VIH Max (125°C)

VIH Min (-40°C)

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

PIC16C63A/65B/73B/74B

DS30605D-page 146  1998-2013 Microchip Technology Inc.

FIGURE 17-13 : VOH vs. IOH AT VDD = 3.0 V

FIGURE 17-14 : VOH vs. IOH AT VDD = 5.0 V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0 5 10 15 20 25

IOH (mA)

VOH (V)

Typical (25°C)

Max (- 40°C )

Min (125°C)

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0 5 10 15 20 25

IOH (mA)

VOH (V)

Typical (25°C)

Max ( - 40°C )

Min (1 2 5 ° C )

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

 1998-2013 Microchip Technology Inc. DS30605D-page 147

PIC16C63A/65B/73B/74B

FIGURE 17-15 : VOL vs. IOL AT VDD = 3.0 V

FIGURE 17-16 : VOL vs. IOL AT VDD = 5.0 V

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

02468101214161820222426

IOL (-mA )

VOL (V)

Max (125°C)

Typ (25°C)

Min (-40°C)

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

02468101214161820222426

IOL (-mA )

VOL (V)

Max ( 1 25°C )

Typ (25°C)

Min (-4 0°C)

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

PIC16C63A/65B/73B/74B

DS30605D-page 148  1998-2013 Microchip Technology Inc.

FIGURE 17-17 : IPD vs. VDD (85°C) – SLEEP MODE, ALL PERIPHERALS DISABLED

FIGURE 17-18 : IPD vs. VDD (125°C) – SLEEP MODE, ALL PERIPHERALS DISABLED

100

120

140

2.53.03.54.04.55.05.5

VDD (V)

IPD (nA)

Max 85°C

Typ 85°C

Max 25°CMax -40 °C

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

200

400

600

800

1,000

1,200

1,400

2.53.03.54.04.55.05.5

VDD (V)

IPD (nA)

Max (125°C)

Typ (125°C)

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

 1998-2013 Microchip Technology Inc. DS30605D-page 149

PIC16C63A/65B/73B/74B

FIGURE 17-19 : IBOR vs. VDD OVER TEMPERATURE (-40°C TO +125°C)

FIGURE 17-20 : ITIMER1 vs. VDD (-10°C TO +70°C)

100

120

140

160

180

200

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IBOR (uA)

Device

RESET

Device

SLEEP

Typ (25°C)

Typ (2 5° C )

Max (125° C)

Max (125 °C)

Indeterminant

State

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

RESET current depends on

oscillator mode, frequency, and

circuit.

100

120

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

ITIMER1 (uA)

Typical (25°C)

Max (-10°C to 70°C)

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

PIC16C63A/65B/73B/74B

DS30605D-page 150  1998-2013 Microchip Technology Inc.

FIGURE 17-21 : IWDT vs. VDD (-40°C TO +125°C)

FIGURE 17-22 : WDT PERIOD vs. VDD OVER TEMPERATURE (-40°C TO +125°C)

2.53.03.54.04.55.05.5

VDD (V)

IWDT (µA)

Typical (25°C)

Max (-40°C to 125°C)

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

2.53.03.54.04.55.05.5

VDD (V)

WDT Period (ms)

Maximum (125°C)

Minimum (-40°C)

Typical (25° C)

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

 1998-2013 Microchip Technology Inc. DS30605D-page 151

PIC16C63A/65B/73B/74B

FIGURE 17-23: AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40°C TO +125°C)

2.53.03.54.04.55.05.5

VDD (V)

WDT Period (ms)

125°C

85°C

25°C

-40°C

Typical: statistical mean @ 25°C

Maximum: mean + 3 (-40°C to 125°C)

Minimum: mean – 3 (-40°C to 125°C)

PIC16C63A/65B/73B/74B

DS30605D-page 152  1998-2013 Microchip Technology Inc.

NOTES:

 1998-2013 Microchip Technology Inc. DS30605D-page 153

PIC16C63A/65B/73B/74B

18.0 PACKAGING INFORMATION

18.1 Package Marking Information

XXXXXXXXXXXXXXXXXXXX

YYWWNNN

XXXXXXXXXXXXXXXXXXXX

Example

XXXXXXXXXXXXXXXXX

YYWWNNN

28-Lead PDIP (Skinny DIP)

XXXXXXXXXXXXXXXXX

Example

Example28-Lead CERDIP Windowed

Example

0017HAT

PIC16C73B-04/SP

PIC16C73B/JW

0017CAT

XXXXXXXXXXXXXXXXXXXX 0017SAA

PIC16C73B-20/SO

0017SBP

20I/SS025

PIC16C73B-

XXXXXXXXXXXXXX

YYWWNNN

28-Lead SOIC

YYWWNNN

XXXXXXXXXXXX

28-Lead SSOP

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the ful l Micro chip p ar t number can not be marke d on one li ne, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

PIC16C63A/65B/73B/74B

DS30605D-page 154  1998-2013 Microchip Technology Inc.

Package Marking Information (Cont’d)

XXXXXXXXXXXXXXXXXX

YYWWNNN

40-Lead PDIP

XXXXXXXXXXXXXXXXXX

Example

XXXXXXXXXXX

YYWWNNN

40-Lead CERDIP Windowed

XXXXXXXXXXX

Example

44-Lead TQFP

XXXXXXXXXX

YYWWNNN

XXXXXXXXXX

Example

44-Lead PLCC

XXXXXXXXXX

YYWWNNN

XXXXXXXXXX

44-Lead MQFP

Example

XXXXXXXXXXXXXXXXXX 0017SAA

PIC16C74B-04/P

PIC16C74B/JW

0017HAT

-20/PT

0017HAT

PIC16C74B

XXXXXXXXXX

YYWWNNN

XXXXXXXXXX

XXXXXXXXXX -20/PQ

0017SAT

PIC16C74B

0017SAT

-20/L

 1998-2013 Microchip Technology Inc. DS30605D-page 155

PIC16C63A/65B/73B/74B

18.2 28-Lead Skinny Plastic Dual In- li ne (SP) – 300 mil (PDIP)

1510515105



Mold Draft Angle Bottom 1510515105



Mold Draft Angle Top 10.928.898.13.430.350.320eBOverall Row Spacing § 0.560.480.41.022.019.016BLower Lead Width 1.651.331.02.065.053.040B1Upper Lead Width 0.380.290.20.015.012.008

Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 35.1834.6734.161.3851.3651.345DOverall Length 7.497.246.99.295.285.275E1Molded Package Width 8.267.877.62.325.310.300EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 3.433.303.18.135.130.125A2Molded Pack age Thickness 4.063.813.56.160.150.140ATop to Seating Plane 2.54

.100

Pitch 2828

Number of Pins MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERSINCHES*Units





Notes:

JEDEC Equivalent: MO-095

Drawing No. C04-070

* Controlling Parameter

Dimension D and E1 do n ot include mold flash or protrusions. Mold flash or protr usions shall not exceed

.010” (0. 254 mm ) per si de.

§ Significant Characteristic

Note: For the most cu rr e nt pac ka ge dr aw i ngs, p le ase se e t he Mi c ro c hi p Pa ck ag ing Specifica t i on lo ca t ed

at http://www.microchip.com/pac kaging

PIC16C63A/65B/73B/74B

DS30605D-page 156  1998-2013 Microchip Technology Inc.

18.3 28-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)

3.30 3.56 3.81

7.877.627.37.310.300.290W2Window Len gth .150.140.130W1Window Width 10.809.788.76.425.385.345eBOverall Row Spacing § 0.530.470.41.021.019.016BLower Lead Width 1.651.461.27.065.058.050B1Upper Lead Width 0.300.250.20.012.010.008

Lead Thickness 3.683.563.43.145.140.135LTip to Seating Plane 37.7237.0236.321.4851.4581.430DOverall Length 7.497.377.24.295.290.285E1Ceramic Pkg. Width 8.267.947.62.325.313.300EShoulder to Shoulder Width 0.760.570.38.030.023.015A1Standoff 4.194.063.94.165.160.155A2Ceramic Package Height 4.954.644.32.195.183.170A

Top to Seating Plane 2.54.100

Pitch 2828

Numb er of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units

eB p

* Controlling Parameter

§ Significant Characteristic

JEDEC Equivalent: MO-058

Drawing No. C04-080

Note: For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.com /p a ckagi ng

 1998-2013 Microchip Technology Inc. DS30605D-page 157

PIC16C63A/65B/73B/74B

18.4 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)

Foot Angle Top 048048

1512015120



Mold Draft Angle Bottom 1512015120



Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.330.280.23.013.011.009

Lead Thickness

1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 18.0817.8717.65.712.704.695DOverall Length 7.597.497.32.299.295.288E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff § 2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27.050

Pitch 2828

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units



45





* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-052

§ Significant Characteristic

Note: For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.com /p a ckagi ng

PIC16C63A/65B/73B/74B

DS30605D-page 158  1998-2013 Microchip Technology Inc.

18.5 28-Lead Plastic Shrink Small Outl ine (SS) – 209 mil, 5.30 mm (SSOP)

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-150

Drawing No. C04-073

10501050Mold Draft Angle Bottom 10501050



Mold Draft Angle Top 0.380.320.25.015.013.010BLead Width 203.20101.600.00840



Foot Angle 0.250.180.10.010.007.004

Lead Thickness 0.940.750.56.037.030.022LFoot Length 10.3410.2010.06.407.402.396DOveral l Length 5.385.255.11.212.207.201E1Molded Package Width 8.107.857.59.319.309.299EOverall Width 0.250.150.05.010.006.002A1Standoff § 1.831.731.63.072.068.064A2Molded Packa ge Thickness 1.981.851.73.078.073.068AOverall Height 0.65.026

Pitch 2828

Number of Pins MAXNOMMINMAXNOMMINDim en si on Limi ts MILLIMETERS*INCHESUnits









§ Significant Characteristic

Note: For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.com/packaging

 1998-2013 Microchip Technology Inc. DS30605D-page 159

PIC16C63A/65B/73B/74B

18.6 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)

1510515105



Mold Draft Angle Bottom 1510515105



Mold Draft Angle Top 17.2716.5115.75.680.650.620

Overall Row S pacing § 0.560.460.36.022.018.014BLow er Lea d Width 1.781.270.76.070.050.030B1Upp er Lea d Width 0.380.290.20.015.012.008

Lead Thic kness 3.433.303.05.135.130.120LTip to Seating Plane 52.4552.2651.942.0652.0582.045DOverall Length 14.2213.8413.46.560.545.530E1Molded Package Width 15.8815.2415.11.625.600.595EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 4.063.813.56.160.150.140A2Molded Package Thickness 4.834.454.06.190.175.160ATop to Seating Plane 2.54

.100

Pitch 4040

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units





* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-011

Drawing No. C04-016

§ Significant Characteristic

Note: For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.com/packaging

PIC16C63A/65B/73B/74B

DS30605D-page 160  1998-2013 Microchip Technology Inc.

18.7 40-Lead Ceramic Dual In-line with Window (JW) – 600 mil (CERDIP)

9.148.898.64.360.350.340WWindow Diame ter 18.0316.7615.49.710.660.610eBOverall Row Spacin g § 0.580.510.41.023.020.016

Lower Lead Wi dth 1.401.331.27.055.053.050BUpper Lead Width 0.360.280.20.014.011.008

Lead Thickness 3.683.563.43.145.140.135LTip to Seating Plane 52.3252.0751.822.0602.0502.040DOverall Length 13.3613.2113.06.526.520.514

Ceramic Pk g. Width 15.8815.2415.11.625.600.595EShoulder to Shoulder Width 1.521.140.76.060.045.030A1Standoff 4.194.063.94.165.160.155A2Ceramic Package Height 5.725.214.70.225.205.185ATop to Seating Plane 2.54.100

Pitch 40

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units

* Controlling Parameter

§ Significant Characteristic

JEDEC Equivalent: MO-103

Drawing No. C04-014

Note: For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.com /p a ckagi ng

 1998-2013 Microchip Technology Inc. DS30605D-page 161

PIC16C63A/65B/73B/74B

18.8 44-Lead Plastic Thin Quad Flatp ack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form

(TQFP)

* Controlling Parameter

Notes:

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-026

Drawing No. C04-076

1.140.890.64.045.035.025CHPin 1 Corner Chamfer

1.00.039

(F)

Footprint (Reference)

(F)

A1 A2



#leads=n1

D1 D



L

Units INCHES MILLIMETERS*

Dim ension Li mits MIN NOM MAX MIN NOM MAX

Numb er of Pin s n44 44

Pitch p.031 0.80

Overall Height A .039 .043 .047 1.00 1.10 1.20

Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05

Standoff § A1 .002 .004 .006 0.05 0.10 0.15

Foot Length L .018 .024 .030 0.45 0.60 0.75

Foot A ngle 03.5 7 03.5 7

Overall Width E .463 .472 .482 11.75 12.00 12.25

Overall Length D .463 .472 .482 11.75 12.00 12.25

Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10

Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10

Pins per Side n1 11 11

Lead Thickness c.004 .006 .008 0.09 0.15 0.20

Lead Width B .012 .015 .017 0.30 0.38 0.44

Mold Draft Angle Top 51015 51015

Mold Draft Angle Bottom 51015 51015

CH x 45

§ Significant Characteristic

Note: For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.com /p ac k agi ng

PIC16C63A/65B/73B/74B

DS30605D-page 162  1998-2013 Microchip Technology Inc.

18.9 44-Lead Plastic Metric Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead

Form (MQFP)

* Controlling Parameter

Notes:

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-022

Drawing No. C04-071

1510515105



Mold Draft Angle Botto m 1510515105



Mold Draft An gle To p

0.450.380.30.018.015.012Lead Width 0.230.180.13.009.007.005

Lead Thickness

1111n1Pins per Side

10.1010.009.90.398.394.390Molded Package Length 10.1010.009.90.398.394.390E1Molded Package Width 13.4513.2012.95.530.520.510DOverall Length 13.4513.2012.95.530.520.510Over all Width 73.5073.50



Foot Angle

1.030.880.73.041.035.029LFoo t Length 0.250.150.05.010.006.002A1Standoff § 2.102.031.95.083.080.077A2Molded Package Thickness 2.35.093A

Overall Height

0.80.031

Pitch 4444

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS*INCHESUnits

D1 D

#leads=n1





CH x 45

Pin 1 Corner Chamfer

Footprint (Reference) (F) .063 1.60

.025 .035 .045 0.64 0.89 1.14

(F)

.079 .086 2.00 2.18

§ Significant Characteristic

Note: For the most current package drawings, please see the Microchip Pack aging Specification located

at http://www.microchip.com/packaging

 1998-2013 Microchip Technology Inc. DS30605D-page 163

PIC16C63A/65B/73B/74B

18.10 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)

CH2 x 45CH1 x 45

10501050



Mold Draft Angle Bottom 10501050



Mold Draft Angle Top 0.530.510.33.021.020.013B0.810.740.66.032.029.026

Upper Lea d Width 0.330.270.20.013.011.008

Lead Thic kness

1111n1Pins per Si de

16.0015.7514.99.630.620.590D2Footprint Length 16.0015.7514.99.630.620.590E2Footprint Width 16.6616.5916.51.656.653.650D1Molded Package Length 16.6616.5916.51.656.653.650

Molded Package Width 17.6517.5317.40.695.690.685DOverall Length 17.6517.5317.40.695.690.685EOverall Width 0.250.130.00.010.005.000

CH2Corner Chamfer (others) 1.271.141.02.050.045.040CH1Corner Chamfer 1 0.860.740.61.034.029.024A3Side 1 Chamf er H eigh t 0.51.020A1Standoff § A2Molded Package Thickness 4.574.394.19.180.173.165AOverall Height

1.27.050

Pitch 4444

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units



#leads=n1



35

.145 .153 .160 3.68 3.87 4.06

.028 .035 0.71 0.89

Lower Lea d Width

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-047

Drawing No. C04-048

§ Significa nt Char acte risti c

Note: For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.com/packaging

PIC16C63A/65B/73B/74B

DS30605D-page 164  1998-2013 Microchip Technology Inc.

NOTES:

 1998-2013 Microchip Technology Inc. DS30605D-page 165

PIC16C63A/65B/73B/74B

APPENDIX A: REVISION HISTORY

APPENDIX B: DEVICE DIFFERENCES

The differences between the devices in this data sheet are listed in Table B-1.

Version Date Revision Desc ri ption

A 7/98 This is a new data sheet. However, the devices described in this data sheet are

the upgrades to the devices found in the PIC16C6X Data Sheet, DS30234, and

the PIC1 6C7X D at a Shee t, DS30390.

B 1/99 Corrections to Version A data sheet for technical accuracy.

Added data:

• Operation of the SMP and CKE bits of the SSPSTAT register in I2C mode

have been specified

• Frequ enc y vs. VDD graphs for device operating area (in Electrical

Specifications)

• Formula f or calculati ng A/D acquisition time, TACQ (in the A/D section)

• Brief desc ription of instructions

Removed data (see PICmicro TM Mid-Range MCU Family Reference Manual,

DS33023, for additional data):

• USART Baud Rate Tables (formulas for calculating baud rate remain )

C 12/00 • Minor changes to text to clarify content

• Revised some DC specifications

• Included characteristic charts and graphs

D 01/13 • Added a note to every package drawing.

TABLE B-1: DEVICE DIFFERENCES

Difference PIC16C63A PIC16C65B PIC16C73B PIC16C74B

A/D no no 5 channels, 8 bits 8 channels, 8 bits

Parallel Slave Port no yes no yes

Packages 28-pin PDIP, 28-pin

windowed CERDIP,

28-pin SOIC, 2 8-pi n

SSOP

40-pin PDIP, 40-pin

windowed CERDIP,

44-pin TQFP, 44-pin

MQFP, 44-pin PLCC

28-pin PDIP, 28-pin

windowed CERDIP,

28-pin SOIC, 2 8-pi n

SSOP

40-pin PDIP, 40-pin

windowed CERDIP,

44-pin TQFP, 44-pin

MQFP, 44-pin PLCC

PIC16C63A/65B/73B/74B

DS30605D-page 166  1998-2013 Microchip Technology Inc.

APPENDIX C: DEVICE MIGRATIONS -

PIC16C63/65A/73A/74A PIC16C63A/65B/73B/74B

This document is intended to describe the functional differences and the electrical specification differences that are

present when migrating from one device to the next. Table C-1 shows functional differences, while Table C-2 shows

electrical and timing differences.

TABLE C-1: FUNCTIONAL DIFFERENCES

Note: Even though compatible devices are specified to be tested to the same electrical specification, the device

characteristics may be different from each other (due to process differences). For systems that were

designed to the device specifications, these process differences should not cause any issues in the appli-

cation. For systems tha t did not tight ly meet the elec trical specif ications, the pr ocess dif ferences ma y cause

the device to behave differently in the application.

Note: While there are no functional or electrical changes to the device oscillator specifications, the user shou ld

verify that the device oscillator starts and performs as expected. Adjusting the loading capacitor values

and/or the oscillator mode may be required.

No. Module Differences from PIC16C63/65A/73A/74A H/W S/W Prog.

1 CCP CCP Special Event Trigger clears Timer1. —✔—

2 Compare mode drives pin correctly. —✔—

3 Timers Writing to TMR1L does not affect TMR1H. —✔—

4 WDT/TMR0 prescaler assignment changes do not affect TMR0 count. —✔—

5 SSP TMR2 SPI clock synchronized to start of SPI Transmission. —✔—

6 Can now transmit multiple words in SPI mode. —✔—

7 Supports all four SPI modes. (Now uses SSP vs. BSSP module.)

See SSP module in the PIC® Mid-Range MCU Family Reference Manual

(DS33023).

—✔—

2C no longer generat es ACK puls es w hen modul e is ena ble d. —✔—

9 USART Async receive errors due to BRGH setting corrected. —✔—

10 A/D VREF = VDD when all inputs are configured as digital.

This allows conversion of di gital inputs. ( A/D on PIC16C73X/74X onl y.) —✔—

H/W - Issues may exist with regard to the application circuits.

S/W - Issues may exist with regard to the user program.

Prog. - Issues may exist when writing the program to the controller.

 1998-2013 Microchip Technology Inc. DS30605D-page 167

PIC16C63A/65B/73B/74B

TABLE C-2: SPECIFICATION DIFFERENCES

Param

No. Symbol Characteristic PIC16C63/65A/73A/74A PIC16C63A/65B/73B/74B Unit

Min Typ† Max Min Typ† Max

Core

D001

D001A VDD Supply Voltage 4.0

——

—6.0

—4.0

VBOR(1) —

—5.5

5.5 V

D005 BVDD Brown-out Reset Voltage 3.7 4.0 4.3 3.65 —4.35 V

D150* VOD Open-D rain High Volt age on

RA4 ——14.0 - —8.5 V

A/D Converter

A20 VREF Reference voltag e 3.0 — VDD + 0.3 2.5 —VDD + 0.3 V

131 TCNV Conve rs i on t ime (Note 2)

(not including S/H time) —9.5

(N ote 3) —11

(No te 4) —11

(Note 4) TAD

SSP in SPI mode

71 TscH SCK input high

time (Slave mode) Continuous TCY+20 — — 1.25TCY + 30 ——ns

71A Single Byt e 40 ——ns

72 TscL SCK input low

time

(Slave mode)

Continuous TCY+20 — — 1.25TCY + 30 ——ns

72A Single Byt e 40 ——ns

73 TdiV2scH

TdiV2scL Setup tim e of SDI da ta input to

SCK edge 50 — — 100 ——ns

73A

(Not e 5) TB2BLast cl oc k edge of Byte1 to the

1st clock edge of Byte2 —— —1.5TCY + 40 ——ns

74 TscH2diL

TscL2diL Hold time of SDI data input to

SCK edge 50 — — 100 ——ns

75 TdoR SDO data output

rise time PIC16CXX — 10 25 — 10 25 ns

PIC16LCXX — 20 45 ns

78 TscR SCK output rise

time (Master

mode)

PIC16CXX — 10 25 — 10 25 ns

PIC16LCXX — 20 45 ns

80 TscH2doV

TscL2doV SDO data output

valid after SC K

edge

PIC16CXX — — 50 — — 50 ns

PIC16LCXX — — 100 ns

83 TscH2ssH

TscL2ssH SS  after SCK edge — — 50 1.5TCY + 40 ——ns

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: When BOR is enabled, th e device will operate un t il VDD drops below VBOR.

2: ADRES register may be read on the following TCY cycle.

3: This is the time th at th e actual conversi on requires.

4: This is the time from when the GO/DONE bit is set, to when the conversion result appears in ADRES.

5: Specification 73A is only required if specifications 71A and 72A are use d.

PIC16C63A/65B/73B/74B

DS30605D-page 168  1998-2013 Microchip Technology Inc.

APPENDIX D: MIGRATION FROM BASELINE TO MID-RANGE DEVICES

This section discusses how to migrate from a baseline

device (i.e., PIC16C5X) to a mid-range device (i.e.,

PIC16CXXX).

The following are the list of modifications over the

PIC16C5X mi cro con trol ler family:

1. Instruction word length is increased to 14-bits.

This allows larger page sizes, both in program

memory (2 K now as opposed to 512 before)

and regis ter file (128 bytes now versu s 32 bytes

before).

2. A PC high latch register (PCLATH) is added to

handle program memory paging. Bits PA2, PA1

and PA0 are removed from STATUS register.

3. Data memory paging is redefined slightly.

STATUS register is modified.

4. Four new instructions have been added:

RETURN, RETFIE, ADDLW and SUBLW.

Two instructions, TRIS and OPTION, are being

phased out, although they are kept for compati-

bility with PIC16C5 X.

5. OPTION and TR IS re gi ste r s a re ma de address-

able.

6. Interrupt capability is added. Interrupt vector is

at 0004h.

7. Stack size is increased to 8-deep.

8. RESET vector is changed to 0000h.

9. RESET of al l regi st ers is revisited. Five d ifferent

RESET (and wake-up) types are recognized.

Registers are reset differently.

10. Wake up from SLEEP through interrupt is

added.

11. Two separate timers, Oscillator Start-up Timer

(OST) and Power-up Timer (PWRT) are

included for more reliable power-up. These tim-

ers are invoked selectively to avoid unneces-

sary delays on pow e r-up and wake-up .

12. PORTB has weak pull-ups and

interrupt-on-change feature.

13. T0CKI pin is also a port pin (RA4) now.

14. FSR is made a full 8-bi t regis ter.

15. “In-Circuit Serial Programming” (ICSP) is made

possible. The user can program PIC16CXX

devices using only five pins: VDD, VSS,

MCLR/VPP, RB6 (clock) and RB7 (data in/out).

16. PCON status register is added with a Power-on

Reset status bit (POR).

17. Code protection s che me is e nhanced, such th at

portions of the program memory can be pro-

tected, while the remainder is unprotected.

18. Brown-out protection circuitry has been added.

Controlled by configuration word bit BODEN.

Brown-ou t Reset ensure s the device is placed in

a RESET condition if VDD dips below a fixed

setpoint.

To convert code written for PIC16C5X to PIC16CXX,

the user should take the following steps:

1. Remove any program memory page select

operatio ns (P A2, PA1, PA0 bits) for CALL, GOTO.

2. Revisit any computed jump operations (w rite to

PC or add to PC, etc.) to make sure page bits

are set properly under the new scheme.

3. Eliminate any data memory page switching.

Redefine data variables to reallocate them.

4. Verify all writes to STATUS, OPTION and FSR

registers since these have changed.

5. Change RESET vector to 0000h.

 1998-2013 Microchip Technology Inc. DS30605D-page 169

PIC16C63A/65B/73B/74B

INDEX

A/D ADCON0 Register.......................................................79

ADCON1 Register.......................................................80

Analog Input Model Block Diagram.............. ......... .... ..82

Analog-to-Digital Converter .........................................79

Block Diag ram................. ........... ..................... .......... ..81

Configuring Analog Port Pins......................................83

Configuring the Interrupt.............................................81

Configuring the Module...............................................81

Conversi o n Clo ck.... .......... ..................... ........... ..........83

Conversions................................................................83

Converter Characteristics .........................................137

Effects of a RESET.....................................................83

Faster Conversion - Lower Resolution Trade-off........83

Internal Sampling Switch (Rss) Impedance................82

Operation During SLEEP............................................83

Sampling Requirements..................... .... .. .... ....... .... .. ..82

Source Impedance................................................ ......82

Timing Diagram .........................................................138

Using the CCP Trigger. ...............................................83

Absolute Maximum Ratings..............................................113

ACK...............................................................................60, 62

ADRES Register...........................................................17, 79

Application Notes

AN552 (Implementing Wake-up on Key Strokes

Using PIC16CXXX).....................................................31

AN556 (Table Reading Using PIC16CXX)..................26

AN578 (Use of the SSP Module in the I2C

Multi-Master Environment)..........................................55

AN607, (Power-up Trouble Shooting).........................89

Architecture

Overview.......................................................................9

Assembler

MPASM® Assembler.................................................107

Baud Rate Formula.............................................................67

BF .................................................................................56, 60

Block Diagrams

A/D..............................................................................81

Analog Input Model.....................................................82

Capture.......................................................................51

Compare.....................................................................52

I2C Mode.....................................................................60

On-Chip Rese t Circuit..... .......................................... ..88

PIC16C74 ...................................................................10

PIC16C74A.................................................................10

PIC16C77 ...................................................................10

PORTC .......................................................................33

PORTD (In I/O Port Mode) . .........................................34

PORTD and PORTE as a Parallel Slave Port.............37

PORTE (In I/O Port Mode)..........................................35

PWM...........................................................................52

RA4/T0CKI Pin. ........... .......... ..................... ........... ......29

RB3:RB0 Port Pins ...................................... ...............31

RB7:RB4 Port Pins ...................................... ...............31

SSP in I2C Mode.........................................................60

SSP in SPI Mode........................................................55

Timer0/WDT Pres cale r.... ........... .......... ........... ............39

Timer2.........................................................................47

USART Receive..........................................................70

USART Transmit.........................................................68

Watchdog Timer..........................................................96

BOR bit......................................................................... 25, 89

BRGH bit ............................................................................ 67

Brown-out Reset (BOR)

Timing Diagram........................................................ 126

Buffer Full Status bit, BF..................................................... 56

C bit ......... .......... ........... .......... ..................... ........... .......... .. 19

Capture/Compare/PWM

Capture

Block Diag ram........ ........... ..................... ............ 51

CCP1CON Register............................................ 50

CCP1IF............................................................... 51

Mode .................................................................. 51

Prescaler ............................................................ 51

CCP Timer Resources................. ........... .................... 49

Compare

Block Diag ram........ ........... ..................... ............ 52

Mode .................................................................. 52

Software Interrupt Mode..................................... 52

Special Event Trigger......................................... 52

Special Trigger Output of CCP1......................... 52

Special Trigger Output of CCP2......................... 52

Interaction of Two CCP Modules................................ 49

Section........................................................................ 49

Spec ial Event Trigger and A /D Conve rsions ............... 52

Capture/Compare/PWM (CCP)

PWM Block Diagr a m ........... .......... ........... .......... ........ 52

PWM Mode................... ........... .......... ........... .......... .... 52

PWM, Example Frequencies/ Resolut ions .................. 53

Timing Diagram........................................................ 128

CCP2IE bit....... ........... .......... ........... .......... ........... .......... .... 24

CCP2IF bit.................. .......... ..................... ........... .......... .... 24

CCPR1H Register......................................................... 17, 49

CCPR1L Register............................................................... 49

CCPR2H Register............................................................... 17

CCPR2L Register............................................................... 17

CCPxM0 bit......................................................................... 50

CCPxM1 bit......................................................................... 50

CCPxM2 bit......................................................................... 50

CCPxM3 bit......................................................................... 50

CCPxX bit........................................................................... 50

CCPxY bit........................................................................... 50

CKE .................................................................................... 56

CKP .................................................................................... 57

Clock Polarity Select bit, CKP................. ............................ 57

Cloc ki n g Scheme..... .. .............. ............. ............. ................. 14

Code Examples

Call of a Subroutine in Page 1 from Page 0............... 26

Indir ect Addressin g.. ............. ................... ................... 27

Initializing PORTA....................................................... 29

Code Protection............................................................ 85, 98

Computed GOTO................................................................ 26

Configur a ti o n Bi ts ........ ................... .............. ................... ... 85

CREN bit................................. ..................... ..................... .. 66

CS pin................................................................................. 37

PIC16C63A/65B/73B/74B

DS30605D-page 170  1998-2013 Microchip Technology Inc.

D/A......................................................................................56

Data Memory

Data/Add r e ss b i t, D/ A..........................................................56

DC bit..................................................................................19

Development Support ...........................................................5

Device Differences............................................................165

Direct Add ressing..... ..................... .......... ........... .................27

Electrical Characteristics...................................................113

Errata ....................................................................................3

FERR bit..............................................................................66

FSR Register...........................................................17, 18, 27

General Description ..................................... .... .... .. .... ......... ..5

GIE bit..... ........... .......... ........... .......... ........... .......... ........... ..93

I/O Por ts

PORTA........................................................................29

PORTB........................................................................31

PORTC........................................................................33

PORTD..................................................................34, 37

PORTE........................................................................35

Section........................................................................29

I2CAddressing..................................................................61

Block Diag ram................... .......... ..................... ...........60

I2C Operation..............................................................60

Master Mode...............................................................64

Mode...........................................................................60

Mode Selection ...........................................................60

Multi-Master Mode......................................................64

Reception....................................................................62

Reception Timing Diagr a m.......... ..................... ...........62

SCL and SDA pins......................................................60

Slave Mode.................................................................60

Transmission...............................................................63

I2C (SSP Module)

Timing Diagram, Data ...............................................134

Timing Diagram, START/STOP Bits ..........................134

In-Circuit Serial Programming.......................................85, 98

INDF Register .........................................................1 7, 18, 27

Indirect Addressing .............................................................27

Instruction Cycle..................................................................14

Instruction Flow/Pipelining ..................................................14

Instruction Format...............................................................99

Instruction Set

ADDLW .....................................................................101

ADDWF.....................................................................101

ANDLW .....................................................................101

ANDWF.....................................................................101

BCF...........................................................................101

BSF...........................................................................101

BTFSC ......................................................................102

BTFSS ......................................................................102

CALL.........................................................................102

CLRF.........................................................................102

CLRW........................................................................102

CLRWDT...................................................................102

COMF....................................................................... 103

DECF........................................................................ 103

DECFSZ ................................................................... 103

GOTO ....................................................................... 103

INCF ......................................................................... 103

INCFSZ..................................................................... 103

IORLW...................................................................... 104

IORWF...................................................................... 104

MOVF ....................................................................... 104

MOVLW .................................................................... 104

MOVWF.................................................................... 104

NOP.......................................................................... 104

RETFIE..................................................................... 105

RETLW ..................................................................... 105

RETURN................................................................... 105

RLF........................................................................... 105

RRF .......................................................................... 105

SLEEP...................................................................... 105

SUBLW..................................................................... 106

SUBWF..................................................................... 106

SWAPF..................................................................... 106

XORLW..................................................................... 106

XORWF .................................................................... 106

Section........................................................................ 99

Summary Table......... .......... ........... .......... ........... ...... 100

INT In t e r ru p t.............. ........................ .................... .............. 94

INTCON Register................................................................ 21

INTEDG bit ................................................................... 20, 94

Internal Sampling Switch (Rss ) Impedance........................ 82

Interrupts............................................................................. 85

PORTB Change.......................................................... 94

RB7:RB4 Port Change................... .... .... .... .. ......... .... .. 31

Section........................................................................ 93

TMR0.......................................................................... 94

IRP bit.............. ............... .......... ........... .............. ........... ...... 19

KEELOQ Evaluation and Programming Tools.................... 110

Loading of PC.................................................. ........... .... .... 26

MCLR............................................................................ 87, 90

Memory

Data Mem o ry .......... ..................... .......... ..................... 15

Program Memory........................................................ 15

Program Mem ory Maps

PIC16C73........................................................... 15

PIC16C73A......................................................... 15

PIC16C74........................................................... 15

PIC16C74A......................................................... 15

PIC16C73........................................................... 16

PIC16C73A......................................................... 16

PIC16C74........................................................... 16

PIC16C74A......................................................... 16

PIC16C76........................................................... 16

PIC16C77........................................................... 16

MPLAB® Integrated Development

Environ ment Software ........ .......... ........... .......... ........... .... 107

 1998-2013 Microchip Technology Inc. DS30605D-page 171

PIC16C63A/65B/73B/74B

OERR bit.............................................................................66

OPCODE ............................................................................99

OPTION Register................................................................20

OSC Selection ....................................................................85

Oscillator

HS.........................................................................86, 90

LP..........................................................................86, 90

RC...............................................................................86

XT .........................................................................86, 90

Oscillator Configurations.....................................................86

Output o f TMR2 .................. .......... ........... ..................... ......47

P..........................................................................................56

Packaging.........................................................................153

Pagin g , Program Memory..... . ......... ........... ............... ..........26

Parallel Slave Port ........................................................34, 37

Parallel Slave Port (PSP)

Timing Diagram .........................................................129

PCFG0 bit......................... .......... ........... .......... ........... ........80

PCFG1 bit......................... .......... ........... .......... ........... ........80

PCFG2 bit......................... .......... ........... .......... ........... ........80

PCL Register...........................................................17, 18, 26

PCLATH..............................................................................91

PCLATH Register ............. .......... ........... .................17, 18, 26

PCON Register .............................................................25, 89

PD bit............................................................................19, 87

PICDEMTM 1 Low Cost PIC MCU

Demonstration Board........................................................109

PICDEMTM 2 Low Cost PIC16CXX

Demonstration Board........................................................109

PICDEMTM 3 Low Cost PIC16CXXX

Demonstration Board........................................................110

PICSTART® Plus Entry Level

Development System........................................................109

PIE1 Register......................................................................22

PIE2 Register......................................................................24

Pin Functions

MCLR/VPP............................................................. 11, 12

OSC1/CLKIN.........................................................11, 12

OSC2/CLKOUT.....................................................11, 12

RA0/AN0...............................................................11, 12

RA1/AN1...............................................................11, 12

RA2/AN2...............................................................11, 12

RA3/AN3/VREF...................................................... 11, 12

RA4/T0CKI............................................................11, 12

RA5/AN4/SS......................................................... 11, 12

RB0/INT................................................................11, 12

RB1.......................................................................11, 12

RB2.......................................................................11, 12

RB3.......................................................................11, 12

RB4.......................................................................11, 12

RB5.......................................................................11, 12

RB6.......................................................................11, 12

RB7.......................................................................11, 12

RC0/T1OSO/T1CKI ..............................................11, 13

RC1/T1OSI/CCP2.................................................11, 13

RC2/CCP1............................................................11, 13

RC3/SCK/SCL ......................................................11, 13

RC4/SDI/SDA .......................................................11, 13

RC5/SDO..............................................................11, 13

RC6/TX/CK...............................................11, 13, 65–76

RC7/RX/DT...............................................11, 13, 65–76

RD0/PSP0...................................................................13

RD1/PSP1.................................................................. 13

RD2/PSP2.................................................................. 13

RD3/PSP3.................................................................. 13

RD4/PSP4.................................................................. 13

RD5/PSP5.................................................................. 13

RD6/PSP6.................................................................. 13

RD7/PSP7.................................................................. 13

RE0/RD/AN5 .............................................................. 13

RE1/WR/AN6.............................................................. 13

RE2/CS/AN7............................................................... 13

VDD........................................................................11, 13

VSS ........................................................................11, 13

Pinout Descriptions

PIC16C73................................................................... 11

PIC16C73A................................................................. 11

PIC16C74................................................................... 12

PIC16C74A................................................................. 12

PIC16C76................................................................... 11

PIC16C77................................................................... 12

PIR1 Register ..................................................................... 23

PIR2 Register ..................................................................... 24

POP.................................................................................... 26

POR.................................................................................... 89

Oscillator Start-up Timer (OST)....... ................. .. .. 85, 89

Power Control Register (PCON)................................. 89

Power-on R e se t (POR).. .. ....... ........ ............. ... 85, 89, 91

Power-up Timer (P W RT ) .......... ........ ............. ........ ..... 85

Power-Up-Timer (PWRT) ........................................... 89

TO............................................................................... 87

POR bit......................................................................... 25, 89

Port RB Interrupt ................................................................. 94

PORTA ............................................................................... 91

PORTA Register........................................................... 17, 29

PORTB ............................................................................... 91

PORTB Register........................................................... 17, 31

PORTC............................................................................... 91

PORTC Register........................................................... 17, 33

PORTD............................................................................... 91

PORTD Register........................................................... 17, 34

PORTE ............................................................................... 91

PORTE Register........................................................... 17, 35

Power-down Mode (SL EEP )............................................... 97

Power-on Reset (POR)

Timing Diagram........................................................ 126

PR2 Register................................................................ 18, 47

PRO MA TE ® II Univers a l Programmer............................. 109

Product Identification System........................................... 177

Program Mem ory

Paging ........................................................................ 26

Program Mem ory Maps

PIC16C73................................................................... 15

PIC16C73A................................................................. 15

PIC16C74................................................................... 15

PIC16C74A................................................................. 15

Prog r a m Ve rifica t ion .... ........ ............. ........ ....... ........ ........... 98

PS0 bit............. ........... .......... ........... .......... ........... .......... .... 20

PS1 bit............. ........... .......... ........... .......... ........... .......... .... 20

PS2 bit............. ........... .......... ........... .......... ........... .......... .... 20

PSA bit................................................................................ 20

PSPMODE bit......................................................... 34, 35, 37

PUSH.................................................................................. 26

PIC16C63A/65B/73B/74B

DS30605D-page 172  1998-2013 Microchip Technology Inc.

R/W.....................................................................................56

R/W bit....................................................................61, 62, 63

RBIF bit................ ..................... .......... ........... .......... .....31, 94

RBPU bit ....... ........... .......... ........... .......... ........... .......... .......20

RC Oscillator.................................................................87, 90

RCSTA Regis te r....... ..................... ..................... .......... .......66

RD pin.................................................................................37

Read/Write bit Information, R/W .........................................56

Receive Overflow Indic a to r bit, SSPOV....... .......................57

Registers

MapsPIC16C73 ...........................................................16

PIC16C73A.........................................................16

PIC16C74 ...........................................................16

PIC16C74A.........................................................16

RESET Conditions........................ ......... .. .... .. .... .. .......90

SSPSTAT....................................................................56

Summary.....................................................................17

RESET..........................................................................85, 87

Timing Diagram.........................................................126

RESET Conditions for Special Registers............................90

Revision History................................................................165

RP0 bit..........................................................................15, 19

RP1 bit................................................................................19

RX9 bit................................................................................66

RX9D bit..............................................................................66

S..........................................................................................56

SCL.....................................................................................60

Serial Communication Interface (SCI) Module,

See USART

Services

One-Time-Pro g rammable (OTP)............ .......... ........... ..7

Quick-Turnaround-Production (QTP)............................7

Serialized Quick-Turnaround Production

(SQTP)..........................................................................7

Slave Mode

SCL.............................................................................60

SDA.............................................................................60

SLEEP...........................................................................85, 87

SMP ....................................................................................56

Softwa re Simulator (MPLAB - SIM)......... ........... .......... .......108

SPBRG Register.................................................................18

Speci a l Features of the CPU....... .......... ..................... .........85

Special Function Registers

PIC16C73 ...................................................................17

PIC16C73A.................................................................17

PIC16C74 ...................................................................17

PIC16C74A.................................................................17

Special Function Registers, Section ...................................16

SPEN bit..............................................................................66

SPI Block Diagra m............ ........... ..................... .......... .......55

Master Mode Timing ...................................................58

Serial Clock.................................................................55

Serial Data In ..............................................................55

Serial Data Out............................................................55

Slave Mode Timing .....................................................59

Slave Mode Timing Diagr a m....... ........... .....................58

Slave Select................................................................55

SSPCON.....................................................................57

SSPSTAT.................................................................... 56

SPI Clock Edge Select bit, CKE ......................................... 56

SPI Data Input Sample Phase Select bit, SMP .................. 56

SREN bit............................................................................. 66

SSP Module Overview........................................................55

Section........................................................................ 55

SSPCON .................................................................... 57

SSPSTAT.................................................................... 56

SSPADD Regist e r.... ........... .......................................... ...... 18

SSPBUF Register............................................................... 17

SSPCON............................................................................. 57

SSPCON Register.............................................................. 17

SSPEN................................................................................ 57

SSPM3:SSPM0 .................................................................. 57

SSPOV ......................................................................... 57, 60

SSPSTAT Regi ster............. .......... ........... .....................18, 56

Stack................................................................................... 26

Overflows.................................................................... 26

Underflow ................................................................... 26

STAR T b i t, S............. ....... ........ ........ ....... .............. ....... ....... 56

STATUS Regi ster ............... .......... ..................... ........... ...... 19

STOP b i t, P... .. ............. .............. ............. .............. ............. . 56

Synchronous Serial Port Enable bit, SSPEN....... ............... 57

Synchronous Serial Port Mode Select bits,

SSPM3:SSPM0 .................................................................. 57

Synchronous Serial Port Module ........................................ 55

Synchronous Serial Port Status Register ........................... 56

T0CS bit.............................................................................. 20

T1C KPS0 bit.................. ................... ......................... ......... 43

T1C KPS1 bit.................. ................... ......................... ......... 43

T1CON Registe r................. .......... ..................... ................. 43

T1OSCEN bit......... ........... ..................... .......... ................... 43

T1SYNC bit......................................................................... 43

T2C KPS0 bit.................. ................... ......................... ......... 47

T2C KPS1 bit.................. ................... ......................... ......... 47

T2CON Registe r................. .......... ..................... ................. 47

TAD...................................................................................... 83

Timer0

RTCC.......................................................................... 91

Timing Diagram ........................................................ 127

Timer1

Timing Diagram ........................................................ 127

Timers

Timer0

External Clock .................................................... 40

Interrupt.............................................................. 39

Prescaler ............................................................ 40

Pres ca l e r Bl o ck Diagra m. . .............. ....... ........ .. ... 3 9

Section................................................................ 39

T0CKI ................................................................. 40

T0IF .................................................................... 94

TMR0 In terrup t ............ ................... .................... 94

Timer1

Asynchronous Counter Mode............................. 45

Capacitor Selection ............................................ 45

Operation in Timer Mode.................................... 44

Oscillator............................................................. 45

Prescaler ............................................................ 45

Resetting of Timer1 Registers............................ 45

Resetting Timer1 using a CCP

Trigger Output ................................... ......... .. .... .. 45

Synchronized Counter Mode.............................. 44

T1CON ............................................................... 43

 1998-2013 Microchip Technology Inc. DS30605D-page 173

PIC16C63A/65B/73B/74B

TMR1H ...............................................................45

TMR1L................................................................45

Timer2

Block Diag ram .............. ........... ..................... ......47

Module................................................................47

Postscaler...........................................................47

Prescaler.............................................................47

T2CON................................................................47

Timing Diagrams

I2C Recepti o n (7 -bit Addr e ss)........ ..................... ........62

SPI Master Mode........................................................58

SPI Slave Mode (CKE = 1) .........................................59

SPI Sla ve M o d e Ti ming (CK E = 0).. .. ........ ....... ........ .. .58

USART Asynchronous Master Transmission..............69

USART Asynchronous Reception...............................71

USART Synchronous Reception.................................75

USART Synchronous Transmission............................73

Wake-up from SLEEP via Interr u p t........ ........... ..........98

Timing Diagrams and Specifications......................... .... ....124

A/D Conversion......... .......... ..................... ........... ......138

Brown-out Reset (BOR)............................................126

Capture/Compare/PWM (CCP).................................128

CLKOUT and I/O. . .....................................................125

External Clock...........................................................124

I2C Bus Data.............................................................134

I2C Bus START/STOP Bits .......................................134

Oscillator Start-up Tim er (OST). ................................126

Paral l e l Sla ve Por t (P SP)........................... ........... ....129

Power-up Timer (PWRT)........................ ........... ........126

RESET......................................................................126

Timer0 and Timer1.............. ........... .... .... .... ........... ....127

USART Synchronous Receive (Master/Slave ) .........136

USART SynchronousTransmission (Master/Slave)..136

Watchdog Ti mer (WDT) ............................................126

TMR0 Register....................................................................17

TMR1CS bit ............. ..................... ........... .......... ........... ......43

TMR1H Register.................................................................17

TMR1L Register..................................................................17

TMR1ON bit........................................................................43

TMR2 Register....................................................................17

TMR2ON bit........................................................................47

TO bit ..................................................................................19

TOUTPS0 bit.......................................................................47

TOUTPS1 bit.......................................................................47

TOUTPS2 bit.......................................................................47

TOUTPS3 bit.......................................................................47

TRISA Register.............................................................18, 29

TRISB Register.............................................................18, 31

TRISC Register.. ........... ..................... .......... ........... ......18, 33

TRISD Register.. ........... ..................... .......... ........... ......18, 34

TRISE Register.......................................................18, 35, 36

TXSTA Regi ster.............. .......... ........... .......... ........... ..........65

UA....................................................................................... 56

Universal Synchronous Asynchronous Receiver

Transmitter (USART)........ ........... .......... ........... .......... ........ 65

Update Address bit, UA............................... ....... .... .... .. .... .. 56

USART

Asynchronous Mode................................................... 68

Asynchronous Receiver.... .......................................... 70

Asynchronous Receptio n............................................ 71

Asynchronous Transmitter.......................................... 68

Baud Rate Generator (BRG) ...................................... 67

Receive Block Diagram.............................. ................ 70

Sampling..................................................................... 67

Synchronous Master Mode......................................... 72

Timing Diagram, Synchronous Receive........... 136

Timing Diagram, Synchronous Transmission... 136

Synchronous Master Reception ................................. 74

Synchronous Master Transmission ............................ 72

Synchronous Slave Mode.................. ............. ...... ...... 76

Synchronous Slave Reception ................................... 76

Synchronous Slave T ransmit...................................... 76

Transmit Block Diagram ............................................. 68

UV Er a sa b l e D e vi c e s.................. ........ ............. .............. ....... 7

Wake-up from SLEEP......................................................... 97

Watchdog Timer (WDT)........ ..................... ....... 85, 8 7 , 90, 95

Timing Diagram........................................................ 126

WCOL................................................................................. 57

WDT ................................................................................... 90

Block Diag ram......................... ..................... .......... .... 96

Period......................................................................... 95

Programming Considerations..................................... 96

Time-out...................................................................... 91

WR pin... .......... ........... .......... ........... .......... ........... .......... .... 37

Write Collision Detect bit, WCOL........................................ 57

WWW, On-Line S upport....................................................... 3

Z bit..................................................................................... 19

PIC16C63A/65B/73B/74B

DS30605D-page 174  1998-2013 Microchip Technology Inc.

NOTES:

 1998-2013 Microchip Technology Inc. DS30605D-page 175

THE MICROCHIP WEB SITE

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Customers should contact their distributor,

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Technical suppo rt is a vailable throug h the we b site

at: http://microchip.com/support

DS30605D-page 176  1998-2013 Microchip Technology Inc.

READER RESP ONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip

product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our

documentation can better serve you, please FAX your comments to the Technical Publications Manager at

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Please li st the following information, and use this outline to provide us with your comments about this document.

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DS30605D

1. What are the best features of this d ocument?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

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 1998-2013 Microchip Technology Inc. DS30605D-page 177

PIC16C63A/65B/73B/74B

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

* JW Devices are UV er asable and can be programm ed to any device configurat ion. JW Devices meet the electr ical requirement of

each oscillator type (including LC devices).

Sales and Support

PART NO. -XX X/XX XXX

PatternPackageTemperature

Range

Frequency

Range

Device

Device PIC16C6X(1), PIC16C6XT(2); VDD range 4.0V to 5.5V

PIC16LC6X(1), PIC16LC6XT(2); VDD range 2.5V to 5.5V

PIC16C7X(1), PIC16C7XT(2); VDD range 4.0V to 5.5V

PIC16LC7X(1), PIC16LC7XT(2); VDD range 2.5V to 5.5V

Freq uency Range 04 = 4 MHz

20 = 20 MHz

Temperature Range blank = 0°C to 70°C (Commercial)

I = -40°C to +85°C (Industrial)

E = -40°C to +125 °C (E xten ded )

Package JW = Windowed CERDIP

PQ = MQFP (Metric PQFP)

PT = TQFP (Thin Quad Flatpack)

SO = SOIC

SP = Skinny plastic dip

P=PDIP

L=PLCC

SS = SSOP

Pattern QTP, SQTP, Code or Special Requirements

(blank oth erwis e )

Examples:

a) PIC16C74B -04/P 301 = Commercial temp.,

PDIP package, 4 MHz, normal VDD limits, QTP

pattern #301.

b) PIC16LC63A - 04I/SO = Industrial temp., SOIC

package, 200 kHz, Extend ed VDD limits.

c) PIC16C65B - 20I/P = Industrial temp., PDIP

package, 20 MHz, norma l VDD limits.

Note 1: C = CMOS

LC = Low Power CMOS

2: T = in tape and reel - SOIC, SSOP,

PLCC, QFP, TQ and FP

packages only.

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Worldwide Site (www. micro chip.com)

PIC16C63A/65B/73B/74B

DS30605D-page 178  1998-2013 Microchip Technology Inc.

NOTES:

 1998-2013 Microchip Technology Inc. DS30605D-page 179

PIC16C63A/65B/73B/74B

NOTES:

PIC16C63A/65B/73B/74B

DS30605D-page 180  1998-2013 Microchip Technology Inc.

NOTES:

 1998-2013 Microchip Technology Inc. DS30605D-page 181

PIC16C63A/65B/73B/74B

NOTES:

PIC16C63A/65B/73B/74B

DS30605D-page 182  1998-2013 Microchip Technology Inc.

NOTES:

 1998-2013 Microchip Technology Inc. DS30605D-page 183

PIC16C63A/65B/73B/74B

NOTES:

PIC16C63A/65B/73B/74B

DS30605D-page 184  1998-2013 Microchip Technology Inc.

 1998-2013 Microchip Technology Inc. DS30605D-page 185

Information contained in this publication regarding device

applications and the like is provided only for your con ve nien ce

and may be supersed ed by updates. It is y our respo ns ibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

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suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, PIC 32 logo, rfPIC, SST, SST Logo, SuperFlash

and UNI/O are registered trademarks of Microchip T echnology

Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor ,

MTP, SEEVAL and The Em bedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom,

chipKIT, chipKI T logo, CodeGuard, dsPICDEM ,

dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONIT OR, FanSens e , HI- TIDE, In-Circu it Se r i a l

Programm ing, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,

Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA

and Z-Scale are trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip

Tec hnolog y Germany II Gm bH & Co. & KG, a subsidiary of

Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 9781620769324

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its f amily of products is one of t he most secure famili es of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contai ned in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT S

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

DS30605D-page 186  1998-2013 Microchip Technology Inc.

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11/29/12