Low Cost, 4-Channel, 16-Bit 1 MSPS
PulSAR® ADC
AD7655
Rev. B
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FEATURES
4-channel, 16-bit resolution ADC
2 track-and-hold amplifiers
Throughput
1 MSPS (normal mode)
888 kSPS (impulse mode)
Analog input voltage range: 0 V to 5 V
No pipeline delay
Parallel and serial 5 V/3 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Single 5 V supply operation
Power dissipation
120 mW typical
2.6 mW @ 10 kSPS
Package
48-lead quad flat package (LQFP)
48-lead frame chip scale package (LFCSP)
Pin-to-pin compatible with the AD7654
Low cost
APPLICATIONS
AC motor control
3-phase power control
4-channel data acquisition
Uninterrupted power supplies
Communications
FUNCTIONAL BLOCK DIAGRAM
CONTROL LOGIC AND
CALIBRATION CIRCUITRY A/B
16 D[15:0]
BUSY
CS
SER/PAR
OGND
OVDD
DGNDDVDD
SERIAL
PORT
BYTESWAP
RD
AVDD AGND REFxREFGND
PD
RESET
CNVST
INAN
SWITCHED
CAP DAC
AD7655
INA1
IMPULSE
MUX
EOC
INA2
A0
INB1
INBN
INB2
TRACK/HOLD
×2
PARALLEL
INTERFACE
03536-001
CLOCK
MUX
MUX
Figure 1.
Table 1. PulSAR Selection
Type/kSPS
100 to 250
500 to 570
800 to
1000
>1000
Pseudo
Differential
AD7660/
AD7661
AD7650/
AD7652
AD7664/
AD7666
AD7653
AD7667
True Bipolar AD7663 AD7665 AD7671
True
Differential
AD7675
AD7676
AD7677
AD7621
AD7623
18 Bit AD7678 AD7679 AD7674 AD7641
Multichannel/
Simultaneous
AD7654 AD7655
GENERAL DESCRIPTION
The AD7655 is a low cost, simultaneous sampling, dual-
channel, 16-bit, charge redistribution SAR, analog-to-digital
converter that operates from a single 5 V power supply. It
contains two low noise, wide bandwidth, track-and-hold
amplifiers that allow simultaneous sampling, a high speed
16-bit sampling ADC, an internal conversion clock, error
correction circuits, and both serial and parallel system interface
ports. Each track-and-hold has a multiplexer in front to provide
a 4-channel input ADC. The A0 multiplexer control input
allows the choice of simultaneously sampling input pairs
INA1/INB1 (A0 = low) or INA2/INB2 (A0 = high). The part
features a very high sampling rate mode (normal) and, for low
power applications, a reduced power mode (impulse) where the
power is scaled with the throughput. Operation is specified
from −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Multichannel ADC.
The AD7655 features 4-channel inputs with two sample-
and-hold circuits that allow simultaneous sampling.
2. Fast Throughput.
The AD7655 is a 1 MSPS, charge redistribution, 16-bit SAR
ADC with internal error correction circuitry.
3. Single-Supply Operation.
The AD7655 operates from a single 5 V supply. In impulse
mode, its power dissipation decreases with throughput.
4. Serial or Parallel Interface.
Versatile parallel or 2-wire serial interface arrangements
are compatible with both 3 V and 5 V logic.
AD7655
Rev. B | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Ter mi no lo g y .................................................................................... 11
Typical Performance Characteristics ........................................... 12
Application Information................................................................ 14
Circuit Information.................................................................... 14
Modes of Operation ................................................................... 14
Transfer Functions...................................................................... 14
Typical Connection Diagram ................................................... 16
Analog Inputs.............................................................................. 16
Input Channel Multiplexer........................................................ 16
Driver Amplifier Choice ........................................................... 16
Voltage Reference Input ............................................................ 17
Power Supply............................................................................... 17
Power Dissipation....................................................................... 17
Conversion Control ................................................................... 18
Digital Interface.......................................................................... 18
Parallel Interface ......................................................................... 18
Serial Interface ............................................................................ 20
Master Serial Interface............................................................... 20
Slave Serial Interface .................................................................. 22
Microprocessor Interfacing....................................................... 24
SPI Interface (ADSP-219X)....................................................... 24
Application Hints ........................................................................... 25
Layout .......................................................................................... 25
Evaluating the AD7655 Performance...................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 27
REVISION HISTORY
9/05—Rev. A to Rev. B
Changes to General Description .................................................... 1
Changes to Specifications................................................................ 3
Changes to Timing Specifications.................................................. 5
Changes to Typical Performance Characteristics....................... 13
Changes to Figure 17...................................................................... 15
Added Table 8.................................................................................. 17
Changes to Figure 28...................................................................... 21
Updated Outline Dimensions....................................................... 26
Changes to Ordering Guide .......................................................... 27
12/04—Rev. 0 to Rev. A
Changes to Figure 17...................................................................... 15
Changes to Figure 18...................................................................... 16
Changes to Voltage Reference Input section .............................. 17
Changes to Conversion Control section ..................................... 18
Changes to Digital Interface section............................................ 18
Updated Outline Dimensions....................................................... 25
11/02—Revision 0: Initial Version
AD7655
Rev. B | Page 3 of 28
SPECIFICATIONS
AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range VINx – VINxN 0 2 VREF V
Common-Mode Input Voltage VINxN −0.1 +0.5 V
Analog Input CMRR fIN = 100 kHz 55 dB
Input Current 1 MSPS throughput 45 μA
Input Impedance1
THROUGHPUT SPEED
Complete Cycle (2 Channels) Normal mode 2 μs
Throughput Rate Normal mode 0 1 MSPS
Complete Cycle (2 Channels) Impulse mode 2.25 μs
Throughput Rate Impulse mode 0 888 kSPS
DC ACCURACY
Integral Linearity Error2 −6 +6 LSB3
No Missing Codes 15 Bits
Transition Noise 0.8 LSB
Full-Scale Error4 TMIN to TMAX ±0.25 ±0.5 % of FSR
Full-Scale Error Drift4 ±2 ppm/°C
Unipolar Zero Error4 T
MIN to TMAX ±0.25 % of FSR
Unipolar Zero Error Drift4 ±0.8 ppm/°C
Power Supply Sensitivity AVDD = 5 V ± 5% ±0.8 LSB
AC ACCURACY
Signal-to-Noise fIN = 100 kHz 86 dB5
Spurious-Free Dynamic Range fIN = 100 kHz 98 dB
Total Harmonic Distortion fIN = 100 kHz −96 dB
Signal-to-Noise and Distortion fIN = 100 kHz 86 dB
f
IN = 100 kHz, −60 dB input 30 dB
Channel-to-Channel Isolation fIN = 100 kHz −92 dB
−3 dB Input Bandwidth 10 MHz
SAMPLING DYNAMICS
Aperture Delay 2 ns
Aperture Delay Matching 30 ps
Aperture Jitter 5 ps rms
Transient Response Full-scale step 250 ns
REFERENCE
External Reference Voltage Range 2.3 2.5 AVDD/2 V
External Reference Current Drain 1 MSPS throughput 180 μA
DIGITAL INPUTS
Logic Levels
VIL −0.3 +0.8 V
VIH +2.0 DVDD + 0.3 V
IIL −1 +1 μA
IIH −1 +1 μA
DIGITAL OUTPUTS
Data Format6
Pipeline Delay7
VOL ISINK = 1.6 mA 0.4 V
VOH ISOURCE = −500 μA OVDD − 0.2 V
AD7655
Rev. B | Page 4 of 28
Parameter Conditions Min Typ Max Unit
POWER SUPPLIES
Specified Performance
AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.258 V
Operating Current9 1 MSPS throughput
AVDD 15.5 mA
DVDD 8.5 mA
OVDD 100 μA
Power Dissipation 1 MSPS throughput9 120 135 mW
20 kSPS throughput10 2.6 mW
888 kSPS throughput10 114 125 mW
TEMPERATURE RANGE11
Specified Performance TMIN to TMAX −40 +85 °C
1 See the Analog Inputs section.
2 Linearity is tested using endpoints, not best fit.
3 LSB means least significant bit. With the 0 V to 5 V input range, 1 LSB is 76.294 μV.
4 See the Terminology section. These specifications do not include the error contribution from the external reference.
5 All specifications in dB are referred to as full-scale input, FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified.
6 Parallel or serial 16 bit.
7 Conversion results are available immediately after completed conversion.
8 The maximum should be the minimum of 5.25 V and DVDD + 0.3 V.
9 In normal mode; tested in parallel reading mode.
10 In impulse mode; tested in parallel reading mode.
11 Consult sales for extended temperature range.
AD7655
Rev. B | Page 5 of 28
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (See Figure 21 and Figure 22)
Convert Pulse Width t1 5 ns
Time Between Conversions
(Normal Mode/Impulse Mode) t2 2/2.25 μs
CNVST Low to BUSY High Delay t3 32 ns
BUSY High All Modes Except in Master Serial Read After Convert Mode
(Normal Mode/Impulse Mode) t4 1.75/2 μs
Aperture Delay t5 2 ns
End of Conversions to BUSY Low Delay t6 10 ns
Conversion Time
(Normal Mode/Impulse Mode) t7 1.75/2 μs
Acquisition Time t8 250 ns
RESET Pulse Width t9 10 ns
CNVST Low to EOC High Delay t10 30 ns
EOC High for Channel A Conversion
(Normal Mode/Impulse Mode) t11 1/1.25 μs
EOC Low after Channel A Conversion t12 45 ns
EOC High for Channel B Conversion t13 0.75 μs
Channel Selection Setup Time t14 250 ns
Channel Selection Hold Time t15 30 ns
PARALLEL INTERFACE MODES (See Figure 23 to Figure 27)
CNVST Low to DATA Valid Delay t16 1.75/2 μs
DATA Valid to BUSY Low Delay t17 14 ns
Bus Access Request to DATA Valid t18 40 ns
Bus Relinquish Time t19 5 15 ns
A/B Low to Data Valid Delay t20 40 ns
MASTER SERIAL INTERFACE MODES (See Figure 28 and Figure 29)
CS Low to SYNC Valid Delay t21 10 ns
CS Low to Internal SCLK Valid Delay1 t22 10 ns
CS Low to SDOUT Delay t23 10 ns
CNVST Low to SYNC Delay, Read During Convert
(Normal Mode/Impulse Mode) t24 250/500 ns
SYNC Asserted to SCLK First Edge Delay t25 3 ns
Internal SCK Period2t26 23 40 ns
Internal SCLK High2t27 12 ns
Internal SCLK Low2 t28 7 ns
SDOUT Valid Setup Time2t29 4 ns
SDOUT Valid Hold Time2t30 2 ns
SCLK Last Edge to SYNC Delay2t31 1 ns
CS High to SYNC HI-Z t32 10 ns
CS High to Internal SCLK HI-Z t33 10 ns
CS High to SDOUT HI-Z t34 10 ns
BUSY High in Master Serial Read after Convert2 t35 See Table 4
CNVST Low to SYNC Asserted Delay
(Normal Mode/Impulse Mode) t36 0.75/1 μs
SYNC Deasserted to BUSY Low Delay t37 25 ns
AD7655
Rev. B | Page 6 of 28
Parameter Symbol Min Typ Max Unit
SLAVE SERIAL INTERFACE MODES (See Figure 31 and Figure 32)
External SCLK Setup Time t38 5 ns
External SCLK Active Edge to SDOUT Delay t39 3 18 ns
SDIN Setup Time t40 5 ns
SDIN Hold Time t41 5 ns
External SCLK Period t42 25 ns
External SCLK High t43 10 ns
External SCLK Low t44 10 ns
1 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise CL is 60 pF maximum.
2 In serial master read during convert mode. See Table 4 for serial master read after convert mode.
Table 4. Serial Clock Timings in Master Read After Convert
DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum t25 3 17 17 17 ns
Internal SCLK Period Minimum t26 25 50 100 200 ns
Internal SCLK Period Typical t26 40 70 140 280 ns
Internal SCLK High Minimum t27 12 22 50 100 ns
Internal SCLK Low Minimum t28 7 21 49 99 ns
SDOUT Valid Setup Time Minimum t29 4 18 18 18 ns
SDOUT Valid Hold Time Minimum t30 2 4 30 80 ns
SCLK Last Edge to SYNC Delay Minimum t31 1 3 30 80 ns
Busy High Width Maximum (Normal) t35 3.25 4.25 6.25 10.75 μs
Busy High Width Maximum (Impulse) t35 3.5 4.5 6.5 11 μs
AD7655
Rev. B | Page 7 of 28
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Values
Analog Input
INAx1, INBx1, REFx, INxN, REFGND AVDD + 0.3 V to
AGND − 0.3 V
Ground Voltage Differences
AGND, DGND, OGND ±0.3 V
Supply Voltages
AVDD, DVDD, OVDD –0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD ±7 V
DVDD to OVDD −0.3 V to +7 V
Digital Inputs −0.3 V to DVDD + 0.3 V
Internal Power Dissipation2700 mW
Internal Power Dissipation32.5 W
Junction Temperature 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range
(Soldering 10 sec) 300°C
1 See the Analog Inputs section.
2 Specification is for device in free air: 48-lead LQFP, θJA = 91°C/W,
θJC = 30°C/W.
3 Specification is for device in free air: 48-lead LFCSP, θJA = 26°C/W.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
TO OUTPUT
PIN C
L
60pF*
500μAI
OH
1.6mA I
OL
1.4V
*IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
03536-002
Figure 2. Load Circuit for Digital Interface Timing
0.8V 2V
2V
0.8V
t
DELAY
2V
0.8V
t
DELAY
03536-003
Figure 3. Voltage Reference Levels for Timing
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
AD7655
Rev. B | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48
AGND
47
AGND
46
INA1
45
INAN
44
INA2
43
REFA
42
REFB
41
INB2
40
INBN
39
INB1
38
REFGN
D
37
REF
35
CNVST
34
PD
33
RESET
30
EOC
31
RD
32
CS
36
DVDD
29
BUSY
28
D15
27
D14
25
D12
26
D13
2
AVDD
3
A0
4
BYTESWAP
7
IMPULSE
6
DGND
5
A/B
1
AGND
8
SER/PAR
9
D0
10
D1
12
D3/DIVSCLK[1]
11
D2/DIVSCLK[0]
13
D4/EXT/INT
14
D5/INVSYNC
15
D6/INVSCLK
16
D7/RDC/SDIN
17
OGND
18
OVDD
19
DVDD
20
DGND
21
D8/SDOUT
22
D9/SCLK
23
D10/SYNC
24
D11/RDERROR
PIN 1
AD7655
TOP VIEW
(Not to Scale)
03536-004
Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1, 47, 48 AGND P Analog Power Ground Pin.
2 AVDD P Input Analog Power Pin. Nominally 5 V.
3 A0 DI Multiplexer Select. When LOW, the analog inputs INA1 and INB1 are sampled simultaneously, then
converted. When HIGH, the analog inputs INA2 and INB2 are sampled simultaneously, then converted.
4 BYTESWAP DI Parallel Mode Selection (8 Bit, 16 Bit). When LOW, the LSB is output on D[7:0] and the MSB is output on
D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
5 A/B DI Data Channel Selection. In parallel mode, when LOW, the data from Channel B is read. When HIGH,
the data from Channel A is read. In serial mode, when HIGH, Channel A is output first followed by
Channel B. When LOW, Channel B is output first followed by Channel A.
6, 20 DGND P Digital Power Ground.
7 IMPULSE DI Mode Selection. When HIGH, this input selects a reduced power mode. In this mode, the power
dissipation is approximately proportional to the sampling rate.
8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface
mode is selected and some bits of the DATA bus are used as a serial port.
9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high
impedance.
11, 12 D[2:3] or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data Output Bus.
DIVSCLK[0:1]
When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW, which is the serial master read after
convert mode. These inputs, part of the serial port, are used to slow down the internal serial clock that
clocks the data output. In the other serial modes, these inputs are not used.
13 D[4] DI/O When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.
or EXT/INT When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing
the internal or an external data clock called, respectively, master and slave mode. With EXT/INT tied
LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is
synchronized to an external clock signal connected to the SCLK input.
14 D[5] DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
or INVSYNC When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC
signal in Master modes. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
AD7655
Rev. B | Page 9 of 28
Pin No. Mnemonic Type1 Description
15 D[6] DI/O When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus.
or INVSCLK When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in
both master and slave modes.
16 D[7] DI/O When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.
or RDC/SDIN When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a
read mode selection input, depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN can be used as a data input to daisy-chain the conversion results
from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT
with a delay of 32 SCLK periods after the initiation of the read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the
previous data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output
on SDOUT only when the conversion is complete.
17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface
(5 V or 3 V).
19, 36 DVDD P Digital Power. Nominally at 5 V.
21 D[8] DO When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
or SDOUT When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized
to SCLK. Conversion results are stored in a 32-bit on-chip register. The AD7655 provides the two
conversion results, MSB first, from its internal shift register. The order of channel outputs is controlled
by A/B. In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK.
In serial mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge.
If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge.
22 D[9] DI/O When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
or SCLK When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output,
depends upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated
depends on the logic state of the INVSCLK pin.
23 D[10] DO When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.
or SYNC When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = Logic LOW).
When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and frames SDOUT. After
the first channel is output, SYNC is pulsed LOW. When a read sequence is initiated and INVSYNC is
HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. After the first channel is
output, SYNC is pulsed HIGH.
24 D[11] DO When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.
or RDERROR When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used as an
incomplete read error flag. In slave mode, when a data read is started but not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed HIGH.
25 to 28 D[12:15] DO Bit 12 to Bit 15 of the parallel port data output bus. When SER/PAR is HIGH, these outputs are in high
impedance.
29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the two
conversions are complete and the data is latched into the on-chip shift register. The falling edge of
BUSY can be used as a data ready clock signal.
30 EOC DO End of Convert Output. Goes LOW at each channel conversion.
31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is
also used to gate the external serial clock.
33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7655. Current conversion, if any, is aborted. If not
used, this pin could be tied to DGND.
34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are
inhibited after the current conversion is completed.
AD7655
Rev. B | Page 10 of 28
Pin No. Mnemonic Type1 Description
35 CNVST DI Start Conversion. A falling edge on CNVST puts the internal sample-and-hold into the hold state and
initiates a conversion. In impulse mode (IMPULSE = HIGH), if CNVST is held LOW when the acquisition
phase (t8) is complete, the internal sample-and-hold is put into the hold state and a conversion is
immediately started.
37 REF AI This input pin is used to provide a reference to the converter.
38 REFGND AI Reference Input Analog Ground.
39, 41 INB1, INB2 AI Channel B Analog Inputs.
40, 45 INBN, INAN AI Analog Inputs Ground Senses. Allow to sense each channel ground independently.
42, 43 REFB, REFA AI These inputs are the references applied to Channel A and Channel B, respectively.
44, 46 INA2, INA1 AI Channel A Analog Inputs.
1 Al = input; DI = digital input; DO = digital output; DI/O = bidirectional digital; P = power.
AD7655
Rev. B | Page 11 of 28
TERMINOLOGY
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSBs beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value,
and is often specified in terms of resolution for which no
missing codes are guaranteed.
Full-Scale Error
The last transition (from 111. . .10 to 111. . .11) should occur for
an analog voltage 1½ LSBs below the nominal full scale
(4.999886 V for the 0 V to 5 V range). The full-scale error is the
deviation of the actual level of the last transition from the ideal
level.
Unipolar Zero Error
The first transition should occur at a level ½ LSB above analog
ground (76.29 μV for the 0 V to 5 V range). The unipolar zero
error is the deviation of the actual transition from that point.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Signal-to-Noise and Distortion Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels, between the rms amplitude of the
input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD and expressed in bits by
ENOB = (SINADdB − 1.76)/6.02
Aperture Delay
Aperture delay is a measure of acquisition performance and is
measured from the falling edge of the CNVST input to when
the input signals are held for a conversion.
Transient Response
The time required for the AD7655 to achieve its rated accuracy
after a full-scale step function is applied to its input.
AD7655
Rev. B | Page 12 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
65536
CODE
INL (LSB)
0
–4
–5
–2
–3
–1
2
1
4
3
5
16384
032768 49152
03536-005
Figure 5. Integral Nonlinearity vs. Code
CODE IN HEX
COUNTS
4000
3000
2000
1000
07FFD
7059
1094 1230
77 29 00
00
7FFE 7FFF 8000 8001 8002 8003 8004 8005
8000
7000
6000
5000
7FFC
6894
03536-006
Figure 6. Histogram of 16,384 Conversions of a DC Input at the
Code Transition
FREQUENCY (kHz)
AMPLITUDE (dB of Full Scale)
–140
–160
–180 025 125 150
50 75 100 175 200 225 250
–80
–100
–120
–20
–40
–60
08192 POINT FFT
f
S
= 500kHz
f
IN
= 100kHz, –0.5dB
SNR = 85.8dB
THD = –91.4dB
SFDR = 93.6dB
SINAD = 84.5dB
03536-007
Figure 7. FFT Plot
65536
CODE
DNL (LSB)
0
–3
–2
–1
1
2
3
163840 32768 49152
03536-008
Figure 8. Differential Nonlinearity vs. Code
CO DE I N HEX
COUNTS
4000
3000
2000
1000
0
8480
3505 3396
220
739
39 0
05
9000
8000
7000
6000
5000
03536-009
7FFD 7FFE 7FFF 8000 8001 8002 8003 80047FFC
Figure 9. Histogram of 16,384 Conversions of a DC Input at the
Code Center
TEMPERATURE (°C)
SNR (dB)
90
87
84 –15 5 25 45 65 85 105 125
96
93
–35
–55
–98
–102
–106
–90
–94
THD (dB)
THD
SNR
03536-010
Figure 10. SNR, THD vs. Temperature
AD7655
Rev. B | Page 13 of 28
FREQUENCY (kHz)
SNR AND SINAD (dB)
85
80
75
70 110 100 1000
100
95
90
SNR
SINAD
ENOB (Bits)
14.5
14.0
13.5
13.0
16.0
15.5
15.0
ENOB
03536-011
Figure 11. SNR, SINAD, and ENOB vs. Frequency
FREQUENCY (kHz)
THD, HARMONICS (dB)
–90
–95
–100
–105
–110 110 100 1000
–75
–80
–85
SFDR
CROSSTALK B TO A
CROSSTALK A TO B
THD
THIRD HARMONIC SECOND HARMONIC
03536-012
SFDR (dB)
90
85
80
75
70
105
100
95
Figure 12. THD, Harmonics, Crosstalk, and SFDR vs. Frequency
–55 5 65 125
TEMPERATURE (
°
C)
LSB
0
–4
–5
–2
–3
–1
2
1
4
3
5
25–35 –15 45 85 105
03536-013
FULL-SCALE ERROR
ZERO ERROR
Figure 13. Full-Scale Error and Zero Error vs. Temperature
OPERATING CURRENTS (mA)
10
1
0.1
100
SAMPLING RATE (kSPS)
10 100 1000
1
NORMAL AVDD
NORMAL DVDD
IMPULSE AVDD
OVDD 2.7V
0.01
0.001
0.0001
IMPULSE DVDD
03536-014
Figure 14. Operating Currents vs. Sample Rate
C
L
(pF)
t
18
DELAY (ns)
20
10
00 50 100 200
50
40
30
OVDD = 2.7V @ 85°C
OVDD = 2.7V @ 25°C
OVDD = 5V @ 85°C
OVDD = 5V @ 25°C
150
03536-015
Figure 15. Typical Delay vs. Load Capacitance CL
AD7655
Rev. B | Page 14 of 28
APPLICATION INFORMATION
CIRCUIT INFORMATION
The AD7655 is a very fast, low power, single-supply, precise
simultaneous sampling 16-bit ADC.
The AD7655 provides the user with two on-chip, track-and-
hold, successive approximation ADCs that do not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications. The AD7655 can also be used as a
4-channel ADC with two pairs simultaneously sampled.
The AD7655 can be operated from a single 5 V supply and be
interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP or a tiny, 48-lead LFCSP that combines space
savings and allows flexible configurations as either a serial or
parallel interface. The AD7655 is pin-to-pin compatible with
PulSAR ADCs.
MODES OF OPERATION
The AD7655 features two modes of operation, normal mode
and impulse mode. Each of these modes is suitable for specific
applications.
Normal mode is the fastest mode (1 MSPS). Except when it is
powered down (PD = HIGH), the power dissipation is almost
independent of the sampling rate.
Impulse mode, the lowest power dissipation mode, allows
power saving between conversions. The maximum throughput
in this mode is 888 kSPS. When operating at 20 kSPS, for
example, it typically consumes only 2.6 mW. This feature makes
the AD7655 ideal for battery-powered applications.
TRANSFER FUNCTIONS
The AD7655 data format is straight binary. The ideal transfer
characteristic for the AD7655 is shown in Figure 16 and Table 7 .
The LSB size is 2 × VREF/65536, which is about 76.3 μV.
000...000
000...001
000...010
111...101
111...110
111...111
ANALOG INPUT+FS – 1.5 LSB
+FS – 1 LSB
–FS + 1 LSB–FS
–FS + 0.5 LSB
ADC CODE (Straight Binary)
03536-016
Figure 16. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Description
Analog Input
VREF = 2.5 V
Digital Output Code
FSR − 1 LSB 4.999924 V 0xFFFF1
FSR − 2 LSB 4.999847 V 0xFFFE
Midscale + 1 LSB 2.500076 V 0x8001
Midscale 2.5 V 0x8000
Midscale − 1 LSB 2.499924 V 0x7FFF
−FSR + 1 LSB −76.29 μV 0x0001
−FSR 0 V 0x00002
1 This is also the code for overrange analog input:
(V – V above 2 × (V – V )).
INx INxN REF REFGND
2 This is also the code for underrange analog input (VINx below VINxN).
AD7655
Rev. B | Page 15 of 28
AVDD AGND DGND DVDD OVDD OGND
SER/PAR
CNVST
BUSY
SDOUT
SCLK
RD
CS
RESET
PD
REFGND
C
REF
2.5V REF
NOTE 1
REF
REF A
REF B
30Ω
D
CLOCK
AD7655
μC/μP/
DSP
SERIAL PORT
DIGITAL SUPPLY
(3.3V OR 5V)
ANALOG
SUPPLY
(5V)
DVDD
A/B
NOTE 7
BYTESWAP
DVDD
50kΩ
100nF
1MΩ
INA1
C
C
2.7nF
U1
NOTE 4
NOTE 5
50Ω
-
+
10Ω
2.7nF
U2
NOTE 4
NOTE 5
50Ω
-
+
10Ω
INAN
INA2
NOTE 2
NOTE 3
NOTE 6
AD780
10μF100nF
+100nF
+100nF +10μF
50Ω
+
NOTES
1. SEE VOLTAGE REFERENCE INPUT SECTION.
2. WITH THE RECOMMENDED VOLTAGE REFERENCES, C
REF
IS 47μF. SEE VOLTAGE REFERENCE INPUT SECTION.
3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION.
4. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
5. SEE ANALOG INPUTS SECTION.
6. OPTIONAL, SEE POWER SUPPLY SECTION.
7. OPTIONAL LOW JITTER CNVST. SEE CONVERSION CONTROL SECTION.
A0
INB1
2.7nF
U3
NOTE 4
NOTE 5
50Ω
-
+
10Ω
INBN
2.7nF
U4
NOTE 4
NOTE 5
50Ω
-
+
10ΩINB2
ANALOG INPUT A1
ANALOG INPUT A2
ANALOG INPUT B1
A
NALOG INPUT B
2
C
C
C
C
C
C
10μF
1μF
03536-017
NOTE 1
Figure 17. Typical Connection Diagram (Serial Interface)
AD7655
Rev. B | Page 16 of 28
TYPICAL CONNECTION DIAGRAM
Figure 17 shows a typical connection diagram for the AD7655.
Some of the circuitry shown in this diagram is optional and is
discussed in the following sections.
ANALOG INPUTS
Figure 18 shows a simplified analog input section of the
AD7655.
INA1 R
A
INB2
C
S
C
S
AGND
AVDD
INA2
INAN
INBN
INB1
R
B
03536-018
A0
A0 = L
A0 = L
A0 = H
A0 = H
Figure 18. Simplified Analog Input
The diodes shown in Figure 18 provide ESD protection for
the inputs. Care must be taken to ensure that the analog input
signal never exceeds the absolute ratings on these inputs.
This causes the diodes to become forward biased and start
conducting current. These diodes can handle a forward-biased
current of 120 mA maximum. This condition can occur when
the input buffer (U1) or (U2) supplies are different from AVDD.
In such a case, an input buffer with a short-circuit current
limitation can be used to protect the part.
This analog input structure allows the sampling of the
differential signal between INx and INxN. Unlike other
converters, the INxN is sampled at the same time as the INx
input. By using differential inputs, small signals common to
both inputs are rejected.
During the acquisition phase, for ac signals, the AD7655
behaves like a one-pole RC filter consisting of the equivalent
resistance RA, RB, and CBS. The resistors RA and RBB are typically
500 Ω and are a lumped component made up of some serial
resistors and the on resistance of the switches. The CS capacitor
is typically 32 pF and is mainly the ADC sampling capacitor.
This one-pole filter with a typical −3 dB cutoff frequency of
10 MHz reduces undesirable aliasing effects and limits the
noise coming from the inputs.
Because the input impedance of the AD7655 is very high, the
AD7655 can be driven directly by a low impedance source
without gain error. To further improve the noise filtering of the
AD7655 analog input circuit, an external, one-pole RC filter
between the amplifier output and the ADC input, as shown in
Figure 17, can be used. However, the source impedance has to
be kept low because it affects the ac performance, especially the
total harmonic distortion. The maximum source impedance
depends on the amount of total harmonic distortion (THD)
that can be tolerated. The THD degrades when the source
impedance increases.
INPUT CHANNEL MULTIPLEXER
The AD7655 allows the choice of simultaneously sampling the
inputs pairs INA1/INB1 or INA2/INB2 with the A0 multiplexer
input. When A0 is low, the input pairs INA1/INB1 are selected,
and when A0 is high, the input pairs INA2/INB2 are selected.
Note that INAx is always converted before INBx regardless of
the state of the digital interface channel selection A/B pin.
Also note that the channel selection control, A0, should not be
changed during the acquisition phase of the converter. Refer to
the Conversion Control section and Figure 21 for timing details.
DRIVER AMPLIFIER CHOICE
Although the AD7655 is easy to drive, the driver amplifier
needs to meet at least the following requirements:
• The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7655. The noise coming from
the driver is filtered by the AD7655 analog input circuit
one-pole, low-pass filter made by RA, RB, and CBS or by an
external filter, if one is used.
• The driver needs to have a THD performance suitable to
that of the AD7655.
• For multichannel, multiplexed applications, the driver
amplifier and the AD7655 analog input circuit together
must be able to settle for a full-scale step of the capacitor
array at a 16-bit level (0.0015%). In the data sheet for the
driver amplifier, the settling at 0.1% or 0.01% is more
commonly specified. This could differ significantly from
the settling time at a 16-bit level and should be verified
prior to driver selection.
The AD8021 meets these requirements and, for almost all
applications, is usually appropriate. The AD8021 needs an
external compensation capacitor of 10 pF. This capacitor should
have good linearity as an NPO ceramic or mica type. The
AD8022 can be used where a dual version is needed and a gain
of +1 is used.
The AD829 is another alternative where high frequency (above
100 kHz) performance is not required. In a gain of +1, it
requires an 82 pF NPO or mica type compensation capacitor.
The AD8610 is another option where low bias current is needed
in low frequency applications.
Refer to Table 8 for some recommended op amps.
AD7655
Rev. B | Page 17 of 28
Table 8. Recommended Driver Amplifiers
Amplifier Typical Application
ADA4841 Very low noise, low distortion, low power,
low frequency
AD829 Very low noise, low frequency
AD8021 Very low noise, high frequency
AD8022 Very low noise, high frequency, dual
AD8605/AD8606/
AD8608/AD8615/
AD8616/ AD8618
5 V single supply, low power,
low frequency, single/dual/quad
AD8610/AD8620 Low bias current, low frequency,
single/dual
VOLTAGE REFERENCE INPUT
The AD7655 requires an external 2.5 V reference. The reference
input should be applied to REF, REFA, and REFB. The voltage
reference input REF of the AD7655 has a dynamic input
impedance; it should therefore be driven by a low impedance
source with an efficient decoupling. This decoupling depends
on the choice of the voltage reference but usually consists of a
1 μF ceramic capacitor and a low ESR tantalum capacitor
connected to the REFA, REFB, and REFGND inputs with
minimum parasitic inductance. A value of 47 μF is appropriate
for the tantalum capacitor when using one of the recommended
reference voltages:
• The low noise, low temperature drift AD780, ADR421,
and ADR431 voltage references
• The low cost AD1582 voltage reference
For applications using multiple AD7655s with one voltage
reference source, it is recommended that the reference source
drives each ADC in a star configuration with individual
decoupling placed as close as possible to the REF/REFGND
inputs. Also, it is recommended that a buffer, such as the
AD8031/AD8032, be used in this configuration.
Care should be taken with the reference temperature coefficient
of the voltage reference, which directly affects the full-scale
accuracy if this parameter is applicable. For instance, a
15 ppm/°C tempco of the reference changes the full-scale
accuracy by 1 LSB/°C.
POWER SUPPLY
The AD7655 uses three sets of power supply pins: an analog
5 V supply AVDD, a digital 5 V core supply DVDD, and a
digital input/output interface supply OVDD. The OVDD
supply allows direct interface with any logic working between
2.7 V and DVDD + 0.3 V. To reduce the number of supplies
needed, the digital core (DVDD) can be supplied through a
simple RC filter from the analog supply, as shown in Figure 17.
The AD7655 is independent of power supply sequencing, once
OVDD does not exceed DVDD by more than 0.3 V, and thus is
free from supply voltage induced latch-up. Additionally, it is
very insensitive to power supply variations over a wide
frequency range, as shown in Figure 19.
FREQUENCY (kHz)
40
PSRR (dB)
100 1000 10000
45
50
55
60
65
70
10
1
03536-019
Figure 19. PSRR vs. Frequency
POWER DISSIPATION
In impulse mode, the AD7655 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which
allows significant power savings when the conversion rate is
reduced, as shown in Figure 20. This feature makes the AD7655
ideal for very low power battery applications.
Note that the digital interface remains active even during the
acquisition phase. To reduce the operating digital supply
currents even further, the digital inputs need to be driven close
to the power rails (that is, DVDD and DGND), and OVDD
should not exceed DVDD by more than 0.3 V.
SAMPLING RATE (kSPS)
0.1
POWER DISSIPATION (mW)
100 1000
1
10
100
1000
NORMAL
IMPULSE
03536-020
101
Figure 20. Power Dissipation vs. Sample Rate
AD7655
Rev. B | Page 18 of 28
CONVERSION CONTROL
Figure 21 shows a detailed timing diagram of the conversion
process. The AD7655 is controlled by the signal CNVST,
which initiates conversion. Once initiated, it cannot be
restarted or aborted, even by the power-down input, PD,
until the conversion is complete. The CNVST signal operates
independently of the CS and RD signals.
BUSY
ACQUIRE
t
2
t
1
t
3
t
4
t
5
t
6
t
7
t
8
CONVERT A ACQUIRE CONVERT
CONVERT B
t
12
A0
t
14
t
15
t
13
t
11
t
10
EOC
CNVST
03536-021
MODE
Figure 21. Basic Conversion Timing
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels, and with minimum
overshoot and undershoot or ringing.
For applications where the SNR is critical, the CNVST signal
should have very low jitter. One solution is to use a dedicated
oscillator for CNVST generation or, at least, to clock it with a
high frequency low jitter clock, as shown in Figure 17.
In impulse mode, conversions can be automatically initiated. If
CNVST is held low when BUSY is low, the AD7655 controls the
acquisition phase and automatically initiates a new conversion.
By keeping CNVST low, the AD7655 keeps the conversion
process running by itself. Note that the analog input has to be
settled when BUSY goes low. Also, at power-up, CNVST should
be brought low once to initiate the conversion process. In this
mode, the AD7655 can sometimes run slightly faster than the
guaranteed limits of 888 kSPS in impulse mode. This feature
does not exist in normal mode.
DIGITAL INTERFACE
The AD7655 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7655 digital interface accommodates either 3 V or 5 V logic
when the OVDD supply pin of the AD7655 is connected to the
host system interface digital supply.
The two signals, CS and RD, control the interface. When at
least one of these signals is high, the interface outputs are in
high impedance. Usually CS allows the selection of each
AD7655 in multicircuit applications and is held low in a single
AD7655 design. RD is generally used to enable the conversion
result on the data bus. In parallel mode, signal A/B allows the
choice of reading either the output of Channel A or Channel B,
whereas in serial mode, signal A/B controls which channel is
output first.
Figure 22 details the timing when using the RESET input. Note
the current conversion, if any, is aborted and the data bus is
high impedance while RESET is high.
t
9
RESET
DATA
BUS
BUSY
t
8
CNVST
03536-022
Figure 22. Reset Timing
PARALLEL INTERFACE
The AD7655 is configured to use the parallel interface when
SER/PAR is held low.
Master Parallel Interface
Data can be read continuously by tying CS and RD low, thus
requiring minimal microprocessor connections. However, in
this mode the data bus is always driven and cannot be used in
shared bus applications (unless the device is held in RESET).
Figure 23 details the timing for this mode.
t
1
t
3
t
4
t
17
BUSY
DATA
BUS
t
16
NEW A
OR B
PREVIOUS CHANNEL A
OR B PREVIOUS CHANNEL B
OR NEW A
t
10
CS = RD = 0
EOC
CNVST
03536-023
Figure 23. Master Parallel Data Timing for Reading (Continuous Read)
AD7655
Rev. B | Page 19 of 28
Slave Parallel Interface
In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the other channel’s conversion, or during the following
conversion, as shown in Figure 24 and Figure 25, respectively.
When the data is read during the conversion, however, it is
recommended that it is read only during the first half of the
conversion phase. This avoids any potential feedthrough
between voltage transients on the digital interface and the most
critical analog conversion circuitry.
DATA BUS
t
18
t
19
BUSY
CURRENT
CONVERSION
CS
RD
03536-024
Figure 24. Slave Parallel Data Timing for Reading (Read after Convert)
PREVIOUS
CONVERSION
t
1
t
3
t
18
t
19
t
4
BUSY
DATA BUS
t
13
t
11
t
12
t
10
CS = 0
EOC
CNVST, RD
03536-025
Figure 25. Slave Parallel Data Timing for Reading (Read During Convert)
8-Bit Interface (Master or Slave)
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 26, the LSB byte is output on D[7:0] and the
MSB is output on D[15:8] when BYTESWAP is low. When
BYTESWAP is high, the LSB and MSB bytes are swapped, the
LSB is output on D[15:8], and the MSB is output on D[7:0]. By
connecting BYTESWAP to an address line, the 16-bit data can
be read in 2 bytes on either D[15:8] or D[7:0].
BYTESWAP
PINS D[15:8]
PINS D[7:0] HI-Z
HI-Z HIGH BYTE LOW BYTE
LOW BYTE HIGH BYTE HI-Z
HI-Z
t
18
t
18
t
19
CS
RD
03536-026
Figure 26. 8-Bit Parallel Interface
Channel A/B Output
The A/B input controls which channel’s conversion results
(INAx or INBx) are output on the data bus. The function-ality
of A/B is detailed in Figure 27. When high, the data from
Channel A is available on the data bus. When low, the data from
Channel B is available on the bus. Note that in parallel reading
mode, Channel A can be read immediately after the end of
conversion (EOC), while Channel B is still in its converting
phase. However, in any of the serial reading modes Channel A
data is updated only after Channel B conversion.
t
18
t
20
CS
DATA BU
S
RD
HI-Z
A/B
HI-Z
CHANNEL A CHANNEL B
03536-027
Figure 27. A/B Channel Reading
AD7655
Rev. B | Page 20 of 28
SERIAL INTERFACE
The AD7655 is configured to use the serial interface when the
SER/PAR is held high. The AD7655 outputs 32 bits of data, MSB
first, on the SDOUT pin. The order of the channels being output
is also controlled by A/B. When high, Channel A is output first;
when low, Channel B is output first. This data is synchronized
with the 32 clock pulses provided on the SCLK pin.
MASTER SERIAL INTERFACE
Internal Clock
The AD7655 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The
AD7655 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted, if desired, using the INVSCLK
and INVSYNC inputs, respectively. The output data is valid on
both the rising and falling edge of the data clock. In this mode,
the D7/RDC/SDIN input is used to select between reading after
conversion (RDC = low) or reading previous conversion results
during conversion (RDC = high). Figure 28 and Figure 29 show
the detailed timing diagrams of these two modes.
Usually, because the AD7655 is used with a fast throughput, the
master read during convert mode is the most recommended
serial mode when it can be used. In this mode, the serial clock
and data toggle at appropriate instants, which minimizes
potential feed through between digital activity and the critical
conversion decisions. The SYNC signal goes low after the LSB
of each channel has been output. Note that in this mode, the
SCLK period changes because the LSBs require more time to
settle, and the SCLK is derived from the SAR conversion clock.
Note that in master read after convert mode, unlike in other
modes, the BUSY signal returns low after the 32 bits of data are
pulsed out and not at the end of the conversion phase, which
results in a longer BUSY width. One advantage of using this
mode is that it can accommodate slow digital hosts because the
serial clock can be slowed down by using the DIVSCLK[1:0]
inputs. Refer to Table 4 for the timing details.
AD7655
Rev. B | Page 21 of 28
t
3
BUSY
SYNC
SCLK
SDOUT
1216 31 32
CH A
D14 CH B
D15 CH B
D1
X
RDC/SDIN = 0 INVSCLK = INVSYNC = 0
t
21
t
23
t
30
t
36
t
25
t
28
t
32
t
31
t
33
t
34
t
12
17
t
35
t
26
EXT/INT = 0 A/B = 1
CNVST
CS, RD
EOC
03536-028
t
11
t
13
t
10
t
26
t
27
t
22
t
29
CH B
D0
CH A
D0
t
37
CH A
D15
Figure 28. Master Serial Data Timing for Reading (Read After Convert)
RDC/SDIN = 1 INVSCLK = INVSYNC = 0
t3
t1
t24
t21 t26
t27 t28 t31 t33
t32
t34
t30
t29
t23
t22
CH A
D15
X
12 16 1 2
t25
BUSY
SYNC
SCLK
SDOUT
16
CH B
D15
CH A D0
CH A
D14 CH B
D14 CH B D0
t10 t11 t13
t12
EXT/INT = 0 A/B = 1
CNVST
CS, RD
EOC
03536-029
Figure 29. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
AD7655
Rev. B | Page 22 of 28
SLAVE SERIAL INTERFACE
External Clock
The AD7655 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is
held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by CS. When both CS
and RD are low, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive. Figure 31 and Figure 32 show the detailed timing
diagrams of these methods.
While the AD7655 is performing a bit decision, it is important
that voltage transients do not occur on digital input/output pins
or degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase of each channel, because the AD7655 provides error
correction circuitry that can correct for an improper bit
decision made during the first half of the conversion phase. For
this reason, it is recommended that when an external clock is
provided, it is a discontinuous clock that is toggling only when
BUSY is low or, more importantly, that it does not transition
during the latter half of EOC high.
External Discontinuous Clock Data Read After Convert
Although the maximum throughput cannot be achieved in this
mode, it is the most recommended of the serial slave modes.
Figure 31 shows the detailed timing diagrams of this mode.
After a conversion is complete, indicated by BUSY returning
low, the conversion results can be read while both CS and RD
are low. Data is shifted out from both channels’ MSB first, with
32 clock pulses, and is valid on both rising and falling edges of
the clock.
Among the advantages of using this mode is that conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion process.
Another advantage is the ability to read the data at any speed up
to 40 MHz, which accommodates both slow digital host
interface and the fastest serial reading.
Finally, in this mode only, the AD7655 provides a daisy-chain
feature using the RDC/SDIN (serial data in) input pin for
cascading multiple converters together. This feature is useful for
reducing component count and wiring connections when it is
desired, as in isolated multiconverter applications.
An example of the concatenation of two devices is shown in
Figure 30. Simultaneous sampling is possible by using a
common CNVST signal. Note that the RDC/SDIN input is
latched on the edge of SCLK opposite the one used to shift out
the data on SDOUT. Therefore, the MSB of the upstream
converter follows the LSB of the downstream converter on the
next SCLK cycle. The SDIN input should be tied either high or
low on the most upstream converter in the chain.
BUSY BUSY
AD7655
#2 (UPSTREAM)
AD7655
#1 (DOWNSTREAM)
RDC/SDIN SDOUT
CNVST
CS
SCLK
RDC/SDIN SDOUT
CNVST
CS
SCLK
DATA
OUT
SCLK IN
CS IN
CNVST IN
BUSY
OUT
03536-030
Figure 30. Two AD7655s in a Daisy-Chain Configuration
External Clock Data Read (Previous) During Convert
Figure 32 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 32 clock pulses, and is valid on both the rising
and falling edges of the clock. The 32 bits have to be read before
the current conversion is completed; otherwise, RDERROR is
pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy-chain
feature in this mode, and RDC/SDIN input should always be
tied either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock (at least 32 MHz in impulse mode and
40 MHz in normal mode) is recommended to ensure that all of
the bits are read during the first half of each conversion phase
(EOC high, t11, t12).
It is also possible to begin to read data after conversion and
continue to read the last bits after a new conversion has been
initiated. This allows the use of a slower clock speed such as
26 MHz in impulse mode and 30 MHz in normal mode.
AD7655
Rev. B | Page 23 of 28
CS
SCLK
SDOUT CH A
D15
BUSY
SDIN
INVSCLK = 0
t
42
t
43
t
44
t
38
t
39
t
23
t
40
t
41
X
1 2 3 30313233 34
EXT/INT = 1
CH B D0CH B D1
CH A
D13
CH A
D14 X CH A
D14
X CH A
D15
X CH A
D13
X CH A
D14 X CH B
D0
X CH B
D1 Y CH A
D14
Y CH A
D15
RD = 0 A/B = 1
EOC
03536-031
X CH A
D15
Figure 31. Slave Serial Data Timing for Reading (Read After Convert)
CNVST
SDOUT
SCLK
XCH A D15
123 3132
t
3
t
42
t
43
t
44
t
38
t
39
t
23
BUSY
INVSCLK = 0
CS
EXT/INT = 1
CH B D0
CH B D1
CH A D13
CH A D14
RD = 0
EOC
t
10
t
11
t
13
t
12
A/B = 1
03536-032
Figure 32. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
AD7655
Rev. B | Page 24 of 28
MICROPROCESSOR INTERFACING
The AD7655 is ideally suited for traditional dc measurement
applications supporting a microprocessor and for ac signal
processing applications interfacing to a digital signal processor.
The AD7655 is designed to interface with either a parallel
8-bit-wide or 16-bit-wide interface, a general-purpose serial port,
or I/O ports on a microcontroller. A variety of external buffers
can be used with the AD7655 to prevent digital noise from
coupling into the ADC. The following section describes the use of
the AD7655 with an SPI-equipped DSP, the ADSP-219x.
SPI INTERFACE (ADSP-219X)
Figure 33 shows an interface diagram between the AD7655 and
the SPI1-equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7655 acts as a slave device and data
must be read after conversion. This mode also allows the daisy-
chain feature to be used. The convert command can be initiated
in response to an internal timer interrupt. The 32-bit output
data is read with two serial peripheral interface (SPI) 16-bit
wide accesses. The reading process can be initiated in response
to the end of conversion signal (BUSY going low) using an
interrupt line of the DSP. The SPI on the ADSP-219x is
configured for master mode—(MSTR) = 1, Clock Polarity bit
(CPOL) = 0, Clock Phase bit (CPHA) = 1, and SPI Interrupt
Enable (TIMOD) = 00—by writing to the SPI control register
(SPICLTx). To meet all timing requirements, the SPI clock
should be limited to 17 Mbps, which allows it to read an ADC
result in less than 1 μs. When a higher sampling rate is desired,
use of one of the parallel interface modes is recommended.
AD7655* ADSP-219x*
SER/PAR
PFx
MISOx
SCKx
PFx or TFSx
BUSY
SDOUT
SCLK
CNVST
EXT/INT
CS
RD
INVSCLK
DVDD
*ADDITIONAL PINS OMITTED FOR CLARITY
SPIxSEL (PFx)
03536-033
Figure 33. Interfacing the AD7655 to SPI Interface
AD7655
Rev. B | Page 25 of 28
APPLICATION HINTS
LAYOUT
The AD7655 has very good immunity to noise on the power
supplies. However, care should still be taken with regard to
grounding layout.
The printed circuit board that houses the AD7655 should be
designed so the analog and digital sections are separated and
confined to certain areas of the board. This facilitates the use of
ground planes that can be separated easily. Digital and analog
ground planes should be joined in only one place, preferably
underneath the AD7655, or as close as possible to the AD7655.
If the AD7655 is in a system where multiple devices require
analog-to-digital ground connections, the connection should
still be made at one point only, a star ground point that should
be established as close as possible to the AD7655.
Avoid unning digital lines under the device because these
couple noise onto the die. The analog ground plane should be
allowed to run under the AD7655 to avoid noise coupling. Fast
switching signals such as CNVST or clocks should be shielded
with digital ground to avoid radiating noise to other sections of
the board and should never run near analog signal paths.
Crossover of digital and analog signals should be avoided.
Traces on different but close layers of the board should run at
right angles to each other. This reduces the effect of crosstalk
through the board.
The power supply lines to the AD7655 should use as large a
trace as possible to provide low impedance paths and reduce the
effect of glitches on the power supply lines. Good decoupling is
also important to lower the supply impedance presented to the
AD7655 and to reduce the magnitude of the supply spikes.
Decoupling ceramic capacitors, typically 100 nF, should be
placed on each power supply pin—AVDD, DVDD, and
OVDD—close to, and ideally right up against these pins and
their corresponding ground pins. Additionally, low ESR 10 μF
capacitors should be located near the ADC to further reduce
low frequency ripple.
The DVDD supply of the AD7655 can be a separate supply or
can come from the analog supply AVDD or the digital interface
supply OVDD. When the system digital supply is noisy or when
fast switching digital signals are present, if no separate supply is
available, the user should connect DVDD to AVDD through an
RC filter (see Figure 17) and the system supply to OVDD and
the remaining digital circuitry. When DVDD is powered from
the system supply, it is useful to insert a bead to further reduce
high frequency spikes.
The AD7655 has five ground pins: INGND, REFGND, AGND,
DGND, and OGND. INGND is used to sense the analog input
signal. REFGND senses the reference voltage and, because it
carries pulsed currents, should be a low impedance return to
the reference. AGND is the ground to which most internal
ADC analog signals are referenced; it must be connected with
the least resistance to the analog ground plane. DGND must be
tied to the analog or digital ground plane depending on the
configuration. OGND is connected to the digital system
ground.
EVALUATING THE AD7655 PERFORMANCE
A recommended layout for the AD7655 is outlined in the
EVAL-AD7655CB evaluation board documentation. The
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the EVAL-CONTROL-BRD3.
AD7655
Rev. B | Page 26 of 28
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
TOP VIEW
(PINS DOWN)
1
12 13 25
24
36
37
48
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
7.00
BSC SQ
1.60
MAX
0.75
0.60
0.45
VIEW A
9.00
BSC SQ
PIN 1
0.20
0.09
1.45
1.40
1.35
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
7°
3.5°
0°
0.15
0.05
Figure 34. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
PIN 1
INDICATOR
TOP
VIEW 6.75
BSC SQ
7.00
BSC SQ
1
12
13
36
24
25
48
37
5.25
5.10 SQ
4.95
0.50
0.40
0.30
0.30
0.23
0.18
0.50 BSC
12° MAX
0.20 REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
5.50
REF
0.05 MAX
0.02 NOM
0.60 MAX
0.60 MAX PIN 1
INDICATOR
COPLANARITY
0.08
SEATING
PLANE
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
PADDLE CONNECTED TO GND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCES
Figure 35. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
AD7655
Rev. B | Page 27 of 28
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD7655ACP −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1
AD7655ACPRL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1
AD7655ACPZ1 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1
AD7655ACPZRL1−40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1
AD7655AST −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48
AD7655ASTRL −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48
AD7655ASTZ1−40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48
AD7655ASTZRL1−40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48
EVAL-AD7655CB2 Evaluation Board
EVAL-CONTROL-BRD33 Controller Board
1 Z = Pb-free part.
2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL-BRD3 for evaluation/demonstration purposes.
3 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in CB designators.
AD7655
Rev. B | Page 28 of 28
T
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03536-0-9/05(B)
TTT
