R10DS0016EJ0200 Rev.2.00 Page 1 of 34
October 6, 2011
Datasheet
μ
PD44164095B
μ
PD44164185B
18M-BIT DDR II SRAM SEPARATE I/O
2-WORD BURST OPERATION
Description
The
μ
PD44164095B is a 2,097,152-word by 9-bit and the
μ
PD44164185B is a 1,048,576-word by 18-bit
synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-
transistor memory cell.
The
μ
PD44164095B and
μ
PD44164185B integrate unique synchronous peripheral circuitry and a burst
counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K
and K#. These products are suitable for application which require synchronous operation, high speed, low
voltage, high density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
• 1.8 ± 0.1 V power supply
• 165-pin PLASTIC BGA (13 x 15)
• HSTL interface
• PLL circuitry for wide output data valid window and future frequency scaling
• Separate independent read and write data ports
• DDR read or write operation initiated each cycle
• Pipelined double data rate operation
• Separate data input/output bus
• Two-tick burst for low DDR transaction size
• Two input clocks (K and K#) for precise DDR timing at clock rising edges only
• Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
• Internally self-timed write control
• Clock-stop capability. Normal operation is restored in 20
μ
s after clock is resumed.
• User programmable impedance output (35 to 70 Ω)
• Fast clock cycle time : 3.3 ns (300 MHz), 3.5 ns (287 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port
R10DS0016EJ0200
Rev.2.00
October 6, 2011
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 2 of 34
October 6, 2011
Ordering Information
Part No. Organization
(word x bit) Cycle
time Clock
frequency Operating Ambient
Temperature Package
μ
PD44164095BF5-E33-EQ3-A
2M x 9 3.3ns 300MHz Ta = 0 to 70°C 165-pin
μ
PD44164095BF5-E35-EQ3-A 3.5ns 287MHz PLASTIC BGA
μ
PD44164095BF5-E40-EQ3-A 4.0ns 250MHz (13 x 15)
μ
PD44164095BF5-E50-EQ3-A 5.0ns 200MHz Lead-free
μ
PD44164185BF5-E33-EQ3-A 1M x 18 3.3ns 300MHz
μ
PD44164185BF5-E35-EQ3-A 3.5ns 287MHz
μ
PD44164185BF5-E40-EQ3-A 4.0ns 250MHz
μ
PD44164185BF5-E50-EQ3-A 5.0ns 200MHz
μ
PD44164095BF5-E33-EQ3
2M x 9 3.3ns 300MHz Ta = 0 to 70°C 165-pin
μ
PD44164095BF5-E35-EQ3 3.5ns 287MHz PLASTIC BGA
μ
PD44164095BF5-E40-EQ3 4.0ns 250MHz (13 x 15)
μ
PD44164095BF5-E50-EQ3 5.0ns 200MHz Lead
μ
PD44164185BF5-E33-EQ3 1M x 18 3.3ns 300MHz
μ
PD44164185BF5-E35-EQ3 3.5ns 287MHz
μ
PD44164185BF5-E40-EQ3 4.0ns 250MHz
μ
PD44164185BF5-E50-EQ3 5.0ns 200MHz
μ
PD44164095BF5-E33Y-EQ3-A
2M x 9 3.3ns 300MHz Ta = −40 to 85°C 165-pin
μ
PD44164095BF5-E35Y-EQ3-A 3.5ns 287MHz PLASTIC BGA
μ
PD44164095BF5-E40Y-EQ3-A 4.0ns 250MHz (13 x 15)
μ
PD44164095BF5-E50Y-EQ3-A 5.0ns 200MHz Lead-free
μ
PD44164185BF5-E33Y-EQ3-A 1M x 18 3.3ns 300MHz
μ
PD44164185BF5-E35Y-EQ3-A 3.5ns 287MHz
μ
PD44164185BF5-E40Y-EQ3-A 4.0ns 250MHz
μ
PD44164185BF5-E50Y-EQ3-A 5.0ns 200MHz
μ
PD44164095BF5-E33Y-EQ3
2M x 9 3.3ns 300MHz Ta = −40 to 85°C 165-pin
μ
PD44164095BF5-E35Y-EQ3 3.5ns 287MHz PLASTIC BGA
μ
PD44164095BF5-E40Y-EQ3 4.0ns 250MHz (13 x 15)
μ
PD44164095BF5-E50Y-EQ3 5.0ns 200MHz Lead
μ
PD44164185BF5-E33Y-EQ3 1M x 18 3.3ns 300MHz
μ
PD44164185BF5-E35Y-EQ3 3.5ns 287MHz
μ
PD44164185BF5-E40Y-EQ3 4.0ns 250MHz
μ
PD44164185BF5-E50Y-EQ3 5.0ns 200MHz
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 3 of 34
October 6, 2011
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD44164095B]
2M x 9
1 2 3 4 5 6 7 8 9 10 11
A CQ# VSS/72M A R, W# NC K#
NC/144M LD# A
VSS/36M CQ
B NC NC NC A
NC/288M K BW0# A NC NC Q4
C NC NC NC VSS A A A VSS NC NC D4
D NC D5 NC VSS VSS VSS VSS VSS NC NC NC
E NC NC Q5 VDDQ VSS VSS VSS VDDQ NC D3 Q3
F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
G NC D6 Q6 VDDQ VDD VSS VDD VDDQ NC NC NC
H DLL# VREF VDDQ VDDQ VDD VSS VDD VDDQVDDQ VREF ZQ
J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q2 D2
K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
L NC Q7 D7 VDDQ VSS VSS VSS VDDQ NC NC Q1
M NC NC NC VSS VSS VSS VSS VSS NC NC D1
N NC D8 NC VSS A A A VSS NC NC NC
P NC NC Q8 A A C A A NC D0 Q0
R TDO TCK A A A C# A A A TMS TDI
A : Address inputs TMS : IEEE 1149.1 Test input
D0 to D8 : Data inputs TDI : IEEE 1149.1 Test input
Q0 to Q8 : Data outputs TCK : IEEE 1149.1 Clock input
LD# : Synchronous load TDO : IEEE 1149.1 Test output
R, W# : Read Write input VREF : HSTL input reference input
BW0# : Byte Write data select VDD : Power Supply
K, K# : Input clock VDDQ : Power Supply
C, C# : Output clock VSS : Ground
CQ, CQ# : Echo clock NC : No connection
ZQ : Output impedance matching NC/xxM : Expansion address for xxMb
DLL# : PLL disable
Remarks 1. ×××# indicates active LOW.
2. Refer to Package Dimensions for the index mark.
3. 2A, 7A, 10A and 5B are expansion addresses : 10A for 36Mb
: 10A and 2A for 72Mb
: 10A, 2A and 7A for 144Mb
: 10A, 2A, 7A and 5B for 288Mb
2A and 10A of this product can also be used as NC.
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 4 of 34
October 6, 2011
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD44164185B]
1M x 18
1 2 3 4 5 6 7 8 9 10 11
A CQ#
VSS/144M NC/36M R, W# BW1# K# NC/288M LD# A
VSS/72M CQ
B NC Q9 D9 A NC K BW0# A NC NC Q8
C NC NC D10 VSS A A A VSS NC Q7 D8
D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7
E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6
F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5
G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5
H DLL# VREF VDDQ VDDQ VDD VSS VDD VDDQVDDQ VREF ZQ
J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4
K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3
L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2
M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
N NC D17 Q16 VSS A A A VSS NC NC D1
P NC NC Q17 A A C A A NC D0 Q0
R TDO TCK A A A C# A A A TMS TDI
A : Address inputs TMS : IEEE 1149.1 Test input
D0 to D17 : Data inputs TDI : IEEE 1149.1 Test input
Q0 to Q17 : Data outputs TCK : IEEE 1149.1 Clock input
LD# : Synchronous load TDO : IEEE 1149.1 Test output
R, W# : Read Write input VREF : HSTL input reference input
BW0#, BW1# : Byte Write data select VDD : Power Supply
K, K# : Input clock VDDQ : Power Supply
C, C# : Output clock VSS : Ground
CQ, CQ# : Echo clock NC : No connection
ZQ : Output impedance matching NC/xxM : Expansion address for xxMb
DLL# : PLL disable
Remarks 1. ×××# indicates active LOW.
2. Refer to Package Dimensions for the index mark.
3. 2A, 3A, 7A and 10A are expansion addresses : 3A for 36Mb
: 3A and 10A for 72Mb
: 3A, 10A and 2A for 144Mb
: 3A, 10A, 2A and 7A for 288Mb
2A and 10A of this product can also be used as NC.
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 5 of 34
October 6, 2011
Pin Description
(1/2)
Symbol Type Description
A
Input
Synchronous Address Inputs: These inputs are registered and must meet the setup
and hold times around the rising edge of K. All transactions operate on a burst of two
words (one clock period of bus activity). These inputs are ignored when device is
deselected, i.e., NOP (LD# = HIGH).
D0 to Dxx Input Synchronous Data Inputs: Input data must meet setup and hold times around the rising
edges of K and K# during WRITE operations. See Pin Arrangement for ball site
location of individual signals.
x9 device uses D0 to D8.
x18 device uses D0 to D17.
Q0 to Qxx Output Synchronous Data Outputs: Output data is synchronized to the respective C and C# or
to K and K# rising edges if C and C# are tied HIGH. Data is output in synchronization
with C and C# (or K and K#), depending on the LD# and R, W# command. See Pin
Arrangement for ball site location of individual signals.
x9 device uses Q0 to Q8.
x18 device uses Q0 to Q17
LD# Input
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be
defined. This definition includes address and read/write direction. All transactions
operate on a burst of 2 data (one clock period of bus activity).
R, W# Input
Synchronous Read/Write Input: When LD# is LOW, this input designates the access
type (READ when R, W# is HIGH, WRITE when R, W# is LOW) for the loaded
address. R, W# must meet the setup and hold times around the rising edge of K.
BWx# Input
Synchronous Byte Writes: When LOW these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals must meet setup and hold
times around the rising edges of K and K# for each of the two rising edges comprising
the WRITE cycle. See Pin Arrangement for signal to data relationships.
x9 device uses BW0#.
x18 device uses BW0#, BW1#.
See Byte Write Operation for relation between BWx# and Dxx.
K, K# Input
Input Clock: This input clock pair registers address and control inputs on the rising
edge of K, and registers data on the rising edge of K and the rising edge of K#. K# is
ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and
hold times around the clock rising edges.
C, C# Input Output Clock: This clock pair provides a user controlled means of tuning device output
data. The rising edge of C# is used as the output timing reference for first output data.
The rising edge of C is used as the output reference for second output data. Ideally, C#
is 180 degrees out of phase with C. When use of K and K# as the reference instead of
C and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed unless C
and C# are fixed to HIGH (i.e. toggle of C and C#)
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 6 of 34
October 6, 2011
(2/2)
Symbol Type Description
CQ, CQ# Output Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched
to the synchronous data outputs and can be used as a data valid indication. These signals
run freely and do not stop when Q tristates. If C and C# are stopped (if K and K# are
stopped in the single clock mode), CQ and CQ# will also stop.
ZQ Input Output Impedance Matching Input: This input is used to tune the device outputs to the
system data bus impedance. Q, CQ and CQ# output impedance are set to 0.2 x RQ,
where RQ is a resistor from this bump to ground. The output impedance can be
minimized by directly connect ZQ to VDDQ. This pin cannot be connected directly to GND
or left unconnected. The output impedance is adjusted every 20
μ
s upon power-up to
account for drifts in supply voltage and temperature. After replacement for a resistor, the
new output impedance is reset by implementing power-on sequence.
DLL# Input PLL Disable: When debugging the system or board, the operation can be performed at a
clock frequency slower than TKHKH (MAX.) without the PLL circuit being used, if DLL# =
LOW. The AC/DC characteristics cannot be guaranteed. For normal operation, DLL# must
be HIGH and it can be connected to VDDQ through a 10 kΩ or less resistor.
TMS
TDI
Input
IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the
JTAG function is not used in the circuit.
TCK Input IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function
is not used in the circuit.
TDO Output IEEE 1149.1 Test Output: 1.8 V I/O level.
When providing any external voltage to TDO signal, it is recommended to pull up to VDD.
VREF
HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the
input buffers.
VDD Supply Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC
Characteristics for range.
VDDQ Supply Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible.
See Recommended DC Operating Conditions and DC Characteristics for range.
VSS Supply Power Supply: Ground
NC
No Connect: These signals are not connected internally.
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 7 of 34
October 6, 2011
Block Diagram
[
μ
PD44164095B]
R, W#
BW0#
LD#
K
K# K
LD#
R, W#
K
ADDRESS 20
D0 to D8 Q0 to Q8
MUX
OUTPUT
REGISTER
K#
K
DATA
REGISTRY
& LOGIC
2
20
x 18
MEMORY
ARRAY
WRITE
DRIVER
SENSE
AMPS
OUTPUT
SELECT
OUTPUT
BUFFER
20
ADDRESS
REGISTRY
& LOGIC
WRITE
REGISTER
C, C#
OR
K, K#
CQ,
CQ#
918 18 18 9
2
[
μ
PD44164185B]
R, W#
BW0#
BW1#
LD#
K
K# K
LD#
R, W#
K
ADDRESS 19
D0 to D17 Q0 to Q17
MUX
OUTPUT
REGISTER
K#
K
DATA
REGISTRY
& LOGIC
2
19
x 36
MEMORY
ARRAY
WRITE
DRIVER
SENSE
AMPS
OUTPUT
SELECT
OUTPUT
BUFFER
19
ADDRESS
REGISTRY
& LOGIC
WRITE
REGISTER
C, C#
OR
K, K#
CQ,
CQ#
18 36 36 36 18
2
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 8 of 34
October 6, 2011
Power-On Sequence in DDR II SRAM
DDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
The following timing charts show the recommended power-on sequence.
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and
VDDQ can be applied simultaneously, as long as VDDQ does not exceed VDD by more tha n 0.5 V during power-up.
The following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD
and VDDQ can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during
power-down.
Power-On Sequence
Apply power and tie DLL# to HIGH.
- Apply VDD before VDDQ.
- Apply VDDQ before VREF or at the same time as VREF.
Provide stable clock f or m ore than 2 0
μ
s to lock the PLL.
PLL Constraints
The PLL uses K clock as its synchronizing input and th e input should have low phase jitter which is specified as
TKC var. The PLL can cover 120 MHz as the lowest frequency. If the input cloc k is unstable and the PLL is
enabled, then the PLL may lock onto an undesired clock frequency.
Power-On Waveforms
DLL#
20 μs or more
Stable Clock
VDD/VDDQ Stable (< ±0.1 V DC per 50 ns)
Fix HIGH (or tied to VDDQ)
VDD/VDDQ
Clock
Unstable Clock Normal Operation
Start
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 9 of 34
October 6, 2011
Truth Table
Operation LD# R, W# CLK D or Q
WRITE cycle L L L → H Data in
Load address, input write data on Input data D(A+0) D(A+1)
consecutive K and K# rising edge Input clock K(t+1) ↑ K#(t+1) ↑
READ cycle L H L → H Data out
Load address, read data on Output data Q(A+0) Q(A+1)
consecutive C and C# rising edge Output clock C#(t+1) ↑ C(t+2) ↑
NOP (No operation) H × L → HD = ×, Q = High-Z
Clock stop × × Stopped Previous state
Remarks 1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges
except if C and C# are HIGH then Data outputs are delivered at K and K# rising edges.
3. All control inpu ts in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 10 of 34
October 6, 2011
Byte Write Operation
[
μ
PD44164095B]
Operation K K# BW0#
Write D0 to D8 L → H − 0
− L → H 0
Write nothing L → H − 1
− L → H 1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
[
μ
PD44164185B]
Operation K K# BW0# BW1#
Write D0 to D17 L → H − 0 0
− L → H 0 0
Write D0 to D8 L → H − 0 1
− L → H 0 1
Write D9 to D17 L → H − 1 0
− L → H 1 0
Write nothing L → H − 1 1
− L → H 1 1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 11 of 34
October 6, 2011
Bus Cycle State Diagram
Remarks State machine control timing sequence is controlled by K.
READ DOUBLE
Count = Count + 2 WRITE DOUBLE
Count = Count + 2
Power UP
Write
NOP
Supply voltage provided
LOAD NEW
ADDRESS
Count = 0
NOP
Load, Count = 2
Read
Load, Count = 2
Load
NOP,
Count = 2
NOP,
Count = 2
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 12 of 34
October 6, 2011
Electrical Characteristics
Absolute Maximum Ratings
Parameter Symbol Conditions Rating Unit
Supply voltage VDD −0.5 to +2.5 V
Output supply voltage VDDQ −0.5 to VDD V
Input voltage VIN −0.5 to VDD+0.5 (2.5 V MAX.) V
Input / Output voltage VI/O −0.5 to VDDQ+0.5 (2.5 V MAX.) V
Operating ambient temperature TA (E** series) 0 to 70 °C
(E**Y series) −40 to 85
Storage temperature Tstg −55 to +125 °C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70°C, TA = −40 to 85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit Note
Supply voltage VDD 1.7 1.8 1.9 V
Output supply voltage VDDQ 1.4 VDD V 1
Input HIGH voltage VIH (DC) V
REF +0.1 VDDQ+0.3 V 1, 2
Input LOW voltage VIL (DC) −0.3 VREF −0.1 V 1, 2
Clock input voltage VIN −0.3 VDDQ+0.3 V 1, 2
Reference voltage VREF 0.68 0.95 V
Notes 1. During normal operation, VDDQ must not exceed VDD.
2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
Recommended AC Operating Conditions (TA = 0 to 70°C, TA = −40 to 85°C)
Parameter Symbol Conditions MIN. MAX. Unit Note
Input HIGH voltage VIH (AC) V
REF +0.2 V 1
Input LOW voltage VIL (AC) VREF −0.2 V 1
Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V (2.5 V MAX.) for t ≤ TKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ TKHKH/2
Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than
TKHKH (MIN .).
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 13 of 34
October 6, 2011
DC Characteristics 1 (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V)
Parameter Symbol Test condition MIN. MAX. Unit Note
x9 x18
Input leakage current ILI −2 +2
μ
A
I/O leakage current ILO −2 +2
μ
A
Operating supply current IDD V
IN ≤ VIL or VIN ≥ VIH, -E33 500 530 mA
(Read cycle / Write cycle) II/O = 0 mA, -E35 490 520
Cycle = MAX. -E40 450 480
-E50 400 420
Standby supply current ISB1 V
IN ≤ VIL or VIN ≥ VIH, -E33 390 400 mA
(NOP) II/O = 0 mA, -E35 380 390
Cycle = MAX. -E40 380 380
Inputs static -E50 350 350
Output HIGH voltage VOH(Low) |IOH| ≤ 0.1 mA VDDQ−0.2 VDDQ V 3, 4
V
OH Note1 VDDQ/2−0.12 VDDQ/2+0.12 V 3, 4
Output LOW voltage VOL(Low) I
OL ≤ 0.1 mA VSS 0.2 V 3, 4
V
OL Note2 VDDQ/2−0.12 VDDQ/2+0.12 V 3, 4
Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) ±15% for va l ues of 175 Ω ≤ RQ ≤ 350 Ω.
2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±1 5% f or val u es of 175 Ω ≤ RQ ≤ 350 Ω.
3. AC load current is higher than the shown DC values.
4. HSTL outputs meet JEDEC HSTL Class I standards.
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 14 of 34
October 6, 2011
DC Characteristics 2 (TA = −40 to 85°C, VDD = 1.8 ± 0.1 V)
Parameter Symbol Test condition MIN. MAX. Unit Note
x9 X18
Input leakage current ILI −2 +2
μ
A
I/O leakage current ILO −2 +2
μ
A
Operating supply current IDD V
IN ≤ VIL or VIN ≥ VIH, -E33Y 650 680 mA
(Read cycle / Write cycle) II/O = 0 mA, -E35Y 640 670
Cycle = MAX. -E40Y 600 630
-E50Y 540 560
Standby supply current ISB1 V
IN ≤ VIL or VIN ≥ VIH, -E33Y 510 530 mA
(NOP) II/O = 0 mA, -E35Y 500 520
Cycle = MAX. -E40Y 490 500
Inputs static -E50Y 460 470
Output HIGH voltage VOH(Low) |IOH| ≤ 0.1 mA VDDQ−0.2 VDDQ V 3, 4
V
OH Note1 VDDQ/2−0.12 VDDQ/2+0.12 V 3, 4
Output LOW voltage VOL(Low) I
OL ≤ 0.1 mA VSS 0.2 V 3, 4
V
OL Note2 VDDQ/2−0.12 VDDQ/2+0.12 V 3, 4
Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) ±15% for va l ues of 175 Ω ≤ RQ ≤ 350 Ω.
2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±1 5% f or val u es of 175 Ω ≤ RQ ≤ 350 Ω.
3. AC load current is higher than the shown DC values.
4. HSTL outputs meet JEDEC HSTL Class I standards.
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 15 of 34
October 6, 2011
Capacitance (TA = 25°C, f = 1 MHz)
Parameter Symbol Test conditions MIN. MAX. Unit
Input capacitance CIN V
IN = 0 V 5 pF
(Address, Control)
Input / Output capacitance CI/O V
I/O = 0 V 7 pF
(D, Q, CQ, CQ#)
Clock Input capacitance Cclk V
clk = 0 V 6 pF
Remark These parameters are periodically sampled and not 100% tested.
Thermal Characteristics
Parameter Symbol Substrate Airflow TYP. Unit
Thermal resistance
θ
ja 4-layer 0 m/s 21.4 °C/W
from junction to ambient air 1 m/s 13.6 °C/W
8-layer 0 m/s
20.3 °C/W
1 m/s
13.1 °C/W
Thermal characterization parameter Ψ jt
4-layer 0 m/s
0.02 °C/W
from junction to the top center 1 m/s 0.06 °C/W
of the package surface
8-layer 0 m/s
0.02 °C/W
1 m/s
0.06 °C/W
Thermal resistance
θ
jc 2.65 °C/W
from junction to case
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 16 of 34
October 6, 2011
AC Characteristics (TA = 0 to 70°C or TA = −40 to 85°C, VDD = 1.8 ± 0.1 V)
AC Test Conditions (VDD = 1.8 ± 0.1 V, VDDQ = 1.4 V to VDD)
Input waveform (Rise / Fall time ≤ 0.3 ns)
0.75 V 0.75 V
Test Points
1.25 V
0.25 V
Output waveform
V
DD
Q / 2 V
DD
Q / 2
Test Points
Output load condition
Figure 1. External load at test
VDDQ / 2
0.75 V 50 Ω
ZO = 50 Ω
250 Ω
SRAM
VREF
ZQ
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 17 of 34
October 6, 2011
Read and Write Cycle
Parameter Symbol -E33, E33Y -E35, E35Y -E40, E40Y -E50, E50Y Unit Note
(300 MHz) (287 MHz) (250 MHz) (200 MHz)
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Clock
Average Clock cycle time TKHKH 3.3 8.4 3.5 8.4 4.0 8.4 5.0 8.4 ns 1
(K, K#, C, C#)
Clock phase jitter (K, K#, C, C#) TKC var 0.2 0.2 0.2 0.2 ns 2
Clock HIGH time (K, K#, C, C#) TKHKL 1.32 1.5 1.6 2.0 ns
Clock LOW time (K, K#, C, C#) TKLKH 1.32 1.5 1.6 2.0 ns
Clock HIGH to Clock# HIGH TKHK#H 1.49 1.7 1.8 2.2 ns
(K → K#, C → C#)
Clock# HIGH to Clock HIGH TK#HKH 1.49 1.7 1.8 2.2 ns
(K# → K, C# → C)
Clock to data clock TKHCH 0 1.45 0 1.65 0 1.8 0 2.3 ns
(K → C, K# → C#)
PLL lock time (K, C) TKC lock 20 20 20 20
μ
s 3
K static to PLL reset TKC reset 30 30 30 30 ns 4
Output Times
CQ HIGH to CQ# HIGH TCQHCQ#H 1.24 1.35 1.55 1.95 ns 5
(CQ → CQ#)
CQ# HIGH to CQ HIGH TCQ#HCQH 1.24 1.35 1.55 1.95 ns 5
(CQ# → CQ)
C, C# HIGH to output valid TCHQV 0.45 0.45 0.45 0.45 ns
C, C# HIGH to output hold TCHQX −0.45 −0.45 −0.45 −0.45 ns
C, C# HIGH to echo clock valid TCHCQV 0.45 0.45 0.45 0.45 ns
C, C# HIGH to echo clock hold TCHCQX −0.45 −0.45 −0.45 −0.45 ns
CQ, CQ# HIGH to output valid TCQHQV 0.27 0.3 0.3 0.35 ns 6
CQ, CQ# HIGH to output hold TCQHQX −0.27 −0.3 −0.3 −0.35 ns 6
C HIGH to output High-Z TCHQZ 0.45 0.45 0.45 0.45 ns
C HIGH to output Low-Z TCHQX1 −0.45 −0.45 −0.45 −0.45 ns
Setup Times
Address valid to K rising edge TAVKH 0.4 0.5 0.5 0.6 ns 7
Synchronous load input (LD#), TIVKH 0.4 0.5 0.5 0.6 ns 7
read write input (R, W#) valid to
K rising edge
Data inputs and write data TDVKH 0.3 0.35 0.35 0.4 ns 7
select inputs (BWx#) valid to
K, K# rising edge
Hold Times
K rising edge to address hold TKHAX 0.4 0.5 0.5 0.6 ns 7
K rising edge to TKHIX 0.4 0.5 0.5 0.6 ns 7
synchronous load input (LD#),
read write input (R, W#) hold
K, K# rising edge to data inputs TKHDX 0.3 0.35 0.35 0.4 ns 7
and write data select inputs
(BWx#) hold
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 18 of 34
October 6, 2011
Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH
(MAX.) without the PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock
cycle in this operation. The AC/DC characteristics cannot be guaranteed, however.
2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var
(MAX.) indicates a peak-to-peak value.
3. V
DD slew rate must be less than 0.1 V DC per 50 ns for PLL lock retention.
PLL lock time begins once VDD and input clock are stable.
It is recommended that the device is kept NOP (LD# = HIGH) during these cycles.
4. K input is monitored for th is operation. See below for the timing.
K
K
TKC reset
or
TKC reset
5. Guaranteed by design.
6. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ± 0.1 n s vari at ion from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
7. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold
times for all latching clock edges.
Remarks 1. This parameter is sampled.
2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise
noted.
3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.
5. VDDQ is 1.5 V DC.
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 19 of 34
October 6, 2011
Read and Write Timing
K
Address
Data in
K#
246813 5 7
TKHK#H
C
C#
TKHCH
NOP READ
(burst of 2) WRITE
(burst of 2)
TKHKL TKLKH
Q00 Q10
Data out
Q01 Q11
LD#
R, W#
TKHCH
TKHKL TKLKH TKHK#H TK#HKH
TCHQX1 TCHQX TCHQZ
D21
TDVKH TKHDX
TDVKH TKHDX
TKHKH
TIVKH TKHIX
TAVKH TKHAX
CQ
CQ#
TCQHQV TCQHQX
TCHQV
TCHCQX
TCHCQV
TCHCQX
TCHCQV
READ
(burst of 2) READ
(burst of 2) NOP
Qx2 Q40 Q41
TCHQX
TCHQV
WRITE
(burst of 2)
A0 A1 A2 A3 A4
TK#HKH
TKHKH
D20 D30 D31
TCQ#HCQHTCQHCQ#H
Remarks 1. Q01 refers to output from address A0+0.
Q02 refers to output from the next internal burst address following A0, i.e., A0+1.
2. Outputs are disabled (high impedance) 2.5 clock cycles after the last READ (LD# = LOW, R, W# =
HIGH) is input in the sequences of [READ]-[NOP] and [READ]-[WRITE].
3. In this example, if address A4 = A3, data Q41 = D31 and Q42 = D32.
Write data is forwarded immediately as read results.
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 20 of 34
October 6, 2011
Application Example
SRAM
Controller
Data In
Data Out
Address
LD#
R, W#
BW#
SRAM#1 CQ/CQ#
SRAM#4 CQ/CQ#
Source CLK/CLK#
Return CLK/CLK#
ZQ
Q
CQ#
CQ
SRAM#4
D
A LD# R, W# BWx# C/C# K/K#
R
RV
t
V
t
RV
t
RV
t
RV
t
RV
t
R =
250 ΩR =
250 Ω
ZQ
Q
CQ#
CQ
SRAM#1
D
A LD# R, W#BWx# C/C# K/K#
R = 50 Ω V
t
= V
ref
. . .
. . .
Remark AC Characteristics are defined at the condition of SRAM outputs, CQ, CQ# and Q with termination.
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 21 of 34
October 6, 2011
JTAG Specification
These products support a limited set of JTA G functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name Pin assignments Description
TCK 2R Test Clock Input. All input are captured on the rising edge of TCK and all
outputs propagate from the falling edge of TCK.
TMS 10R Test Mode Select. This is the command input for the TAP controller state
machine.
TDI 11R Test Data Input. This is the input side of the serial registers placed between
TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP controller state machine and the instruction that is currently
loaded in the TAP instruction.
TDO 1R Test Data Output. This is the output side of the serial registers placed between
TDI and TDO. Output changes in response to the falling edge of TCK.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH
for five rising edge s of TC K. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V, unless otherwise noted)
Parameter Symbol Conditions MIN. MAX. Unit
JTAG Input leakage current ILI 0 V ≤ VIN ≤ VDD −5.0 +5.0
μ
A
JTAG I/O leakage current ILO 0 V ≤ VIN ≤ VDDQ, −5.0 +5.0
μ
A
Outputs disabled
JTAG input HIGH voltage VIH 1.3 VDD+0.3 V
JTAG input LOW voltage VIL −0.3 +0.5 V
JTAG output HIGH voltage VOH1 | IOHC | = 100
μ
A 1.6 V
V
OH2 | IOHT | = 2 mA 1.4 V
JTAG output LOW voltage VOL1 I
OLC = 100
μ
A 0.2 V
V
OL2 I
OLT = 2 mA 0.4 V
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 22 of 34
October 6, 2011
JTAG AC Test Conditions
Input waveform (Rise / Fall time ≤ 1 ns)
0.9 V 0.9 V
Test Points
1.8 V
0 V
Output waveform
0.9 V 0.9 V
Test Points
Output load
Figure 2. External load at test
TDO Z
O
= 50 Ω
V
TT
= 0.9 V
20 pF
50 Ω
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 23 of 34
October 6, 2011
JTAG AC Characteristics (TA = 0 to 70°C)
Parameter Symbol Conditions MIN. MAX. Unit
Clock
Clock cycle time tTHTH 50 ns
Clock frequency fTF 20 MHz
Clock HIGH time tTHTL 20 ns
Clock LOW time tTLTH 20 ns
Output time
TCK LOW to TDO unknown tTLOX 0 ns
TCK LOW to TDO valid tTLOV 10 ns
Setup time
TMS setup time tMVTH 5 ns
TDI valid to TCK HIGH tDVTH 5 ns
Capture setup time tCS 5 ns
Hold time
TMS hold time tTHMX 5 ns
TCK HIGH to TDI invalid tTHDX 5 ns
Capture hold time tCH 5 ns
JTAG Timing Diagram
t
THTH
t
TLOV
t
TLTH
t
THTL
t
MVTH
t
THDX
t
DVTH
t
THMX
TCK
TMS
TDI
TDO
t
TLOX
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 24 of 34
October 6, 2011
Scan Register Definition (1)
Register name Description
Instruction register The instruction register holds the instructions that are executed by the TAP controller
when it is moved into the run-test/idle or the various data register state. The register can
be loaded when it is placed between the TDI and TDO pins. The instruction register is
automatically preloaded with the IDCODE instruction at power-up whenever the controller
is placed in test-logic-reset state.
Bypass register The bypass register is a single bit register that can be placed between TDI and TDO. It
allows serial test data to be passed through the RAMs TAP to another device in the scan
chain with as little delay as possible.
ID register The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit
code when the controller is put in capture-DR state with the IDCODE command loaded in
the instruction register. The register is then placed between the TDI and TDO pins when
the controller is moved into shift-DR state.
Boundary register The boundary register, under the control of the TAP controller, is loaded with the contents
of the RAMs I/O ring when the controller is in capture-DR state and then is placed
between the TDI and TDO pins when the controller is moved to shift-DR state. Several
TAP instructions can be used to activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary
register location. The first column defines the bit’s position in the boundary register. The
second column is the name of the input or I/O at the bump and the third column is the
bump number.
Scan Register Definition (2)
Register name Bit size Unit
Instruction register 3 bit
Bypass register 1 bit
ID register 32 bit
Boundary register 107 bit
ID Register Definition
Part number Organization ID [31:28]
vendor revision no. ID [27:12]
part no. ID [11:1]
vendor ID no. ID [0]
fix bit
μ
PD44164095B 2M x 9 XXXX 0000 0000 0101 0101 00000010000 1
μ
PD44164185B 1M x 18 XXXX 0000 0000 0001 1001 00000010000 1
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 25 of 34
October 6, 2011
SCAN Exit Order
Bit Signal name Bump Bit Signal name Bump Bit Signal name Bump
no. x9 x18 ID no. x9 x18 ID no. x9 x18 ID
1 C# 6R 37 NC 10D 73 NC 2C
2 C 6P 38 NC 9E 74 Q5 Q11 3E
3 A 6N 39 NC Q7 10C 75 D5 D11 2D
4 A 7P 40 NC D7 11D 76 NC 2E
5 A 7N 41 NC 9C 77 NC 1E
6 A 7R 42 NC 9D 78 NC Q12 2F
7 A 8R 43 Q4 Q8 11B 79 NC D12 3F
8 A 8P 44 D4 D8 11C 80 NC 1G
9 A 9R 45 NC 9B 81 NC 1F
10 Q0 11P 46 NC 10B 82 Q6 Q13 3G
11 D0 10P 47 CQ 11A 83 D6 D13 2G
12 NC 10N 48 – Internal 84 NC 1J
13 NC 9P 49 A 9A 85 NC 2J
14 NC Q1 10M 50 A 8B 86 NC Q14 3K
15 NC D1 11N 51 A 7C 87 NC D14 3J
16 NC 9M 52 A 6C 88 NC 2K
17 NC 9N 53 LD# 8A 89 NC 1K
18 Q1 Q2 11L 54 NC 7A 90 Q7 Q15 2L
19 D1 D2 11M 55 BW0# 7B 91 D7 D15 3L
20 NC 9L 56 K 6B 92 NC 1M
21 NC 10L 57 K# 6A 93 NC 1L
22 NC Q3 11K 58 NC 5B 94 NC Q16 3N
23 NC D3 10K 59 NC BW1# 5A 95 NC D16 3M
24 NC 9J 60 R, W# 4A 96 NC 1N
25 NC 9K 61 A 5C 97 NC 2M
26 Q2 Q4 10J 62 A 4B 98 Q8 Q17 3P
27 D2 D4 11J 63 A NC 3A 99 D8 D17 2N
28 ZQ 11H 64 DLL# 1H 100 NC 2P
29 NC 10G 65 CQ# 1A 101 NC 1P
30 NC 9G 66 NC Q9 2B 102 A 3R
31 NC Q5 11F 67 NC D9 3B 103 A 4R
32 NC D5 11G 68 NC 1C 104 A 4P
33 NC 9F 69 NC 1B 105 A 5P
34 NC 10F 70 NC Q10 3D 106 A 5N
35 Q3 Q6 11E 71 NC D10 3C 107 A 5R
36 D3 D6 10E 72 NC 1D
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 26 of 34
October 6, 2011
JTAG Instructions
Instructions Description
EXTEST The EXTEST instruction allows circuitry external to the component package to be tested.
Boundary-scan register cells at output pins are used to apply test vectors, while those at
input pins capture test results. Typically, the first test vector to be applied using the
EXTEST instruction will be shifted into the boundary scan register using the PRELOAD
instruction. Thus, during the update-IR state of EXTEST, the output drive is turned on and
the PRELOAD data is driven onto the output pins.
IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the
controller is in capture-DR mode and places the ID register between the TDI and TDO pins
in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up
and any time the controller is placed in the test-logic-reset state.
BYPASS When the BYPASS instruction is loaded in the instruction register, the bypass register is
placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-
DR state. This allows the board level scan path to be shortened to facilitate testing of other
devices in the scan path.
SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the
SAMPLE / PRELOAD instruction is loaded in the instruction register, moving the TAP
controller into the capture-DR state loads the data in the RAMs input and Q pins into the
boundary scan register. Because the RAM clock(s) are independent from the TAP clock
(TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample
metastable input will not harm the device, repeatable results cannot be expected. RAM
input signals must be stabilized for long enough to meet the TAPs input data capture setup
plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other
TAP operation except capturing the I/O ring contents into the boundary scan register.
Moving the controller to shift-DR state then places the boundary scan register between the
TDI and TDO
p
ins.
SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM Q pins are forced
to an inactive drive state (high impedance) and the boundary register is connected between
TDI and TDO when the TAP controller is moved to the shift-DR state.
JTAG Instruction Cod ing
IR2 IR1 IR0 Instruction Note
0 0 0 EXTEST
0 0 1 IDCODE
0 1 0 SAMPLE-Z 1
0 1 1 RESERVED 2
1 0 0 SAMPLE / PRELOAD
1 0 1 RESERVED 2
1 1 0 RESERVED 2
1 1 1 BYPASS
Notes 1. TRISTATE all Q pins and CAPTURE the pad values into a SERIAL SCAN LATCH.
2. Do not use this instruction code because the vendor uses it to evaluate this product.
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 27 of 34
October 6, 2011
Output Pin States of CQ, CQ# and Q
Instructions Control-Register Status Output Pin Status
CQ,CQ# Q
EXTEST 0 Update High-Z
1 Update Update
IDCODE 0 SRAM SRAM
1 SRAM SRAM
SAMPLE-Z 0 High-Z High-Z
1 High-Z High-Z
SAMPLE 0 SRAM SRAM
1 SRAM SRAM
BYPASS 0 SRAM SRAM
1 SRAM SRAM
Remark The output pin statuses during each instruction vary according
to the Control-Register status (value of Boundary Scan
Register, bit no. 107).
There are three statuses:
Update : Contents of the “Update Register” are output to the
output pin (DDR Pad).
SRAM : Contents of the SRAM internal output “SRAM
Output” are output to the output pin (DDR Pad).
High-Z :The output pin (D DR Pad) become s high
impedance by controlling of the “High-Z JTAG
ctrl”.
The Control-Register status is set during Update-DR at the
EXTEST or SAMPLE instruction.
SRAM
CAPTURE
Register
Boundary Scan
Register
Update
Register
DDR
Pad
SRAM
Output
Driver
High-Z
JTAG ctrl
High-Z
Update
SRAM
Output
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 28 of 34
October 6, 2011
Boundary Scan Register Status of Output Pins CQ, CQ# and Q
Instructions SR AM Status Boundary Scan Register Status Note
CQ,CQ# Q
EXTEST READ (Low-Z) Pad Pad
NOP (High-Z) Pad Pad
IDCODE READ (Low-Z) − − No definition
NOP (High-Z) − −
SAMPLE-Z READ (Low-Z) Pad Pad
NOP (High-Z) Pad Pad
SAMPLE READ (Low-Z) Internal Internal
NOP (High-Z) Internal Pad
BYPASS READ (Low-Z) − − No definition
NOP (High-Z) − −
Remark The Boundary Scan Register statuses during execution each
instruction vary according to the instruction code and SRAM
operation mo de.
There are two statuses:
Pad : Contents of the output pin (DDR Pad) are captured
in the “CAPTURE Register” in the Boundary Scan
Register.
Internal : Contents of the SRAM internal output “SRAM
Output” are captured in the “CAPTURE Register”
in the Boundary Scan Register.
Pad
Internal
SRAM
Output
Driver
Update
Register
DDR
Pad
High-Z
JTAG ctrl
CAPTURE
Register
SRAM
Output
Boundary Scan
Register
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 29 of 34
October 6, 2011
TAP Controller State Diagram
Test-Logic-Reset
Run-Test / Idle Select-DR-Scan
Capture-DR Capture-IR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR Update-IR
Exit2-IR
Pause-IR
Exit1-IR
Shift-IR
Select-IR-Scan
0
0
0
1
0
1
1
0
0
1
0
1
1
0
0
0
0
10 10
11 1
0
1
1
0
1
0
11
Disabling the Test Access Port
It is possible to use this device withou t utilizing the TAP. To disable the TAP Controller without interfering with
normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS may be left open
but fix them to VDD via a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected
also when the TAP controller is not used.
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 30 of 34
October 6, 2011
Test Logic Operation (Instruction Scan)
TCK
Controller
state
TDI
TMS
TDO
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Shift-IR
Exit1-IR
Update-IR
Run-Test/Idle
IDCODE
Instruction
Register state New Instruction
Output Inactive
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 31 of 34
October 6, 2011
Test Logic (Data Scan)
Controller
state
TDI
TMS
TDO
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Shift-DR
Exit1-DR
Update-DR
Test-Logic-Reset
Instruction
Instruction
Register state IDCODE
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Output Inactive
TCK
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 32 of 34
October 6, 2011
Package Dimensions
165-PIN PLASTIC BGA(13x15)
ITEM DIMENSIONS
D
E
w
A
A1
A2
e
13.00±0.10
15.00±0.10
0.30
0.37±0.05
−0.05
0.10
1.35±0.11
0.98
1.00
(UNIT:mm)
0.15
0.25
1.50
0.50
S
e
y1 S
A
A1
A2
S
y
SxbAB
M
SwA
SwB ZE
ZD
INDEX MARK
A
B
1
2
3
4
5
6
7
8
9
10
11
ABCDEFGHJKLMNPR
E
D
x
y
y1
ZD
ZE
b0.50
P165F5-100-EQ3
+0.10
μ
PD44164095B,
μ
PD44164185B
R10DS0016EJ0200 Rev.2.00 Page 33 of 34
October 6, 2011
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of these products.
Types of Surface Mount Devices
μ
PD44164095BF5-EQ3 : 165-pin PLASTIC BGA (13 x 15)
μ
PD44164185BF5-EQ3 : 165-pin PLASTIC BGA (13 x 15)
Quality Grade
• A quality grade of the products is “Standard”.
• Anti-radioactive design is not implemented in the products.
• Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to
the ground and so forth.
All trademarks and registered trademarks are the property of their respective owners.
C - 34
Revision History
μ
PD44164095B,
μ
PD44164185B
Description
Rev. Date Page Summary
1st edition ’10.02.01 - New Preliminary Data Sheet
Rev.0.02 ’10.08.18 P13 DC Characteristics (Modification, Spec of IDD and ISB1)
P14 Thermal Characteristics (Modification, Spec)
Rev.1.00 ’10.12.13 P30 Package Dimensions (Modification, Dimensions)
Throughout Preliminary Data Sheet Æ Data Sheet
Rev.2.00 ’11.10.06 Throughout Add Lead and the extended temperature operation product
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to
the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is
prohibited under any applicable domestic or foreign laws or regulations.
6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product
depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas
Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the
use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.
The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
personal electronic equipment; and industrial robots.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
designed for life support.
"Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical
implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
http://www.renesas.com
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
7F, No. 363 Fu Shing North Road Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
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