©2004 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev.1.0.2
Features
• Curr ent Mode Contr ol for Main P ow er
• Voltage Mode Control for Auxiliary Power
• Synchronized switching of Main and Auxiliary Power
(70kHz)
• Internal Start-up Circuit
• Internal Soft Start for Auxiliary Power
• User Defined Soft Start for Main Power
• Pulse by Pulse Current Limiting
• Over Load Protection (Main : Latch Mode, Aux : Auto
Restart Mode)
• Internal Ove r Temperature Protection
• Vcc Un der Voltage Lockout
• Line Under voltage/ Ov er Voltage Lockout
• Burst Mode Operation for auxiliary power to reduc e the
Power Consumption in the Standby Mode
• Internal High Voltage Sense FET for auxiliary power
Application
• SMPS for PC power
• LCD TV Power Supply
Description
FSD1000 is a Fairchild Power Switch (FPS) that is specially
designed for SMPS of personal computer. This device is a
high voltage power SenseFET combined with two PWM
controllers in a single monolithic device; One is for main power
and the other is for auxiliary power. The PWM controllers
feature integrated oscillator, under voltage lockout,
optimized gate driver and temperature compensated precise
current sources for the loop compensation. This device also
includes various fau lt protection circuits such as line under/
over voltage lock out, over voltage protection, over load
protection and over temperature protection. Compared with
discrete MOSFET and PWM controller solution, FSD1000
can reduce total cost, component count, size and weight
simultaneously increasing efficiency, productivity and
system reliability
Typical Circuit
FSD1000
Combo Fairchild Power Switch (FPSTM)
Figure 1. Typical Application c ir cuit
Vcc
M a in Ou tput
Main
PWM
V
FB.main
AC
IN
Aux
PWM
V
FB.aux
Aux Output
Main Off
LS1
LS2
V
STR
Output
I
sense
Drain
GND
I
LIM
S/S
FSD1000
2
Internal Block Diagram
Figure 2. Functional Block Diagra m of FSD1000
5
6
1
11
Vref
Internal
Bias
S
Q
Q
R
OSC
I
delay
I
FB
S
Q
Q
R
R
Vcc
V
FB,AUX
Isense
Gate drive
12
Vstr
I
ch
Vcc good
Soft Start
(10ms)
4Output
9.5/13.5V
21V
Vcc OVP
8
I
delay
I
FB
2V
FB.MAIN
Vcc Vcc
Power off Reset
(Vcc <6V)
OTP
Line OVP
Vcc OVP
9
S
Q
Q
R
Gate
drive
Burst
R
Q
Q
S
Auto
restart
Latch
Counter
/4
Burst
Aux OLP
7
Line OVP
Aux OFF
3
OSC
7V
S/S
LS2Drain
GND
I
LIM
LS1
0.8 V
1.0 V 1.4 V
1.68 V
Main OFF
4.4 V 2.4 V
2.0 V
PWM
Comparator
0.5 V
0.7 V
4.5V
R
3R
Vcc
VrefVref Main OLP
Vcc good
1:110 0.3V
Vcc good
Vcc
good
time delay
(30ms)
Main
OLP
Vth
H : D
main
< 0.67
L : D
main
< 0.50
I
SS
FSD1000
3
Pin Definitions
Pin Number Pin Name Pin Function Description
1V
FB,AUX
This pin is for the feedback control of the auxiliary power. This pin is internally
connected to the inverting input of the PWM comparator. The collector of an
opto-coupler is typically tied to this pin. For stable operation, a capacitor should
be placed between this pin and GND. Voltage mode control is employed for the
auxiliary power and the duty cycle ratio of Internal MOSFET for the auxiliary
power is proportional to the voltage of this pin. If the voltage of this pin exceeds
4.5V, the over load protection is triggered terminating the switching operation of
the main and auxiliary power (Auto-restart mode protection).
2V
FB,MAIN
This pin is for the feedback control of the main power. This pin is internally
connected to the inverting input of the PWM comparator. The collector of an
opto-coupler is typically tied to this pin. For stable operation, a capacitor should
be placed between this pin and GND. Current mode control is employed for the
main power and the peak drain current of the external MOSFET for the main
power is proportional to the voltage of this pin. If the voltage of this pin exceeds
7V, the over load protection is triggered disabling the gating output for the main
power (Latch mode protection).
3S/S
This pin is for the soft start of the main power. Soft start time is programmed by
a capacitor on this pin.
4 Output This pin is for the gate drive of the external MOSFET of the main power.
5Vcc
This pin is the positive supply voltage input. During startup, the power is supplied
by an internal high voltage current source that is connected to the Vstr pin. When
Vcc reaches 13.5V, the internal high voltage current source is disabled and the
power is supplied from auxiliary transformer winding.
6I
SENSE
This pin is for the current sense of the external MOSFET for the m ain power. It is
internally connected to the PWM comparator for the main.
7LS1
This pin is for line under voltage detection. When the voltage of this in drops
below 1.4V the main power is shutdown. When the voltage drops below 0.8V,
the auxiliary power is shutdown.
8LS2
This pin is for line over voltage detection and maxim um duty cycl e ratio change.
The maximum duty cycle ratio is set to be 50% when the voltage of LS2 pin is
higher than 2.4V. The maximum duty cycle ratio is increased to 67% when LS2
voltage goes below 2.0V. When the voltage of LS2 goes above 4.4V, the
switching operations for the main and auxiliary powers are disabled to protect
the switching devices.
9I
LIM
This pin is for the current limit of the auxiliary power. The pulse-by-pulse current
limit level of the internal SenseFET is programmed by a resistor on this pin.
10 NC
11 Drain This pin is the high voltage power SenseFET drain. It is designed to drive the
auxiliary transformer directly.
12 V
STR
This pin is connected directly to the high voltage DC link. At startup, the internal
high voltage current source supplies internal bias and charges the external
capacitor that is connected to the Vcc pin. Once Vcc reaches 13V, the internal
current source is disabled.
FSD1000
4
Pin Configuration
Figure 3. Pin Configuration (Top View)
12
11
10
7
8
9
GND
2
3
6
5
4
GND
FSD1000
GND
1
GND
12DIPH
VFB,AUX
Isense
Vcc
Output
S/S
VFB,MAIN
LS1
LS2
ILIM
NC
Drain
Vstr
FSD1000
5
Absolute Maximum Ratings
(Ta=25°C, unless otherwise specified)
Parameter Symbol Value Unit
Maximum Vstr Pin Voltage V
STR,MAX
700 V
Continuous SenseFET Drain Current (T
C
=25°C) I
D
2A
DC
Maximum Supply Voltage V
CC,MAX
20 V
Input Voltage Range V
FB,MAIN /
V
FB,AUX
-0.3 to V
SD
V
Operating Ambient Temperature T
A
-25 to +85 °C
Storage Temperature Range T
STG
-55 to +150 °C
FSD1000
6
Electrical Characteristics
(Ta=25°C unless otherwise specified)
Note:
1. These parameters, although guaranteed, are not 100% tested in production
Parameter Symbol Condition Min. Typ. Max. Unit
SENSEFET SECTION
Drain-Source Breakdown Voltage BV
dss
V
CC
= 0V, I
D
= 100µA 700 - - V
Off-State Current I
dss
V
DS
= 560V - - 100 µA
On-State Resistance R
DS(ON)
Tj = 25°C I
D
= 100mA - 7.8 9.0 Ω
Tj = 100°C I
D
= 100mA - 12.9 15.0 Ω
Rising Time 2
(1)
T
R2
V
DS
= 350V, I
D
= 500mA - 100 - ns
Falling Time 2
(1)
T
F2
V
DS
= 350V, l
D
= 500mA - 50 - ns
Leading Edge Blanking
(1)
T
LEB
- - 250 - ns
Pulse-by-pulse current limit I
LIM
With 33Ω resistor between
I
LIM
pin and ground pin 0.8 1.0 1.2 A
CONTROL SECTION
Switching Frequency Fosc Tj = 25°C 616773kHz
Main Feedback Source Current I
FB,MAIN
Ta = 25°C, V
FB,MAIN
= 0V 0.6 0.7 0.8 mA
Shutdown Main Delay Current I
DELAY,MAIN
Ta = 25°C
5V < V
FB,MAIN
< V
SD,MAIN
3.5 5.0 6.5 uA
Aux. Feedback Source Current I
FB,MAIN
Ta = 25°C, V
FB,AUX
= 0V 0.3 0.4 0.5 mA
Shutdown Aux. Delay Current I
DELAY,MAIN
Ta = 25°C
3V < V
FB,AUX
< V
SD,AUX
3.5 5.0 6.5 uA
Maximum Duty Cycle Dmax V
FB,AUX
= 3.5V
1.4V < LS2 < 2V 62 67 72 %
Maximum Duty Cycle Dmax V
FB,AUX
= 3.5V
2V < LS2 < 4.4V 45 50 55 %
Minimum Duty Cycle Dmin V
FB,AUX
= 0V - 0 0 %
UVLO Threshold Voltage Vstart - 12.5 13.5 14.5 V
Vstop After turn on 8.5 9.5 10.5 V
SOFT START SECTION
Soft Start Current I
SOFT
- 354555uA
Internal Soft Start Time T
SS
--10-ms
Internal Time Delay T
d
--30-ms
PROTECTION SECTION
Thermal Shutdown Temperature (Tj)
(1)
T
SD
(Note 1) 140 160 - °C
Shutdown Main Feedback Voltage V
SD,MAIN
- 6.0 7.0 8.0 V
Shutdown Aux. Feedback Voltage V
SD,AUX
Vfb = 4V 4.0 4.5 5.0 V
OUTPUT SECTION
Rising Time 1
(1)
T
R1
Ta = 25°C, C
L
= 100pF - 45 150 ns
Falling Time 1
(1)
T
F1
Ta = 25°C, C
L
= 100pF - 35 150 ns
FSD1000
7
Electrical Characteristics
(Continued)
(Ta=25°C unless otherwise specified)
Parameter Symbol Condition Min. Typ. Max. Unit
LINE SENSE SECTION
Line Over Voltage BUS OVP - 4.0 4.4 5.0 V
PWM Max Duty Control Voltage Max Duty - 2.0 2.4 2.8 V
Hysteresis - - 400 - mV
Main Off Voltage Main OFF - 1.17 1.4 1.63 V
Hysteresis - - 280 - mV
Aux. Off Voltage Aux OFF - 0.67 0.8 0.93 V
Hysteresis - - 200 - mV
BURST MODE SECTION
Burst Mode Voltage BURST - - 0.7 - V
Hysteresis - - 200 - mV
TOTAL DEVICE SECTION
Start up Chragng Current I
ch
V
CC
= 0V, V
STR
= min. 30V - 1.5 2.3 mA
Operating Supply Current I
op
Ta = 25°C, V
CC
= 18V - 4 5 mA
FSD1000
8
Typical Performance Characteristics
(Some characteristic Graphs are Normalized at Ta= 25°C)
-40 -20 0 20 40 60 80 100 120 140
0.7
0.8
0.9
1.0
1.1
1.2
1.3
Iop
-40 -20 0 20 40 60 80 100 120 140
0.7
0.8
0.9
1.0
1.1
1.2
1.3
Ifb_aux
-40 -20 0 20 40 60 80 100 120 140
0.7
0.8
0.9
1.0
1.1
1.2
1.3
Ifb
-40 -20 0 20 40 60 80 100 120 140
0.7
0.8
0.9
1.0
1.1
1.2
1.3
Fosc
Figure 1. Normali zed Ope ra ting Curre nt vs. Temp Figure 2. Normalized Aux feedback current vs. Temp
Figure 3. Normaliz ed Main feedback current vs. Temp Figure 4. N ormali zed Operating Freqency vs. Temp
Figure 5. Output source curre nt (m A) vs. Temp Figure 6. Output sink Current (mA) vs. Temp
-40 -20 0 20 40 60 80 100 120 140
200
250
300
350
400
450
500
550
Isouce
-40 -20 0 20 40 60 80 100 120 140
300
350
400
450
500
550
600
650
700
Isink
FSD1000
9
Functional Description
1.
1. 1.
1. Startup : At startup, an internal high voltage current
source supplies the internal bias and charges the external
capacitor that is connected to the Vcc pin as illustrated in
figure 4. When Vcc reaches 13.5 V, the FPS begins switching
operation and the internal high voltage current source is
disabled. Then, the FPS continues its normal switching
operation unless Vcc goes below the stop voltage of 9.5 V
and the power is supplied from the auxiliary transformer
winding. Once the aux iliary power star ts up, the main power
starts up with a time delay of 30ms.
Figure 4. Int ernal startup circuit
2. Feedback Control : FSD1000 has two PWM controllers
in a single packag e; one is for the main power a nd the other
is for the auxiliary power. The PWM block for the main
controls the external MOSFET, while the PWM block for the
auxiliary power contr ols the internal SenseFET.
2.1 Feedback Control for the main power : Figure 5
illustrates the simplified PWM block for the main power.
The current mode control is employed for the main power.
The voltage of the feedback pin is compar ed with the current
sense voltage for pulse width modulation (PWM). As shown
in figure 5, the feedback voltage determines the peak value
of the dra in current of the external power MOSFET for main
power. Usually opto-coupler is used to implement feedback
network. The collector of the opto-coupler transistor is
connected to feedback pin and the emitter is connected to the
ground pin. For stable operation, a capacitor should be
placed between this pin and GND.
2.2 Feedback Control for the auxiliary power : Figure 6
shows the internal high voltage SenseFET together with
PWM block for auxiliary power. Auxiliary power employs
voltage mode control and the feedback pin voltage is
compared with internal ramp signal for pulse width
modulation (PWM). The pulse-by-pulse current limit level of
the SenseFET is programmed by an external resistor on the
I
LIM
pin. Since the sense ratio is 1/110 and the reference
voltage of the comparator is 0.3V, the pulse-by-pulse current
limit level (I
CL
) is given by
Figure 5. PWM control block for the main power
Figure 6. PWM control block for the auxiliary power
3. Protection Circuit : Besides pulse-by-pulse current limit,
FSD1000 has various self protection functions; over load
protections (OLP) for main and auxiliary powers, over
voltage protection (OVP), line over/under voltage lockout
and over temperature protection (OTP). Because these
protection circuits are fully integrated into the IC without
external compone nts, the relia bility can b e improved. In the
event of fault conditions such as OLP of auxiliary power and
9.5V/13.5V
3
Vref
Internal
Bias
Vcc 6Vstr
I
start
Vcc good
DC lin k
voltage
I
CL
110 0.3×
R
LIM
------------------------=A()
6
S
Q
Q
R
Isense
Gate
drive 4Output
I
delay
I
FB
2
V
FB.MAIN
Vcc Vcc
PWM
Comparator
R
3R
OSC
5Max dut y
control
2.0 V
2.4 V
LS2
C
FB
D1D2
4
11
OSC
I
delay
I
FB
R
V
FB,AUX
Soft start
9
S
Q
Q
R
Gate
drive
Burst
OSC
Drain
GND
I
LIM
Vref
Vref
1/110
0.3V
C
FB
D1 D2
R
LIM
FSD1000
10
line under voltage lockout, FSD1000 enters into auto restart
operation. Once the fault condition occurs, switching is
terminated and the SenseFET remains off. This causes Vcc
to fall. When Vcc reaches the stop voltage (9.5V), the
internal startup circuit charges Vcc capacitor up to start
voltage (13.5V). When Vcc reaches 13.5V, the internal
startup circuit is disabled and Vcc is discharged down to
9.5V. In this manner, FSD1000 repeats charging and
discharging Vcc capacitor 4 tim es. After th en, the protection
is reset and the FSD1000 resumes its normal operation. In
this manner, the auto-restart can alternately enable and
disable the switching of the power SenseFET until the fault
condition is eliminated as shown Figure 7. Meanwhile,
FSD1000 enters into latch mode in the case of Vcc OVP,
Line OVP and Main OLP and OTP. The fault latch is reset
only when Vcc is fully discharged below 6V by un-plugging
the AC line as shown in Figure 8.
Figure 7. Auto restart mode pr otect ion
Figure 8. Latch mode prote ction
3.1 Over Load Protection : Over load means that the load
current exceed s a pre-set level due to an abnormal situation.
In this situation, protection circuit should be triggered in
order to protect the SMPS. Because of the pulse-by-pulse
current limit capability, the maximum peak current through
the SMPS is limited, and therefore the maximum input
power is restricted with a given input voltage. If the output
consumes beyond this maximum power, the output voltage
(Vo) decreases below the set voltage. This reduces opto-
coupler transistor curren t increasing feedback vo ltage (Vfb).
If the inverting input of PWM comparator reaches its
maximum value, D1 is blocked and the current source I
delay
starts to charge C
FB
slowly compared to when the current
source I
FB
charges C
FB
. In this condition, the feedback
voltage continues increasing until it reaches OLP threshold,
and the switching operation is terminated at that time. The
OLP for the auxiliar y power is auto restart mo de while OLP
for the main is latch mode.
3.2 Line Under voltage lockout : The switching operation
for the main power is terminated when the voltage of LS1
drops below 1.4V and the switching operation for auxiliary
power is terminated when this voltage goes below 0.8V.
3.3 Over voltage protection : In an abnormal situation such
as feedback loop open, the supply voltage for FSD1000
(Vcc) may rise above the breakdown voltage of the FPS. In
order to protects the FPS from the over voltage damage,
FSD1000 employs over voltage protection for Vcc. If Vcc
exceeds 21V, OVP circuit is triggered resulting in a
termination of switching operation of both main and
auxiliary powers. In order to avoid undesired triggering of
OVP during normal operation, Vcc should be properly
designed to be below 21V.
3.4 Line Over voltage protection : When the voltage of
LS2 rise s a bov e be lo w 4.4 V , th e sw it chi n g o per a ti ons for t he
main and auxiliary powers are disabled to protect the
switch i ng de vic e s.
3.5 Over Temperature Protection : The therm al shutdown
circuitry senses the junction temperature. The threshold is set
at 160°C. When the junction temperature rises above this
threshold, the switching operations of main and auxiliary
powers are disabled.
4. Burst Mode Operation : In order to minimize the power
dissipation in the standby mode, FDS1000 has burst
operation for the auxiliary power. The FPS enters into the
burst mode when the feedback voltage dec reases as the load
decreases. The operation principle of the burst mode is
illustrated in Figure 9. When the feedback voltage drops
below 0.5V, the FPS stops the switching operation. Then, the
output voltage decreases below the set voltage, which
increases the feedback voltage. When the feedback voltage
rises above 0.7V, the FPS resumes the switching operation
and the feedback voltage decreases. When the feedback
voltage drops below 0.5V again, the FPS ceases the
Vcc
13.5V
9.5V
Over Load of Aux
Restart
Aux V
ds
Over Load removed
Vcc
13.5V
9.5V
OTP, Vcc OVP, Line
OVP, Main OLP
Aux Vds
AC power Off
6V
Latch Reset
AC pow er O n
FSD1000
11
switching operation. In this manner, the burst operation
alternately enables and disables the switching of the power
MOSFET to reduce the switching loss in the standby mode.
Figure 9. Waveforms of burst operation
5. Sequence of start-up and shutdown : FSD1000 has a
sequence of the startup and shutdown operation between
main and auxiliary powers. As can be seen in Figure 11,
main power starts up with 30 ms time delay after auxiliary
power starts up. When the AC line is powered off, the main
power sh uts down first as the v olta ge of LS1 pin drop s belo w
1.4V. The auxiliary power shuts down when the voltage of
LS1 drops below 0.8V. Figure 12 shows the shutdown and
restart sequence in the case of auto restart mode protection.
When the protectio n is triggered, main an d auxiliary powers
shut down together. When FSD1000 restarts, the auxiliary
power starts up first and the main power starts up after 30ms.
Figure 13 shows the shutdown and restart sequence in the
case of latch mode protection. When the protection is
triggered, main and auxiliary powers shut down together and
Vcc continues being charged and discharged until Vcc is
fully discharged. The protection is reset when Vcc is
discharged below 6V by unplugging the AC line. Figure 14
shows the remote ON/OFF of the main power. The remote
ON/OFF of the main power is easily implemented using a
transistor connected to the cathode of KA431 in the main
power feedback network as shown in Figure 10. When the
transistor is turned on, the current through the opto-coupler
increases pulling down the feedback voltage to almost zero.
The main starts up with soft-start when the transistor is
turned off.
Figure 10. Remote ON/OFF of Main power
V
FB
Vds
0.50V
0.70V
Ids
Vo
Vo
set
time
Ma in Ou t p ut
Aux Output
Ma in Off
FSD1000
12
Figure 11. Typical Waveforms (1)
Figure 12. Typical Waveforms (2)
AC Line
voltage
DC link
voltage
Vcc
Aux drain
current
Main drain
current
Tss=10ms
Td=30ms
AC power on AC pow er off AC power on
13.5V
9.5V
Td=30ms
Tss=10ms
LS1<1.4V
LS1<0.8V
Vcc
Aux drain
current
Main drain
current
T
ss
=10ms
T
d
=30ms
13.5V
9.5V
T
d
=30ms
T
ss
=10ms
OLP of Aux Auto Restart
FSD1000
13
Figure 13. Typical Waveforms (3)
Figure 14. Typical Waveforms (4)
Vcc
A ux drain
current
Main drain
current
T
ss
=10ms
T
d
=30ms
13.5V
9.5V
T
ss
=10ms
Vcc OVP, Line OVP,
Main OLP or OTP
AC Power off
6V
Latch
reset AC Power ON
T
d
=30ms
Vcc
Aux drain
current
Main drain
current
T
ss
=10ms
T
d
=30ms
13.5V
Main Off by
pulling down V
FB
Main ON
Main V
FB
FSD1000
14
Typical application circuit
Features
• Low standby mode power consumption (<1W at 240Vac input and 0.5W load)
• Low component count
• Enhanced system reliability through various protection functions
• Intern al soft-start (10ms)
1. Schematic
Application Output power Input voltage Output voltage (Max current)
PC power supply 110W Universal input
with voltage doubler
Main power : 5V (12A), 3.3V (12A)
Aux. power : 5V (2A)
P2
817A
12
43
GND_S
R210
4.7k
12
IC2
TL431
32
1
C203
472
1 2
C201
472
1 2
0
Is
D201
1 2
3
C108
222,1kV
1 2
R214
10k
1 2
R101
500K
12
R206
1k
1 2
R216
10k
1 2
R205
1k
1 2
T1
EI3329
6
4
141
13
5
3
2
87
9
10
11
12
3.3V
R211
33k 12
R201
10
1 2
C114
222,1kV
1 2
C206
2200uF,10V
2 1
MBRF3060PT
Gate
t
RT1
10D9
1 2
GND_P
R212
1k
1 2
C202
472
12
R208
3.2k
1 2
-+
BD1
GSIB660
1
2
3
4
GND_S
Is
R209
5k
1 2
C208
470uF,16V
2 1
R111
10k
1 2
D101
UF4007
1 2
C110
47uF,50V
12
R108
50K/3W
12
R110
30
1 2
D103
1N4745
L201
EER2834
6
4
1
5
3
2
8
9
10
11
12
7
GND_P L202
2uH
1 2
C105222/3kV
12
S1
SW SPDT
21
3
R213
1k
1 2
C113
1uF
1 2
5V_aux
GND_S
Q2
2N2222
1
2
3
IC1
TL431
32
1
VDC
C107
470uF,200V
12
D203
GP30G
1 2
D102
UF4004
12
GND_S
R203
10
1 2
C205
2200uF,10V
2 1
C104
222/3kV
1 2
C101
473/275VAC
1 2
C210
100nF
12
R112
33
1 2
C207
470uF,16V
2 1
GND_P
R207
33k
12
R104
33K/3W
12
F1
FUSE
R107
10/0.5W
1 2
C115
473
1 2
VFB1
C106
470uF,200V
12
Gate
C102
473/275VAC
1 2
MBRF3060PT
VDC
R109
30k
1 2
R202
10
12
R204
10
12
D104
UF4003
12
T2
EE1625
6
4
101
9
5
3
2
8
7
R103
10K
12
C111
103
1 2
GND_P
VFB1
D106
UF4007
12
C103
222/3kV
1 2
LF1
1 2
GND_S
C109
102
12
C112
473
1 2
GND_P
R106
0.1/2W
12
JP2
HEADER 3
1
2
3
Drain
U1
FSD1000
1
2
3
4
5
67
8
9
10
14 13
12
11
VFB.aux
VFB.main
S/S
Output
Vcc
IsenseLS1
LS2
I_LIM
NC
GND GND
Vstart
Drain
R102
500K
12
GND_S
C209
47nF
12
D202
1 2
3
Line f ilter
1 2
VFB2
GND_P
Drain
5V
VDC
C204
472
12
GND_P
GND_S
GND_P
LS
0
R105
1K
1 2
D105
1N4745
GND_P
GND_S
LS
P1
817A
12
43
R215
10k
1 2
VFB2
GND_P
D
S
G
Q1
FQA10N80
1
3 2
FSD1000
15
2.1 Main Transformer Schematic Diagram
CORE : EI3329
BOBBIN : EI3329
2.2 Main Transformer Winding Specification
2.3 Main Transformer Electrical Characteristics
No Pin (s→f) Wire Turns Winding Method
N
P/2
1 → 30.5
φ
× 1 24 Solenoid Winding
Insulation: Polyester Tape t = 0.050mm, 2Layers
N
3.3V
10 → 80.4
φ
× 6 2 Center Winding
Insulation: Polyester Tape t = 0.050mm, 2Layers
N
5V
14→ 12 0.4
φ
× 6 3 Center Winding
Insulation: Polyester Tape t = 0.050mm, 2Layers
N
P/2
3 → 50.5
φ
× 1 24 Solenoid Winding
Outer Insulation: Polyester Tape t = 0.050mm, 2Layers
Pin Specification Remarks
Inductance 1 - 5 9mH ± 10% 100kHz, 1V
Leakage Inductance 1 - 5 10uH Max 2
nd
all short
*THE' ' MARKS
A
RE START POINT.
1
2
3
4
511
9
8
7
610
+5V
+3.3V
N
P/2
N
P/2
N
P/2
N
P/2
3㎜
Bobbin
BOTTOM TOP
N
3.3V
N
5V
12
13
14 3㎜
FSD1000
16
3.1 Main inductor Schematic Diagram
CORE : EER2834
BOBBIN : EER2834
3.2 Main inductor Winding Specification
3.3 Main inductor Electrical Characteristics
No Pin (s→f) Wire Turns Winding Method
N
5V
1 → 12 0.4
φ
× 8 9 Center Winding
Insulation: Polyester Tape t = 0.050mm, 2Layers
N
3.3V
6 → 70.4
φ
× 8 6 Solenoid Winding
Insulation: Polyester Tape t = 0.050mm, 2Layers
Pin Specification Remarks
Inductance 1 - 12 15 uH ± 10% 100kHz, 1V
*THE' ' MARKS
A
RE START POINT.
123
4
5
11987
6
10
N
3.3V
N
5V
N
3.3V
3㎜
Bobbin
TOP
N
5V
12
3㎜
FSD1000
17
4.1 Auxiliary Transformer Schematic Diagram
CORE : EE1625
BOBBIN : EE1625
4.2 Auxiliary Transformer Winding Specification
4.3 Auxiliary Transformer Electrical Characteristics
No Pin (s→f) Wire Turns Winding Method
N
P/2
4 → 50.15
φ
75 Solenoid Winding
N
5V
8 → 70.5
φ
9 Solenoid Winding
N
Vcc
2 → 10.2
φ
25 Solenoid Winding
N
P/2
5 → 60.15
φ
75 Solenoid Winding
Pin Specification Remarks
Inductance 4 - 6 1.35mH ± 10% 100kHz, 1V
Leakage Inductance 4 - 6 60uH Max 2
nd
all short
*THE' ' MARKS
A
RE START POINT.
1
2
3
4
5
9
8
7
6
10
+5V
N
P/2
N
P/2
N
P/2
N
P/2
3㎜
Bobbin
BOTTOM TOP
N
5V
N
Vcc
3㎜
N
Vcc
FSD1000
18
5. Layout Auxiliary Transformer Electrical Characteristics
FSD1000
19
Package Dimensions
12DIPH-300
FSD1000
7/9/04 0.0m 001
2004 Fairchild Semiconductor Corporation
LIFE SU PP ORT POL ICY
FAIRCHILD’ S PRODUCTS ARE NOT AUTHORIZ ED FOR USE AS CRI TICAL C OMPONENTS IN LIFE SUPP ORT DEVI CES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORA TION. As used he rein :
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or syst em who se fai lure to pe rform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effec tiv ene ss.
www.fairchildsemi.com
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MA KE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRO DUCTS HEREIN TO IMPROVE RELIABILITY, FUN CTION OR DESIG N. FAIRCHILD DO ES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIG HTS, NOR THE RIGHTS OF OT HERS.
Ordering Information
Product Number Package Package Marking Rdson
max
FSD1000 12-DIPH FSD1000 9 Ω
