ADM811ZART-REEL-7 - Analog Devices

REV. C

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ADM811/ADM812

Microprocessor Supervisory

Circuit in 4-Lead SOT-143

FEATURES

Superior Upgrade for MAX811/MAX812

Specified over Temperature

Low Power Consumption (5 ␮A Typ)

Precision Voltage Monitor: 2.5 V, 3 V, 3.3 V, 5 V Options

Reset Assertion Down to 1 V VCC

140 ms Min Power-On Reset

Logic Low RESET Output (ADM811)

Logic High RESET Output (ADM812)

Built-In Manual Reset

APPLICATIONS

Microprocessor Systems

Controllers

Intelligent Instruments

Automotive Systems

Safety Systems

Portable Instruments

FUNCTIONAL BLOCK DIAGRAM

DEBOUNCE

RESET/RESET

GND

VCC

VREF

ADM811/ADM812

RESET

GENERATOR

GENERAL DESCRIPTION

The ADM811/ADM812 is a reliable voltage monitoring device

suitable for use in most voltage monitoring applications. The

ADM811/ADM812 is designed to monitor six different voltages,

each allowing for a 5% or 10% degradation of standard PSU

voltages before a reset occurs. These voltages have been selected

for the effective monitoring of 2.5 V, 3 V, 3.3 V, and 5 V supply

voltage levels.

Included in this circuit is a debounced manual reset input.

Reset can be activated using an electrical switch (or an input

from another digital device) or by a degradation of the supply

voltage. The manual reset function is very useful, especially if

the circuit in which the ADM811/ADM812 is operating enters

into a state that can only be detected by the user. Allowing the

user to reset a system manually can reduce the damage or

danger that could otherwise be caused by an out-of-control or

locked system.

RESET RESET

ADM811

GND

MICROPROCESSOR

SYSTEM

100k⍀

Figure 1. Typical ADM811 Operating Circuit

REV. C–2–

ADM811/ADM812–SPECIFICATIONS

Parameter Min Typ Max Unit Test Conditions/Comments

SUPPLY

Voltage 1.0 5.5 V T

= 0°C to 70°C

1.2 V T

= –40°C to +85°C

Current 8 15 µAV

< 5.5 V, ADM81_L/M, I

OUT

= 0 mA

510 µAV

< 3.6 V, ADM81_R/S/T/Z, I

OUT

= 0 mA

RESET VOLTAGE THRESHOLD

ADM81_L 4.54 4.63 4.72 V T

= 25°C

ADM81_L 4.50 4.75 V T

= –40°C to +85°C

ADM81_M 4.30 4.38 4.46 V T

= 25°C

ADM81_M 4.25 4.50 V T

= –40°C to +85°C

ADM81_T 3.03 3.08 3.14 V T

= 25°C

ADM81_T 3.00 3.15 V T

= –40°C to +85°C

ADM81_S 2.88 2.93 2.98 V T

= 25°C

ADM81_S 2.85 3.00 V T

= –40°C to +85°C

ADM81_R 2.58 2.63 2.68 V T

= 25°C

ADM81_R 2.55 2.70 V T

= –40°C to +85°C

ADM81_Z 2.28 2.32 2.35 V T

= 25°C

ADM81_Z 2.25 2.38 V T

= –40°C to +85°C

RESET THRESHOLD

TEMPERATURE COEFFICIENT 30 ppm/°C

TO RESET/RESET DELAY 40 µsV

= 125 mV, ADM81_L/M

20 µsV

= 125 mV, ADM81_R/S/T/Z

RESET ACTIVE TIMEOUT PERIOD 140 560 ms V

= V

TH(MAX)

300 700 ms (ADM811-3T Only)

MANUAL RESET

Minimum Pulsewidth 10 µs

Glitch Immunity 100 ns

RESET/RESET Propagation Delay 0.5 µs

Pull-Up Resistance 10 20 30 kΩ

The Manual Reset Circuit Will Act On:

An Input Rising Above 2.3 V V

> V

TH(MAX)

ADM81_L/M

An Input Falling Below 0.8 V V

> V

TH(MAX)

ADM81_L/M

An Input Rising Above 0.7 ⫻ V

> V

TH(MAX)

ADM81_R/S/T/Z

An Input Falling Below 0.25 ⫻ V

> V

TH(MAX)

ADM81_R/S/T/Z

RESET/RESET Output Voltage

Low (ADM812R/S/T/Z) 0.3 V V

= V

TH(MAX)

, I

SINK

= 1.2 mA

Low (ADM812L/M) 0.4 V V

= V

TH(MAX)

, I

SINK

= 3.2 mA

High (ADM812R/S/T/Z/L/M) 0.8 ⫻ V

V1.8 V < V

< V

TH(MIN)

, I

SOURCE

= 150 µA

Low (ADM811R/S/T/Z) 0.3 V V

= V

TH(MIN)

, I

SINK

= 1.2 mA

Low (ADM811L/M) 0.4 V V

= V

TH(MIN)

, I

SINK

= 3.2 mA

Low (ADM811R/S/T/Z/L/M) 0.3 V V

> 1.0 V, I

SINK

= 50 µA

High (ADM811R/S/T/Z) 0.8 ⫻ V

> V

TH(MAX)

, I

SOURCE

= 500 µA

High (ADM811L/M) V

– 1.5 V V

> V

TH(MAX)

, I

SOURCE

= 800 µA

Specifications subject to change without notice.

(VCC = Full Operating Range; TA = TMIN to TMAX; VCC typ = 5 V for L/M,

3.3 V for T/S, 3 V for R, 2.5 V for Z Models; unless otherwise noted.)

REV. C

ADM811/ADM812

–3–

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

ADM811/ADM812 feature proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

ABSOLUTE MAXIMUM RATINGS*

(Typical values are at T

= 25°C, unless otherwise noted.)

Terminal Voltage (With Respect to Ground)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

All Other Inputs . . . . . . . . . . . . . . . . . –0.3 V to V

+ 0.3 V

Input Current

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

MR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Output Current

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Power Dissipation (T

= 70°C)

RT-4, (SOT-143) . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mW

Derate by 4 mW/°C above 70°C

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 330°C/W

Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +160°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum ratings

for extended periods of time may affect device reliability.

ORDERING GUIDE

Reset Temperature Branding

Model*Threshold (V) Range Information Quantity (K)

ADM811LART-REEL 4.63 –40°C to +85°CMBV 10

ADM811LART-REEL-7 4.63 –40°C to +85°CMBV 3

ADM811MART-REEL 4.38 –40°C to +85°CMBT 10

ADM811MART-REEL-7 4.38 –40°C to +85°CMBT 3

ADM811TART-REEL 3.08 –40°C to +85°CMBG 10

ADM811TART-REEL-7 3.08 –40°C to +85°CMBG 3

ADM811-3TART-REEL 3.08 –40°C to +85°CMB3 10

ADM811-3TART-REEL-7 3.08 –40°C to +85°CMB3 3

ADM811SART-REEL 2.93 –40°C to +85°CMBE 10

ADM811SART-REEL-7 2.93 –40°C to +85°CMBE 3

ADM811RART-REEL 2.63 –40°C to +85°CMBB 10

ADM811RART-REEL-7 2.63 –40°C to +85°CMBB 3

ADM811ZART-REEL 2.32 –40°C to +85°CMBZ 10

ADM811ZART-REEL-7 2.32 –40°C to +85°CMBZ 3

ADM812LART-REEL 4.63 –40°C to +85°CMCV 10

ADM812LART-REEL-7 4.63 –40°C to +85°CMCV 3

ADM812MART-REEL 4.38 –40°C to +85°CMCT 10

ADM812MART-REEL-7 4.38 –40°C to +85°CMCT 3

ADM812TART-REEL 3.08 –40°C to +85°CMCG 10

ADM812TART-REEL-7 3.08 –40°C to +85°CMCG 3

ADM812SART-REEL 2.93 –40°C to +85°CMCE 10

ADM812SART-REEL-7 2.93 –40°C to +85°CMCE 3

ADM812RART-REEL 2.63 –40°C to +85°CMCB 10

ADM812RART-REEL-7 2.63 –40°C to +85°CMCB 3

ADM812ZART-REEL 2.32 –40°C to +85°CMCZ 10

ADM812ZART-REEL-7 2.32 –40°C to +85°CMCZ 3

*Only available in reels.

REV. C

ADM811/ADM812

–4–

PIN CONFIGURATION

2TOP VIEW

(Not to Scale)

GND

ADM811/

ADM812

RESET/RESET

VCC

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function

1GND 0 V. Ground reference for all signals.

2RESET (ADM811) Active Low Logic Output. RESET remains low while V

is below the reset threshold or when MR is low;

RESET then remains low for at least 140 ms (at least 300 ms for the ADM811-3T) after V

rises above

the reset threshold.

RESET (ADM812) Active High Logic Output. RESET remains high while V

is below the reset threshold or when MR is low;

RESET then remains high for 240 ms (typical) after V

rises above the reset threshold.

3MR Manual Reset. This active low debounced input will ignore input pulses of 100 ns or less (typical) and is

guaranteed to accept input pulses of greater than 10 µs. Leave floating when not used.

2.5 V, 3 V, 3.3 V, or 5 V Monitored Supply Voltage.

REV. C

Typical Performance Characteristics—ADM811/ADM812

–5–

TEMPERATURE – ⴗC

–40

–20 0 20 30 50 70 85 100 120

IDD – ␮A

IDD @ VCC = 5.5V

IDD @ VCC = 3V

IDD @ VCC = 1V

TPC 1. Supply Current vs. Temperature (ADM81_R/S/T/Z)

1000

POWER-DOWN RESET DELAY – ␮s

VOD = 20mV

VOD = 200mV

VOD = 125mV

900

800

700

600

500

400

300

200

100

TEMPERATURE – ⴗC

–40 –20 0 20 30 50 70 85 100 120

TPC 2. Power-Down

RESET

Delay vs. Temperature

(ADM81_R/S/T/Z)

289

POWER-UP RESET TIMEOUT – ms

284

279

274

269

264

259

254

249

244

ADM81_L/M

ADM81_R/S/T/Z

TEMPERATURE – ⴗC

–40 –20 0 20 30 50 70 85 100 120

TPC 3. Power-Up Reset Timeout vs. Temperature

IDD – ␮A

IDD @ VCC = 5.5V

IDD @ VCC = 3V

IDD @ VCC = 1V

TEMPERATURE – ⴗC

–40 –20 0 20 30 50 70 85 100 120

TPC 4. Supply Current vs. Temperature (ADM81_L/M)

900

POWER-DOWN RESET DELAY – ␮s

800

700

600

500

400

300

200

100

= 20mV

= 200mV

= 125mV

TEMPERATURE – ⴗC

–40 –20 0 20 30 50 70 85 100 120

TPC 5. Power-Down

RESET

Delay vs. Temperature

(ADM81_L/M)

1.007

NORMALIZED RESET THRESHOLD

1.006

1.005

1.004

1.003

1.002

1.001

1.000

0.999

0.998

0.997

0.996

0.995

TEMPERATURE – ⴗC

–40 –20 0 20 30 50 70 85 100 120

TPC 6. Reset Threshold Deviation vs. Temperature

REV. C

ADM811/ADM812

–6–

CIRCUIT INFORMATION

Reset Thresholds

A reset output is provided to the microprocessor whenever the

input is below the reset threshold. The actual reset thresh-

old is dependent on whether an L, M, T, S, R, or Z suffix is

used. Refer to Table I.

Table I. Reset Threshold Options

Reset

Model Threshold (V)

ADM811LART 4.63

ADM811MART 4.38

ADM811TART 3.08

ADM811-3TART 3.08

ADM811SART 2.93

ADM811RART 2.63

ADM811ZART 2.32

ADM812LART 4.63

ADM812MART 4.38

ADM812TART 3.08

ADM812SART 2.93

ADM812RART 2.63

ADM812ZART 2.32

RESET OUTPUT

On power-up and after V

rises above the reset threshold, an

internal timer holds the reset output active for 240 ms (typical).

This is intended as a power-on reset signal for the processor. It

allows time for both the power supply and the microprocessor to

stabilize after power-up. If a power supply brownout or inter-

ruption occurs, the reset output is similarly activated and remains

active for 240 ms (typical) after the supply recovers. This allows

time for the power supply and microprocessor to stabilize.

The ADM811 provides an active low reset output (RESET)

while the ADM812 provides an active high output (RESET).

During power-down of the ADM811, the RESET output remains

valid (low) with V

as low as 1 V. This ensures that the micro-

processor is held in a stable shutdown condition as the supply

falls and also ensures that no spurious activity can occur via

the microprocessor as it powers up.

MANUAL RESET

The ADM811/ADM812 is equipped with a manual reset input.

This input is designed to operate in a noisy environment where

unwanted glitches could be induced. These glitches could be

produced by the bouncing action of a switch contact, or where a

manual reset switch may be located some distance away from

the circuit (the cabling of which may pick-up noise).

The manual reset input is guaranteed to ignore logically valid

inputs that are faster than 100 ns and to accept inputs longer in

duration than 10 µs.

Glitch Immunity

The ADM811/ADM812 contains internal filtering circuitry

providing glitch immunity from fast transient glitches on the

power supply line.

RESET

REF

= RESET TIME = 240ms TYPICAL

REF

= RESET VOLTAGE THRESHOLD

Figure 2. Power Fail

RESET

Timing

INTERFACING TO OTHER DEVICES

Output

The ADM811/ADM812 is designed to integrate with as many

devices as possible. One feature of the ADM811/ADM812 is

the reset output, which is directly proportional to V

(this is

guaranteed only while V

is greater than 1 V). This enables the

part to be used with both 3 V and 5 V, or any nominal voltage

within the minimum and maximum specifications for V

BENEFITS OF A VERY ACCURATE RESET THRESHOLD

Because the ADM811/ADM812 can operate effectively even when

there are large degradations of the supply voltages, the possibility

of a malfunction during a power failure is greatly reduced. Another

advantage of the ADM811/ADM812 is its very accurate internal

voltage reference circuit. Combined, these benefits produce an

exceptionally reliable microprocessor supervisory circuit.

RESET

ADM811

GND

VCC

Figure 3. Ensuring a Valid

RESET

Output

Down to V

= 0 V

ENSURING A VALID RESET OUTPUT DOWN TO V

= 0 V

When V

falls below 0.8 V, the ADM811/ADM812’s RESET

no longer sinks current. Therefore, a high impedance CMOS

logic input connected to RESET may drift to undetermined

logic levels. To eliminate this problem, a 100 kΩ resistor should

be connected from RESET to ground.

REV. C

ADM811/ADM812

–7–

OUTLINE DIMENSIONS

4-Lead Small Outline Transistor Package [SOT-143]

(RT-4)

Dimensions shown in millimeters

0.89

0.76

SEATING

PLANE

0.45

0.30

0.15

0.05

3.04

2.80

1.22

0.80

PIN 1

1.92 BSC

1 2

1.40

1.20

2.64

2.10

8ⴗ

0ⴗ

0.60

0.40

0.20

0.08

COMPLIANT TO JEDEC STANDARDS TO-253D

0.20

BSC

REV. C

C00092–0–2/03(C)

PRINTED IN U.S.A.

–8–

ADM811/ADM812

Revision History

Location Page

2/03—Data Sheet changed from REV. B to REV. C.

Changes FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Removed Note 2 from ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Removed Note from Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1/03—Data Sheet changed from REV. A to REV. B.

Added ADM812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal

Changes SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Changes to PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Additions to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Changes to Manual Reset section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5/02—Data Sheet changed from REV. 0 to REV. A.

Deletion of ADM812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal