PALCE16V8L-25JCT - Cypress Semiconductor

Flash Erasable,

Reprogrammable CMOS PAL® Device

PALCE16V8

Cypress Semiconductor Corporation •3901 North First Street •San Jose •CA 95134 •408-943-2600

Document #: 38-03025 Rev. ** Revised September 3, 1998

16V8

Features

• Active pull-up on data input pins

• Low power version (16V8L)

—55 mA max. commercial (10, 15, 25 ns)

—65 mA max. industrial (10, 15, 25 ns)

—65 mA military (15 and 25 ns)

• Standard version has low power

—90 mA max. commercial (10, 15, 25 ns)

—115 mA max. commercial (7 ns)

—130 mA max. military/industrial (10, 15, 25 ns)

• CMOS Flash technology for electrical erasability and

reprogrammability

• PCI compliant

• User-programmable macrocell

—Output polarity control

—Individually selectable for registered or combinato-

rial operation

• Up to 16 input terms and 8 outputs

•7.5 ns com’l version

5 ns tCO

5 ns tS

7.5 ns tPD

125-MHz state machine

•10 ns military/industrial versions

7 ns tCO

10 ns tS

10 ns tPD

62-MHz state machine

•High reliability

—Proven Flash technology

—100% programming and functional testing

Functional Description

The Cypress PALCE16V8 is a CMOS Flash Electrical Eras-

able s econd-gen eration programm able arra y logic device . It is

implem ented wi th the fam iliar sum -of-prod uct ( AND-OR) lo gic

structure and the programmable macrocell.

16V8–1

8888888 8

10987654321

11 12 13 14 15 16 17 18 19 20

PROGRAMMABLE

AND ARRAY

(64 x 32)

Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell

GND I8I7I6I5I4I3I2I1CLK/I0

OE/I9I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7VCC

Logic Block Diagram (PDIP/CDIP)

Pin Configurations PLCC/LCC

Top View

16V8–216V8–3

89 10111213

321 19

CLK/I

I/O

OE/I

I/O

CLK/I0

GND OE/I9

VCC

I/O7

I/O6

I/O4

I/O3

I/O2

I/O0

I/O5

I7I/O1

10 11

DIP

I/O6

I/O4

I/O3

I/O2

I/O5

GND

Top View

PALCE16V8

Document #: 38-03025 Rev. ** Page 2 of 13

Functional Description (continued)

The PALCE16V8 is executed in a 20-pin 300-mil molded DIP,

a 300-mil cerdip, a 20-lead square ceramic leadless chip car-

rier, and a 20-lead square plastic leaded chip carrier.

The device provides up to 16 inputs and 8 outputs. The

PALCE16V8 can be electrically erased and reprogrammed.

The programmable macrocell enables the device to function

as a s uperset to t he famil iar 20-pin PLDs suc h as 16L8, 16R8,

16R6, and 16R4.

The PALCE16V8 features 8 product terms per output and 32

input ter ms into the AND array . The fi rst product term in a mac-

rocel l can be us ed ei the r as an in tern al ou tpu t ena ble c ont rol

or as a data product term.

There are a total of 18 architecture bits in the PALCE16V8

macrocell; two are global bits that apply to all macrocells and

16 that apply locally, two bits per macrocell. The architecture

bits determine whether th e macrocell functions as a register or

combin atorial wi th invert ing or noninver ting outp ut. The o utput

enable control can come from an external pin or internally from

a product term . The ou tpu t can al so be perma ne ntly ena ble d,

functioning as a dedicated output or permanently disabled,

functioning as a dedicated input. Feedback paths are select-

able from either the input/output pin associated with the mac-

rocell, the input/out pu t pin as so ci ated with an adjacent pin, or

from the m acrocell regis ter itself.

Power-Up Reset

All r egister s in the PALCE1 6V8 power -up to a l ogic LOW for

predictable system initialization. For each register , the associ-

ated output pin will be HIGH due to active-LOW outputs.

Electronic Signature

An electronic signature word is provided in the PALCE16V8

that consists of 64 bits of programmable m emory that can con-

tain user-de f in ed data .

Security Bit

A security bit is provided that defeats the readback of the in-

ternal programmed pattern when the bit is programmed.

Low Power

The Cypress PALCE16V8 provides low-power operation

through the use of CMOS technology , and increased testability

with Flash reprogrammability.

Product Term Disable

Product Term Dis able (PT D) fuses are included for e ach prod-

uct term . The PTD fuses allo w each pro duct term to b e individ-

ually disabled.

Selection Guide

Generic Part Number tPD ns tS ns tCO ns ICC mA

Com’l/Ind Mil Com’l/Ind Mil Com’l/Ind Mil Com’lMil/Ind

PALCE16V8-5 5 3 4 115

PALCE16V8-7 7.5 7 5 115

PALCE16V8-10 10 10 10 10 710 90 130

PALCE16V8-15 15 15 12 12 10 10 90 130

PALCE16V8-25 25 25 15 20 12 12 90 130

PALCE16V8L-15 15 15 12 12 10 12 55 65

PALCE16V8L-25 25 25 15 20 12 20 55 65

Shaded area contains preliminary information.

Configurati on Table

CG0CG1CL0xCell Configuration Devices Emulated

010Regi stered Output Registe red Med PALs

011Combinatorial I/O Registe red Med PALs

100Combinatorial Output Small PALs

101Input Small PAL s

111Combinatorial I/O 16L8 only

PALCE16V8

Document #: 38-03025 Rev. ** Page 3 of 13

Macrocell

CLK

16V8–4

CL1x

I/Ox

From

Adjacent

CL0x

CG1for pin 13 to 18

CG0for pin 12 and 19

11OE

VCC

Adjacent

Macrocell

CL0x

CG1

VCC

PALCE16V8

Document #: 38-03025 Rev. ** Page 4 of 13

Maximum Ratings

(Above w hi ch the useful life may be impaired. For user g uid e-

lines, not tes ted .)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential

(Pin 24 to Pin 12)...........................................–0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State...............................................–0.5V to +7.0V

DC Input Voltage............................................–0.5V to +7.0V

Output Current into Outputs (LOW).............................24 mA

DC Programming Voltage.............................................12.5V

Latch-Up Current.....................................................>200 mA

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to +75°C 5V ±5%

Military[1] –55°C to +125°C 5V ±10%

Industrial –40°C to +85°C5V ±10%

Electrical Characteristics Over the Operating Range[2]

Parameter Description Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min.,

VIN = VIH or VIL IOH = –3.2 mA Com’l2.4 V

IOH = –2 mA Mil/Ind

VOL Output LOW Voltage VCC = Min.,

VIN = VIH or VIL IOL = 24 mA Com’l0.5 V

IOL = 12 mA Mil/Ind

VIH Input HIGH Level Guaranteed Input Logical HIGH V oltage for All Inputs[3] 2.0 V

VIL[4] Input LOW Level Guarante ed Inpu t Logic al LOW Voltage f or All In puts[3] –0.5 0.8 V

IIH Input or I/O HIGH Leakage

Current 3.5V < VIN < VCC 10 µA

IIL[5] Input or I/O LOW Leakage

Current 0V < VIN < VIN (Max.) –100 µA

ISC Output Sho rt Circuit Cur rent VCC = Max., VOUT = 0.5V[6, 7] –30 –150 mA

ICC Operating Power Supply

Current VCC = Max.,

VIL = 0V, V IH = 3V,

Output Open,

f = 15 MHz

(counter)

5, 7 ns Com’l115 mA

10, 15, 25 ns 90 mA

15L, 25L ns 55 mA

10, 15, 25 ns Mil/Ind 130 mA

15L, 25L ns Mil. 65 mA

15L, 25L ns Ind. 65 mA

Capacitance[7]

Parameter Description Test Conditions Typ. Unit

CIN Input Capacitance VIN = 2.0V @ f = 1 MHz 5pF

COUT Output Capacitance VOUT = 2.0V @ f = 1 MHz 5pF

Endurance Characteri stics[7]

Parameter Description Test Conditions Min. Max. Unit

NMinimu m Re pro gram m ing Cycle s Nor m al Programming Conditions 100 Cycles

Notes:

1. TA is the “instant on” case temperature.

2. See the last page of this specifi cat io n for Gro up A subgro up test in g infor ma ti on .

3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.

4. VIL (Min.) i s equal to –3.0V for p ulse durations less than 20 ns.

5. The leakage current is due to the internal pull-up resistor on all pins.

6. Not more t han one output should be test ed at a time. Duration of the short cir cuit should no t be more than one se cond. V OUT = 0.5V has been ch osen to a void test prob lems

caused by te ster ground degrad ation.

7. Tested initially and after any design or process changes that may affect these parameters.

PALCE16V8

Document #: 38-03025 Rev. ** Page 5 of 13

AC Test Loads and Wavefor ms

90%

10%

3.0V

GND

90%

10%

ALL INPUT PULSES

<2ns <2ns

16V8–5

OUTPUT

TEST POINT

16V8–6

Commercial Military

Specification S1CLR1R2R1R2Measured Output Value

tPD, tCO Closed 50 pF 200Ω390Ω390Ω750Ω1.5V

tPZX, tEA Z · H: Open

Z · L: Closed 1.5V

tPXZ, tER H · Z: Open

L · Z: Closed 5 pF H · Z: VOH – 0.5V

L · Z: VOL + 0.5V

PALCE16V8

Document #: 38-03025 Rev. ** Page 6 of 13

Commercial and Industri al Switching Characterist ic s[2]

16V8-5 16V8-7 16V8-10 16V8-15 16V8-25

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

tPD Input to Output

Propagation

Delay[8, 9]

1 5 3 7.5 310 315 325 ns

tPZX OE to Output

Enable 1 6 6 10 15 20 ns

tPXZ OE to Output

Disable 1 5 6 10 15 20 ns

tEA Input to Output

Enable Delay[7]1 6 9 10 15 25 ns

tER Input to Output

Disable Del ay[7, 10] 1 5 9 10 15 25 ns

tCO Clock to Output

Delay[8,9] 1 4 2 5 2 7 2 10 212 ns

tSInput or Feedbac k

Set-Up Time 3 5 7.5 12 15 ns

tHInput Hold Time 0 0 0 0 0 ns

tPExternal Clock

Period (tCO + tS)710 14.5 22 27 ns

tWH Clock Width HIGH[7] 3 4 6 8 12 ns

tWL Clock Width LOW[7] 3 4 6 8 12 ns

fMAX1 Ext ernal Maximu m

Frequency

(1/(tCO + tS))[7, 11]

143 100 69 45.5 37 MHz

fMAX2 Data Path Maximum Fre-

quency (1/(tWH + tWL))[7, 12] 166 125 83 62.5 41.6 MHz

fMAX3 Internal Feedback

Maximum Frequen cy

(1/(tCF + tS))[7, 13]

166 125 74 50 40 MHz

tCF Register Clock to

Feedback Input[7, 14] 3 3 6 8 10 ns

tPR Power-Up Reset Time[7] 1 1 1 1 1 µs

Shaded area contains preliminary information.

Notes:

8. Min. times are tested initially and after any design or process changes that may affect these parameters.

9. This specification is guaranteed for all device outputs changing state in a given access cycle.

10. This parameter is measured as the time after O E pi n or int ernal disable inpu t disabl es or en ables the o utput pi n. Thi s delay is meas ured t o the poi nt at which a prev ious

HIGH level has fallen to 0.5 vol ts below VOH min. or a prev ious LO W level has rise n to 0 .5 volt s abov e VOL max.

11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback c an o pe rate.

12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.

13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.

14. This parameter is calculated from the clock period at fMAX inte rnal ( 1/f MAX3) as me asured (see N ote 7 ab ove) mi nus t S.

PALCE16V8

Document #: 38-03025 Rev. ** Page 7 of 13

Military Switching Characteristics[7]

16V8-10 16V8-15 16V8-25

Parameter Description Min. Max. Min. Max. Min. Max. Unit

tPD Input to Output

Propagation Delay[8 , 9] 310 315 325 ns

tPZX OE to Output Enable 10 15 20 ns

tPXZ OE to Output Disable 10 15 20 ns

tEA Input to Output Enable Delay[7] 10 15 25 ns

tER Input to Output Disable Delay[7, 10] 10 15 25 ns

tCO Clock to Output Delay[8, 9] 2 7 2 10 212 ns

tSInput or Feedbac k Set-U p Time 10 12 15 ns

tHInput Hold Time .5 .5 .5 ns

tPExternal Clock Period (tCO + tS)17 22 27 ns

tWH Clock Width HIGH[7] 6 8 12 ns

tWL Clock Width LOW[7] 6 8 12 ns

fMAX1 External Maximum Frequ enc y

(1/(tCO + tS)[7, 11] 58 45.5 37 MHz

fMAX2 Data Path Maximum Frequency

(1/(tWH + tWL))[7, 12 ] 83 62.5 41.6 MHz

fMAX3 Internal Feedback Maximum

Frequency (1/(tCF + tS))[7, 13] 62.5 50 40 MHz

tCF Register Clock to

Feedback Input[7, 14] 6 8 10 ns

tPR Power-Up Reset Time[7] 111µs

Switching Waveform

tStHtWL

tWH

tCO

tPD

16V8–7

tPXZ,t

INPUTS, I/O,

REGISTERED

FEEDBACK

REGISTERED

OUTPUTS

COMBINATORIAL

OUTPUTS

tPXZ,t

tEA,t

PZX

tEA,t

PZX

[10]

[10] [10]

[10]

Power-Up Reset Waveform

tPR

POWER

CLOCK

tWL

10%

REGISTERED

ACTIVE LOW

OUTPUTS

16V8–8

SUPPLY VO LT AG E

tPR MAX= 1 µs

90% VCC

PALCE16V8

Document #: 38-03025 Rev. ** Page 8 of 13

Functional Logic Diagram for PALCE16V8

116 20 24 28

12843119 23 27151173

0 1620242812843119 23 27151173 11

16V8–9

MC7

CL1=2048

CL0=2120

PTD=2128

-2135

MC6

CL1=2049

CL0=2121

PTD=2136

-2143

MC5

CL1=2050

CL0=2122

PTD=2144

-2151

MC4

CL1=2051

CL0=2123

PTD=2152

-2159

MC3

CL1=2052

CL0=2124

PTD=2160

-2167

MC2

CL1=2053

CL0=2125

PTD=2168

-2175

MC1

CL1=2054

CL0=2126

PTD=2176

-2183

MC0

CL1=2055

CL0=2127

PTD=2184

-2191

USER ELECTRONIC SIGNATURE ROW

BYTE0 BYTE1BYTE2BYTE3BYTE4BYTE5 BYTE6 BYTE7

2056 2064 2072 2080 2088 2096 2104 2112 2119

MSB MSB LSBLSB

CG0=2192

CG1=2193

VCC

PRODUCTLINE FIRSTCELL NUMBERS

PIN NUMBERS INPUT LINE

NUMBERS

PIN NUMBERS

160

224

128

192

256 288

352

416

480

320

384

448

512 544

608

672

736

576

640

704

768 800

864

928

992

832

896

960

10241056

1120

1184

1248

1088

1152

1216

12801312

1376

1440

1504

1344

1408

1472

15361568

1632

1696

1760

1600

1664

1728

17921824

1888

1952

2016

1856

1920

1984

GLOBALARCHBITS

PALCE16V8

Document #: 38-03025 Rev. ** Page 9 of 13

Ordering Information

ICC

(mA) tPD

(ns) tS

(ns) tCO

(ns) Ordering Code

Pack-

age

Name Package Type Operating

Range

115 534PALCE16V8-5JC J61 20-Lead Plastic Leaded Chip Carrier Commercial

115 7.5 5 5 PALCE16V8-7JC J61 20-Lead Plastic Leaded Chip Carrier Commercial

PALCE16V8-7PC P5 20-Lead (300-Mil) Molded DIP

90 10 7.5 7PALCE16V8-10JC J61 20-Lead Plastic Leaded Chip Carrier

PALCE16V8-10PC P5 20-Lead (300-Mil) Molded DIP

130 10 7.5 7PALCE16V8-10JI J61 20-Lead Plastic Leaded Chip Carrier Industrial

PALCE16V8-10PI P5 20-Lead (300-Mil) Molded DIP

130 10 10 7PALCE16V8-10DMB D6 20-Lead (300-Mil) CerDIP Military

PALCE16V8-10LMB L61 20-Pin Square Leadless Chip Carrier

90 15 12 10 PALCE16V8-15JC J61 20-Lead Plastic Leaded Chip Carrier Commercial

PALCE16V8-15PC P5 20-Lead (300-Mil) Molded DIP

130 15 12 10 PALCE16V8-15PI P5 20-Lead(300Mil) Molded DIP Industrial

PALCE16V8-15DMB D6 20-Lead (300-Mil) CerDIP Military

PALCE16V8-15LMB L61 20-Pin Square Leadless Chip Carrier

90 25 15 12 PALCE16V8-25JC J61 20-Lead Plastic Leaded Chip Carrier Commercial

PALCE16V8-25PC P5 20-Lead (300-Mil) Molded DIP

130 25 15 12 PALCE16V8-25JI J61 20-Lead Plastic Leaded Chip Carrier Industrial

PALCE16V8-25DMB D6 20-Lead (300-Mil) CerDIP Military

PALCE16V8-25LMB L61 20-Pin Square Leadless Chip Carrier

55 10 7.5 7PALCE16V8L-10JC J61 20-Lead Plastic Leaded Chip Carrier Commercial

PALCE16V8L-10PC P5 20-Lead (300-Mil) Molded DIP

65 10 10 7PALCE16V8L-10JI J61 20-Lead Plastic Leaded Chip Carrier Industrial

PALCE16V8L-10PI P5 20-Lead (300-Mil) Molded DIP

55 15 12 10 PALCE16V8L-15JC J61 20-Lead Plastic Leaded Chip Carrier Commercial

PALCE16V8L-15PC P5 20-Lead (300-Mil) Molded DIP

65 15 12 10 PALCE16V8L-15DMB D6 20-Lead (300-Mil) CerDIP Military

PALCE16V8L-15LMB L61 20-Pin Square Leadless Chip Carrier

55 25 15 12 PALCE16V8L-25JC J61 20-Lead Plastic Leaded Chip Carrier Commercial

PALCE16V8L-25PC P5 20-Lead (300-Mil) Molded DIP Military65 25 15 12 PALCE16V8L-25DMB D6 20-Lead (300-Mil) CerDIP

PALCE16V8L-25LMB L61 20-Pin Square Leadless Chip Carrier

Shaded area contains preliminary information.

PALCE16V8

Document #: 38-03025 Rev. ** Page 10 of 13

MILITAR Y SPECIFICATIONS

Group A Subgroup Testing

DC Characteristics

Parameter Subgroups

VOH 1, 2, 3

VOL 1, 2, 3

VIH 1, 2, 3

VIL 1, 2, 3

IIX 1, 2, 3

IOZ 1, 2, 3

ICC 1, 2, 3

Switching Characteristics

Parameter Subgroups

tPD 9, 10, 11

tCO 9, 10, 11

tS9, 10, 11

tH9, 10, 11

Package Diagrams

20-Lead (300-Mil) CerDIP D6

MIL-STD-1835 D-8 Config. A

51-80029

PALCE16V8

Document #: 38-03025 Rev. ** Page 11 of 13

Package Diagrams (continued)

20-Lead Plastic Leaded Chip Carrier J61

51-85000-A

20-Square Leadless Chip Carrier L61

51-80049

PALCE16V8

Document #: 38-03025 Rev. ** Page 12 of 13

of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi

ng so indemnifies Cypress Semiconductor against all charges.

Package Diagrams (continued)

51-85011-A

20-Lead (300-Mil) Molded DIP P5

PALCE16V8

Document #: 38-03025 Rev. ** Page 13 of 13

Document Title: PALCE16V8 Flash Erasable, Reprogrammable CMOS PAL® De v i ce

Document Number: 38-03025

REV. ECN NO. Issue

Date Orig. of

Change Description of Change

** 106370 07/11/01 SZV Change from Spec Number: 38-00364 to 38-03025