FIN1101K8X_Q - FAIRCHILD SEMICONDUCTOR

January 2002

Revised September 2002

FIN1101 LVDS Single Port High Speed Repeater

FIN1101

LVDS Single Port High Speed Repeater

General Description

This single port repeater is designed for high speed inter-

connects utilizing Low Voltage Differential Signaling

(LVDS) technology. It accepts and outputs LVDS levels

with a typical differential output swing of 330 mV which pro-

vides low EMI at ultra low power dissipation even at high

frequencies. It can directly accept multiple differential I/O

including: LVPECL, HSTL, and SSTL-2 for translating

directly to LVDS.

Features

■Up to 1.6 Gb/s full differential path

■3.5 ps max random jitter and 135 ps max deterministic

jitter

■3.3V power supply operation

■Wide rail-to-rail common mode range

■Ultra low power consumption

■LVDS receiver inputs accept LVPECL, HSTL, and

SSTL-2 directly

■Power off protection

■7 kV HBM ESD protection (all pins)

■Meets or exceed the TA/EIA-644-A LVDS standard

■Packaged in 8-pin SOIC and US 8

■Open circuit fail safe protection

Ordering Code:

Connection Diagrams

SOIC Package

US8 Pack age

Functional Diagram

Pin Descriptions

Function Table

H = HIGH Lo gic Level L = LOW Logi c Level

X = Don’t Care Z = High Impeda nc e

Order Num b er Packa ge Num be r Packag e Descr ip tio n

FIN1101M M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

[TUBE]

FIN1101MX M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

[TAPE and REEL]

FIN1101K8X MAB08A 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide

[TAPE and REEL]

Pin Name Description

RIN+Non-Inverting LVDS Inputs

RIN−Inverting LVDS Inputs

DOUT+Non-Inverting Driver Outputs

DOUT−Inverting Driver Outputs

EN Driver Enable Pin

VCC Power Supply

GND Ground

Inputs Outputs

EN RIN+RIN−DOUT+DOUT−

HHLHL

HLHLH

H Fail Safe Case H L

LXXZZ

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FIN1101

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “Absolute Maximum Ratings”: are those values beyond which

damage to the device may occur. The databook specifications should be

met, without exception, to ensure that the system design is reliable over its

power supply, temperature and output/input loading variables. Fairchild

does no t re c om m end operation of circuit s o ut s ide data book specif ic ation.

DC Electrical Characteristi cs

Over supply voltage and operating temperature ranges, unless otherwise specified

Note 2: All typi c al values are at TA = 25°C and with VCC = 3.3V.

Supply Voltage (VCC)−0.5V to +4.6V

LVDS DC Input Voltage (VIN)−0.5V to +4.6V

LVDS DC Output Voltage (VOUT)−0.5V to +4.6V

Driver Short Circuit Current (IOSD) Continuous 10 mA

Storage Temperature Range (TSTG)−65°C to +150°C

Max Junction Temperature (TJ)150°C

Lead Temperature (TL)

(Soldering, 10 seconds) 260°C

ESD (Human Body Model) 7000V

ESD (Machine Model) 300V

Supply Voltage (VCC) 3.0V to 3.6V

Operating Temperature (TA)−40°C to +85°C

Magnitude of Input

Differential Voltage (|VID|) 100 m V to VCC

Common Mode Input Voltage

(VIC)(0V + |VID|/2) to (VCC − |VID|/2)

Symbol Param eter Test Conditions Min Typ Max Units

(Note 2)

VTH Differential Input Threshold HIGH See Figure 1; VIC = +0.05V, +1.2V, or (VCC − 0.05V) 100 mV

VTL Differential Input Threshold LOW See Figure 1; VIC = +0.05V, +1.2V, or (VCC − 0.05V) −100 mV

VIH Input High Voltage (EN) 2.0 VCC V

VIL Input Low Voltage (EN) GND 0.8 V

VOD Output Differential Voltage 250 330 450 mV

∆VOD VOD Magnitude Change from RL = 100 Ω, Driver Enabled, 25 mV

Differential LOW-to-HIGH See Figure 2

VOS Offset Voltage 1.125 1.23 1.375 V

∆VOS Offset Magnitude Change from 25 mV

Differential LOW-to-HIGH

IOS Short Circuit Output Current DOUT+ = 0V & DOUT− = 0V, Driver Enabled −3.4 −6mA

VOD = 0V, Driver Enabled ±3.4 ±6mA

IIN Input Current (EN, DINX+, DINX−)V

IN = 0V to VCC, ±20 µA

Other Input = VCC or 0V (for Differential Inputs)

IOFF Power-Off Input or Output Current VCC = 0V, VIN or VOUT = 0V to 3.6V ±20 µA

ICCZ Disabled Power Supply Current Drivers Disabled 3.2 5.5 mA

ICC Power Supply Current Drivers Enabled, Any Valid Input Condition 9.3 13.5 mA

IOZ Disabled Output Leakage Current Driver Disabled, DOUT+ = 0V to 3.6V or ±20 µA

DOUT− = 0V to 3.6V

VIC Common Mode Voltage Range |VID| = 100 mV to VCC 0V + |VID|/2 VCC− (|VID|/2) V

CIN Input Capacitance EN Input 2.2 pF

Data Input 2.0

COUT Output Capacitance 2.6 pF

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FIN1101

AC Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified

Note 3: All typical values are at TA = 25°C and wit h VCC = 3.3V, VID = 300mV, VIC = 1.2V unless ot herwise specified .

Note 4: tSK(PP) is th e magnitude of the differe nce in differen tial propag ation delay t imes betwe en identic al channels o f two devic es switch ing in the same

direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test cir-

cuits.

Note 5: Passing criteria for maximum frequency is the output VOD > 200 mV and the duty cycle is 45% to 55% with all channels switching.

Note 6: Output loading is transmiss ion line environm ent only; CL is < 1 pF of stray test fixture capacitance.

FIGURE 1. Differential Receiver V oltage Definitions and

Propagation I and Transit ion Time Test Circuit FIGURE 2. Differential Driver DC Test Circuit

Note A: All LVDS input pulses ha v e f reque nc y = 10MHz, tR or tF < = 0.5 ns

Note B: CL includes all probe and t es t fi xture capac it ances

FIGURE 3. Differential Driver Propagation Delay and Transition Time Test Circuit

Symbol Parameter Test Conditions Min Typ Max Units

(Note 3)

tPLHD Differentia l Propagati on Delay 0.75 1.1 1.75 ns

LOW-to-HIGH

tPHLD Differentia l Propaga tion Delay RL = 100 Ω, CL = 5 pF, 0.75 1.1 1.75 ns

HIGH-to-LOW VID = 200 mV to 450 mV,

tTLHD Differential Output Rise Time (20% to 80%) VIC = |VID|/2 to (VCC− (VID/2), 0.29 0.40 0.58 ns

tTHLD Differential Output Fall Time (80% to 20%) Duty Cycle = 50%, 0.29 0.40 0.58 ns

tSK(P) Pulse Skew |tPLH - tPHL| See Figure 3 and Figure 4 0.01 0.2 ns

tSK(PP) Part-to-Part Skew (Note 4) 0.5 ns

fMAX Maximum Frequency (Note 5)(Note 6) 400 800 MHz

tPZHD Differential Output Enable Time from Z to HIGH 2.1 5 ns

tPZLD Differential Output Enable Time from Z to LOW RL = 100 Ω, CL = 5 pF, 2.3 5 ns

tPHZD Differential Output Disable Time from HIGH to Z See Figure 2 and Figure 3 1.5 5 ns

tPLZD Differential Output Disable Time from LOW to Z 1.8 5 ns

tDJ LVDS Data Jitter, VID = 300 mV, PRBS = 223 − 1, 85 135 ps

Deterministic VIC = 1.2V at 800 Mbps

tRJ LVDS Clock Jitter, Random VID = 300 mV 2.1 3.5 ps

(RMS) VIC = 1.2 V at 400 MHz

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FIN1101

FIGURE 4. AC Waveforms

Note A: All LVTTL input pulses have frequency = 10 MHz, tR or t F < = 2 ns

Note B: CL includes all probe and test fixt ure capac it ances

FIGURE 5. Differential Driver Enable and Disable Test Circuit

FIGURE 6. Enable and Disable AC Waveforms

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FIN1101

Physical Dimensions inches (millimeters) unless otherwise noted

8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M08A

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FIN1101 LVDS Single Port High Speed Repeater

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide

Package Number MAB08A

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syste ms are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a lif e supp ort

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.